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1/*
2 * NAND Flash Controller Device Driver
3 * Copyright © 2009-2010, Intel Corporation and its suppliers.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 */
19
20#include <linux/interrupt.h>
21#include <linux/delay.h>
22#include <linux/dma-mapping.h>
23#include <linux/wait.h>
24#include <linux/mutex.h>
25#include <linux/slab.h>
26#include <linux/pci.h>
27#include <linux/mtd/mtd.h>
28#include <linux/module.h>
29
30#include "denali.h"
31
32MODULE_LICENSE("GPL");
33
34/* We define a module parameter that allows the user to override
35 * the hardware and decide what timing mode should be used.
36 */
37#define NAND_DEFAULT_TIMINGS -1
38
39static int onfi_timing_mode = NAND_DEFAULT_TIMINGS;
40module_param(onfi_timing_mode, int, S_IRUGO);
41MODULE_PARM_DESC(onfi_timing_mode, "Overrides default ONFI setting."
42 " -1 indicates use default timings");
43
44#define DENALI_NAND_NAME "denali-nand"
45
46/* We define a macro here that combines all interrupts this driver uses into
47 * a single constant value, for convenience. */
48#define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \
49 INTR_STATUS__ECC_TRANSACTION_DONE | \
50 INTR_STATUS__ECC_ERR | \
51 INTR_STATUS__PROGRAM_FAIL | \
52 INTR_STATUS__LOAD_COMP | \
53 INTR_STATUS__PROGRAM_COMP | \
54 INTR_STATUS__TIME_OUT | \
55 INTR_STATUS__ERASE_FAIL | \
56 INTR_STATUS__RST_COMP | \
57 INTR_STATUS__ERASE_COMP)
58
59/* indicates whether or not the internal value for the flash bank is
60 * valid or not */
61#define CHIP_SELECT_INVALID -1
62
63#define SUPPORT_8BITECC 1
64
65/* This macro divides two integers and rounds fractional values up
66 * to the nearest integer value. */
67#define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y)))
68
69/* this macro allows us to convert from an MTD structure to our own
70 * device context (denali) structure.
71 */
72#define mtd_to_denali(m) container_of(m, struct denali_nand_info, mtd)
73
74/* These constants are defined by the driver to enable common driver
75 * configuration options. */
76#define SPARE_ACCESS 0x41
77#define MAIN_ACCESS 0x42
78#define MAIN_SPARE_ACCESS 0x43
79
80#define DENALI_READ 0
81#define DENALI_WRITE 0x100
82
83/* types of device accesses. We can issue commands and get status */
84#define COMMAND_CYCLE 0
85#define ADDR_CYCLE 1
86#define STATUS_CYCLE 2
87
88/* this is a helper macro that allows us to
89 * format the bank into the proper bits for the controller */
90#define BANK(x) ((x) << 24)
91
92/* List of platforms this NAND controller has be integrated into */
93static const struct pci_device_id denali_pci_ids[] = {
94 { PCI_VDEVICE(INTEL, 0x0701), INTEL_CE4100 },
95 { PCI_VDEVICE(INTEL, 0x0809), INTEL_MRST },
96 { /* end: all zeroes */ }
97};
98
99/* forward declarations */
100static void clear_interrupts(struct denali_nand_info *denali);
101static uint32_t wait_for_irq(struct denali_nand_info *denali,
102 uint32_t irq_mask);
103static void denali_irq_enable(struct denali_nand_info *denali,
104 uint32_t int_mask);
105static uint32_t read_interrupt_status(struct denali_nand_info *denali);
106
107/* Certain operations for the denali NAND controller use
108 * an indexed mode to read/write data. The operation is
109 * performed by writing the address value of the command
110 * to the device memory followed by the data. This function
111 * abstracts this common operation.
112*/
113static void index_addr(struct denali_nand_info *denali,
114 uint32_t address, uint32_t data)
115{
116 iowrite32(address, denali->flash_mem);
117 iowrite32(data, denali->flash_mem + 0x10);
118}
119
120/* Perform an indexed read of the device */
121static void index_addr_read_data(struct denali_nand_info *denali,
122 uint32_t address, uint32_t *pdata)
123{
124 iowrite32(address, denali->flash_mem);
125 *pdata = ioread32(denali->flash_mem + 0x10);
126}
127
128/* We need to buffer some data for some of the NAND core routines.
129 * The operations manage buffering that data. */
130static void reset_buf(struct denali_nand_info *denali)
131{
132 denali->buf.head = denali->buf.tail = 0;
133}
134
135static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte)
136{
137 BUG_ON(denali->buf.tail >= sizeof(denali->buf.buf));
138 denali->buf.buf[denali->buf.tail++] = byte;
139}
140
141/* reads the status of the device */
142static void read_status(struct denali_nand_info *denali)
143{
144 uint32_t cmd = 0x0;
145
146 /* initialize the data buffer to store status */
147 reset_buf(denali);
148
149 cmd = ioread32(denali->flash_reg + WRITE_PROTECT);
150 if (cmd)
151 write_byte_to_buf(denali, NAND_STATUS_WP);
152 else
153 write_byte_to_buf(denali, 0);
154}
155
156/* resets a specific device connected to the core */
157static void reset_bank(struct denali_nand_info *denali)
158{
159 uint32_t irq_status = 0;
160 uint32_t irq_mask = INTR_STATUS__RST_COMP |
161 INTR_STATUS__TIME_OUT;
162
163 clear_interrupts(denali);
164
165 iowrite32(1 << denali->flash_bank, denali->flash_reg + DEVICE_RESET);
166
167 irq_status = wait_for_irq(denali, irq_mask);
168
169 if (irq_status & INTR_STATUS__TIME_OUT)
170 dev_err(denali->dev, "reset bank failed.\n");
171}
172
173/* Reset the flash controller */
174static uint16_t denali_nand_reset(struct denali_nand_info *denali)
175{
176 uint32_t i;
177
178 dev_dbg(denali->dev, "%s, Line %d, Function: %s\n",
179 __FILE__, __LINE__, __func__);
180
181 for (i = 0 ; i < denali->max_banks; i++)
182 iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
183 denali->flash_reg + INTR_STATUS(i));
184
185 for (i = 0 ; i < denali->max_banks; i++) {
186 iowrite32(1 << i, denali->flash_reg + DEVICE_RESET);
187 while (!(ioread32(denali->flash_reg +
188 INTR_STATUS(i)) &
189 (INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT)))
190 cpu_relax();
191 if (ioread32(denali->flash_reg + INTR_STATUS(i)) &
192 INTR_STATUS__TIME_OUT)
193 dev_dbg(denali->dev,
194 "NAND Reset operation timed out on bank %d\n", i);
195 }
196
197 for (i = 0; i < denali->max_banks; i++)
198 iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
199 denali->flash_reg + INTR_STATUS(i));
200
201 return PASS;
202}
203
204/* this routine calculates the ONFI timing values for a given mode and
205 * programs the clocking register accordingly. The mode is determined by
206 * the get_onfi_nand_para routine.
207 */
208static void nand_onfi_timing_set(struct denali_nand_info *denali,
209 uint16_t mode)
210{
211 uint16_t Trea[6] = {40, 30, 25, 20, 20, 16};
212 uint16_t Trp[6] = {50, 25, 17, 15, 12, 10};
213 uint16_t Treh[6] = {30, 15, 15, 10, 10, 7};
214 uint16_t Trc[6] = {100, 50, 35, 30, 25, 20};
215 uint16_t Trhoh[6] = {0, 15, 15, 15, 15, 15};
216 uint16_t Trloh[6] = {0, 0, 0, 0, 5, 5};
217 uint16_t Tcea[6] = {100, 45, 30, 25, 25, 25};
218 uint16_t Tadl[6] = {200, 100, 100, 100, 70, 70};
219 uint16_t Trhw[6] = {200, 100, 100, 100, 100, 100};
220 uint16_t Trhz[6] = {200, 100, 100, 100, 100, 100};
221 uint16_t Twhr[6] = {120, 80, 80, 60, 60, 60};
222 uint16_t Tcs[6] = {70, 35, 25, 25, 20, 15};
223
224 uint16_t TclsRising = 1;
225 uint16_t data_invalid_rhoh, data_invalid_rloh, data_invalid;
226 uint16_t dv_window = 0;
227 uint16_t en_lo, en_hi;
228 uint16_t acc_clks;
229 uint16_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt;
230
231 dev_dbg(denali->dev, "%s, Line %d, Function: %s\n",
232 __FILE__, __LINE__, __func__);
233
234 en_lo = CEIL_DIV(Trp[mode], CLK_X);
235 en_hi = CEIL_DIV(Treh[mode], CLK_X);
236#if ONFI_BLOOM_TIME
237 if ((en_hi * CLK_X) < (Treh[mode] + 2))
238 en_hi++;
239#endif
240
241 if ((en_lo + en_hi) * CLK_X < Trc[mode])
242 en_lo += CEIL_DIV((Trc[mode] - (en_lo + en_hi) * CLK_X), CLK_X);
243
244 if ((en_lo + en_hi) < CLK_MULTI)
245 en_lo += CLK_MULTI - en_lo - en_hi;
246
247 while (dv_window < 8) {
248 data_invalid_rhoh = en_lo * CLK_X + Trhoh[mode];
249
250 data_invalid_rloh = (en_lo + en_hi) * CLK_X + Trloh[mode];
251
252 data_invalid =
253 data_invalid_rhoh <
254 data_invalid_rloh ? data_invalid_rhoh : data_invalid_rloh;
255
256 dv_window = data_invalid - Trea[mode];
257
258 if (dv_window < 8)
259 en_lo++;
260 }
261
262 acc_clks = CEIL_DIV(Trea[mode], CLK_X);
263
264 while (((acc_clks * CLK_X) - Trea[mode]) < 3)
265 acc_clks++;
266
267 if ((data_invalid - acc_clks * CLK_X) < 2)
268 dev_warn(denali->dev, "%s, Line %d: Warning!\n",
269 __FILE__, __LINE__);
270
271 addr_2_data = CEIL_DIV(Tadl[mode], CLK_X);
272 re_2_we = CEIL_DIV(Trhw[mode], CLK_X);
273 re_2_re = CEIL_DIV(Trhz[mode], CLK_X);
274 we_2_re = CEIL_DIV(Twhr[mode], CLK_X);
275 cs_cnt = CEIL_DIV((Tcs[mode] - Trp[mode]), CLK_X);
276 if (!TclsRising)
277 cs_cnt = CEIL_DIV(Tcs[mode], CLK_X);
278 if (cs_cnt == 0)
279 cs_cnt = 1;
280
281 if (Tcea[mode]) {
282 while (((cs_cnt * CLK_X) + Trea[mode]) < Tcea[mode])
283 cs_cnt++;
284 }
285
286#if MODE5_WORKAROUND
287 if (mode == 5)
288 acc_clks = 5;
289#endif
290
291 /* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */
292 if ((ioread32(denali->flash_reg + MANUFACTURER_ID) == 0) &&
293 (ioread32(denali->flash_reg + DEVICE_ID) == 0x88))
294 acc_clks = 6;
295
296 iowrite32(acc_clks, denali->flash_reg + ACC_CLKS);
297 iowrite32(re_2_we, denali->flash_reg + RE_2_WE);
298 iowrite32(re_2_re, denali->flash_reg + RE_2_RE);
299 iowrite32(we_2_re, denali->flash_reg + WE_2_RE);
300 iowrite32(addr_2_data, denali->flash_reg + ADDR_2_DATA);
301 iowrite32(en_lo, denali->flash_reg + RDWR_EN_LO_CNT);
302 iowrite32(en_hi, denali->flash_reg + RDWR_EN_HI_CNT);
303 iowrite32(cs_cnt, denali->flash_reg + CS_SETUP_CNT);
304}
305
306/* queries the NAND device to see what ONFI modes it supports. */
307static uint16_t get_onfi_nand_para(struct denali_nand_info *denali)
308{
309 int i;
310 /* we needn't to do a reset here because driver has already
311 * reset all the banks before
312 * */
313 if (!(ioread32(denali->flash_reg + ONFI_TIMING_MODE) &
314 ONFI_TIMING_MODE__VALUE))
315 return FAIL;
316
317 for (i = 5; i > 0; i--) {
318 if (ioread32(denali->flash_reg + ONFI_TIMING_MODE) &
319 (0x01 << i))
320 break;
321 }
322
323 nand_onfi_timing_set(denali, i);
324
325 /* By now, all the ONFI devices we know support the page cache */
326 /* rw feature. So here we enable the pipeline_rw_ahead feature */
327 /* iowrite32(1, denali->flash_reg + CACHE_WRITE_ENABLE); */
328 /* iowrite32(1, denali->flash_reg + CACHE_READ_ENABLE); */
329
330 return PASS;
331}
332
333static void get_samsung_nand_para(struct denali_nand_info *denali,
334 uint8_t device_id)
335{
336 if (device_id == 0xd3) { /* Samsung K9WAG08U1A */
337 /* Set timing register values according to datasheet */
338 iowrite32(5, denali->flash_reg + ACC_CLKS);
339 iowrite32(20, denali->flash_reg + RE_2_WE);
340 iowrite32(12, denali->flash_reg + WE_2_RE);
341 iowrite32(14, denali->flash_reg + ADDR_2_DATA);
342 iowrite32(3, denali->flash_reg + RDWR_EN_LO_CNT);
343 iowrite32(2, denali->flash_reg + RDWR_EN_HI_CNT);
344 iowrite32(2, denali->flash_reg + CS_SETUP_CNT);
345 }
346}
347
348static void get_toshiba_nand_para(struct denali_nand_info *denali)
349{
350 uint32_t tmp;
351
352 /* Workaround to fix a controller bug which reports a wrong */
353 /* spare area size for some kind of Toshiba NAND device */
354 if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) &&
355 (ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) {
356 iowrite32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
357 tmp = ioread32(denali->flash_reg + DEVICES_CONNECTED) *
358 ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
359 iowrite32(tmp,
360 denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
361#if SUPPORT_15BITECC
362 iowrite32(15, denali->flash_reg + ECC_CORRECTION);
363#elif SUPPORT_8BITECC
364 iowrite32(8, denali->flash_reg + ECC_CORRECTION);
365#endif
366 }
367}
368
369static void get_hynix_nand_para(struct denali_nand_info *denali,
370 uint8_t device_id)
371{
372 uint32_t main_size, spare_size;
373
374 switch (device_id) {
375 case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */
376 case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */
377 iowrite32(128, denali->flash_reg + PAGES_PER_BLOCK);
378 iowrite32(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
379 iowrite32(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
380 main_size = 4096 *
381 ioread32(denali->flash_reg + DEVICES_CONNECTED);
382 spare_size = 224 *
383 ioread32(denali->flash_reg + DEVICES_CONNECTED);
384 iowrite32(main_size,
385 denali->flash_reg + LOGICAL_PAGE_DATA_SIZE);
386 iowrite32(spare_size,
387 denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
388 iowrite32(0, denali->flash_reg + DEVICE_WIDTH);
389#if SUPPORT_15BITECC
390 iowrite32(15, denali->flash_reg + ECC_CORRECTION);
391#elif SUPPORT_8BITECC
392 iowrite32(8, denali->flash_reg + ECC_CORRECTION);
393#endif
394 break;
395 default:
396 dev_warn(denali->dev,
397 "Spectra: Unknown Hynix NAND (Device ID: 0x%x)."
398 "Will use default parameter values instead.\n",
399 device_id);
400 }
401}
402
403/* determines how many NAND chips are connected to the controller. Note for
404 * Intel CE4100 devices we don't support more than one device.
405 */
406static void find_valid_banks(struct denali_nand_info *denali)
407{
408 uint32_t id[denali->max_banks];
409 int i;
410
411 denali->total_used_banks = 1;
412 for (i = 0; i < denali->max_banks; i++) {
413 index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 0), 0x90);
414 index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 1), 0);
415 index_addr_read_data(denali,
416 (uint32_t)(MODE_11 | (i << 24) | 2), &id[i]);
417
418 dev_dbg(denali->dev,
419 "Return 1st ID for bank[%d]: %x\n", i, id[i]);
420
421 if (i == 0) {
422 if (!(id[i] & 0x0ff))
423 break; /* WTF? */
424 } else {
425 if ((id[i] & 0x0ff) == (id[0] & 0x0ff))
426 denali->total_used_banks++;
427 else
428 break;
429 }
430 }
431
432 if (denali->platform == INTEL_CE4100) {
433 /* Platform limitations of the CE4100 device limit
434 * users to a single chip solution for NAND.
435 * Multichip support is not enabled.
436 */
437 if (denali->total_used_banks != 1) {
438 dev_err(denali->dev,
439 "Sorry, Intel CE4100 only supports "
440 "a single NAND device.\n");
441 BUG();
442 }
443 }
444 dev_dbg(denali->dev,
445 "denali->total_used_banks: %d\n", denali->total_used_banks);
446}
447
448/*
449 * Use the configuration feature register to determine the maximum number of
450 * banks that the hardware supports.
451 */
452static void detect_max_banks(struct denali_nand_info *denali)
453{
454 uint32_t features = ioread32(denali->flash_reg + FEATURES);
455
456 denali->max_banks = 2 << (features & FEATURES__N_BANKS);
457}
458
459static void detect_partition_feature(struct denali_nand_info *denali)
460{
461 /* For MRST platform, denali->fwblks represent the
462 * number of blocks firmware is taken,
463 * FW is in protect partition and MTD driver has no
464 * permission to access it. So let driver know how many
465 * blocks it can't touch.
466 * */
467 if (ioread32(denali->flash_reg + FEATURES) & FEATURES__PARTITION) {
468 if ((ioread32(denali->flash_reg + PERM_SRC_ID(1)) &
469 PERM_SRC_ID__SRCID) == SPECTRA_PARTITION_ID) {
470 denali->fwblks =
471 ((ioread32(denali->flash_reg + MIN_MAX_BANK(1)) &
472 MIN_MAX_BANK__MIN_VALUE) *
473 denali->blksperchip)
474 +
475 (ioread32(denali->flash_reg + MIN_BLK_ADDR(1)) &
476 MIN_BLK_ADDR__VALUE);
477 } else
478 denali->fwblks = SPECTRA_START_BLOCK;
479 } else
480 denali->fwblks = SPECTRA_START_BLOCK;
481}
482
483static uint16_t denali_nand_timing_set(struct denali_nand_info *denali)
484{
485 uint16_t status = PASS;
486 uint32_t id_bytes[5], addr;
487 uint8_t i, maf_id, device_id;
488
489 dev_dbg(denali->dev,
490 "%s, Line %d, Function: %s\n",
491 __FILE__, __LINE__, __func__);
492
493 /* Use read id method to get device ID and other
494 * params. For some NAND chips, controller can't
495 * report the correct device ID by reading from
496 * DEVICE_ID register
497 * */
498 addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);
499 index_addr(denali, (uint32_t)addr | 0, 0x90);
500 index_addr(denali, (uint32_t)addr | 1, 0);
501 for (i = 0; i < 5; i++)
502 index_addr_read_data(denali, addr | 2, &id_bytes[i]);
503 maf_id = id_bytes[0];
504 device_id = id_bytes[1];
505
506 if (ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) &
507 ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */
508 if (FAIL == get_onfi_nand_para(denali))
509 return FAIL;
510 } else if (maf_id == 0xEC) { /* Samsung NAND */
511 get_samsung_nand_para(denali, device_id);
512 } else if (maf_id == 0x98) { /* Toshiba NAND */
513 get_toshiba_nand_para(denali);
514 } else if (maf_id == 0xAD) { /* Hynix NAND */
515 get_hynix_nand_para(denali, device_id);
516 }
517
518 dev_info(denali->dev,
519 "Dump timing register values:"
520 "acc_clks: %d, re_2_we: %d, re_2_re: %d\n"
521 "we_2_re: %d, addr_2_data: %d, rdwr_en_lo_cnt: %d\n"
522 "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n",
523 ioread32(denali->flash_reg + ACC_CLKS),
524 ioread32(denali->flash_reg + RE_2_WE),
525 ioread32(denali->flash_reg + RE_2_RE),
526 ioread32(denali->flash_reg + WE_2_RE),
527 ioread32(denali->flash_reg + ADDR_2_DATA),
528 ioread32(denali->flash_reg + RDWR_EN_LO_CNT),
529 ioread32(denali->flash_reg + RDWR_EN_HI_CNT),
530 ioread32(denali->flash_reg + CS_SETUP_CNT));
531
532 find_valid_banks(denali);
533
534 detect_partition_feature(denali);
535
536 /* If the user specified to override the default timings
537 * with a specific ONFI mode, we apply those changes here.
538 */
539 if (onfi_timing_mode != NAND_DEFAULT_TIMINGS)
540 nand_onfi_timing_set(denali, onfi_timing_mode);
541
542 return status;
543}
544
545static void denali_set_intr_modes(struct denali_nand_info *denali,
546 uint16_t INT_ENABLE)
547{
548 dev_dbg(denali->dev, "%s, Line %d, Function: %s\n",
549 __FILE__, __LINE__, __func__);
550
551 if (INT_ENABLE)
552 iowrite32(1, denali->flash_reg + GLOBAL_INT_ENABLE);
553 else
554 iowrite32(0, denali->flash_reg + GLOBAL_INT_ENABLE);
555}
556
557/* validation function to verify that the controlling software is making
558 * a valid request
559 */
560static inline bool is_flash_bank_valid(int flash_bank)
561{
562 return (flash_bank >= 0 && flash_bank < 4);
563}
564
565static void denali_irq_init(struct denali_nand_info *denali)
566{
567 uint32_t int_mask = 0;
568 int i;
569
570 /* Disable global interrupts */
571 denali_set_intr_modes(denali, false);
572
573 int_mask = DENALI_IRQ_ALL;
574
575 /* Clear all status bits */
576 for (i = 0; i < denali->max_banks; ++i)
577 iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS(i));
578
579 denali_irq_enable(denali, int_mask);
580}
581
582static void denali_irq_cleanup(int irqnum, struct denali_nand_info *denali)
583{
584 denali_set_intr_modes(denali, false);
585 free_irq(irqnum, denali);
586}
587
588static void denali_irq_enable(struct denali_nand_info *denali,
589 uint32_t int_mask)
590{
591 int i;
592
593 for (i = 0; i < denali->max_banks; ++i)
594 iowrite32(int_mask, denali->flash_reg + INTR_EN(i));
595}
596
597/* This function only returns when an interrupt that this driver cares about
598 * occurs. This is to reduce the overhead of servicing interrupts
599 */
600static inline uint32_t denali_irq_detected(struct denali_nand_info *denali)
601{
602 return read_interrupt_status(denali) & DENALI_IRQ_ALL;
603}
604
605/* Interrupts are cleared by writing a 1 to the appropriate status bit */
606static inline void clear_interrupt(struct denali_nand_info *denali,
607 uint32_t irq_mask)
608{
609 uint32_t intr_status_reg = 0;
610
611 intr_status_reg = INTR_STATUS(denali->flash_bank);
612
613 iowrite32(irq_mask, denali->flash_reg + intr_status_reg);
614}
615
616static void clear_interrupts(struct denali_nand_info *denali)
617{
618 uint32_t status = 0x0;
619 spin_lock_irq(&denali->irq_lock);
620
621 status = read_interrupt_status(denali);
622 clear_interrupt(denali, status);
623
624 denali->irq_status = 0x0;
625 spin_unlock_irq(&denali->irq_lock);
626}
627
628static uint32_t read_interrupt_status(struct denali_nand_info *denali)
629{
630 uint32_t intr_status_reg = 0;
631
632 intr_status_reg = INTR_STATUS(denali->flash_bank);
633
634 return ioread32(denali->flash_reg + intr_status_reg);
635}
636
637/* This is the interrupt service routine. It handles all interrupts
638 * sent to this device. Note that on CE4100, this is a shared
639 * interrupt.
640 */
641static irqreturn_t denali_isr(int irq, void *dev_id)
642{
643 struct denali_nand_info *denali = dev_id;
644 uint32_t irq_status = 0x0;
645 irqreturn_t result = IRQ_NONE;
646
647 spin_lock(&denali->irq_lock);
648
649 /* check to see if a valid NAND chip has
650 * been selected.
651 */
652 if (is_flash_bank_valid(denali->flash_bank)) {
653 /* check to see if controller generated
654 * the interrupt, since this is a shared interrupt */
655 irq_status = denali_irq_detected(denali);
656 if (irq_status != 0) {
657 /* handle interrupt */
658 /* first acknowledge it */
659 clear_interrupt(denali, irq_status);
660 /* store the status in the device context for someone
661 to read */
662 denali->irq_status |= irq_status;
663 /* notify anyone who cares that it happened */
664 complete(&denali->complete);
665 /* tell the OS that we've handled this */
666 result = IRQ_HANDLED;
667 }
668 }
669 spin_unlock(&denali->irq_lock);
670 return result;
671}
672#define BANK(x) ((x) << 24)
673
674static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask)
675{
676 unsigned long comp_res = 0;
677 uint32_t intr_status = 0;
678 bool retry = false;
679 unsigned long timeout = msecs_to_jiffies(1000);
680
681 do {
682 comp_res =
683 wait_for_completion_timeout(&denali->complete, timeout);
684 spin_lock_irq(&denali->irq_lock);
685 intr_status = denali->irq_status;
686
687 if (intr_status & irq_mask) {
688 denali->irq_status &= ~irq_mask;
689 spin_unlock_irq(&denali->irq_lock);
690 /* our interrupt was detected */
691 break;
692 } else {
693 /* these are not the interrupts you are looking for -
694 * need to wait again */
695 spin_unlock_irq(&denali->irq_lock);
696 retry = true;
697 }
698 } while (comp_res != 0);
699
700 if (comp_res == 0) {
701 /* timeout */
702 printk(KERN_ERR "timeout occurred, status = 0x%x, mask = 0x%x\n",
703 intr_status, irq_mask);
704
705 intr_status = 0;
706 }
707 return intr_status;
708}
709
710/* This helper function setups the registers for ECC and whether or not
711 * the spare area will be transferred. */
712static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en,
713 bool transfer_spare)
714{
715 int ecc_en_flag = 0, transfer_spare_flag = 0;
716
717 /* set ECC, transfer spare bits if needed */
718 ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0;
719 transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0;
720
721 /* Enable spare area/ECC per user's request. */
722 iowrite32(ecc_en_flag, denali->flash_reg + ECC_ENABLE);
723 iowrite32(transfer_spare_flag,
724 denali->flash_reg + TRANSFER_SPARE_REG);
725}
726
727/* sends a pipeline command operation to the controller. See the Denali NAND
728 * controller's user guide for more information (section 4.2.3.6).
729 */
730static int denali_send_pipeline_cmd(struct denali_nand_info *denali,
731 bool ecc_en,
732 bool transfer_spare,
733 int access_type,
734 int op)
735{
736 int status = PASS;
737 uint32_t addr = 0x0, cmd = 0x0, page_count = 1, irq_status = 0,
738 irq_mask = 0;
739
740 if (op == DENALI_READ)
741 irq_mask = INTR_STATUS__LOAD_COMP;
742 else if (op == DENALI_WRITE)
743 irq_mask = 0;
744 else
745 BUG();
746
747 setup_ecc_for_xfer(denali, ecc_en, transfer_spare);
748
749 /* clear interrupts */
750 clear_interrupts(denali);
751
752 addr = BANK(denali->flash_bank) | denali->page;
753
754 if (op == DENALI_WRITE && access_type != SPARE_ACCESS) {
755 cmd = MODE_01 | addr;
756 iowrite32(cmd, denali->flash_mem);
757 } else if (op == DENALI_WRITE && access_type == SPARE_ACCESS) {
758 /* read spare area */
759 cmd = MODE_10 | addr;
760 index_addr(denali, (uint32_t)cmd, access_type);
761
762 cmd = MODE_01 | addr;
763 iowrite32(cmd, denali->flash_mem);
764 } else if (op == DENALI_READ) {
765 /* setup page read request for access type */
766 cmd = MODE_10 | addr;
767 index_addr(denali, (uint32_t)cmd, access_type);
768
769 /* page 33 of the NAND controller spec indicates we should not
770 use the pipeline commands in Spare area only mode. So we
771 don't.
772 */
773 if (access_type == SPARE_ACCESS) {
774 cmd = MODE_01 | addr;
775 iowrite32(cmd, denali->flash_mem);
776 } else {
777 index_addr(denali, (uint32_t)cmd,
778 0x2000 | op | page_count);
779
780 /* wait for command to be accepted
781 * can always use status0 bit as the
782 * mask is identical for each
783 * bank. */
784 irq_status = wait_for_irq(denali, irq_mask);
785
786 if (irq_status == 0) {
787 dev_err(denali->dev,
788 "cmd, page, addr on timeout "
789 "(0x%x, 0x%x, 0x%x)\n",
790 cmd, denali->page, addr);
791 status = FAIL;
792 } else {
793 cmd = MODE_01 | addr;
794 iowrite32(cmd, denali->flash_mem);
795 }
796 }
797 }
798 return status;
799}
800
801/* helper function that simply writes a buffer to the flash */
802static int write_data_to_flash_mem(struct denali_nand_info *denali,
803 const uint8_t *buf,
804 int len)
805{
806 uint32_t i = 0, *buf32;
807
808 /* verify that the len is a multiple of 4. see comment in
809 * read_data_from_flash_mem() */
810 BUG_ON((len % 4) != 0);
811
812 /* write the data to the flash memory */
813 buf32 = (uint32_t *)buf;
814 for (i = 0; i < len / 4; i++)
815 iowrite32(*buf32++, denali->flash_mem + 0x10);
816 return i*4; /* intent is to return the number of bytes read */
817}
818
819/* helper function that simply reads a buffer from the flash */
820static int read_data_from_flash_mem(struct denali_nand_info *denali,
821 uint8_t *buf,
822 int len)
823{
824 uint32_t i = 0, *buf32;
825
826 /* we assume that len will be a multiple of 4, if not
827 * it would be nice to know about it ASAP rather than
828 * have random failures...
829 * This assumption is based on the fact that this
830 * function is designed to be used to read flash pages,
831 * which are typically multiples of 4...
832 */
833
834 BUG_ON((len % 4) != 0);
835
836 /* transfer the data from the flash */
837 buf32 = (uint32_t *)buf;
838 for (i = 0; i < len / 4; i++)
839 *buf32++ = ioread32(denali->flash_mem + 0x10);
840 return i*4; /* intent is to return the number of bytes read */
841}
842
843/* writes OOB data to the device */
844static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
845{
846 struct denali_nand_info *denali = mtd_to_denali(mtd);
847 uint32_t irq_status = 0;
848 uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP |
849 INTR_STATUS__PROGRAM_FAIL;
850 int status = 0;
851
852 denali->page = page;
853
854 if (denali_send_pipeline_cmd(denali, false, false, SPARE_ACCESS,
855 DENALI_WRITE) == PASS) {
856 write_data_to_flash_mem(denali, buf, mtd->oobsize);
857
858 /* wait for operation to complete */
859 irq_status = wait_for_irq(denali, irq_mask);
860
861 if (irq_status == 0) {
862 dev_err(denali->dev, "OOB write failed\n");
863 status = -EIO;
864 }
865 } else {
866 dev_err(denali->dev, "unable to send pipeline command\n");
867 status = -EIO;
868 }
869 return status;
870}
871
872/* reads OOB data from the device */
873static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
874{
875 struct denali_nand_info *denali = mtd_to_denali(mtd);
876 uint32_t irq_mask = INTR_STATUS__LOAD_COMP,
877 irq_status = 0, addr = 0x0, cmd = 0x0;
878
879 denali->page = page;
880
881 if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS,
882 DENALI_READ) == PASS) {
883 read_data_from_flash_mem(denali, buf, mtd->oobsize);
884
885 /* wait for command to be accepted
886 * can always use status0 bit as the mask is identical for each
887 * bank. */
888 irq_status = wait_for_irq(denali, irq_mask);
889
890 if (irq_status == 0)
891 dev_err(denali->dev, "page on OOB timeout %d\n",
892 denali->page);
893
894 /* We set the device back to MAIN_ACCESS here as I observed
895 * instability with the controller if you do a block erase
896 * and the last transaction was a SPARE_ACCESS. Block erase
897 * is reliable (according to the MTD test infrastructure)
898 * if you are in MAIN_ACCESS.
899 */
900 addr = BANK(denali->flash_bank) | denali->page;
901 cmd = MODE_10 | addr;
902 index_addr(denali, (uint32_t)cmd, MAIN_ACCESS);
903 }
904}
905
906/* this function examines buffers to see if they contain data that
907 * indicate that the buffer is part of an erased region of flash.
908 */
909bool is_erased(uint8_t *buf, int len)
910{
911 int i = 0;
912 for (i = 0; i < len; i++)
913 if (buf[i] != 0xFF)
914 return false;
915 return true;
916}
917#define ECC_SECTOR_SIZE 512
918
919#define ECC_SECTOR(x) (((x) & ECC_ERROR_ADDRESS__SECTOR_NR) >> 12)
920#define ECC_BYTE(x) (((x) & ECC_ERROR_ADDRESS__OFFSET))
921#define ECC_CORRECTION_VALUE(x) ((x) & ERR_CORRECTION_INFO__BYTEMASK)
922#define ECC_ERROR_CORRECTABLE(x) (!((x) & ERR_CORRECTION_INFO__ERROR_TYPE))
923#define ECC_ERR_DEVICE(x) (((x) & ERR_CORRECTION_INFO__DEVICE_NR) >> 8)
924#define ECC_LAST_ERR(x) ((x) & ERR_CORRECTION_INFO__LAST_ERR_INFO)
925
926static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf,
927 uint32_t irq_status, unsigned int *max_bitflips)
928{
929 bool check_erased_page = false;
930 unsigned int bitflips = 0;
931
932 if (irq_status & INTR_STATUS__ECC_ERR) {
933 /* read the ECC errors. we'll ignore them for now */
934 uint32_t err_address = 0, err_correction_info = 0;
935 uint32_t err_byte = 0, err_sector = 0, err_device = 0;
936 uint32_t err_correction_value = 0;
937 denali_set_intr_modes(denali, false);
938
939 do {
940 err_address = ioread32(denali->flash_reg +
941 ECC_ERROR_ADDRESS);
942 err_sector = ECC_SECTOR(err_address);
943 err_byte = ECC_BYTE(err_address);
944
945 err_correction_info = ioread32(denali->flash_reg +
946 ERR_CORRECTION_INFO);
947 err_correction_value =
948 ECC_CORRECTION_VALUE(err_correction_info);
949 err_device = ECC_ERR_DEVICE(err_correction_info);
950
951 if (ECC_ERROR_CORRECTABLE(err_correction_info)) {
952 /* If err_byte is larger than ECC_SECTOR_SIZE,
953 * means error happened in OOB, so we ignore
954 * it. It's no need for us to correct it
955 * err_device is represented the NAND error
956 * bits are happened in if there are more
957 * than one NAND connected.
958 * */
959 if (err_byte < ECC_SECTOR_SIZE) {
960 int offset;
961 offset = (err_sector *
962 ECC_SECTOR_SIZE +
963 err_byte) *
964 denali->devnum +
965 err_device;
966 /* correct the ECC error */
967 buf[offset] ^= err_correction_value;
968 denali->mtd.ecc_stats.corrected++;
969 bitflips++;
970 }
971 } else {
972 /* if the error is not correctable, need to
973 * look at the page to see if it is an erased
974 * page. if so, then it's not a real ECC error
975 * */
976 check_erased_page = true;
977 }
978 } while (!ECC_LAST_ERR(err_correction_info));
979 /* Once handle all ecc errors, controller will triger
980 * a ECC_TRANSACTION_DONE interrupt, so here just wait
981 * for a while for this interrupt
982 * */
983 while (!(read_interrupt_status(denali) &
984 INTR_STATUS__ECC_TRANSACTION_DONE))
985 cpu_relax();
986 clear_interrupts(denali);
987 denali_set_intr_modes(denali, true);
988 }
989 *max_bitflips = bitflips;
990 return check_erased_page;
991}
992
993/* programs the controller to either enable/disable DMA transfers */
994static void denali_enable_dma(struct denali_nand_info *denali, bool en)
995{
996 uint32_t reg_val = 0x0;
997
998 if (en)
999 reg_val = DMA_ENABLE__FLAG;
1000
1001 iowrite32(reg_val, denali->flash_reg + DMA_ENABLE);
1002 ioread32(denali->flash_reg + DMA_ENABLE);
1003}
1004
1005/* setups the HW to perform the data DMA */
1006static void denali_setup_dma(struct denali_nand_info *denali, int op)
1007{
1008 uint32_t mode = 0x0;
1009 const int page_count = 1;
1010 dma_addr_t addr = denali->buf.dma_buf;
1011
1012 mode = MODE_10 | BANK(denali->flash_bank);
1013
1014 /* DMA is a four step process */
1015
1016 /* 1. setup transfer type and # of pages */
1017 index_addr(denali, mode | denali->page, 0x2000 | op | page_count);
1018
1019 /* 2. set memory high address bits 23:8 */
1020 index_addr(denali, mode | ((uint16_t)(addr >> 16) << 8), 0x2200);
1021
1022 /* 3. set memory low address bits 23:8 */
1023 index_addr(denali, mode | ((uint16_t)addr << 8), 0x2300);
1024
1025 /* 4. interrupt when complete, burst len = 64 bytes*/
1026 index_addr(denali, mode | 0x14000, 0x2400);
1027}
1028
1029/* writes a page. user specifies type, and this function handles the
1030 * configuration details. */
1031static void write_page(struct mtd_info *mtd, struct nand_chip *chip,
1032 const uint8_t *buf, bool raw_xfer)
1033{
1034 struct denali_nand_info *denali = mtd_to_denali(mtd);
1035
1036 dma_addr_t addr = denali->buf.dma_buf;
1037 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
1038
1039 uint32_t irq_status = 0;
1040 uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP |
1041 INTR_STATUS__PROGRAM_FAIL;
1042
1043 /* if it is a raw xfer, we want to disable ecc, and send
1044 * the spare area.
1045 * !raw_xfer - enable ecc
1046 * raw_xfer - transfer spare
1047 */
1048 setup_ecc_for_xfer(denali, !raw_xfer, raw_xfer);
1049
1050 /* copy buffer into DMA buffer */
1051 memcpy(denali->buf.buf, buf, mtd->writesize);
1052
1053 if (raw_xfer) {
1054 /* transfer the data to the spare area */
1055 memcpy(denali->buf.buf + mtd->writesize,
1056 chip->oob_poi,
1057 mtd->oobsize);
1058 }
1059
1060 dma_sync_single_for_device(denali->dev, addr, size, DMA_TO_DEVICE);
1061
1062 clear_interrupts(denali);
1063 denali_enable_dma(denali, true);
1064
1065 denali_setup_dma(denali, DENALI_WRITE);
1066
1067 /* wait for operation to complete */
1068 irq_status = wait_for_irq(denali, irq_mask);
1069
1070 if (irq_status == 0) {
1071 dev_err(denali->dev,
1072 "timeout on write_page (type = %d)\n",
1073 raw_xfer);
1074 denali->status =
1075 (irq_status & INTR_STATUS__PROGRAM_FAIL) ?
1076 NAND_STATUS_FAIL : PASS;
1077 }
1078
1079 denali_enable_dma(denali, false);
1080 dma_sync_single_for_cpu(denali->dev, addr, size, DMA_TO_DEVICE);
1081}
1082
1083/* NAND core entry points */
1084
1085/* this is the callback that the NAND core calls to write a page. Since
1086 * writing a page with ECC or without is similar, all the work is done
1087 * by write_page above.
1088 * */
1089static void denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1090 const uint8_t *buf, int oob_required)
1091{
1092 /* for regular page writes, we let HW handle all the ECC
1093 * data written to the device. */
1094 write_page(mtd, chip, buf, false);
1095}
1096
1097/* This is the callback that the NAND core calls to write a page without ECC.
1098 * raw access is similar to ECC page writes, so all the work is done in the
1099 * write_page() function above.
1100 */
1101static void denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1102 const uint8_t *buf, int oob_required)
1103{
1104 /* for raw page writes, we want to disable ECC and simply write
1105 whatever data is in the buffer. */
1106 write_page(mtd, chip, buf, true);
1107}
1108
1109static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
1110 int page)
1111{
1112 return write_oob_data(mtd, chip->oob_poi, page);
1113}
1114
1115static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
1116 int page)
1117{
1118 read_oob_data(mtd, chip->oob_poi, page);
1119
1120 return 0;
1121}
1122
1123static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1124 uint8_t *buf, int oob_required, int page)
1125{
1126 unsigned int max_bitflips;
1127 struct denali_nand_info *denali = mtd_to_denali(mtd);
1128
1129 dma_addr_t addr = denali->buf.dma_buf;
1130 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
1131
1132 uint32_t irq_status = 0;
1133 uint32_t irq_mask = INTR_STATUS__ECC_TRANSACTION_DONE |
1134 INTR_STATUS__ECC_ERR;
1135 bool check_erased_page = false;
1136
1137 if (page != denali->page) {
1138 dev_err(denali->dev, "IN %s: page %d is not"
1139 " equal to denali->page %d, investigate!!",
1140 __func__, page, denali->page);
1141 BUG();
1142 }
1143
1144 setup_ecc_for_xfer(denali, true, false);
1145
1146 denali_enable_dma(denali, true);
1147 dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE);
1148
1149 clear_interrupts(denali);
1150 denali_setup_dma(denali, DENALI_READ);
1151
1152 /* wait for operation to complete */
1153 irq_status = wait_for_irq(denali, irq_mask);
1154
1155 dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE);
1156
1157 memcpy(buf, denali->buf.buf, mtd->writesize);
1158
1159 check_erased_page = handle_ecc(denali, buf, irq_status, &max_bitflips);
1160 denali_enable_dma(denali, false);
1161
1162 if (check_erased_page) {
1163 read_oob_data(&denali->mtd, chip->oob_poi, denali->page);
1164
1165 /* check ECC failures that may have occurred on erased pages */
1166 if (check_erased_page) {
1167 if (!is_erased(buf, denali->mtd.writesize))
1168 denali->mtd.ecc_stats.failed++;
1169 if (!is_erased(buf, denali->mtd.oobsize))
1170 denali->mtd.ecc_stats.failed++;
1171 }
1172 }
1173 return max_bitflips;
1174}
1175
1176static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1177 uint8_t *buf, int oob_required, int page)
1178{
1179 struct denali_nand_info *denali = mtd_to_denali(mtd);
1180
1181 dma_addr_t addr = denali->buf.dma_buf;
1182 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
1183
1184 uint32_t irq_status = 0;
1185 uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP;
1186
1187 if (page != denali->page) {
1188 dev_err(denali->dev, "IN %s: page %d is not"
1189 " equal to denali->page %d, investigate!!",
1190 __func__, page, denali->page);
1191 BUG();
1192 }
1193
1194 setup_ecc_for_xfer(denali, false, true);
1195 denali_enable_dma(denali, true);
1196
1197 dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE);
1198
1199 clear_interrupts(denali);
1200 denali_setup_dma(denali, DENALI_READ);
1201
1202 /* wait for operation to complete */
1203 irq_status = wait_for_irq(denali, irq_mask);
1204
1205 dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE);
1206
1207 denali_enable_dma(denali, false);
1208
1209 memcpy(buf, denali->buf.buf, mtd->writesize);
1210 memcpy(chip->oob_poi, denali->buf.buf + mtd->writesize, mtd->oobsize);
1211
1212 return 0;
1213}
1214
1215static uint8_t denali_read_byte(struct mtd_info *mtd)
1216{
1217 struct denali_nand_info *denali = mtd_to_denali(mtd);
1218 uint8_t result = 0xff;
1219
1220 if (denali->buf.head < denali->buf.tail)
1221 result = denali->buf.buf[denali->buf.head++];
1222
1223 return result;
1224}
1225
1226static void denali_select_chip(struct mtd_info *mtd, int chip)
1227{
1228 struct denali_nand_info *denali = mtd_to_denali(mtd);
1229
1230 spin_lock_irq(&denali->irq_lock);
1231 denali->flash_bank = chip;
1232 spin_unlock_irq(&denali->irq_lock);
1233}
1234
1235static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
1236{
1237 struct denali_nand_info *denali = mtd_to_denali(mtd);
1238 int status = denali->status;
1239 denali->status = 0;
1240
1241 return status;
1242}
1243
1244static void denali_erase(struct mtd_info *mtd, int page)
1245{
1246 struct denali_nand_info *denali = mtd_to_denali(mtd);
1247
1248 uint32_t cmd = 0x0, irq_status = 0;
1249
1250 /* clear interrupts */
1251 clear_interrupts(denali);
1252
1253 /* setup page read request for access type */
1254 cmd = MODE_10 | BANK(denali->flash_bank) | page;
1255 index_addr(denali, (uint32_t)cmd, 0x1);
1256
1257 /* wait for erase to complete or failure to occur */
1258 irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP |
1259 INTR_STATUS__ERASE_FAIL);
1260
1261 denali->status = (irq_status & INTR_STATUS__ERASE_FAIL) ?
1262 NAND_STATUS_FAIL : PASS;
1263}
1264
1265static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
1266 int page)
1267{
1268 struct denali_nand_info *denali = mtd_to_denali(mtd);
1269 uint32_t addr, id;
1270 int i;
1271
1272 switch (cmd) {
1273 case NAND_CMD_PAGEPROG:
1274 break;
1275 case NAND_CMD_STATUS:
1276 read_status(denali);
1277 break;
1278 case NAND_CMD_READID:
1279 case NAND_CMD_PARAM:
1280 reset_buf(denali);
1281 /*sometimes ManufactureId read from register is not right
1282 * e.g. some of Micron MT29F32G08QAA MLC NAND chips
1283 * So here we send READID cmd to NAND insteand
1284 * */
1285 addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);
1286 index_addr(denali, (uint32_t)addr | 0, 0x90);
1287 index_addr(denali, (uint32_t)addr | 1, 0);
1288 for (i = 0; i < 5; i++) {
1289 index_addr_read_data(denali,
1290 (uint32_t)addr | 2,
1291 &id);
1292 write_byte_to_buf(denali, id);
1293 }
1294 break;
1295 case NAND_CMD_READ0:
1296 case NAND_CMD_SEQIN:
1297 denali->page = page;
1298 break;
1299 case NAND_CMD_RESET:
1300 reset_bank(denali);
1301 break;
1302 case NAND_CMD_READOOB:
1303 /* TODO: Read OOB data */
1304 break;
1305 default:
1306 printk(KERN_ERR ": unsupported command"
1307 " received 0x%x\n", cmd);
1308 break;
1309 }
1310}
1311
1312/* stubs for ECC functions not used by the NAND core */
1313static int denali_ecc_calculate(struct mtd_info *mtd, const uint8_t *data,
1314 uint8_t *ecc_code)
1315{
1316 struct denali_nand_info *denali = mtd_to_denali(mtd);
1317 dev_err(denali->dev,
1318 "denali_ecc_calculate called unexpectedly\n");
1319 BUG();
1320 return -EIO;
1321}
1322
1323static int denali_ecc_correct(struct mtd_info *mtd, uint8_t *data,
1324 uint8_t *read_ecc, uint8_t *calc_ecc)
1325{
1326 struct denali_nand_info *denali = mtd_to_denali(mtd);
1327 dev_err(denali->dev,
1328 "denali_ecc_correct called unexpectedly\n");
1329 BUG();
1330 return -EIO;
1331}
1332
1333static void denali_ecc_hwctl(struct mtd_info *mtd, int mode)
1334{
1335 struct denali_nand_info *denali = mtd_to_denali(mtd);
1336 dev_err(denali->dev,
1337 "denali_ecc_hwctl called unexpectedly\n");
1338 BUG();
1339}
1340/* end NAND core entry points */
1341
1342/* Initialization code to bring the device up to a known good state */
1343static void denali_hw_init(struct denali_nand_info *denali)
1344{
1345 /* tell driver how many bit controller will skip before
1346 * writing ECC code in OOB, this register may be already
1347 * set by firmware. So we read this value out.
1348 * if this value is 0, just let it be.
1349 * */
1350 denali->bbtskipbytes = ioread32(denali->flash_reg +
1351 SPARE_AREA_SKIP_BYTES);
1352 detect_max_banks(denali);
1353 denali_nand_reset(denali);
1354 iowrite32(0x0F, denali->flash_reg + RB_PIN_ENABLED);
1355 iowrite32(CHIP_EN_DONT_CARE__FLAG,
1356 denali->flash_reg + CHIP_ENABLE_DONT_CARE);
1357
1358 iowrite32(0xffff, denali->flash_reg + SPARE_AREA_MARKER);
1359
1360 /* Should set value for these registers when init */
1361 iowrite32(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES);
1362 iowrite32(1, denali->flash_reg + ECC_ENABLE);
1363 denali_nand_timing_set(denali);
1364 denali_irq_init(denali);
1365}
1366
1367/* Althogh controller spec said SLC ECC is forceb to be 4bit,
1368 * but denali controller in MRST only support 15bit and 8bit ECC
1369 * correction
1370 * */
1371#define ECC_8BITS 14
1372static struct nand_ecclayout nand_8bit_oob = {
1373 .eccbytes = 14,
1374};
1375
1376#define ECC_15BITS 26
1377static struct nand_ecclayout nand_15bit_oob = {
1378 .eccbytes = 26,
1379};
1380
1381static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' };
1382static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' };
1383
1384static struct nand_bbt_descr bbt_main_descr = {
1385 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1386 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1387 .offs = 8,
1388 .len = 4,
1389 .veroffs = 12,
1390 .maxblocks = 4,
1391 .pattern = bbt_pattern,
1392};
1393
1394static struct nand_bbt_descr bbt_mirror_descr = {
1395 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1396 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1397 .offs = 8,
1398 .len = 4,
1399 .veroffs = 12,
1400 .maxblocks = 4,
1401 .pattern = mirror_pattern,
1402};
1403
1404/* initialize driver data structures */
1405void denali_drv_init(struct denali_nand_info *denali)
1406{
1407 denali->idx = 0;
1408
1409 /* setup interrupt handler */
1410 /* the completion object will be used to notify
1411 * the callee that the interrupt is done */
1412 init_completion(&denali->complete);
1413
1414 /* the spinlock will be used to synchronize the ISR
1415 * with any element that might be access shared
1416 * data (interrupt status) */
1417 spin_lock_init(&denali->irq_lock);
1418
1419 /* indicate that MTD has not selected a valid bank yet */
1420 denali->flash_bank = CHIP_SELECT_INVALID;
1421
1422 /* initialize our irq_status variable to indicate no interrupts */
1423 denali->irq_status = 0;
1424}
1425
1426/* driver entry point */
1427static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
1428{
1429 int ret = -ENODEV;
1430 resource_size_t csr_base, mem_base;
1431 unsigned long csr_len, mem_len;
1432 struct denali_nand_info *denali;
1433
1434 denali = kzalloc(sizeof(*denali), GFP_KERNEL);
1435 if (!denali)
1436 return -ENOMEM;
1437
1438 ret = pci_enable_device(dev);
1439 if (ret) {
1440 printk(KERN_ERR "Spectra: pci_enable_device failed.\n");
1441 goto failed_alloc_memery;
1442 }
1443
1444 if (id->driver_data == INTEL_CE4100) {
1445 /* Due to a silicon limitation, we can only support
1446 * ONFI timing mode 1 and below.
1447 */
1448 if (onfi_timing_mode < -1 || onfi_timing_mode > 1) {
1449 printk(KERN_ERR "Intel CE4100 only supports"
1450 " ONFI timing mode 1 or below\n");
1451 ret = -EINVAL;
1452 goto failed_enable_dev;
1453 }
1454 denali->platform = INTEL_CE4100;
1455 mem_base = pci_resource_start(dev, 0);
1456 mem_len = pci_resource_len(dev, 1);
1457 csr_base = pci_resource_start(dev, 1);
1458 csr_len = pci_resource_len(dev, 1);
1459 } else {
1460 denali->platform = INTEL_MRST;
1461 csr_base = pci_resource_start(dev, 0);
1462 csr_len = pci_resource_len(dev, 0);
1463 mem_base = pci_resource_start(dev, 1);
1464 mem_len = pci_resource_len(dev, 1);
1465 if (!mem_len) {
1466 mem_base = csr_base + csr_len;
1467 mem_len = csr_len;
1468 }
1469 }
1470
1471 /* Is 32-bit DMA supported? */
1472 ret = dma_set_mask(&dev->dev, DMA_BIT_MASK(32));
1473 if (ret) {
1474 printk(KERN_ERR "Spectra: no usable DMA configuration\n");
1475 goto failed_enable_dev;
1476 }
1477 denali->buf.dma_buf = dma_map_single(&dev->dev, denali->buf.buf,
1478 DENALI_BUF_SIZE,
1479 DMA_BIDIRECTIONAL);
1480
1481 if (dma_mapping_error(&dev->dev, denali->buf.dma_buf)) {
1482 dev_err(&dev->dev, "Spectra: failed to map DMA buffer\n");
1483 goto failed_enable_dev;
1484 }
1485
1486 pci_set_master(dev);
1487 denali->dev = &dev->dev;
1488 denali->mtd.dev.parent = &dev->dev;
1489
1490 ret = pci_request_regions(dev, DENALI_NAND_NAME);
1491 if (ret) {
1492 printk(KERN_ERR "Spectra: Unable to request memory regions\n");
1493 goto failed_dma_map;
1494 }
1495
1496 denali->flash_reg = ioremap_nocache(csr_base, csr_len);
1497 if (!denali->flash_reg) {
1498 printk(KERN_ERR "Spectra: Unable to remap memory region\n");
1499 ret = -ENOMEM;
1500 goto failed_req_regions;
1501 }
1502
1503 denali->flash_mem = ioremap_nocache(mem_base, mem_len);
1504 if (!denali->flash_mem) {
1505 printk(KERN_ERR "Spectra: ioremap_nocache failed!");
1506 ret = -ENOMEM;
1507 goto failed_remap_reg;
1508 }
1509
1510 denali_hw_init(denali);
1511 denali_drv_init(denali);
1512
1513 /* denali_isr register is done after all the hardware
1514 * initilization is finished*/
1515 if (request_irq(dev->irq, denali_isr, IRQF_SHARED,
1516 DENALI_NAND_NAME, denali)) {
1517 printk(KERN_ERR "Spectra: Unable to allocate IRQ\n");
1518 ret = -ENODEV;
1519 goto failed_remap_mem;
1520 }
1521
1522 /* now that our ISR is registered, we can enable interrupts */
1523 denali_set_intr_modes(denali, true);
1524
1525 pci_set_drvdata(dev, denali);
1526
1527 denali->mtd.name = "denali-nand";
1528 denali->mtd.owner = THIS_MODULE;
1529 denali->mtd.priv = &denali->nand;
1530
1531 /* register the driver with the NAND core subsystem */
1532 denali->nand.select_chip = denali_select_chip;
1533 denali->nand.cmdfunc = denali_cmdfunc;
1534 denali->nand.read_byte = denali_read_byte;
1535 denali->nand.waitfunc = denali_waitfunc;
1536
1537 /* scan for NAND devices attached to the controller
1538 * this is the first stage in a two step process to register
1539 * with the nand subsystem */
1540 if (nand_scan_ident(&denali->mtd, denali->max_banks, NULL)) {
1541 ret = -ENXIO;
1542 goto failed_req_irq;
1543 }
1544
1545 /* MTD supported page sizes vary by kernel. We validate our
1546 * kernel supports the device here.
1547 */
1548 if (denali->mtd.writesize > NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE) {
1549 ret = -ENODEV;
1550 printk(KERN_ERR "Spectra: device size not supported by this "
1551 "version of MTD.");
1552 goto failed_req_irq;
1553 }
1554
1555 /* support for multi nand
1556 * MTD known nothing about multi nand,
1557 * so we should tell it the real pagesize
1558 * and anything necessery
1559 */
1560 denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED);
1561 denali->nand.chipsize <<= (denali->devnum - 1);
1562 denali->nand.page_shift += (denali->devnum - 1);
1563 denali->nand.pagemask = (denali->nand.chipsize >>
1564 denali->nand.page_shift) - 1;
1565 denali->nand.bbt_erase_shift += (denali->devnum - 1);
1566 denali->nand.phys_erase_shift = denali->nand.bbt_erase_shift;
1567 denali->nand.chip_shift += (denali->devnum - 1);
1568 denali->mtd.writesize <<= (denali->devnum - 1);
1569 denali->mtd.oobsize <<= (denali->devnum - 1);
1570 denali->mtd.erasesize <<= (denali->devnum - 1);
1571 denali->mtd.size = denali->nand.numchips * denali->nand.chipsize;
1572 denali->bbtskipbytes *= denali->devnum;
1573
1574 /* second stage of the NAND scan
1575 * this stage requires information regarding ECC and
1576 * bad block management. */
1577
1578 /* Bad block management */
1579 denali->nand.bbt_td = &bbt_main_descr;
1580 denali->nand.bbt_md = &bbt_mirror_descr;
1581
1582 /* skip the scan for now until we have OOB read and write support */
1583 denali->nand.bbt_options |= NAND_BBT_USE_FLASH;
1584 denali->nand.options |= NAND_SKIP_BBTSCAN;
1585 denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
1586
1587 /* Denali Controller only support 15bit and 8bit ECC in MRST,
1588 * so just let controller do 15bit ECC for MLC and 8bit ECC for
1589 * SLC if possible.
1590 * */
1591 if (denali->nand.cellinfo & 0xc &&
1592 (denali->mtd.oobsize > (denali->bbtskipbytes +
1593 ECC_15BITS * (denali->mtd.writesize /
1594 ECC_SECTOR_SIZE)))) {
1595 /* if MLC OOB size is large enough, use 15bit ECC*/
1596 denali->nand.ecc.strength = 15;
1597 denali->nand.ecc.layout = &nand_15bit_oob;
1598 denali->nand.ecc.bytes = ECC_15BITS;
1599 iowrite32(15, denali->flash_reg + ECC_CORRECTION);
1600 } else if (denali->mtd.oobsize < (denali->bbtskipbytes +
1601 ECC_8BITS * (denali->mtd.writesize /
1602 ECC_SECTOR_SIZE))) {
1603 printk(KERN_ERR "Your NAND chip OOB is not large enough to"
1604 " contain 8bit ECC correction codes");
1605 goto failed_req_irq;
1606 } else {
1607 denali->nand.ecc.strength = 8;
1608 denali->nand.ecc.layout = &nand_8bit_oob;
1609 denali->nand.ecc.bytes = ECC_8BITS;
1610 iowrite32(8, denali->flash_reg + ECC_CORRECTION);
1611 }
1612
1613 denali->nand.ecc.bytes *= denali->devnum;
1614 denali->nand.ecc.strength *= denali->devnum;
1615 denali->nand.ecc.layout->eccbytes *=
1616 denali->mtd.writesize / ECC_SECTOR_SIZE;
1617 denali->nand.ecc.layout->oobfree[0].offset =
1618 denali->bbtskipbytes + denali->nand.ecc.layout->eccbytes;
1619 denali->nand.ecc.layout->oobfree[0].length =
1620 denali->mtd.oobsize - denali->nand.ecc.layout->eccbytes -
1621 denali->bbtskipbytes;
1622
1623 /* Let driver know the total blocks number and
1624 * how many blocks contained by each nand chip.
1625 * blksperchip will help driver to know how many
1626 * blocks is taken by FW.
1627 * */
1628 denali->totalblks = denali->mtd.size >>
1629 denali->nand.phys_erase_shift;
1630 denali->blksperchip = denali->totalblks / denali->nand.numchips;
1631
1632 /* These functions are required by the NAND core framework, otherwise,
1633 * the NAND core will assert. However, we don't need them, so we'll stub
1634 * them out. */
1635 denali->nand.ecc.calculate = denali_ecc_calculate;
1636 denali->nand.ecc.correct = denali_ecc_correct;
1637 denali->nand.ecc.hwctl = denali_ecc_hwctl;
1638
1639 /* override the default read operations */
1640 denali->nand.ecc.size = ECC_SECTOR_SIZE * denali->devnum;
1641 denali->nand.ecc.read_page = denali_read_page;
1642 denali->nand.ecc.read_page_raw = denali_read_page_raw;
1643 denali->nand.ecc.write_page = denali_write_page;
1644 denali->nand.ecc.write_page_raw = denali_write_page_raw;
1645 denali->nand.ecc.read_oob = denali_read_oob;
1646 denali->nand.ecc.write_oob = denali_write_oob;
1647 denali->nand.erase_cmd = denali_erase;
1648
1649 if (nand_scan_tail(&denali->mtd)) {
1650 ret = -ENXIO;
1651 goto failed_req_irq;
1652 }
1653
1654 ret = mtd_device_register(&denali->mtd, NULL, 0);
1655 if (ret) {
1656 dev_err(&dev->dev, "Spectra: Failed to register MTD: %d\n",
1657 ret);
1658 goto failed_req_irq;
1659 }
1660 return 0;
1661
1662failed_req_irq:
1663 denali_irq_cleanup(dev->irq, denali);
1664failed_remap_mem:
1665 iounmap(denali->flash_mem);
1666failed_remap_reg:
1667 iounmap(denali->flash_reg);
1668failed_req_regions:
1669 pci_release_regions(dev);
1670failed_dma_map:
1671 dma_unmap_single(&dev->dev, denali->buf.dma_buf, DENALI_BUF_SIZE,
1672 DMA_BIDIRECTIONAL);
1673failed_enable_dev:
1674 pci_disable_device(dev);
1675failed_alloc_memery:
1676 kfree(denali);
1677 return ret;
1678}
1679
1680/* driver exit point */
1681static void denali_pci_remove(struct pci_dev *dev)
1682{
1683 struct denali_nand_info *denali = pci_get_drvdata(dev);
1684
1685 nand_release(&denali->mtd);
1686
1687 denali_irq_cleanup(dev->irq, denali);
1688
1689 iounmap(denali->flash_reg);
1690 iounmap(denali->flash_mem);
1691 pci_release_regions(dev);
1692 pci_disable_device(dev);
1693 dma_unmap_single(&dev->dev, denali->buf.dma_buf, DENALI_BUF_SIZE,
1694 DMA_BIDIRECTIONAL);
1695 pci_set_drvdata(dev, NULL);
1696 kfree(denali);
1697}
1698
1699MODULE_DEVICE_TABLE(pci, denali_pci_ids);
1700
1701static struct pci_driver denali_pci_driver = {
1702 .name = DENALI_NAND_NAME,
1703 .id_table = denali_pci_ids,
1704 .probe = denali_pci_probe,
1705 .remove = denali_pci_remove,
1706};
1707
1708module_pci_driver(denali_pci_driver);