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1/*
2 * Copyright (C) 2003 Rick Bronson
3 *
4 * Derived from drivers/mtd/nand/autcpu12.c
5 * Copyright (c) 2001 Thomas Gleixner (gleixner@autronix.de)
6 *
7 * Derived from drivers/mtd/spia.c
8 * Copyright (C) 2000 Steven J. Hill (sjhill@cotw.com)
9 *
10 *
11 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
12 * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright (C) 2007
13 *
14 * Derived from Das U-Boot source code
15 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
16 * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
17 *
18 *
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License version 2 as
21 * published by the Free Software Foundation.
22 *
23 */
24
25#include <linux/dma-mapping.h>
26#include <linux/slab.h>
27#include <linux/module.h>
28#include <linux/moduleparam.h>
29#include <linux/platform_device.h>
30#include <linux/of.h>
31#include <linux/of_device.h>
32#include <linux/of_gpio.h>
33#include <linux/of_mtd.h>
34#include <linux/mtd/mtd.h>
35#include <linux/mtd/nand.h>
36#include <linux/mtd/partitions.h>
37
38#include <linux/dmaengine.h>
39#include <linux/gpio.h>
40#include <linux/io.h>
41#include <linux/platform_data/atmel.h>
42
43#include <mach/cpu.h>
44
45static int use_dma = 1;
46module_param(use_dma, int, 0);
47
48static int on_flash_bbt = 0;
49module_param(on_flash_bbt, int, 0);
50
51/* Register access macros */
52#define ecc_readl(add, reg) \
53 __raw_readl(add + ATMEL_ECC_##reg)
54#define ecc_writel(add, reg, value) \
55 __raw_writel((value), add + ATMEL_ECC_##reg)
56
57#include "atmel_nand_ecc.h" /* Hardware ECC registers */
58
59/* oob layout for large page size
60 * bad block info is on bytes 0 and 1
61 * the bytes have to be consecutives to avoid
62 * several NAND_CMD_RNDOUT during read
63 */
64static struct nand_ecclayout atmel_oobinfo_large = {
65 .eccbytes = 4,
66 .eccpos = {60, 61, 62, 63},
67 .oobfree = {
68 {2, 58}
69 },
70};
71
72/* oob layout for small page size
73 * bad block info is on bytes 4 and 5
74 * the bytes have to be consecutives to avoid
75 * several NAND_CMD_RNDOUT during read
76 */
77static struct nand_ecclayout atmel_oobinfo_small = {
78 .eccbytes = 4,
79 .eccpos = {0, 1, 2, 3},
80 .oobfree = {
81 {6, 10}
82 },
83};
84
85struct atmel_nand_host {
86 struct nand_chip nand_chip;
87 struct mtd_info mtd;
88 void __iomem *io_base;
89 dma_addr_t io_phys;
90 struct atmel_nand_data board;
91 struct device *dev;
92 void __iomem *ecc;
93
94 struct completion comp;
95 struct dma_chan *dma_chan;
96};
97
98static int cpu_has_dma(void)
99{
100 return cpu_is_at91sam9rl() || cpu_is_at91sam9g45();
101}
102
103/*
104 * Enable NAND.
105 */
106static void atmel_nand_enable(struct atmel_nand_host *host)
107{
108 if (gpio_is_valid(host->board.enable_pin))
109 gpio_set_value(host->board.enable_pin, 0);
110}
111
112/*
113 * Disable NAND.
114 */
115static void atmel_nand_disable(struct atmel_nand_host *host)
116{
117 if (gpio_is_valid(host->board.enable_pin))
118 gpio_set_value(host->board.enable_pin, 1);
119}
120
121/*
122 * Hardware specific access to control-lines
123 */
124static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
125{
126 struct nand_chip *nand_chip = mtd->priv;
127 struct atmel_nand_host *host = nand_chip->priv;
128
129 if (ctrl & NAND_CTRL_CHANGE) {
130 if (ctrl & NAND_NCE)
131 atmel_nand_enable(host);
132 else
133 atmel_nand_disable(host);
134 }
135 if (cmd == NAND_CMD_NONE)
136 return;
137
138 if (ctrl & NAND_CLE)
139 writeb(cmd, host->io_base + (1 << host->board.cle));
140 else
141 writeb(cmd, host->io_base + (1 << host->board.ale));
142}
143
144/*
145 * Read the Device Ready pin.
146 */
147static int atmel_nand_device_ready(struct mtd_info *mtd)
148{
149 struct nand_chip *nand_chip = mtd->priv;
150 struct atmel_nand_host *host = nand_chip->priv;
151
152 return gpio_get_value(host->board.rdy_pin) ^
153 !!host->board.rdy_pin_active_low;
154}
155
156/*
157 * Minimal-overhead PIO for data access.
158 */
159static void atmel_read_buf8(struct mtd_info *mtd, u8 *buf, int len)
160{
161 struct nand_chip *nand_chip = mtd->priv;
162
163 __raw_readsb(nand_chip->IO_ADDR_R, buf, len);
164}
165
166static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len)
167{
168 struct nand_chip *nand_chip = mtd->priv;
169
170 __raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2);
171}
172
173static void atmel_write_buf8(struct mtd_info *mtd, const u8 *buf, int len)
174{
175 struct nand_chip *nand_chip = mtd->priv;
176
177 __raw_writesb(nand_chip->IO_ADDR_W, buf, len);
178}
179
180static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len)
181{
182 struct nand_chip *nand_chip = mtd->priv;
183
184 __raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2);
185}
186
187static void dma_complete_func(void *completion)
188{
189 complete(completion);
190}
191
192static int atmel_nand_dma_op(struct mtd_info *mtd, void *buf, int len,
193 int is_read)
194{
195 struct dma_device *dma_dev;
196 enum dma_ctrl_flags flags;
197 dma_addr_t dma_src_addr, dma_dst_addr, phys_addr;
198 struct dma_async_tx_descriptor *tx = NULL;
199 dma_cookie_t cookie;
200 struct nand_chip *chip = mtd->priv;
201 struct atmel_nand_host *host = chip->priv;
202 void *p = buf;
203 int err = -EIO;
204 enum dma_data_direction dir = is_read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
205
206 if (buf >= high_memory)
207 goto err_buf;
208
209 dma_dev = host->dma_chan->device;
210
211 flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT | DMA_COMPL_SKIP_SRC_UNMAP |
212 DMA_COMPL_SKIP_DEST_UNMAP;
213
214 phys_addr = dma_map_single(dma_dev->dev, p, len, dir);
215 if (dma_mapping_error(dma_dev->dev, phys_addr)) {
216 dev_err(host->dev, "Failed to dma_map_single\n");
217 goto err_buf;
218 }
219
220 if (is_read) {
221 dma_src_addr = host->io_phys;
222 dma_dst_addr = phys_addr;
223 } else {
224 dma_src_addr = phys_addr;
225 dma_dst_addr = host->io_phys;
226 }
227
228 tx = dma_dev->device_prep_dma_memcpy(host->dma_chan, dma_dst_addr,
229 dma_src_addr, len, flags);
230 if (!tx) {
231 dev_err(host->dev, "Failed to prepare DMA memcpy\n");
232 goto err_dma;
233 }
234
235 init_completion(&host->comp);
236 tx->callback = dma_complete_func;
237 tx->callback_param = &host->comp;
238
239 cookie = tx->tx_submit(tx);
240 if (dma_submit_error(cookie)) {
241 dev_err(host->dev, "Failed to do DMA tx_submit\n");
242 goto err_dma;
243 }
244
245 dma_async_issue_pending(host->dma_chan);
246 wait_for_completion(&host->comp);
247
248 err = 0;
249
250err_dma:
251 dma_unmap_single(dma_dev->dev, phys_addr, len, dir);
252err_buf:
253 if (err != 0)
254 dev_warn(host->dev, "Fall back to CPU I/O\n");
255 return err;
256}
257
258static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len)
259{
260 struct nand_chip *chip = mtd->priv;
261 struct atmel_nand_host *host = chip->priv;
262
263 if (use_dma && len > mtd->oobsize)
264 /* only use DMA for bigger than oob size: better performances */
265 if (atmel_nand_dma_op(mtd, buf, len, 1) == 0)
266 return;
267
268 if (host->board.bus_width_16)
269 atmel_read_buf16(mtd, buf, len);
270 else
271 atmel_read_buf8(mtd, buf, len);
272}
273
274static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
275{
276 struct nand_chip *chip = mtd->priv;
277 struct atmel_nand_host *host = chip->priv;
278
279 if (use_dma && len > mtd->oobsize)
280 /* only use DMA for bigger than oob size: better performances */
281 if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) == 0)
282 return;
283
284 if (host->board.bus_width_16)
285 atmel_write_buf16(mtd, buf, len);
286 else
287 atmel_write_buf8(mtd, buf, len);
288}
289
290/*
291 * Calculate HW ECC
292 *
293 * function called after a write
294 *
295 * mtd: MTD block structure
296 * dat: raw data (unused)
297 * ecc_code: buffer for ECC
298 */
299static int atmel_nand_calculate(struct mtd_info *mtd,
300 const u_char *dat, unsigned char *ecc_code)
301{
302 struct nand_chip *nand_chip = mtd->priv;
303 struct atmel_nand_host *host = nand_chip->priv;
304 unsigned int ecc_value;
305
306 /* get the first 2 ECC bytes */
307 ecc_value = ecc_readl(host->ecc, PR);
308
309 ecc_code[0] = ecc_value & 0xFF;
310 ecc_code[1] = (ecc_value >> 8) & 0xFF;
311
312 /* get the last 2 ECC bytes */
313 ecc_value = ecc_readl(host->ecc, NPR) & ATMEL_ECC_NPARITY;
314
315 ecc_code[2] = ecc_value & 0xFF;
316 ecc_code[3] = (ecc_value >> 8) & 0xFF;
317
318 return 0;
319}
320
321/*
322 * HW ECC read page function
323 *
324 * mtd: mtd info structure
325 * chip: nand chip info structure
326 * buf: buffer to store read data
327 * oob_required: caller expects OOB data read to chip->oob_poi
328 */
329static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
330 uint8_t *buf, int oob_required, int page)
331{
332 int eccsize = chip->ecc.size;
333 int eccbytes = chip->ecc.bytes;
334 uint32_t *eccpos = chip->ecc.layout->eccpos;
335 uint8_t *p = buf;
336 uint8_t *oob = chip->oob_poi;
337 uint8_t *ecc_pos;
338 int stat;
339 unsigned int max_bitflips = 0;
340
341 /*
342 * Errata: ALE is incorrectly wired up to the ECC controller
343 * on the AP7000, so it will include the address cycles in the
344 * ECC calculation.
345 *
346 * Workaround: Reset the parity registers before reading the
347 * actual data.
348 */
349 if (cpu_is_at32ap7000()) {
350 struct atmel_nand_host *host = chip->priv;
351 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
352 }
353
354 /* read the page */
355 chip->read_buf(mtd, p, eccsize);
356
357 /* move to ECC position if needed */
358 if (eccpos[0] != 0) {
359 /* This only works on large pages
360 * because the ECC controller waits for
361 * NAND_CMD_RNDOUTSTART after the
362 * NAND_CMD_RNDOUT.
363 * anyway, for small pages, the eccpos[0] == 0
364 */
365 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
366 mtd->writesize + eccpos[0], -1);
367 }
368
369 /* the ECC controller needs to read the ECC just after the data */
370 ecc_pos = oob + eccpos[0];
371 chip->read_buf(mtd, ecc_pos, eccbytes);
372
373 /* check if there's an error */
374 stat = chip->ecc.correct(mtd, p, oob, NULL);
375
376 if (stat < 0) {
377 mtd->ecc_stats.failed++;
378 } else {
379 mtd->ecc_stats.corrected += stat;
380 max_bitflips = max_t(unsigned int, max_bitflips, stat);
381 }
382
383 /* get back to oob start (end of page) */
384 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
385
386 /* read the oob */
387 chip->read_buf(mtd, oob, mtd->oobsize);
388
389 return max_bitflips;
390}
391
392/*
393 * HW ECC Correction
394 *
395 * function called after a read
396 *
397 * mtd: MTD block structure
398 * dat: raw data read from the chip
399 * read_ecc: ECC from the chip (unused)
400 * isnull: unused
401 *
402 * Detect and correct a 1 bit error for a page
403 */
404static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
405 u_char *read_ecc, u_char *isnull)
406{
407 struct nand_chip *nand_chip = mtd->priv;
408 struct atmel_nand_host *host = nand_chip->priv;
409 unsigned int ecc_status;
410 unsigned int ecc_word, ecc_bit;
411
412 /* get the status from the Status Register */
413 ecc_status = ecc_readl(host->ecc, SR);
414
415 /* if there's no error */
416 if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
417 return 0;
418
419 /* get error bit offset (4 bits) */
420 ecc_bit = ecc_readl(host->ecc, PR) & ATMEL_ECC_BITADDR;
421 /* get word address (12 bits) */
422 ecc_word = ecc_readl(host->ecc, PR) & ATMEL_ECC_WORDADDR;
423 ecc_word >>= 4;
424
425 /* if there are multiple errors */
426 if (ecc_status & ATMEL_ECC_MULERR) {
427 /* check if it is a freshly erased block
428 * (filled with 0xff) */
429 if ((ecc_bit == ATMEL_ECC_BITADDR)
430 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
431 /* the block has just been erased, return OK */
432 return 0;
433 }
434 /* it doesn't seems to be a freshly
435 * erased block.
436 * We can't correct so many errors */
437 dev_dbg(host->dev, "atmel_nand : multiple errors detected."
438 " Unable to correct.\n");
439 return -EIO;
440 }
441
442 /* if there's a single bit error : we can correct it */
443 if (ecc_status & ATMEL_ECC_ECCERR) {
444 /* there's nothing much to do here.
445 * the bit error is on the ECC itself.
446 */
447 dev_dbg(host->dev, "atmel_nand : one bit error on ECC code."
448 " Nothing to correct\n");
449 return 0;
450 }
451
452 dev_dbg(host->dev, "atmel_nand : one bit error on data."
453 " (word offset in the page :"
454 " 0x%x bit offset : 0x%x)\n",
455 ecc_word, ecc_bit);
456 /* correct the error */
457 if (nand_chip->options & NAND_BUSWIDTH_16) {
458 /* 16 bits words */
459 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
460 } else {
461 /* 8 bits words */
462 dat[ecc_word] ^= (1 << ecc_bit);
463 }
464 dev_dbg(host->dev, "atmel_nand : error corrected\n");
465 return 1;
466}
467
468/*
469 * Enable HW ECC : unused on most chips
470 */
471static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
472{
473 if (cpu_is_at32ap7000()) {
474 struct nand_chip *nand_chip = mtd->priv;
475 struct atmel_nand_host *host = nand_chip->priv;
476 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
477 }
478}
479
480#if defined(CONFIG_OF)
481static int __devinit atmel_of_init_port(struct atmel_nand_host *host,
482 struct device_node *np)
483{
484 u32 val;
485 int ecc_mode;
486 struct atmel_nand_data *board = &host->board;
487 enum of_gpio_flags flags;
488
489 if (of_property_read_u32(np, "atmel,nand-addr-offset", &val) == 0) {
490 if (val >= 32) {
491 dev_err(host->dev, "invalid addr-offset %u\n", val);
492 return -EINVAL;
493 }
494 board->ale = val;
495 }
496
497 if (of_property_read_u32(np, "atmel,nand-cmd-offset", &val) == 0) {
498 if (val >= 32) {
499 dev_err(host->dev, "invalid cmd-offset %u\n", val);
500 return -EINVAL;
501 }
502 board->cle = val;
503 }
504
505 ecc_mode = of_get_nand_ecc_mode(np);
506
507 board->ecc_mode = ecc_mode < 0 ? NAND_ECC_SOFT : ecc_mode;
508
509 board->on_flash_bbt = of_get_nand_on_flash_bbt(np);
510
511 if (of_get_nand_bus_width(np) == 16)
512 board->bus_width_16 = 1;
513
514 board->rdy_pin = of_get_gpio_flags(np, 0, &flags);
515 board->rdy_pin_active_low = (flags == OF_GPIO_ACTIVE_LOW);
516
517 board->enable_pin = of_get_gpio(np, 1);
518 board->det_pin = of_get_gpio(np, 2);
519
520 return 0;
521}
522#else
523static int __devinit atmel_of_init_port(struct atmel_nand_host *host,
524 struct device_node *np)
525{
526 return -EINVAL;
527}
528#endif
529
530/*
531 * Probe for the NAND device.
532 */
533static int __init atmel_nand_probe(struct platform_device *pdev)
534{
535 struct atmel_nand_host *host;
536 struct mtd_info *mtd;
537 struct nand_chip *nand_chip;
538 struct resource *regs;
539 struct resource *mem;
540 struct mtd_part_parser_data ppdata = {};
541 int res;
542
543 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
544 if (!mem) {
545 printk(KERN_ERR "atmel_nand: can't get I/O resource mem\n");
546 return -ENXIO;
547 }
548
549 /* Allocate memory for the device structure (and zero it) */
550 host = kzalloc(sizeof(struct atmel_nand_host), GFP_KERNEL);
551 if (!host) {
552 printk(KERN_ERR "atmel_nand: failed to allocate device structure.\n");
553 return -ENOMEM;
554 }
555
556 host->io_phys = (dma_addr_t)mem->start;
557
558 host->io_base = ioremap(mem->start, resource_size(mem));
559 if (host->io_base == NULL) {
560 printk(KERN_ERR "atmel_nand: ioremap failed\n");
561 res = -EIO;
562 goto err_nand_ioremap;
563 }
564
565 mtd = &host->mtd;
566 nand_chip = &host->nand_chip;
567 host->dev = &pdev->dev;
568 if (pdev->dev.of_node) {
569 res = atmel_of_init_port(host, pdev->dev.of_node);
570 if (res)
571 goto err_nand_ioremap;
572 } else {
573 memcpy(&host->board, pdev->dev.platform_data,
574 sizeof(struct atmel_nand_data));
575 }
576
577 nand_chip->priv = host; /* link the private data structures */
578 mtd->priv = nand_chip;
579 mtd->owner = THIS_MODULE;
580
581 /* Set address of NAND IO lines */
582 nand_chip->IO_ADDR_R = host->io_base;
583 nand_chip->IO_ADDR_W = host->io_base;
584 nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
585
586 if (gpio_is_valid(host->board.rdy_pin))
587 nand_chip->dev_ready = atmel_nand_device_ready;
588
589 nand_chip->ecc.mode = host->board.ecc_mode;
590
591 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
592 if (!regs && nand_chip->ecc.mode == NAND_ECC_HW) {
593 printk(KERN_ERR "atmel_nand: can't get I/O resource "
594 "regs\nFalling back on software ECC\n");
595 nand_chip->ecc.mode = NAND_ECC_SOFT;
596 }
597
598 if (nand_chip->ecc.mode == NAND_ECC_HW) {
599 host->ecc = ioremap(regs->start, resource_size(regs));
600 if (host->ecc == NULL) {
601 printk(KERN_ERR "atmel_nand: ioremap failed\n");
602 res = -EIO;
603 goto err_ecc_ioremap;
604 }
605 nand_chip->ecc.calculate = atmel_nand_calculate;
606 nand_chip->ecc.correct = atmel_nand_correct;
607 nand_chip->ecc.hwctl = atmel_nand_hwctl;
608 nand_chip->ecc.read_page = atmel_nand_read_page;
609 nand_chip->ecc.bytes = 4;
610 nand_chip->ecc.strength = 1;
611 }
612
613 nand_chip->chip_delay = 20; /* 20us command delay time */
614
615 if (host->board.bus_width_16) /* 16-bit bus width */
616 nand_chip->options |= NAND_BUSWIDTH_16;
617
618 nand_chip->read_buf = atmel_read_buf;
619 nand_chip->write_buf = atmel_write_buf;
620
621 platform_set_drvdata(pdev, host);
622 atmel_nand_enable(host);
623
624 if (gpio_is_valid(host->board.det_pin)) {
625 if (gpio_get_value(host->board.det_pin)) {
626 printk(KERN_INFO "No SmartMedia card inserted.\n");
627 res = -ENXIO;
628 goto err_no_card;
629 }
630 }
631
632 if (host->board.on_flash_bbt || on_flash_bbt) {
633 printk(KERN_INFO "atmel_nand: Use On Flash BBT\n");
634 nand_chip->bbt_options |= NAND_BBT_USE_FLASH;
635 }
636
637 if (!cpu_has_dma())
638 use_dma = 0;
639
640 if (use_dma) {
641 dma_cap_mask_t mask;
642
643 dma_cap_zero(mask);
644 dma_cap_set(DMA_MEMCPY, mask);
645 host->dma_chan = dma_request_channel(mask, NULL, NULL);
646 if (!host->dma_chan) {
647 dev_err(host->dev, "Failed to request DMA channel\n");
648 use_dma = 0;
649 }
650 }
651 if (use_dma)
652 dev_info(host->dev, "Using %s for DMA transfers.\n",
653 dma_chan_name(host->dma_chan));
654 else
655 dev_info(host->dev, "No DMA support for NAND access.\n");
656
657 /* first scan to find the device and get the page size */
658 if (nand_scan_ident(mtd, 1, NULL)) {
659 res = -ENXIO;
660 goto err_scan_ident;
661 }
662
663 if (nand_chip->ecc.mode == NAND_ECC_HW) {
664 /* ECC is calculated for the whole page (1 step) */
665 nand_chip->ecc.size = mtd->writesize;
666
667 /* set ECC page size and oob layout */
668 switch (mtd->writesize) {
669 case 512:
670 nand_chip->ecc.layout = &atmel_oobinfo_small;
671 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
672 break;
673 case 1024:
674 nand_chip->ecc.layout = &atmel_oobinfo_large;
675 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
676 break;
677 case 2048:
678 nand_chip->ecc.layout = &atmel_oobinfo_large;
679 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
680 break;
681 case 4096:
682 nand_chip->ecc.layout = &atmel_oobinfo_large;
683 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
684 break;
685 default:
686 /* page size not handled by HW ECC */
687 /* switching back to soft ECC */
688 nand_chip->ecc.mode = NAND_ECC_SOFT;
689 nand_chip->ecc.calculate = NULL;
690 nand_chip->ecc.correct = NULL;
691 nand_chip->ecc.hwctl = NULL;
692 nand_chip->ecc.read_page = NULL;
693 nand_chip->ecc.postpad = 0;
694 nand_chip->ecc.prepad = 0;
695 nand_chip->ecc.bytes = 0;
696 break;
697 }
698 }
699
700 /* second phase scan */
701 if (nand_scan_tail(mtd)) {
702 res = -ENXIO;
703 goto err_scan_tail;
704 }
705
706 mtd->name = "atmel_nand";
707 ppdata.of_node = pdev->dev.of_node;
708 res = mtd_device_parse_register(mtd, NULL, &ppdata,
709 host->board.parts, host->board.num_parts);
710 if (!res)
711 return res;
712
713err_scan_tail:
714err_scan_ident:
715err_no_card:
716 atmel_nand_disable(host);
717 platform_set_drvdata(pdev, NULL);
718 if (host->dma_chan)
719 dma_release_channel(host->dma_chan);
720 if (host->ecc)
721 iounmap(host->ecc);
722err_ecc_ioremap:
723 iounmap(host->io_base);
724err_nand_ioremap:
725 kfree(host);
726 return res;
727}
728
729/*
730 * Remove a NAND device.
731 */
732static int __exit atmel_nand_remove(struct platform_device *pdev)
733{
734 struct atmel_nand_host *host = platform_get_drvdata(pdev);
735 struct mtd_info *mtd = &host->mtd;
736
737 nand_release(mtd);
738
739 atmel_nand_disable(host);
740
741 if (host->ecc)
742 iounmap(host->ecc);
743
744 if (host->dma_chan)
745 dma_release_channel(host->dma_chan);
746
747 iounmap(host->io_base);
748 kfree(host);
749
750 return 0;
751}
752
753#if defined(CONFIG_OF)
754static const struct of_device_id atmel_nand_dt_ids[] = {
755 { .compatible = "atmel,at91rm9200-nand" },
756 { /* sentinel */ }
757};
758
759MODULE_DEVICE_TABLE(of, atmel_nand_dt_ids);
760#endif
761
762static struct platform_driver atmel_nand_driver = {
763 .remove = __exit_p(atmel_nand_remove),
764 .driver = {
765 .name = "atmel_nand",
766 .owner = THIS_MODULE,
767 .of_match_table = of_match_ptr(atmel_nand_dt_ids),
768 },
769};
770
771static int __init atmel_nand_init(void)
772{
773 return platform_driver_probe(&atmel_nand_driver, atmel_nand_probe);
774}
775
776
777static void __exit atmel_nand_exit(void)
778{
779 platform_driver_unregister(&atmel_nand_driver);
780}
781
782
783module_init(atmel_nand_init);
784module_exit(atmel_nand_exit);
785
786MODULE_LICENSE("GPL");
787MODULE_AUTHOR("Rick Bronson");
788MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32");
789MODULE_ALIAS("platform:atmel_nand");