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1/*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#ifndef _CX23885_REG_H_
23#define _CX23885_REG_H_
24
25/*
26Address Map
270x00000000 -> 0x00009000 TX SRAM (Fifos)
280x00010000 -> 0x00013c00 RX SRAM CMDS + CDT
29
30EACH CMDS struct is 0x80 bytes long
31
32DMAx_PTR1 = 0x03040 address of first cluster
33DMAx_PTR2 = 0x10600 address of the CDT
34DMAx_CNT1 = cluster size in (bytes >> 4) -1
35DMAx_CNT2 = total cdt size for all entries >> 3
36
37Cluster Descriptor entry = 4 DWORDS
38 DWORD 0 -> ptr to cluster
39 DWORD 1 Reserved
40 DWORD 2 Reserved
41 DWORD 3 Reserved
42
43Channel manager Data Structure entry = 20 DWORD
44 0 IntialProgramCounterLow
45 1 IntialProgramCounterHigh
46 2 ClusterDescriptorTableBase
47 3 ClusterDescriptorTableSize
48 4 InstructionQueueBase
49 5 InstructionQueueSize
50... Reserved
51 19 Reserved
52*/
53
54/* Risc Instructions */
55#define RISC_CNT_INC 0x00010000
56#define RISC_CNT_RESET 0x00030000
57#define RISC_IRQ1 0x01000000
58#define RISC_IRQ2 0x02000000
59#define RISC_EOL 0x04000000
60#define RISC_SOL 0x08000000
61#define RISC_WRITE 0x10000000
62#define RISC_SKIP 0x20000000
63#define RISC_JUMP 0x70000000
64#define RISC_SYNC 0x80000000
65#define RISC_RESYNC 0x80008000
66#define RISC_READ 0x90000000
67#define RISC_WRITERM 0xB0000000
68#define RISC_WRITECM 0xC0000000
69#define RISC_WRITECR 0xD0000000
70#define RISC_WRITEC 0x50000000
71#define RISC_READC 0xA0000000
72
73
74/* Audio and Video Core */
75#define HOST_REG1 0x00000000
76#define HOST_REG2 0x00000001
77#define HOST_REG3 0x00000002
78
79/* Chip Configuration Registers */
80#define CHIP_CTRL 0x00000100
81#define AFE_CTRL 0x00000104
82#define VID_PLL_INT_POST 0x00000108
83#define VID_PLL_FRAC 0x0000010C
84#define AUX_PLL_INT_POST 0x00000110
85#define AUX_PLL_FRAC 0x00000114
86#define SYS_PLL_INT_POST 0x00000118
87#define SYS_PLL_FRAC 0x0000011C
88#define PIN_CTRL 0x00000120
89#define AUD_IO_CTRL 0x00000124
90#define AUD_LOCK1 0x00000128
91#define AUD_LOCK2 0x0000012C
92#define POWER_CTRL 0x00000130
93#define AFE_DIAG_CTRL1 0x00000134
94#define AFE_DIAG_CTRL3 0x0000013C
95#define PLL_DIAG_CTRL 0x00000140
96#define AFE_CLK_OUT_CTRL 0x00000144
97#define DLL1_DIAG_CTRL 0x0000015C
98
99/* GPIO[23:19] Output Enable */
100#define GPIO2_OUT_EN_REG 0x00000160
101/* GPIO[23:19] Data Registers */
102#define GPIO2 0x00000164
103
104#define IFADC_CTRL 0x00000180
105
106/* Infrared Remote Registers */
107#define IR_CNTRL_REG 0x00000200
108#define IR_TXCLK_REG 0x00000204
109#define IR_RXCLK_REG 0x00000208
110#define IR_CDUTY_REG 0x0000020C
111#define IR_STAT_REG 0x00000210
112#define IR_IRQEN_REG 0x00000214
113#define IR_FILTR_REG 0x00000218
114#define IR_FIFO_REG 0x0000023C
115
116/* Video Decoder Registers */
117#define MODE_CTRL 0x00000400
118#define OUT_CTRL1 0x00000404
119#define OUT_CTRL2 0x00000408
120#define GEN_STAT 0x0000040C
121#define INT_STAT_MASK 0x00000410
122#define LUMA_CTRL 0x00000414
123#define HSCALE_CTRL 0x00000418
124#define VSCALE_CTRL 0x0000041C
125#define CHROMA_CTRL 0x00000420
126#define VBI_LINE_CTRL1 0x00000424
127#define VBI_LINE_CTRL2 0x00000428
128#define VBI_LINE_CTRL3 0x0000042C
129#define VBI_LINE_CTRL4 0x00000430
130#define VBI_LINE_CTRL5 0x00000434
131#define VBI_FC_CFG 0x00000438
132#define VBI_MISC_CFG1 0x0000043C
133#define VBI_MISC_CFG2 0x00000440
134#define VBI_PAY1 0x00000444
135#define VBI_PAY2 0x00000448
136#define VBI_CUST1_CFG1 0x0000044C
137#define VBI_CUST1_CFG2 0x00000450
138#define VBI_CUST1_CFG3 0x00000454
139#define VBI_CUST2_CFG1 0x00000458
140#define VBI_CUST2_CFG2 0x0000045C
141#define VBI_CUST2_CFG3 0x00000460
142#define VBI_CUST3_CFG1 0x00000464
143#define VBI_CUST3_CFG2 0x00000468
144#define VBI_CUST3_CFG3 0x0000046C
145#define HORIZ_TIM_CTRL 0x00000470
146#define VERT_TIM_CTRL 0x00000474
147#define SRC_COMB_CFG 0x00000478
148#define CHROMA_VBIOFF_CFG 0x0000047C
149#define FIELD_COUNT 0x00000480
150#define MISC_TIM_CTRL 0x00000484
151#define DFE_CTRL1 0x00000488
152#define DFE_CTRL2 0x0000048C
153#define DFE_CTRL3 0x00000490
154#define PLL_CTRL 0x00000494
155#define HTL_CTRL 0x00000498
156#define COMB_CTRL 0x0000049C
157#define CRUSH_CTRL 0x000004A0
158#define SOFT_RST_CTRL 0x000004A4
159#define CX885_VERSION 0x000004B4
160#define VBI_PASS_CTRL 0x000004BC
161
162/* Audio Decoder Registers */
163/* 8051 Configuration */
164#define DL_CTL 0x00000800
165#define STD_DET_STATUS 0x00000804
166#define STD_DET_CTL 0x00000808
167#define DW8051_INT 0x0000080C
168#define GENERAL_CTL 0x00000810
169#define AAGC_CTL 0x00000814
170#define DEMATRIX_CTL 0x000008CC
171#define PATH1_CTL1 0x000008D0
172#define PATH1_VOL_CTL 0x000008D4
173#define PATH1_EQ_CTL 0x000008D8
174#define PATH1_SC_CTL 0x000008DC
175#define PATH2_CTL1 0x000008E0
176#define PATH2_VOL_CTL 0x000008E4
177#define PATH2_EQ_CTL 0x000008E8
178#define PATH2_SC_CTL 0x000008EC
179
180/* Sample Rate Converter */
181#define SRC_CTL 0x000008F0
182#define SRC_LF_COEF 0x000008F4
183#define SRC1_CTL 0x000008F8
184#define SRC2_CTL 0x000008FC
185#define SRC3_CTL 0x00000900
186#define SRC4_CTL 0x00000904
187#define SRC5_CTL 0x00000908
188#define SRC6_CTL 0x0000090C
189#define BAND_OUT_SEL 0x00000910
190#define I2S_N_CTL 0x00000914
191#define I2S_OUT_CTL 0x00000918
192#define AUTOCONFIG_REG 0x000009C4
193
194/* Audio ADC Registers */
195#define DSM_CTRL1 0x00000000
196#define DSM_CTRL2 0x00000001
197#define CHP_EN_CTRL 0x00000002
198#define CHP_CLK_CTRL1 0x00000004
199#define CHP_CLK_CTRL2 0x00000005
200#define BG_REF_CTRL 0x00000006
201#define SD2_SW_CTRL1 0x00000008
202#define SD2_SW_CTRL2 0x00000009
203#define SD2_BIAS_CTRL 0x0000000A
204#define AMP_BIAS_CTRL 0x0000000C
205#define CH_PWR_CTRL1 0x0000000E
206#define FLD_CH_SEL (1 << 3)
207#define CH_PWR_CTRL2 0x0000000F
208#define DSM_STATUS1 0x00000010
209#define DSM_STATUS2 0x00000011
210#define DIG_CTL1 0x00000012
211#define DIG_CTL2 0x00000013
212#define I2S_TX_CFG 0x0000001A
213
214#define DEV_CNTRL2 0x00040000
215
216#define PCI_MSK_IR (1 << 28)
217#define PCI_MSK_AV_CORE (1 << 27)
218#define PCI_MSK_GPIO1 (1 << 24)
219#define PCI_MSK_GPIO0 (1 << 23)
220#define PCI_MSK_APB_DMA (1 << 12)
221#define PCI_MSK_AL_WR (1 << 11)
222#define PCI_MSK_AL_RD (1 << 10)
223#define PCI_MSK_RISC_WR (1 << 9)
224#define PCI_MSK_RISC_RD (1 << 8)
225#define PCI_MSK_AUD_EXT (1 << 4)
226#define PCI_MSK_AUD_INT (1 << 3)
227#define PCI_MSK_VID_C (1 << 2)
228#define PCI_MSK_VID_B (1 << 1)
229#define PCI_MSK_VID_A 1
230#define PCI_INT_MSK 0x00040010
231
232#define PCI_INT_STAT 0x00040014
233#define PCI_INT_MSTAT 0x00040018
234
235#define VID_A_INT_MSK 0x00040020
236#define VID_A_INT_STAT 0x00040024
237#define VID_A_INT_MSTAT 0x00040028
238#define VID_A_INT_SSTAT 0x0004002C
239
240#define VID_B_INT_MSK 0x00040030
241#define VID_B_MSK_BAD_PKT (1 << 20)
242#define VID_B_MSK_VBI_OPC_ERR (1 << 17)
243#define VID_B_MSK_OPC_ERR (1 << 16)
244#define VID_B_MSK_VBI_SYNC (1 << 13)
245#define VID_B_MSK_SYNC (1 << 12)
246#define VID_B_MSK_VBI_OF (1 << 9)
247#define VID_B_MSK_OF (1 << 8)
248#define VID_B_MSK_VBI_RISCI2 (1 << 5)
249#define VID_B_MSK_RISCI2 (1 << 4)
250#define VID_B_MSK_VBI_RISCI1 (1 << 1)
251#define VID_B_MSK_RISCI1 1
252#define VID_B_INT_STAT 0x00040034
253#define VID_B_INT_MSTAT 0x00040038
254#define VID_B_INT_SSTAT 0x0004003C
255
256#define VID_B_MSK_BAD_PKT (1 << 20)
257#define VID_B_MSK_OPC_ERR (1 << 16)
258#define VID_B_MSK_SYNC (1 << 12)
259#define VID_B_MSK_OF (1 << 8)
260#define VID_B_MSK_RISCI2 (1 << 4)
261#define VID_B_MSK_RISCI1 1
262
263#define VID_C_MSK_BAD_PKT (1 << 20)
264#define VID_C_MSK_OPC_ERR (1 << 16)
265#define VID_C_MSK_SYNC (1 << 12)
266#define VID_C_MSK_OF (1 << 8)
267#define VID_C_MSK_RISCI2 (1 << 4)
268#define VID_C_MSK_RISCI1 1
269
270/* A superset for testing purposes */
271#define VID_BC_MSK_BAD_PKT (1 << 20)
272#define VID_BC_MSK_OPC_ERR (1 << 16)
273#define VID_BC_MSK_SYNC (1 << 12)
274#define VID_BC_MSK_OF (1 << 8)
275#define VID_BC_MSK_VBI_RISCI2 (1 << 5)
276#define VID_BC_MSK_RISCI2 (1 << 4)
277#define VID_BC_MSK_VBI_RISCI1 (1 << 1)
278#define VID_BC_MSK_RISCI1 1
279
280#define VID_C_INT_MSK 0x00040040
281#define VID_C_INT_STAT 0x00040044
282#define VID_C_INT_MSTAT 0x00040048
283#define VID_C_INT_SSTAT 0x0004004C
284
285#define AUDIO_INT_INT_MSK 0x00040050
286#define AUDIO_INT_INT_STAT 0x00040054
287#define AUDIO_INT_INT_MSTAT 0x00040058
288#define AUDIO_INT_INT_SSTAT 0x0004005C
289
290#define AUDIO_EXT_INT_MSK 0x00040060
291#define AUDIO_EXT_INT_STAT 0x00040064
292#define AUDIO_EXT_INT_MSTAT 0x00040068
293#define AUDIO_EXT_INT_SSTAT 0x0004006C
294
295#define RDR_CFG0 0x00050000
296#define RDR_CFG1 0x00050004
297#define RDR_CFG2 0x00050008
298#define RDR_RDRCTL1 0x0005030c
299#define RDR_TLCTL0 0x00050318
300
301/* APB DMAC Current Buffer Pointer */
302#define DMA1_PTR1 0x00100000
303#define DMA2_PTR1 0x00100004
304#define DMA3_PTR1 0x00100008
305#define DMA4_PTR1 0x0010000C
306#define DMA5_PTR1 0x00100010
307#define DMA6_PTR1 0x00100014
308#define DMA7_PTR1 0x00100018
309#define DMA8_PTR1 0x0010001C
310
311/* APB DMAC Current Table Pointer */
312#define DMA1_PTR2 0x00100040
313#define DMA2_PTR2 0x00100044
314#define DMA3_PTR2 0x00100048
315#define DMA4_PTR2 0x0010004C
316#define DMA5_PTR2 0x00100050
317#define DMA6_PTR2 0x00100054
318#define DMA7_PTR2 0x00100058
319#define DMA8_PTR2 0x0010005C
320
321/* APB DMAC Buffer Limit */
322#define DMA1_CNT1 0x00100080
323#define DMA2_CNT1 0x00100084
324#define DMA3_CNT1 0x00100088
325#define DMA4_CNT1 0x0010008C
326#define DMA5_CNT1 0x00100090
327#define DMA6_CNT1 0x00100094
328#define DMA7_CNT1 0x00100098
329#define DMA8_CNT1 0x0010009C
330
331/* APB DMAC Table Size */
332#define DMA1_CNT2 0x001000C0
333#define DMA2_CNT2 0x001000C4
334#define DMA3_CNT2 0x001000C8
335#define DMA4_CNT2 0x001000CC
336#define DMA5_CNT2 0x001000D0
337#define DMA6_CNT2 0x001000D4
338#define DMA7_CNT2 0x001000D8
339#define DMA8_CNT2 0x001000DC
340
341/* Timer Counters */
342#define TM_CNT_LDW 0x00110000
343#define TM_CNT_UW 0x00110004
344#define TM_LMT_LDW 0x00110008
345#define TM_LMT_UW 0x0011000C
346
347/* GPIO */
348#define GP0_IO 0x00110010
349#define GPIO_ISM 0x00110014
350#define SOFT_RESET 0x0011001C
351
352/* GPIO (417 Microsoftcontroller) RW Data */
353#define MC417_RWD 0x00110020
354
355/* GPIO (417 Microsoftcontroller) Output Enable, Low Active */
356#define MC417_OEN 0x00110024
357#define MC417_CTL 0x00110028
358#define ALT_PIN_OUT_SEL 0x0011002C
359#define CLK_DELAY 0x00110048
360#define PAD_CTRL 0x0011004C
361
362/* Video A Interface */
363#define VID_A_GPCNT 0x00130020
364#define VBI_A_GPCNT 0x00130024
365#define VID_A_GPCNT_CTL 0x00130030
366#define VBI_A_GPCNT_CTL 0x00130034
367#define VID_A_DMA_CTL 0x00130040
368#define VID_A_VIP_CTRL 0x00130080
369#define VID_A_PIXEL_FRMT 0x00130084
370#define VID_A_VBI_CTRL 0x00130088
371
372/* Video B Interface */
373#define VID_B_DMA 0x00130100
374#define VBI_B_DMA 0x00130108
375#define VID_B_GPCNT 0x00130120
376#define VBI_B_GPCNT 0x00130124
377#define VID_B_GPCNT_CTL 0x00130134
378#define VBI_B_GPCNT_CTL 0x00130138
379#define VID_B_DMA_CTL 0x00130140
380#define VID_B_SRC_SEL 0x00130144
381#define VID_B_LNGTH 0x00130150
382#define VID_B_HW_SOP_CTL 0x00130154
383#define VID_B_GEN_CTL 0x00130158
384#define VID_B_BD_PKT_STATUS 0x0013015C
385#define VID_B_SOP_STATUS 0x00130160
386#define VID_B_FIFO_OVFL_STAT 0x00130164
387#define VID_B_VLD_MISC 0x00130168
388#define VID_B_TS_CLK_EN 0x0013016C
389#define VID_B_VIP_CTRL 0x00130180
390#define VID_B_PIXEL_FRMT 0x00130184
391
392/* Video C Interface */
393#define VID_C_GPCNT 0x00130220
394#define VID_C_GPCNT_CTL 0x00130230
395#define VBI_C_GPCNT_CTL 0x00130234
396#define VID_C_DMA_CTL 0x00130240
397#define VID_C_LNGTH 0x00130250
398#define VID_C_HW_SOP_CTL 0x00130254
399#define VID_C_GEN_CTL 0x00130258
400#define VID_C_BD_PKT_STATUS 0x0013025C
401#define VID_C_SOP_STATUS 0x00130260
402#define VID_C_FIFO_OVFL_STAT 0x00130264
403#define VID_C_VLD_MISC 0x00130268
404#define VID_C_TS_CLK_EN 0x0013026C
405
406/* Internal Audio Interface */
407#define AUD_INT_A_GPCNT 0x00140020
408#define AUD_INT_B_GPCNT 0x00140024
409#define AUD_INT_A_GPCNT_CTL 0x00140030
410#define AUD_INT_B_GPCNT_CTL 0x00140034
411#define AUD_INT_DMA_CTL 0x00140040
412#define AUD_INT_A_LNGTH 0x00140050
413#define AUD_INT_B_LNGTH 0x00140054
414#define AUD_INT_A_MODE 0x00140058
415#define AUD_INT_B_MODE 0x0014005C
416
417/* External Audio Interface */
418#define AUD_EXT_DMA 0x00140100
419#define AUD_EXT_GPCNT 0x00140120
420#define AUD_EXT_GPCNT_CTL 0x00140130
421#define AUD_EXT_DMA_CTL 0x00140140
422#define AUD_EXT_LNGTH 0x00140150
423#define AUD_EXT_A_MODE 0x00140158
424
425/* I2C Bus 1 */
426#define I2C1_ADDR 0x00180000
427#define I2C1_WDATA 0x00180004
428#define I2C1_CTRL 0x00180008
429#define I2C1_RDATA 0x0018000C
430#define I2C1_STAT 0x00180010
431
432/* I2C Bus 2 */
433#define I2C2_ADDR 0x00190000
434#define I2C2_WDATA 0x00190004
435#define I2C2_CTRL 0x00190008
436#define I2C2_RDATA 0x0019000C
437#define I2C2_STAT 0x00190010
438
439/* I2C Bus 3 */
440#define I2C3_ADDR 0x001A0000
441#define I2C3_WDATA 0x001A0004
442#define I2C3_CTRL 0x001A0008
443#define I2C3_RDATA 0x001A000C
444#define I2C3_STAT 0x001A0010
445
446/* UART */
447#define UART_CTL 0x001B0000
448#define UART_BRD 0x001B0004
449#define UART_ISR 0x001B000C
450#define UART_CNT 0x001B0010
451
452#endif /* _CX23885_REG_H_ */