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1/*
2 * Freescale MXS I2C bus driver
3 *
4 * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
5 *
6 * based on a (non-working) driver which was:
7 *
8 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
9 *
10 * TODO: add dma-support if platform-support for it is available
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 */
18
19#include <linux/slab.h>
20#include <linux/device.h>
21#include <linux/module.h>
22#include <linux/i2c.h>
23#include <linux/err.h>
24#include <linux/interrupt.h>
25#include <linux/completion.h>
26#include <linux/platform_device.h>
27#include <linux/jiffies.h>
28#include <linux/io.h>
29#include <linux/pinctrl/consumer.h>
30#include <linux/stmp_device.h>
31#include <linux/of.h>
32#include <linux/of_device.h>
33#include <linux/of_i2c.h>
34
35#define DRIVER_NAME "mxs-i2c"
36
37#define MXS_I2C_CTRL0 (0x00)
38#define MXS_I2C_CTRL0_SET (0x04)
39
40#define MXS_I2C_CTRL0_SFTRST 0x80000000
41#define MXS_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000
42#define MXS_I2C_CTRL0_RETAIN_CLOCK 0x00200000
43#define MXS_I2C_CTRL0_POST_SEND_STOP 0x00100000
44#define MXS_I2C_CTRL0_PRE_SEND_START 0x00080000
45#define MXS_I2C_CTRL0_MASTER_MODE 0x00020000
46#define MXS_I2C_CTRL0_DIRECTION 0x00010000
47#define MXS_I2C_CTRL0_XFER_COUNT(v) ((v) & 0x0000FFFF)
48
49#define MXS_I2C_CTRL1 (0x40)
50#define MXS_I2C_CTRL1_SET (0x44)
51#define MXS_I2C_CTRL1_CLR (0x48)
52
53#define MXS_I2C_CTRL1_BUS_FREE_IRQ 0x80
54#define MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x40
55#define MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x20
56#define MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x10
57#define MXS_I2C_CTRL1_EARLY_TERM_IRQ 0x08
58#define MXS_I2C_CTRL1_MASTER_LOSS_IRQ 0x04
59#define MXS_I2C_CTRL1_SLAVE_STOP_IRQ 0x02
60#define MXS_I2C_CTRL1_SLAVE_IRQ 0x01
61
62#define MXS_I2C_IRQ_MASK (MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | \
63 MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ | \
64 MXS_I2C_CTRL1_EARLY_TERM_IRQ | \
65 MXS_I2C_CTRL1_MASTER_LOSS_IRQ | \
66 MXS_I2C_CTRL1_SLAVE_STOP_IRQ | \
67 MXS_I2C_CTRL1_SLAVE_IRQ)
68
69#define MXS_I2C_QUEUECTRL (0x60)
70#define MXS_I2C_QUEUECTRL_SET (0x64)
71#define MXS_I2C_QUEUECTRL_CLR (0x68)
72
73#define MXS_I2C_QUEUECTRL_QUEUE_RUN 0x20
74#define MXS_I2C_QUEUECTRL_PIO_QUEUE_MODE 0x04
75
76#define MXS_I2C_QUEUESTAT (0x70)
77#define MXS_I2C_QUEUESTAT_RD_QUEUE_EMPTY 0x00002000
78#define MXS_I2C_QUEUESTAT_WRITE_QUEUE_CNT_MASK 0x0000001F
79
80#define MXS_I2C_QUEUECMD (0x80)
81
82#define MXS_I2C_QUEUEDATA (0x90)
83
84#define MXS_I2C_DATA (0xa0)
85
86
87#define MXS_CMD_I2C_SELECT (MXS_I2C_CTRL0_RETAIN_CLOCK | \
88 MXS_I2C_CTRL0_PRE_SEND_START | \
89 MXS_I2C_CTRL0_MASTER_MODE | \
90 MXS_I2C_CTRL0_DIRECTION | \
91 MXS_I2C_CTRL0_XFER_COUNT(1))
92
93#define MXS_CMD_I2C_WRITE (MXS_I2C_CTRL0_PRE_SEND_START | \
94 MXS_I2C_CTRL0_MASTER_MODE | \
95 MXS_I2C_CTRL0_DIRECTION)
96
97#define MXS_CMD_I2C_READ (MXS_I2C_CTRL0_SEND_NAK_ON_LAST | \
98 MXS_I2C_CTRL0_MASTER_MODE)
99
100/**
101 * struct mxs_i2c_dev - per device, private MXS-I2C data
102 *
103 * @dev: driver model device node
104 * @regs: IO registers pointer
105 * @cmd_complete: completion object for transaction wait
106 * @cmd_err: error code for last transaction
107 * @adapter: i2c subsystem adapter node
108 */
109struct mxs_i2c_dev {
110 struct device *dev;
111 void __iomem *regs;
112 struct completion cmd_complete;
113 u32 cmd_err;
114 struct i2c_adapter adapter;
115};
116
117static void mxs_i2c_reset(struct mxs_i2c_dev *i2c)
118{
119 stmp_reset_block(i2c->regs);
120 writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
121 writel(MXS_I2C_QUEUECTRL_PIO_QUEUE_MODE,
122 i2c->regs + MXS_I2C_QUEUECTRL_SET);
123}
124
125static void mxs_i2c_pioq_setup_read(struct mxs_i2c_dev *i2c, u8 addr, int len,
126 int flags)
127{
128 u32 data;
129
130 writel(MXS_CMD_I2C_SELECT, i2c->regs + MXS_I2C_QUEUECMD);
131
132 data = (addr << 1) | I2C_SMBUS_READ;
133 writel(data, i2c->regs + MXS_I2C_DATA);
134
135 data = MXS_CMD_I2C_READ | MXS_I2C_CTRL0_XFER_COUNT(len) | flags;
136 writel(data, i2c->regs + MXS_I2C_QUEUECMD);
137}
138
139static void mxs_i2c_pioq_setup_write(struct mxs_i2c_dev *i2c,
140 u8 addr, u8 *buf, int len, int flags)
141{
142 u32 data;
143 int i, shifts_left;
144
145 data = MXS_CMD_I2C_WRITE | MXS_I2C_CTRL0_XFER_COUNT(len + 1) | flags;
146 writel(data, i2c->regs + MXS_I2C_QUEUECMD);
147
148 /*
149 * We have to copy the slave address (u8) and buffer (arbitrary number
150 * of u8) into the data register (u32). To achieve that, the u8 are put
151 * into the MSBs of 'data' which is then shifted for the next u8. When
152 * appropriate, 'data' is written to MXS_I2C_DATA. So, the first u32
153 * looks like this:
154 *
155 * 3 2 1 0
156 * 10987654|32109876|54321098|76543210
157 * --------+--------+--------+--------
158 * buffer+2|buffer+1|buffer+0|slave_addr
159 */
160
161 data = ((addr << 1) | I2C_SMBUS_WRITE) << 24;
162
163 for (i = 0; i < len; i++) {
164 data >>= 8;
165 data |= buf[i] << 24;
166 if ((i & 3) == 2)
167 writel(data, i2c->regs + MXS_I2C_DATA);
168 }
169
170 /* Write out the remaining bytes if any */
171 shifts_left = 24 - (i & 3) * 8;
172 if (shifts_left)
173 writel(data >> shifts_left, i2c->regs + MXS_I2C_DATA);
174}
175
176/*
177 * TODO: should be replaceable with a waitqueue and RD_QUEUE_IRQ (setting the
178 * rd_threshold to 1). Couldn't get this to work, though.
179 */
180static int mxs_i2c_wait_for_data(struct mxs_i2c_dev *i2c)
181{
182 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
183
184 while (readl(i2c->regs + MXS_I2C_QUEUESTAT)
185 & MXS_I2C_QUEUESTAT_RD_QUEUE_EMPTY) {
186 if (time_after(jiffies, timeout))
187 return -ETIMEDOUT;
188 cond_resched();
189 }
190
191 return 0;
192}
193
194static int mxs_i2c_finish_read(struct mxs_i2c_dev *i2c, u8 *buf, int len)
195{
196 u32 data;
197 int i;
198
199 for (i = 0; i < len; i++) {
200 if ((i & 3) == 0) {
201 if (mxs_i2c_wait_for_data(i2c))
202 return -ETIMEDOUT;
203 data = readl(i2c->regs + MXS_I2C_QUEUEDATA);
204 }
205 buf[i] = data & 0xff;
206 data >>= 8;
207 }
208
209 return 0;
210}
211
212/*
213 * Low level master read/write transaction.
214 */
215static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
216 int stop)
217{
218 struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
219 int ret;
220 int flags;
221
222 dev_dbg(i2c->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
223 msg->addr, msg->len, msg->flags, stop);
224
225 if (msg->len == 0)
226 return -EINVAL;
227
228 init_completion(&i2c->cmd_complete);
229 i2c->cmd_err = 0;
230
231 flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0;
232
233 if (msg->flags & I2C_M_RD)
234 mxs_i2c_pioq_setup_read(i2c, msg->addr, msg->len, flags);
235 else
236 mxs_i2c_pioq_setup_write(i2c, msg->addr, msg->buf, msg->len,
237 flags);
238
239 writel(MXS_I2C_QUEUECTRL_QUEUE_RUN,
240 i2c->regs + MXS_I2C_QUEUECTRL_SET);
241
242 ret = wait_for_completion_timeout(&i2c->cmd_complete,
243 msecs_to_jiffies(1000));
244 if (ret == 0)
245 goto timeout;
246
247 if ((!i2c->cmd_err) && (msg->flags & I2C_M_RD)) {
248 ret = mxs_i2c_finish_read(i2c, msg->buf, msg->len);
249 if (ret)
250 goto timeout;
251 }
252
253 if (i2c->cmd_err == -ENXIO)
254 mxs_i2c_reset(i2c);
255 else
256 writel(MXS_I2C_QUEUECTRL_QUEUE_RUN,
257 i2c->regs + MXS_I2C_QUEUECTRL_CLR);
258
259 dev_dbg(i2c->dev, "Done with err=%d\n", i2c->cmd_err);
260
261 return i2c->cmd_err;
262
263timeout:
264 dev_dbg(i2c->dev, "Timeout!\n");
265 mxs_i2c_reset(i2c);
266 return -ETIMEDOUT;
267}
268
269static int mxs_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
270 int num)
271{
272 int i;
273 int err;
274
275 for (i = 0; i < num; i++) {
276 err = mxs_i2c_xfer_msg(adap, &msgs[i], i == (num - 1));
277 if (err)
278 return err;
279 }
280
281 return num;
282}
283
284static u32 mxs_i2c_func(struct i2c_adapter *adap)
285{
286 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
287}
288
289static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id)
290{
291 struct mxs_i2c_dev *i2c = dev_id;
292 u32 stat = readl(i2c->regs + MXS_I2C_CTRL1) & MXS_I2C_IRQ_MASK;
293 bool is_last_cmd;
294
295 if (!stat)
296 return IRQ_NONE;
297
298 if (stat & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
299 i2c->cmd_err = -ENXIO;
300 else if (stat & (MXS_I2C_CTRL1_EARLY_TERM_IRQ |
301 MXS_I2C_CTRL1_MASTER_LOSS_IRQ |
302 MXS_I2C_CTRL1_SLAVE_STOP_IRQ | MXS_I2C_CTRL1_SLAVE_IRQ))
303 /* MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ is only for slaves */
304 i2c->cmd_err = -EIO;
305
306 is_last_cmd = (readl(i2c->regs + MXS_I2C_QUEUESTAT) &
307 MXS_I2C_QUEUESTAT_WRITE_QUEUE_CNT_MASK) == 0;
308
309 if (is_last_cmd || i2c->cmd_err)
310 complete(&i2c->cmd_complete);
311
312 writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR);
313
314 return IRQ_HANDLED;
315}
316
317static const struct i2c_algorithm mxs_i2c_algo = {
318 .master_xfer = mxs_i2c_xfer,
319 .functionality = mxs_i2c_func,
320};
321
322static int __devinit mxs_i2c_probe(struct platform_device *pdev)
323{
324 struct device *dev = &pdev->dev;
325 struct mxs_i2c_dev *i2c;
326 struct i2c_adapter *adap;
327 struct pinctrl *pinctrl;
328 struct resource *res;
329 resource_size_t res_size;
330 int err, irq;
331
332 pinctrl = devm_pinctrl_get_select_default(dev);
333 if (IS_ERR(pinctrl))
334 return PTR_ERR(pinctrl);
335
336 i2c = devm_kzalloc(dev, sizeof(struct mxs_i2c_dev), GFP_KERNEL);
337 if (!i2c)
338 return -ENOMEM;
339
340 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
341 if (!res)
342 return -ENOENT;
343
344 res_size = resource_size(res);
345 if (!devm_request_mem_region(dev, res->start, res_size, res->name))
346 return -EBUSY;
347
348 i2c->regs = devm_ioremap_nocache(dev, res->start, res_size);
349 if (!i2c->regs)
350 return -EBUSY;
351
352 irq = platform_get_irq(pdev, 0);
353 if (irq < 0)
354 return irq;
355
356 err = devm_request_irq(dev, irq, mxs_i2c_isr, 0, dev_name(dev), i2c);
357 if (err)
358 return err;
359
360 i2c->dev = dev;
361 platform_set_drvdata(pdev, i2c);
362
363 /* Do reset to enforce correct startup after pinmuxing */
364 mxs_i2c_reset(i2c);
365
366 adap = &i2c->adapter;
367 strlcpy(adap->name, "MXS I2C adapter", sizeof(adap->name));
368 adap->owner = THIS_MODULE;
369 adap->algo = &mxs_i2c_algo;
370 adap->dev.parent = dev;
371 adap->nr = pdev->id;
372 adap->dev.of_node = pdev->dev.of_node;
373 i2c_set_adapdata(adap, i2c);
374 err = i2c_add_numbered_adapter(adap);
375 if (err) {
376 dev_err(dev, "Failed to add adapter (%d)\n", err);
377 writel(MXS_I2C_CTRL0_SFTRST,
378 i2c->regs + MXS_I2C_CTRL0_SET);
379 return err;
380 }
381
382 of_i2c_register_devices(adap);
383
384 return 0;
385}
386
387static int __devexit mxs_i2c_remove(struct platform_device *pdev)
388{
389 struct mxs_i2c_dev *i2c = platform_get_drvdata(pdev);
390 int ret;
391
392 ret = i2c_del_adapter(&i2c->adapter);
393 if (ret)
394 return -EBUSY;
395
396 writel(MXS_I2C_CTRL0_SFTRST, i2c->regs + MXS_I2C_CTRL0_SET);
397
398 platform_set_drvdata(pdev, NULL);
399
400 return 0;
401}
402
403static const struct of_device_id mxs_i2c_dt_ids[] = {
404 { .compatible = "fsl,imx28-i2c", },
405 { /* sentinel */ }
406};
407MODULE_DEVICE_TABLE(of, mxs_i2c_dt_ids);
408
409static struct platform_driver mxs_i2c_driver = {
410 .driver = {
411 .name = DRIVER_NAME,
412 .owner = THIS_MODULE,
413 .of_match_table = mxs_i2c_dt_ids,
414 },
415 .remove = __devexit_p(mxs_i2c_remove),
416};
417
418static int __init mxs_i2c_init(void)
419{
420 return platform_driver_probe(&mxs_i2c_driver, mxs_i2c_probe);
421}
422subsys_initcall(mxs_i2c_init);
423
424static void __exit mxs_i2c_exit(void)
425{
426 platform_driver_unregister(&mxs_i2c_driver);
427}
428module_exit(mxs_i2c_exit);
429
430MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>");
431MODULE_DESCRIPTION("MXS I2C Bus Driver");
432MODULE_LICENSE("GPL");
433MODULE_ALIAS("platform:" DRIVER_NAME);