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1/*
2 * Intel 82975X Memory Controller kernel module
3 * (C) 2007 aCarLab (India) Pvt. Ltd. (http://acarlab.com)
4 * (C) 2007 jetzbroadband (http://jetzbroadband.com)
5 * This file may be distributed under the terms of the
6 * GNU General Public License.
7 *
8 * Written by Arvind R.
9 * Copied from i82875p_edac.c source:
10 */
11
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/pci.h>
15#include <linux/pci_ids.h>
16#include <linux/edac.h>
17#include "edac_core.h"
18
19#define I82975X_REVISION " Ver: 1.0.0"
20#define EDAC_MOD_STR "i82975x_edac"
21
22#define i82975x_printk(level, fmt, arg...) \
23 edac_printk(level, "i82975x", fmt, ##arg)
24
25#define i82975x_mc_printk(mci, level, fmt, arg...) \
26 edac_mc_chipset_printk(mci, level, "i82975x", fmt, ##arg)
27
28#ifndef PCI_DEVICE_ID_INTEL_82975_0
29#define PCI_DEVICE_ID_INTEL_82975_0 0x277c
30#endif /* PCI_DEVICE_ID_INTEL_82975_0 */
31
32#define I82975X_NR_DIMMS 8
33#define I82975X_NR_CSROWS(nr_chans) (I82975X_NR_DIMMS / (nr_chans))
34
35/* Intel 82975X register addresses - device 0 function 0 - DRAM Controller */
36#define I82975X_EAP 0x58 /* Dram Error Address Pointer (32b)
37 *
38 * 31:7 128 byte cache-line address
39 * 6:1 reserved
40 * 0 0: CH0; 1: CH1
41 */
42
43#define I82975X_DERRSYN 0x5c /* Dram Error SYNdrome (8b)
44 *
45 * 7:0 DRAM ECC Syndrome
46 */
47
48#define I82975X_DES 0x5d /* Dram ERRor DeSTination (8b)
49 * 0h: Processor Memory Reads
50 * 1h:7h reserved
51 * More - See Page 65 of Intel DocSheet.
52 */
53
54#define I82975X_ERRSTS 0xc8 /* Error Status Register (16b)
55 *
56 * 15:12 reserved
57 * 11 Thermal Sensor Event
58 * 10 reserved
59 * 9 non-DRAM lock error (ndlock)
60 * 8 Refresh Timeout
61 * 7:2 reserved
62 * 1 ECC UE (multibit DRAM error)
63 * 0 ECC CE (singlebit DRAM error)
64 */
65
66/* Error Reporting is supported by 3 mechanisms:
67 1. DMI SERR generation ( ERRCMD )
68 2. SMI DMI generation ( SMICMD )
69 3. SCI DMI generation ( SCICMD )
70NOTE: Only ONE of the three must be enabled
71*/
72#define I82975X_ERRCMD 0xca /* Error Command (16b)
73 *
74 * 15:12 reserved
75 * 11 Thermal Sensor Event
76 * 10 reserved
77 * 9 non-DRAM lock error (ndlock)
78 * 8 Refresh Timeout
79 * 7:2 reserved
80 * 1 ECC UE (multibit DRAM error)
81 * 0 ECC CE (singlebit DRAM error)
82 */
83
84#define I82975X_SMICMD 0xcc /* Error Command (16b)
85 *
86 * 15:2 reserved
87 * 1 ECC UE (multibit DRAM error)
88 * 0 ECC CE (singlebit DRAM error)
89 */
90
91#define I82975X_SCICMD 0xce /* Error Command (16b)
92 *
93 * 15:2 reserved
94 * 1 ECC UE (multibit DRAM error)
95 * 0 ECC CE (singlebit DRAM error)
96 */
97
98#define I82975X_XEAP 0xfc /* Extended Dram Error Address Pointer (8b)
99 *
100 * 7:1 reserved
101 * 0 Bit32 of the Dram Error Address
102 */
103
104#define I82975X_MCHBAR 0x44 /*
105 *
106 * 31:14 Base Addr of 16K memory-mapped
107 * configuration space
108 * 13:1 reserverd
109 * 0 mem-mapped config space enable
110 */
111
112/* NOTE: Following addresses have to indexed using MCHBAR offset (44h, 32b) */
113/* Intel 82975x memory mapped register space */
114
115#define I82975X_DRB_SHIFT 25 /* fixed 32MiB grain */
116
117#define I82975X_DRB 0x100 /* DRAM Row Boundary (8b x 8)
118 *
119 * 7 set to 1 in highest DRB of
120 * channel if 4GB in ch.
121 * 6:2 upper boundary of rank in
122 * 32MB grains
123 * 1:0 set to 0
124 */
125#define I82975X_DRB_CH0R0 0x100
126#define I82975X_DRB_CH0R1 0x101
127#define I82975X_DRB_CH0R2 0x102
128#define I82975X_DRB_CH0R3 0x103
129#define I82975X_DRB_CH1R0 0x180
130#define I82975X_DRB_CH1R1 0x181
131#define I82975X_DRB_CH1R2 0x182
132#define I82975X_DRB_CH1R3 0x183
133
134
135#define I82975X_DRA 0x108 /* DRAM Row Attribute (4b x 8)
136 * defines the PAGE SIZE to be used
137 * for the rank
138 * 7 reserved
139 * 6:4 row attr of odd rank, i.e. 1
140 * 3 reserved
141 * 2:0 row attr of even rank, i.e. 0
142 *
143 * 000 = unpopulated
144 * 001 = reserved
145 * 010 = 4KiB
146 * 011 = 8KiB
147 * 100 = 16KiB
148 * others = reserved
149 */
150#define I82975X_DRA_CH0R01 0x108
151#define I82975X_DRA_CH0R23 0x109
152#define I82975X_DRA_CH1R01 0x188
153#define I82975X_DRA_CH1R23 0x189
154
155
156#define I82975X_BNKARC 0x10e /* Type of device in each rank - Bank Arch (16b)
157 *
158 * 15:8 reserved
159 * 7:6 Rank 3 architecture
160 * 5:4 Rank 2 architecture
161 * 3:2 Rank 1 architecture
162 * 1:0 Rank 0 architecture
163 *
164 * 00 => 4 banks
165 * 01 => 8 banks
166 */
167#define I82975X_C0BNKARC 0x10e
168#define I82975X_C1BNKARC 0x18e
169
170
171
172#define I82975X_DRC 0x120 /* DRAM Controller Mode0 (32b)
173 *
174 * 31:30 reserved
175 * 29 init complete
176 * 28:11 reserved, according to Intel
177 * 22:21 number of channels
178 * 00=1 01=2 in 82875
179 * seems to be ECC mode
180 * bits in 82975 in Asus
181 * P5W
182 * 19:18 Data Integ Mode
183 * 00=none 01=ECC in 82875
184 * 10:8 refresh mode
185 * 7 reserved
186 * 6:4 mode select
187 * 3:2 reserved
188 * 1:0 DRAM type 10=Second Revision
189 * DDR2 SDRAM
190 * 00, 01, 11 reserved
191 */
192#define I82975X_DRC_CH0M0 0x120
193#define I82975X_DRC_CH1M0 0x1A0
194
195
196#define I82975X_DRC_M1 0x124 /* DRAM Controller Mode1 (32b)
197 * 31 0=Standard Address Map
198 * 1=Enhanced Address Map
199 * 30:0 reserved
200 */
201
202#define I82975X_DRC_CH0M1 0x124
203#define I82975X_DRC_CH1M1 0x1A4
204
205enum i82975x_chips {
206 I82975X = 0,
207};
208
209struct i82975x_pvt {
210 void __iomem *mch_window;
211};
212
213struct i82975x_dev_info {
214 const char *ctl_name;
215};
216
217struct i82975x_error_info {
218 u16 errsts;
219 u32 eap;
220 u8 des;
221 u8 derrsyn;
222 u16 errsts2;
223 u8 chan; /* the channel is bit 0 of EAP */
224 u8 xeap; /* extended eap bit */
225};
226
227static const struct i82975x_dev_info i82975x_devs[] = {
228 [I82975X] = {
229 .ctl_name = "i82975x"
230 },
231};
232
233static struct pci_dev *mci_pdev; /* init dev: in case that AGP code has
234 * already registered driver
235 */
236
237static int i82975x_registered = 1;
238
239static void i82975x_get_error_info(struct mem_ctl_info *mci,
240 struct i82975x_error_info *info)
241{
242 struct pci_dev *pdev;
243
244 pdev = to_pci_dev(mci->dev);
245
246 /*
247 * This is a mess because there is no atomic way to read all the
248 * registers at once and the registers can transition from CE being
249 * overwritten by UE.
250 */
251 pci_read_config_word(pdev, I82975X_ERRSTS, &info->errsts);
252 pci_read_config_dword(pdev, I82975X_EAP, &info->eap);
253 pci_read_config_byte(pdev, I82975X_XEAP, &info->xeap);
254 pci_read_config_byte(pdev, I82975X_DES, &info->des);
255 pci_read_config_byte(pdev, I82975X_DERRSYN, &info->derrsyn);
256 pci_read_config_word(pdev, I82975X_ERRSTS, &info->errsts2);
257
258 pci_write_bits16(pdev, I82975X_ERRSTS, 0x0003, 0x0003);
259
260 /*
261 * If the error is the same then we can for both reads then
262 * the first set of reads is valid. If there is a change then
263 * there is a CE no info and the second set of reads is valid
264 * and should be UE info.
265 */
266 if (!(info->errsts2 & 0x0003))
267 return;
268
269 if ((info->errsts ^ info->errsts2) & 0x0003) {
270 pci_read_config_dword(pdev, I82975X_EAP, &info->eap);
271 pci_read_config_byte(pdev, I82975X_XEAP, &info->xeap);
272 pci_read_config_byte(pdev, I82975X_DES, &info->des);
273 pci_read_config_byte(pdev, I82975X_DERRSYN,
274 &info->derrsyn);
275 }
276}
277
278static int i82975x_process_error_info(struct mem_ctl_info *mci,
279 struct i82975x_error_info *info, int handle_errors)
280{
281 int row, chan;
282 unsigned long offst, page;
283
284 if (!(info->errsts2 & 0x0003))
285 return 0;
286
287 if (!handle_errors)
288 return 1;
289
290 if ((info->errsts ^ info->errsts2) & 0x0003) {
291 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 0, 0, 0,
292 -1, -1, -1, "UE overwrote CE", "", NULL);
293 info->errsts = info->errsts2;
294 }
295
296 page = (unsigned long) info->eap;
297 page >>= 1;
298 if (info->xeap & 1)
299 page |= 0x80000000;
300 page >>= (PAGE_SHIFT - 1);
301 row = edac_mc_find_csrow_by_page(mci, page);
302
303 if (row == -1) {
304 i82975x_mc_printk(mci, KERN_ERR, "error processing EAP:\n"
305 "\tXEAP=%u\n"
306 "\t EAP=0x%08x\n"
307 "\tPAGE=0x%08x\n",
308 (info->xeap & 1) ? 1 : 0, info->eap, (unsigned int) page);
309 return 0;
310 }
311 chan = (mci->csrows[row].nr_channels == 1) ? 0 : info->eap & 1;
312 offst = info->eap
313 & ((1 << PAGE_SHIFT) -
314 (1 << mci->csrows[row].channels[chan].dimm->grain));
315
316 if (info->errsts & 0x0002)
317 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
318 page, offst, 0,
319 row, -1, -1,
320 "i82975x UE", "", NULL);
321 else
322 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
323 page, offst, info->derrsyn,
324 row, chan ? chan : 0, -1,
325 "i82975x CE", "", NULL);
326
327 return 1;
328}
329
330static void i82975x_check(struct mem_ctl_info *mci)
331{
332 struct i82975x_error_info info;
333
334 debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
335 i82975x_get_error_info(mci, &info);
336 i82975x_process_error_info(mci, &info, 1);
337}
338
339/* Return 1 if dual channel mode is active. Else return 0. */
340static int dual_channel_active(void __iomem *mch_window)
341{
342 /*
343 * We treat interleaved-symmetric configuration as dual-channel - EAP's
344 * bit-0 giving the channel of the error location.
345 *
346 * All other configurations are treated as single channel - the EAP's
347 * bit-0 will resolve ok in symmetric area of mixed
348 * (symmetric/asymmetric) configurations
349 */
350 u8 drb[4][2];
351 int row;
352 int dualch;
353
354 for (dualch = 1, row = 0; dualch && (row < 4); row++) {
355 drb[row][0] = readb(mch_window + I82975X_DRB + row);
356 drb[row][1] = readb(mch_window + I82975X_DRB + row + 0x80);
357 dualch = dualch && (drb[row][0] == drb[row][1]);
358 }
359 return dualch;
360}
361
362static enum dev_type i82975x_dram_type(void __iomem *mch_window, int rank)
363{
364 /*
365 * ECC is possible on i92975x ONLY with DEV_X8
366 */
367 return DEV_X8;
368}
369
370static void i82975x_init_csrows(struct mem_ctl_info *mci,
371 struct pci_dev *pdev, void __iomem *mch_window)
372{
373 static const char *labels[4] = {
374 "DIMM A1", "DIMM A2",
375 "DIMM B1", "DIMM B2"
376 };
377 struct csrow_info *csrow;
378 unsigned long last_cumul_size;
379 u8 value;
380 u32 cumul_size, nr_pages;
381 int index, chan;
382 struct dimm_info *dimm;
383 enum dev_type dtype;
384
385 last_cumul_size = 0;
386
387 /*
388 * 82875 comment:
389 * The dram row boundary (DRB) reg values are boundary address
390 * for each DRAM row with a granularity of 32 or 64MB (single/dual
391 * channel operation). DRB regs are cumulative; therefore DRB7 will
392 * contain the total memory contained in all rows.
393 *
394 */
395
396 for (index = 0; index < mci->nr_csrows; index++) {
397 csrow = &mci->csrows[index];
398
399 value = readb(mch_window + I82975X_DRB + index +
400 ((index >= 4) ? 0x80 : 0));
401 cumul_size = value;
402 cumul_size <<= (I82975X_DRB_SHIFT - PAGE_SHIFT);
403 /*
404 * Adjust cumul_size w.r.t number of channels
405 *
406 */
407 if (csrow->nr_channels > 1)
408 cumul_size <<= 1;
409 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
410 cumul_size);
411
412 nr_pages = cumul_size - last_cumul_size;
413 if (!nr_pages)
414 continue;
415
416 /*
417 * Initialise dram labels
418 * index values:
419 * [0-7] for single-channel; i.e. csrow->nr_channels = 1
420 * [0-3] for dual-channel; i.e. csrow->nr_channels = 2
421 */
422 dtype = i82975x_dram_type(mch_window, index);
423 for (chan = 0; chan < csrow->nr_channels; chan++) {
424 dimm = mci->csrows[index].channels[chan].dimm;
425
426 dimm->nr_pages = nr_pages / csrow->nr_channels;
427 strncpy(csrow->channels[chan].dimm->label,
428 labels[(index >> 1) + (chan * 2)],
429 EDAC_MC_LABEL_LEN);
430 dimm->grain = 1 << 7; /* 128Byte cache-line resolution */
431 dimm->dtype = i82975x_dram_type(mch_window, index);
432 dimm->mtype = MEM_DDR2; /* I82975x supports only DDR2 */
433 dimm->edac_mode = EDAC_SECDED; /* only supported */
434 }
435
436 csrow->first_page = last_cumul_size;
437 csrow->last_page = cumul_size - 1;
438 last_cumul_size = cumul_size;
439 }
440}
441
442/* #define i82975x_DEBUG_IOMEM */
443
444#ifdef i82975x_DEBUG_IOMEM
445static void i82975x_print_dram_timings(void __iomem *mch_window)
446{
447 /*
448 * The register meanings are from Intel specs;
449 * (shows 13-5-5-5 for 800-DDR2)
450 * Asus P5W Bios reports 15-5-4-4
451 * What's your religion?
452 */
453 static const int caslats[4] = { 5, 4, 3, 6 };
454 u32 dtreg[2];
455
456 dtreg[0] = readl(mch_window + 0x114);
457 dtreg[1] = readl(mch_window + 0x194);
458 i82975x_printk(KERN_INFO, "DRAM Timings : Ch0 Ch1\n"
459 " RAS Active Min = %d %d\n"
460 " CAS latency = %d %d\n"
461 " RAS to CAS = %d %d\n"
462 " RAS precharge = %d %d\n",
463 (dtreg[0] >> 19 ) & 0x0f,
464 (dtreg[1] >> 19) & 0x0f,
465 caslats[(dtreg[0] >> 8) & 0x03],
466 caslats[(dtreg[1] >> 8) & 0x03],
467 ((dtreg[0] >> 4) & 0x07) + 2,
468 ((dtreg[1] >> 4) & 0x07) + 2,
469 (dtreg[0] & 0x07) + 2,
470 (dtreg[1] & 0x07) + 2
471 );
472
473}
474#endif
475
476static int i82975x_probe1(struct pci_dev *pdev, int dev_idx)
477{
478 int rc = -ENODEV;
479 struct mem_ctl_info *mci;
480 struct edac_mc_layer layers[2];
481 struct i82975x_pvt *pvt;
482 void __iomem *mch_window;
483 u32 mchbar;
484 u32 drc[2];
485 struct i82975x_error_info discard;
486 int chans;
487#ifdef i82975x_DEBUG_IOMEM
488 u8 c0drb[4];
489 u8 c1drb[4];
490#endif
491
492 debugf0("%s()\n", __func__);
493
494 pci_read_config_dword(pdev, I82975X_MCHBAR, &mchbar);
495 if (!(mchbar & 1)) {
496 debugf3("%s(): failed, MCHBAR disabled!\n", __func__);
497 goto fail0;
498 }
499 mchbar &= 0xffffc000; /* bits 31:14 used for 16K window */
500 mch_window = ioremap_nocache(mchbar, 0x1000);
501
502#ifdef i82975x_DEBUG_IOMEM
503 i82975x_printk(KERN_INFO, "MCHBAR real = %0x, remapped = %p\n",
504 mchbar, mch_window);
505
506 c0drb[0] = readb(mch_window + I82975X_DRB_CH0R0);
507 c0drb[1] = readb(mch_window + I82975X_DRB_CH0R1);
508 c0drb[2] = readb(mch_window + I82975X_DRB_CH0R2);
509 c0drb[3] = readb(mch_window + I82975X_DRB_CH0R3);
510 c1drb[0] = readb(mch_window + I82975X_DRB_CH1R0);
511 c1drb[1] = readb(mch_window + I82975X_DRB_CH1R1);
512 c1drb[2] = readb(mch_window + I82975X_DRB_CH1R2);
513 c1drb[3] = readb(mch_window + I82975X_DRB_CH1R3);
514 i82975x_printk(KERN_INFO, "DRBCH0R0 = 0x%02x\n", c0drb[0]);
515 i82975x_printk(KERN_INFO, "DRBCH0R1 = 0x%02x\n", c0drb[1]);
516 i82975x_printk(KERN_INFO, "DRBCH0R2 = 0x%02x\n", c0drb[2]);
517 i82975x_printk(KERN_INFO, "DRBCH0R3 = 0x%02x\n", c0drb[3]);
518 i82975x_printk(KERN_INFO, "DRBCH1R0 = 0x%02x\n", c1drb[0]);
519 i82975x_printk(KERN_INFO, "DRBCH1R1 = 0x%02x\n", c1drb[1]);
520 i82975x_printk(KERN_INFO, "DRBCH1R2 = 0x%02x\n", c1drb[2]);
521 i82975x_printk(KERN_INFO, "DRBCH1R3 = 0x%02x\n", c1drb[3]);
522#endif
523
524 drc[0] = readl(mch_window + I82975X_DRC_CH0M0);
525 drc[1] = readl(mch_window + I82975X_DRC_CH1M0);
526#ifdef i82975x_DEBUG_IOMEM
527 i82975x_printk(KERN_INFO, "DRC_CH0 = %0x, %s\n", drc[0],
528 ((drc[0] >> 21) & 3) == 1 ?
529 "ECC enabled" : "ECC disabled");
530 i82975x_printk(KERN_INFO, "DRC_CH1 = %0x, %s\n", drc[1],
531 ((drc[1] >> 21) & 3) == 1 ?
532 "ECC enabled" : "ECC disabled");
533
534 i82975x_printk(KERN_INFO, "C0 BNKARC = %0x\n",
535 readw(mch_window + I82975X_C0BNKARC));
536 i82975x_printk(KERN_INFO, "C1 BNKARC = %0x\n",
537 readw(mch_window + I82975X_C1BNKARC));
538 i82975x_print_dram_timings(mch_window);
539 goto fail1;
540#endif
541 if (!(((drc[0] >> 21) & 3) == 1 || ((drc[1] >> 21) & 3) == 1)) {
542 i82975x_printk(KERN_INFO, "ECC disabled on both channels.\n");
543 goto fail1;
544 }
545
546 chans = dual_channel_active(mch_window) + 1;
547
548 /* assuming only one controller, index thus is 0 */
549 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
550 layers[0].size = I82975X_NR_DIMMS;
551 layers[0].is_virt_csrow = true;
552 layers[1].type = EDAC_MC_LAYER_CHANNEL;
553 layers[1].size = I82975X_NR_CSROWS(chans);
554 layers[1].is_virt_csrow = false;
555 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
556 if (!mci) {
557 rc = -ENOMEM;
558 goto fail1;
559 }
560
561 debugf3("%s(): init mci\n", __func__);
562 mci->dev = &pdev->dev;
563 mci->mtype_cap = MEM_FLAG_DDR2;
564 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
565 mci->edac_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
566 mci->mod_name = EDAC_MOD_STR;
567 mci->mod_ver = I82975X_REVISION;
568 mci->ctl_name = i82975x_devs[dev_idx].ctl_name;
569 mci->dev_name = pci_name(pdev);
570 mci->edac_check = i82975x_check;
571 mci->ctl_page_to_phys = NULL;
572 debugf3("%s(): init pvt\n", __func__);
573 pvt = (struct i82975x_pvt *) mci->pvt_info;
574 pvt->mch_window = mch_window;
575 i82975x_init_csrows(mci, pdev, mch_window);
576 mci->scrub_mode = SCRUB_HW_SRC;
577 i82975x_get_error_info(mci, &discard); /* clear counters */
578
579 /* finalize this instance of memory controller with edac core */
580 if (edac_mc_add_mc(mci)) {
581 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
582 goto fail2;
583 }
584
585 /* get this far and it's successful */
586 debugf3("%s(): success\n", __func__);
587 return 0;
588
589fail2:
590 edac_mc_free(mci);
591
592fail1:
593 iounmap(mch_window);
594fail0:
595 return rc;
596}
597
598/* returns count (>= 0), or negative on error */
599static int __devinit i82975x_init_one(struct pci_dev *pdev,
600 const struct pci_device_id *ent)
601{
602 int rc;
603
604 debugf0("%s()\n", __func__);
605
606 if (pci_enable_device(pdev) < 0)
607 return -EIO;
608
609 rc = i82975x_probe1(pdev, ent->driver_data);
610
611 if (mci_pdev == NULL)
612 mci_pdev = pci_dev_get(pdev);
613
614 return rc;
615}
616
617static void __devexit i82975x_remove_one(struct pci_dev *pdev)
618{
619 struct mem_ctl_info *mci;
620 struct i82975x_pvt *pvt;
621
622 debugf0("%s()\n", __func__);
623
624 mci = edac_mc_del_mc(&pdev->dev);
625 if (mci == NULL)
626 return;
627
628 pvt = mci->pvt_info;
629 if (pvt->mch_window)
630 iounmap( pvt->mch_window );
631
632 edac_mc_free(mci);
633}
634
635static DEFINE_PCI_DEVICE_TABLE(i82975x_pci_tbl) = {
636 {
637 PCI_VEND_DEV(INTEL, 82975_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
638 I82975X
639 },
640 {
641 0,
642 } /* 0 terminated list. */
643};
644
645MODULE_DEVICE_TABLE(pci, i82975x_pci_tbl);
646
647static struct pci_driver i82975x_driver = {
648 .name = EDAC_MOD_STR,
649 .probe = i82975x_init_one,
650 .remove = __devexit_p(i82975x_remove_one),
651 .id_table = i82975x_pci_tbl,
652};
653
654static int __init i82975x_init(void)
655{
656 int pci_rc;
657
658 debugf3("%s()\n", __func__);
659
660 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
661 opstate_init();
662
663 pci_rc = pci_register_driver(&i82975x_driver);
664 if (pci_rc < 0)
665 goto fail0;
666
667 if (mci_pdev == NULL) {
668 mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
669 PCI_DEVICE_ID_INTEL_82975_0, NULL);
670
671 if (!mci_pdev) {
672 debugf0("i82975x pci_get_device fail\n");
673 pci_rc = -ENODEV;
674 goto fail1;
675 }
676
677 pci_rc = i82975x_init_one(mci_pdev, i82975x_pci_tbl);
678
679 if (pci_rc < 0) {
680 debugf0("i82975x init fail\n");
681 pci_rc = -ENODEV;
682 goto fail1;
683 }
684 }
685
686 return 0;
687
688fail1:
689 pci_unregister_driver(&i82975x_driver);
690
691fail0:
692 if (mci_pdev != NULL)
693 pci_dev_put(mci_pdev);
694
695 return pci_rc;
696}
697
698static void __exit i82975x_exit(void)
699{
700 debugf3("%s()\n", __func__);
701
702 pci_unregister_driver(&i82975x_driver);
703
704 if (!i82975x_registered) {
705 i82975x_remove_one(mci_pdev);
706 pci_dev_put(mci_pdev);
707 }
708}
709
710module_init(i82975x_init);
711module_exit(i82975x_exit);
712
713MODULE_LICENSE("GPL");
714MODULE_AUTHOR("Arvind R. <arvino55@gmail.com>");
715MODULE_DESCRIPTION("MC support for Intel 82975 memory hub controllers");
716
717module_param(edac_op_state, int, 0444);
718MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");