Loading...
1/*
2 * 2006-2009 (C) DENX Software Engineering.
3 *
4 * Author: Yuri Tikhonov <yur@emcraft.com>
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of
8 * any kind, whether express or implied.
9 */
10
11#ifndef _PPC440SPE_ADMA_H
12#define _PPC440SPE_ADMA_H
13
14#include <linux/types.h>
15#include "dma.h"
16#include "xor.h"
17
18#define to_ppc440spe_adma_chan(chan) \
19 container_of(chan, struct ppc440spe_adma_chan, common)
20#define to_ppc440spe_adma_device(dev) \
21 container_of(dev, struct ppc440spe_adma_device, common)
22#define tx_to_ppc440spe_adma_slot(tx) \
23 container_of(tx, struct ppc440spe_adma_desc_slot, async_tx)
24
25/* Default polynomial (for 440SP is only available) */
26#define PPC440SPE_DEFAULT_POLY 0x4d
27
28#define PPC440SPE_ADMA_ENGINES_NUM (XOR_ENGINES_NUM + DMA_ENGINES_NUM)
29
30#define PPC440SPE_ADMA_WATCHDOG_MSEC 3
31#define PPC440SPE_ADMA_THRESHOLD 1
32
33#define PPC440SPE_DMA0_ID 0
34#define PPC440SPE_DMA1_ID 1
35#define PPC440SPE_XOR_ID 2
36
37#define PPC440SPE_ADMA_DMA_MAX_BYTE_COUNT 0xFFFFFFUL
38/* this is the XOR_CBBCR width */
39#define PPC440SPE_ADMA_XOR_MAX_BYTE_COUNT (1 << 31)
40#define PPC440SPE_ADMA_ZERO_SUM_MAX_BYTE_COUNT PPC440SPE_ADMA_XOR_MAX_BYTE_COUNT
41
42#define PPC440SPE_RXOR_RUN 0
43
44#define MQ0_CF2H_RXOR_BS_MASK 0x1FF
45
46#undef ADMA_LL_DEBUG
47
48/**
49 * struct ppc440spe_adma_device - internal representation of an ADMA device
50 * @dev: device
51 * @dma_reg: base for DMAx register access
52 * @xor_reg: base for XOR register access
53 * @i2o_reg: base for I2O register access
54 * @id: HW ADMA Device selector
55 * @dma_desc_pool_virt: base of DMA descriptor region (CPU address)
56 * @dma_desc_pool: base of DMA descriptor region (DMA address)
57 * @pool_size: size of the pool
58 * @irq: DMAx or XOR irq number
59 * @err_irq: DMAx error irq number
60 * @common: embedded struct dma_device
61 */
62struct ppc440spe_adma_device {
63 struct device *dev;
64 struct dma_regs __iomem *dma_reg;
65 struct xor_regs __iomem *xor_reg;
66 struct i2o_regs __iomem *i2o_reg;
67 int id;
68 void *dma_desc_pool_virt;
69 dma_addr_t dma_desc_pool;
70 size_t pool_size;
71 int irq;
72 int err_irq;
73 struct dma_device common;
74};
75
76/**
77 * struct ppc440spe_adma_chan - internal representation of an ADMA channel
78 * @lock: serializes enqueue/dequeue operations to the slot pool
79 * @device: parent device
80 * @chain: device chain view of the descriptors
81 * @common: common dmaengine channel object members
82 * @all_slots: complete domain of slots usable by the channel
83 * @pending: allows batching of hardware operations
84 * @slots_allocated: records the actual size of the descriptor slot pool
85 * @hw_chain_inited: h/w descriptor chain initialization flag
86 * @irq_tasklet: bottom half where ppc440spe_adma_slot_cleanup runs
87 * @needs_unmap: if buffers should not be unmapped upon final processing
88 * @pdest_page: P destination page for async validate operation
89 * @qdest_page: Q destination page for async validate operation
90 * @pdest: P dma addr for async validate operation
91 * @qdest: Q dma addr for async validate operation
92 */
93struct ppc440spe_adma_chan {
94 spinlock_t lock;
95 struct ppc440spe_adma_device *device;
96 struct list_head chain;
97 struct dma_chan common;
98 struct list_head all_slots;
99 struct ppc440spe_adma_desc_slot *last_used;
100 int pending;
101 int slots_allocated;
102 int hw_chain_inited;
103 struct tasklet_struct irq_tasklet;
104 u8 needs_unmap;
105 struct page *pdest_page;
106 struct page *qdest_page;
107 dma_addr_t pdest;
108 dma_addr_t qdest;
109};
110
111struct ppc440spe_rxor {
112 u32 addrl;
113 u32 addrh;
114 int len;
115 int xor_count;
116 int addr_count;
117 int desc_count;
118 int state;
119};
120
121/**
122 * struct ppc440spe_adma_desc_slot - PPC440SPE-ADMA software descriptor
123 * @phys: hardware address of the hardware descriptor chain
124 * @group_head: first operation in a transaction
125 * @hw_next: pointer to the next descriptor in chain
126 * @async_tx: support for the async_tx api
127 * @slot_node: node on the iop_adma_chan.all_slots list
128 * @chain_node: node on the op_adma_chan.chain list
129 * @group_list: list of slots that make up a multi-descriptor transaction
130 * for example transfer lengths larger than the supported hw max
131 * @unmap_len: transaction bytecount
132 * @hw_desc: virtual address of the hardware descriptor chain
133 * @stride: currently chained or not
134 * @idx: pool index
135 * @slot_cnt: total slots used in an transaction (group of operations)
136 * @src_cnt: number of sources set in this descriptor
137 * @dst_cnt: number of destinations set in the descriptor
138 * @slots_per_op: number of slots per operation
139 * @descs_per_op: number of slot per P/Q operation see comment
140 * for ppc440spe_prep_dma_pqxor function
141 * @flags: desc state/type
142 * @reverse_flags: 1 if a corresponding rxor address uses reversed address order
143 * @xor_check_result: result of zero sum
144 * @crc32_result: result crc calculation
145 */
146struct ppc440spe_adma_desc_slot {
147 dma_addr_t phys;
148 struct ppc440spe_adma_desc_slot *group_head;
149 struct ppc440spe_adma_desc_slot *hw_next;
150 struct dma_async_tx_descriptor async_tx;
151 struct list_head slot_node;
152 struct list_head chain_node; /* node in channel ops list */
153 struct list_head group_list; /* list */
154 unsigned int unmap_len;
155 void *hw_desc;
156 u16 stride;
157 u16 idx;
158 u16 slot_cnt;
159 u8 src_cnt;
160 u8 dst_cnt;
161 u8 slots_per_op;
162 u8 descs_per_op;
163 unsigned long flags;
164 unsigned long reverse_flags[8];
165
166#define PPC440SPE_DESC_INT 0 /* generate interrupt on complete */
167#define PPC440SPE_ZERO_P 1 /* clear P destionaion */
168#define PPC440SPE_ZERO_Q 2 /* clear Q destination */
169#define PPC440SPE_COHERENT 3 /* src/dst are coherent */
170
171#define PPC440SPE_DESC_WXOR 4 /* WXORs are in chain */
172#define PPC440SPE_DESC_RXOR 5 /* RXOR is in chain */
173
174#define PPC440SPE_DESC_RXOR123 8 /* CDB for RXOR123 operation */
175#define PPC440SPE_DESC_RXOR124 9 /* CDB for RXOR124 operation */
176#define PPC440SPE_DESC_RXOR125 10 /* CDB for RXOR125 operation */
177#define PPC440SPE_DESC_RXOR12 11 /* CDB for RXOR12 operation */
178#define PPC440SPE_DESC_RXOR_REV 12 /* CDB has srcs in reversed order */
179
180#define PPC440SPE_DESC_PCHECK 13
181#define PPC440SPE_DESC_QCHECK 14
182
183#define PPC440SPE_DESC_RXOR_MSK 0x3
184
185 struct ppc440spe_rxor rxor_cursor;
186
187 union {
188 u32 *xor_check_result;
189 u32 *crc32_result;
190 };
191};
192
193#endif /* _PPC440SPE_ADMA_H */