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1/*
2 * Intel I/OAT DMA Linux driver
3 * Copyright(c) 2004 - 2009 Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 */
22
23/*
24 * This driver supports an Intel I/OAT DMA engine (versions >= 2), which
25 * does asynchronous data movement and checksumming operations.
26 */
27
28#include <linux/init.h>
29#include <linux/module.h>
30#include <linux/slab.h>
31#include <linux/pci.h>
32#include <linux/interrupt.h>
33#include <linux/dmaengine.h>
34#include <linux/delay.h>
35#include <linux/dma-mapping.h>
36#include <linux/workqueue.h>
37#include <linux/prefetch.h>
38#include <linux/i7300_idle.h>
39#include "dma.h"
40#include "dma_v2.h"
41#include "registers.h"
42#include "hw.h"
43
44#include "../dmaengine.h"
45
46int ioat_ring_alloc_order = 8;
47module_param(ioat_ring_alloc_order, int, 0644);
48MODULE_PARM_DESC(ioat_ring_alloc_order,
49 "ioat2+: allocate 2^n descriptors per channel"
50 " (default: 8 max: 16)");
51static int ioat_ring_max_alloc_order = IOAT_MAX_ORDER;
52module_param(ioat_ring_max_alloc_order, int, 0644);
53MODULE_PARM_DESC(ioat_ring_max_alloc_order,
54 "ioat2+: upper limit for ring size (default: 16)");
55
56void __ioat2_issue_pending(struct ioat2_dma_chan *ioat)
57{
58 struct ioat_chan_common *chan = &ioat->base;
59
60 ioat->dmacount += ioat2_ring_pending(ioat);
61 ioat->issued = ioat->head;
62 writew(ioat->dmacount, chan->reg_base + IOAT_CHAN_DMACOUNT_OFFSET);
63 dev_dbg(to_dev(chan),
64 "%s: head: %#x tail: %#x issued: %#x count: %#x\n",
65 __func__, ioat->head, ioat->tail, ioat->issued, ioat->dmacount);
66}
67
68void ioat2_issue_pending(struct dma_chan *c)
69{
70 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
71
72 if (ioat2_ring_pending(ioat)) {
73 spin_lock_bh(&ioat->prep_lock);
74 __ioat2_issue_pending(ioat);
75 spin_unlock_bh(&ioat->prep_lock);
76 }
77}
78
79/**
80 * ioat2_update_pending - log pending descriptors
81 * @ioat: ioat2+ channel
82 *
83 * Check if the number of unsubmitted descriptors has exceeded the
84 * watermark. Called with prep_lock held
85 */
86static void ioat2_update_pending(struct ioat2_dma_chan *ioat)
87{
88 if (ioat2_ring_pending(ioat) > ioat_pending_level)
89 __ioat2_issue_pending(ioat);
90}
91
92static void __ioat2_start_null_desc(struct ioat2_dma_chan *ioat)
93{
94 struct ioat_ring_ent *desc;
95 struct ioat_dma_descriptor *hw;
96
97 if (ioat2_ring_space(ioat) < 1) {
98 dev_err(to_dev(&ioat->base),
99 "Unable to start null desc - ring full\n");
100 return;
101 }
102
103 dev_dbg(to_dev(&ioat->base), "%s: head: %#x tail: %#x issued: %#x\n",
104 __func__, ioat->head, ioat->tail, ioat->issued);
105 desc = ioat2_get_ring_ent(ioat, ioat->head);
106
107 hw = desc->hw;
108 hw->ctl = 0;
109 hw->ctl_f.null = 1;
110 hw->ctl_f.int_en = 1;
111 hw->ctl_f.compl_write = 1;
112 /* set size to non-zero value (channel returns error when size is 0) */
113 hw->size = NULL_DESC_BUFFER_SIZE;
114 hw->src_addr = 0;
115 hw->dst_addr = 0;
116 async_tx_ack(&desc->txd);
117 ioat2_set_chainaddr(ioat, desc->txd.phys);
118 dump_desc_dbg(ioat, desc);
119 wmb();
120 ioat->head += 1;
121 __ioat2_issue_pending(ioat);
122}
123
124static void ioat2_start_null_desc(struct ioat2_dma_chan *ioat)
125{
126 spin_lock_bh(&ioat->prep_lock);
127 __ioat2_start_null_desc(ioat);
128 spin_unlock_bh(&ioat->prep_lock);
129}
130
131static void __cleanup(struct ioat2_dma_chan *ioat, dma_addr_t phys_complete)
132{
133 struct ioat_chan_common *chan = &ioat->base;
134 struct dma_async_tx_descriptor *tx;
135 struct ioat_ring_ent *desc;
136 bool seen_current = false;
137 u16 active;
138 int idx = ioat->tail, i;
139
140 dev_dbg(to_dev(chan), "%s: head: %#x tail: %#x issued: %#x\n",
141 __func__, ioat->head, ioat->tail, ioat->issued);
142
143 active = ioat2_ring_active(ioat);
144 for (i = 0; i < active && !seen_current; i++) {
145 smp_read_barrier_depends();
146 prefetch(ioat2_get_ring_ent(ioat, idx + i + 1));
147 desc = ioat2_get_ring_ent(ioat, idx + i);
148 tx = &desc->txd;
149 dump_desc_dbg(ioat, desc);
150 if (tx->cookie) {
151 ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw);
152 dma_cookie_complete(tx);
153 if (tx->callback) {
154 tx->callback(tx->callback_param);
155 tx->callback = NULL;
156 }
157 }
158
159 if (tx->phys == phys_complete)
160 seen_current = true;
161 }
162 smp_mb(); /* finish all descriptor reads before incrementing tail */
163 ioat->tail = idx + i;
164 BUG_ON(active && !seen_current); /* no active descs have written a completion? */
165
166 chan->last_completion = phys_complete;
167 if (active - i == 0) {
168 dev_dbg(to_dev(chan), "%s: cancel completion timeout\n",
169 __func__);
170 clear_bit(IOAT_COMPLETION_PENDING, &chan->state);
171 mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT);
172 }
173}
174
175/**
176 * ioat2_cleanup - clean finished descriptors (advance tail pointer)
177 * @chan: ioat channel to be cleaned up
178 */
179static void ioat2_cleanup(struct ioat2_dma_chan *ioat)
180{
181 struct ioat_chan_common *chan = &ioat->base;
182 dma_addr_t phys_complete;
183
184 spin_lock_bh(&chan->cleanup_lock);
185 if (ioat_cleanup_preamble(chan, &phys_complete))
186 __cleanup(ioat, phys_complete);
187 spin_unlock_bh(&chan->cleanup_lock);
188}
189
190void ioat2_cleanup_event(unsigned long data)
191{
192 struct ioat2_dma_chan *ioat = to_ioat2_chan((void *) data);
193
194 ioat2_cleanup(ioat);
195 writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET);
196}
197
198void __ioat2_restart_chan(struct ioat2_dma_chan *ioat)
199{
200 struct ioat_chan_common *chan = &ioat->base;
201
202 /* set the tail to be re-issued */
203 ioat->issued = ioat->tail;
204 ioat->dmacount = 0;
205 set_bit(IOAT_COMPLETION_PENDING, &chan->state);
206 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
207
208 dev_dbg(to_dev(chan),
209 "%s: head: %#x tail: %#x issued: %#x count: %#x\n",
210 __func__, ioat->head, ioat->tail, ioat->issued, ioat->dmacount);
211
212 if (ioat2_ring_pending(ioat)) {
213 struct ioat_ring_ent *desc;
214
215 desc = ioat2_get_ring_ent(ioat, ioat->tail);
216 ioat2_set_chainaddr(ioat, desc->txd.phys);
217 __ioat2_issue_pending(ioat);
218 } else
219 __ioat2_start_null_desc(ioat);
220}
221
222int ioat2_quiesce(struct ioat_chan_common *chan, unsigned long tmo)
223{
224 unsigned long end = jiffies + tmo;
225 int err = 0;
226 u32 status;
227
228 status = ioat_chansts(chan);
229 if (is_ioat_active(status) || is_ioat_idle(status))
230 ioat_suspend(chan);
231 while (is_ioat_active(status) || is_ioat_idle(status)) {
232 if (tmo && time_after(jiffies, end)) {
233 err = -ETIMEDOUT;
234 break;
235 }
236 status = ioat_chansts(chan);
237 cpu_relax();
238 }
239
240 return err;
241}
242
243int ioat2_reset_sync(struct ioat_chan_common *chan, unsigned long tmo)
244{
245 unsigned long end = jiffies + tmo;
246 int err = 0;
247
248 ioat_reset(chan);
249 while (ioat_reset_pending(chan)) {
250 if (end && time_after(jiffies, end)) {
251 err = -ETIMEDOUT;
252 break;
253 }
254 cpu_relax();
255 }
256
257 return err;
258}
259
260static void ioat2_restart_channel(struct ioat2_dma_chan *ioat)
261{
262 struct ioat_chan_common *chan = &ioat->base;
263 dma_addr_t phys_complete;
264
265 ioat2_quiesce(chan, 0);
266 if (ioat_cleanup_preamble(chan, &phys_complete))
267 __cleanup(ioat, phys_complete);
268
269 __ioat2_restart_chan(ioat);
270}
271
272void ioat2_timer_event(unsigned long data)
273{
274 struct ioat2_dma_chan *ioat = to_ioat2_chan((void *) data);
275 struct ioat_chan_common *chan = &ioat->base;
276
277 if (test_bit(IOAT_COMPLETION_PENDING, &chan->state)) {
278 dma_addr_t phys_complete;
279 u64 status;
280
281 status = ioat_chansts(chan);
282
283 /* when halted due to errors check for channel
284 * programming errors before advancing the completion state
285 */
286 if (is_ioat_halted(status)) {
287 u32 chanerr;
288
289 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
290 dev_err(to_dev(chan), "%s: Channel halted (%x)\n",
291 __func__, chanerr);
292 if (test_bit(IOAT_RUN, &chan->state))
293 BUG_ON(is_ioat_bug(chanerr));
294 else /* we never got off the ground */
295 return;
296 }
297
298 /* if we haven't made progress and we have already
299 * acknowledged a pending completion once, then be more
300 * forceful with a restart
301 */
302 spin_lock_bh(&chan->cleanup_lock);
303 if (ioat_cleanup_preamble(chan, &phys_complete)) {
304 __cleanup(ioat, phys_complete);
305 } else if (test_bit(IOAT_COMPLETION_ACK, &chan->state)) {
306 spin_lock_bh(&ioat->prep_lock);
307 ioat2_restart_channel(ioat);
308 spin_unlock_bh(&ioat->prep_lock);
309 } else {
310 set_bit(IOAT_COMPLETION_ACK, &chan->state);
311 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
312 }
313 spin_unlock_bh(&chan->cleanup_lock);
314 } else {
315 u16 active;
316
317 /* if the ring is idle, empty, and oversized try to step
318 * down the size
319 */
320 spin_lock_bh(&chan->cleanup_lock);
321 spin_lock_bh(&ioat->prep_lock);
322 active = ioat2_ring_active(ioat);
323 if (active == 0 && ioat->alloc_order > ioat_get_alloc_order())
324 reshape_ring(ioat, ioat->alloc_order-1);
325 spin_unlock_bh(&ioat->prep_lock);
326 spin_unlock_bh(&chan->cleanup_lock);
327
328 /* keep shrinking until we get back to our minimum
329 * default size
330 */
331 if (ioat->alloc_order > ioat_get_alloc_order())
332 mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT);
333 }
334}
335
336static int ioat2_reset_hw(struct ioat_chan_common *chan)
337{
338 /* throw away whatever the channel was doing and get it initialized */
339 u32 chanerr;
340
341 ioat2_quiesce(chan, msecs_to_jiffies(100));
342
343 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
344 writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET);
345
346 return ioat2_reset_sync(chan, msecs_to_jiffies(200));
347}
348
349/**
350 * ioat2_enumerate_channels - find and initialize the device's channels
351 * @device: the device to be enumerated
352 */
353int ioat2_enumerate_channels(struct ioatdma_device *device)
354{
355 struct ioat2_dma_chan *ioat;
356 struct device *dev = &device->pdev->dev;
357 struct dma_device *dma = &device->common;
358 u8 xfercap_log;
359 int i;
360
361 INIT_LIST_HEAD(&dma->channels);
362 dma->chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET);
363 dma->chancnt &= 0x1f; /* bits [4:0] valid */
364 if (dma->chancnt > ARRAY_SIZE(device->idx)) {
365 dev_warn(dev, "(%d) exceeds max supported channels (%zu)\n",
366 dma->chancnt, ARRAY_SIZE(device->idx));
367 dma->chancnt = ARRAY_SIZE(device->idx);
368 }
369 xfercap_log = readb(device->reg_base + IOAT_XFERCAP_OFFSET);
370 xfercap_log &= 0x1f; /* bits [4:0] valid */
371 if (xfercap_log == 0)
372 return 0;
373 dev_dbg(dev, "%s: xfercap = %d\n", __func__, 1 << xfercap_log);
374
375 /* FIXME which i/oat version is i7300? */
376#ifdef CONFIG_I7300_IDLE_IOAT_CHANNEL
377 if (i7300_idle_platform_probe(NULL, NULL, 1) == 0)
378 dma->chancnt--;
379#endif
380 for (i = 0; i < dma->chancnt; i++) {
381 ioat = devm_kzalloc(dev, sizeof(*ioat), GFP_KERNEL);
382 if (!ioat)
383 break;
384
385 ioat_init_channel(device, &ioat->base, i);
386 ioat->xfercap_log = xfercap_log;
387 spin_lock_init(&ioat->prep_lock);
388 if (device->reset_hw(&ioat->base)) {
389 i = 0;
390 break;
391 }
392 }
393 dma->chancnt = i;
394 return i;
395}
396
397static dma_cookie_t ioat2_tx_submit_unlock(struct dma_async_tx_descriptor *tx)
398{
399 struct dma_chan *c = tx->chan;
400 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
401 struct ioat_chan_common *chan = &ioat->base;
402 dma_cookie_t cookie;
403
404 cookie = dma_cookie_assign(tx);
405 dev_dbg(to_dev(&ioat->base), "%s: cookie: %d\n", __func__, cookie);
406
407 if (!test_and_set_bit(IOAT_COMPLETION_PENDING, &chan->state))
408 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
409
410 /* make descriptor updates visible before advancing ioat->head,
411 * this is purposefully not smp_wmb() since we are also
412 * publishing the descriptor updates to a dma device
413 */
414 wmb();
415
416 ioat->head += ioat->produce;
417
418 ioat2_update_pending(ioat);
419 spin_unlock_bh(&ioat->prep_lock);
420
421 return cookie;
422}
423
424static struct ioat_ring_ent *ioat2_alloc_ring_ent(struct dma_chan *chan, gfp_t flags)
425{
426 struct ioat_dma_descriptor *hw;
427 struct ioat_ring_ent *desc;
428 struct ioatdma_device *dma;
429 dma_addr_t phys;
430
431 dma = to_ioatdma_device(chan->device);
432 hw = pci_pool_alloc(dma->dma_pool, flags, &phys);
433 if (!hw)
434 return NULL;
435 memset(hw, 0, sizeof(*hw));
436
437 desc = kmem_cache_alloc(ioat2_cache, flags);
438 if (!desc) {
439 pci_pool_free(dma->dma_pool, hw, phys);
440 return NULL;
441 }
442 memset(desc, 0, sizeof(*desc));
443
444 dma_async_tx_descriptor_init(&desc->txd, chan);
445 desc->txd.tx_submit = ioat2_tx_submit_unlock;
446 desc->hw = hw;
447 desc->txd.phys = phys;
448 return desc;
449}
450
451static void ioat2_free_ring_ent(struct ioat_ring_ent *desc, struct dma_chan *chan)
452{
453 struct ioatdma_device *dma;
454
455 dma = to_ioatdma_device(chan->device);
456 pci_pool_free(dma->dma_pool, desc->hw, desc->txd.phys);
457 kmem_cache_free(ioat2_cache, desc);
458}
459
460static struct ioat_ring_ent **ioat2_alloc_ring(struct dma_chan *c, int order, gfp_t flags)
461{
462 struct ioat_ring_ent **ring;
463 int descs = 1 << order;
464 int i;
465
466 if (order > ioat_get_max_alloc_order())
467 return NULL;
468
469 /* allocate the array to hold the software ring */
470 ring = kcalloc(descs, sizeof(*ring), flags);
471 if (!ring)
472 return NULL;
473 for (i = 0; i < descs; i++) {
474 ring[i] = ioat2_alloc_ring_ent(c, flags);
475 if (!ring[i]) {
476 while (i--)
477 ioat2_free_ring_ent(ring[i], c);
478 kfree(ring);
479 return NULL;
480 }
481 set_desc_id(ring[i], i);
482 }
483
484 /* link descs */
485 for (i = 0; i < descs-1; i++) {
486 struct ioat_ring_ent *next = ring[i+1];
487 struct ioat_dma_descriptor *hw = ring[i]->hw;
488
489 hw->next = next->txd.phys;
490 }
491 ring[i]->hw->next = ring[0]->txd.phys;
492
493 return ring;
494}
495
496void ioat2_free_chan_resources(struct dma_chan *c);
497
498/* ioat2_alloc_chan_resources - allocate/initialize ioat2 descriptor ring
499 * @chan: channel to be initialized
500 */
501int ioat2_alloc_chan_resources(struct dma_chan *c)
502{
503 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
504 struct ioat_chan_common *chan = &ioat->base;
505 struct ioat_ring_ent **ring;
506 u64 status;
507 int order;
508 int i = 0;
509
510 /* have we already been set up? */
511 if (ioat->ring)
512 return 1 << ioat->alloc_order;
513
514 /* Setup register to interrupt and write completion status on error */
515 writew(IOAT_CHANCTRL_RUN, chan->reg_base + IOAT_CHANCTRL_OFFSET);
516
517 /* allocate a completion writeback area */
518 /* doing 2 32bit writes to mmio since 1 64b write doesn't work */
519 chan->completion = pci_pool_alloc(chan->device->completion_pool,
520 GFP_KERNEL, &chan->completion_dma);
521 if (!chan->completion)
522 return -ENOMEM;
523
524 memset(chan->completion, 0, sizeof(*chan->completion));
525 writel(((u64) chan->completion_dma) & 0x00000000FFFFFFFF,
526 chan->reg_base + IOAT_CHANCMP_OFFSET_LOW);
527 writel(((u64) chan->completion_dma) >> 32,
528 chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH);
529
530 order = ioat_get_alloc_order();
531 ring = ioat2_alloc_ring(c, order, GFP_KERNEL);
532 if (!ring)
533 return -ENOMEM;
534
535 spin_lock_bh(&chan->cleanup_lock);
536 spin_lock_bh(&ioat->prep_lock);
537 ioat->ring = ring;
538 ioat->head = 0;
539 ioat->issued = 0;
540 ioat->tail = 0;
541 ioat->alloc_order = order;
542 spin_unlock_bh(&ioat->prep_lock);
543 spin_unlock_bh(&chan->cleanup_lock);
544
545 tasklet_enable(&chan->cleanup_task);
546 ioat2_start_null_desc(ioat);
547
548 /* check that we got off the ground */
549 do {
550 udelay(1);
551 status = ioat_chansts(chan);
552 } while (i++ < 20 && !is_ioat_active(status) && !is_ioat_idle(status));
553
554 if (is_ioat_active(status) || is_ioat_idle(status)) {
555 set_bit(IOAT_RUN, &chan->state);
556 return 1 << ioat->alloc_order;
557 } else {
558 u32 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
559
560 dev_WARN(to_dev(chan),
561 "failed to start channel chanerr: %#x\n", chanerr);
562 ioat2_free_chan_resources(c);
563 return -EFAULT;
564 }
565}
566
567bool reshape_ring(struct ioat2_dma_chan *ioat, int order)
568{
569 /* reshape differs from normal ring allocation in that we want
570 * to allocate a new software ring while only
571 * extending/truncating the hardware ring
572 */
573 struct ioat_chan_common *chan = &ioat->base;
574 struct dma_chan *c = &chan->common;
575 const u32 curr_size = ioat2_ring_size(ioat);
576 const u16 active = ioat2_ring_active(ioat);
577 const u32 new_size = 1 << order;
578 struct ioat_ring_ent **ring;
579 u16 i;
580
581 if (order > ioat_get_max_alloc_order())
582 return false;
583
584 /* double check that we have at least 1 free descriptor */
585 if (active == curr_size)
586 return false;
587
588 /* when shrinking, verify that we can hold the current active
589 * set in the new ring
590 */
591 if (active >= new_size)
592 return false;
593
594 /* allocate the array to hold the software ring */
595 ring = kcalloc(new_size, sizeof(*ring), GFP_NOWAIT);
596 if (!ring)
597 return false;
598
599 /* allocate/trim descriptors as needed */
600 if (new_size > curr_size) {
601 /* copy current descriptors to the new ring */
602 for (i = 0; i < curr_size; i++) {
603 u16 curr_idx = (ioat->tail+i) & (curr_size-1);
604 u16 new_idx = (ioat->tail+i) & (new_size-1);
605
606 ring[new_idx] = ioat->ring[curr_idx];
607 set_desc_id(ring[new_idx], new_idx);
608 }
609
610 /* add new descriptors to the ring */
611 for (i = curr_size; i < new_size; i++) {
612 u16 new_idx = (ioat->tail+i) & (new_size-1);
613
614 ring[new_idx] = ioat2_alloc_ring_ent(c, GFP_NOWAIT);
615 if (!ring[new_idx]) {
616 while (i--) {
617 u16 new_idx = (ioat->tail+i) & (new_size-1);
618
619 ioat2_free_ring_ent(ring[new_idx], c);
620 }
621 kfree(ring);
622 return false;
623 }
624 set_desc_id(ring[new_idx], new_idx);
625 }
626
627 /* hw link new descriptors */
628 for (i = curr_size-1; i < new_size; i++) {
629 u16 new_idx = (ioat->tail+i) & (new_size-1);
630 struct ioat_ring_ent *next = ring[(new_idx+1) & (new_size-1)];
631 struct ioat_dma_descriptor *hw = ring[new_idx]->hw;
632
633 hw->next = next->txd.phys;
634 }
635 } else {
636 struct ioat_dma_descriptor *hw;
637 struct ioat_ring_ent *next;
638
639 /* copy current descriptors to the new ring, dropping the
640 * removed descriptors
641 */
642 for (i = 0; i < new_size; i++) {
643 u16 curr_idx = (ioat->tail+i) & (curr_size-1);
644 u16 new_idx = (ioat->tail+i) & (new_size-1);
645
646 ring[new_idx] = ioat->ring[curr_idx];
647 set_desc_id(ring[new_idx], new_idx);
648 }
649
650 /* free deleted descriptors */
651 for (i = new_size; i < curr_size; i++) {
652 struct ioat_ring_ent *ent;
653
654 ent = ioat2_get_ring_ent(ioat, ioat->tail+i);
655 ioat2_free_ring_ent(ent, c);
656 }
657
658 /* fix up hardware ring */
659 hw = ring[(ioat->tail+new_size-1) & (new_size-1)]->hw;
660 next = ring[(ioat->tail+new_size) & (new_size-1)];
661 hw->next = next->txd.phys;
662 }
663
664 dev_dbg(to_dev(chan), "%s: allocated %d descriptors\n",
665 __func__, new_size);
666
667 kfree(ioat->ring);
668 ioat->ring = ring;
669 ioat->alloc_order = order;
670
671 return true;
672}
673
674/**
675 * ioat2_check_space_lock - verify space and grab ring producer lock
676 * @ioat: ioat2,3 channel (ring) to operate on
677 * @num_descs: allocation length
678 */
679int ioat2_check_space_lock(struct ioat2_dma_chan *ioat, int num_descs)
680{
681 struct ioat_chan_common *chan = &ioat->base;
682 bool retry;
683
684 retry:
685 spin_lock_bh(&ioat->prep_lock);
686 /* never allow the last descriptor to be consumed, we need at
687 * least one free at all times to allow for on-the-fly ring
688 * resizing.
689 */
690 if (likely(ioat2_ring_space(ioat) > num_descs)) {
691 dev_dbg(to_dev(chan), "%s: num_descs: %d (%x:%x:%x)\n",
692 __func__, num_descs, ioat->head, ioat->tail, ioat->issued);
693 ioat->produce = num_descs;
694 return 0; /* with ioat->prep_lock held */
695 }
696 retry = test_and_set_bit(IOAT_RESHAPE_PENDING, &chan->state);
697 spin_unlock_bh(&ioat->prep_lock);
698
699 /* is another cpu already trying to expand the ring? */
700 if (retry)
701 goto retry;
702
703 spin_lock_bh(&chan->cleanup_lock);
704 spin_lock_bh(&ioat->prep_lock);
705 retry = reshape_ring(ioat, ioat->alloc_order + 1);
706 clear_bit(IOAT_RESHAPE_PENDING, &chan->state);
707 spin_unlock_bh(&ioat->prep_lock);
708 spin_unlock_bh(&chan->cleanup_lock);
709
710 /* if we were able to expand the ring retry the allocation */
711 if (retry)
712 goto retry;
713
714 if (printk_ratelimit())
715 dev_dbg(to_dev(chan), "%s: ring full! num_descs: %d (%x:%x:%x)\n",
716 __func__, num_descs, ioat->head, ioat->tail, ioat->issued);
717
718 /* progress reclaim in the allocation failure case we may be
719 * called under bh_disabled so we need to trigger the timer
720 * event directly
721 */
722 if (jiffies > chan->timer.expires && timer_pending(&chan->timer)) {
723 struct ioatdma_device *device = chan->device;
724
725 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
726 device->timer_fn((unsigned long) &chan->common);
727 }
728
729 return -ENOMEM;
730}
731
732struct dma_async_tx_descriptor *
733ioat2_dma_prep_memcpy_lock(struct dma_chan *c, dma_addr_t dma_dest,
734 dma_addr_t dma_src, size_t len, unsigned long flags)
735{
736 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
737 struct ioat_dma_descriptor *hw;
738 struct ioat_ring_ent *desc;
739 dma_addr_t dst = dma_dest;
740 dma_addr_t src = dma_src;
741 size_t total_len = len;
742 int num_descs, idx, i;
743
744 num_descs = ioat2_xferlen_to_descs(ioat, len);
745 if (likely(num_descs) && ioat2_check_space_lock(ioat, num_descs) == 0)
746 idx = ioat->head;
747 else
748 return NULL;
749 i = 0;
750 do {
751 size_t copy = min_t(size_t, len, 1 << ioat->xfercap_log);
752
753 desc = ioat2_get_ring_ent(ioat, idx + i);
754 hw = desc->hw;
755
756 hw->size = copy;
757 hw->ctl = 0;
758 hw->src_addr = src;
759 hw->dst_addr = dst;
760
761 len -= copy;
762 dst += copy;
763 src += copy;
764 dump_desc_dbg(ioat, desc);
765 } while (++i < num_descs);
766
767 desc->txd.flags = flags;
768 desc->len = total_len;
769 hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
770 hw->ctl_f.fence = !!(flags & DMA_PREP_FENCE);
771 hw->ctl_f.compl_write = 1;
772 dump_desc_dbg(ioat, desc);
773 /* we leave the channel locked to ensure in order submission */
774
775 return &desc->txd;
776}
777
778/**
779 * ioat2_free_chan_resources - release all the descriptors
780 * @chan: the channel to be cleaned
781 */
782void ioat2_free_chan_resources(struct dma_chan *c)
783{
784 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
785 struct ioat_chan_common *chan = &ioat->base;
786 struct ioatdma_device *device = chan->device;
787 struct ioat_ring_ent *desc;
788 const u16 total_descs = 1 << ioat->alloc_order;
789 int descs;
790 int i;
791
792 /* Before freeing channel resources first check
793 * if they have been previously allocated for this channel.
794 */
795 if (!ioat->ring)
796 return;
797
798 tasklet_disable(&chan->cleanup_task);
799 del_timer_sync(&chan->timer);
800 device->cleanup_fn((unsigned long) c);
801 device->reset_hw(chan);
802 clear_bit(IOAT_RUN, &chan->state);
803
804 spin_lock_bh(&chan->cleanup_lock);
805 spin_lock_bh(&ioat->prep_lock);
806 descs = ioat2_ring_space(ioat);
807 dev_dbg(to_dev(chan), "freeing %d idle descriptors\n", descs);
808 for (i = 0; i < descs; i++) {
809 desc = ioat2_get_ring_ent(ioat, ioat->head + i);
810 ioat2_free_ring_ent(desc, c);
811 }
812
813 if (descs < total_descs)
814 dev_err(to_dev(chan), "Freeing %d in use descriptors!\n",
815 total_descs - descs);
816
817 for (i = 0; i < total_descs - descs; i++) {
818 desc = ioat2_get_ring_ent(ioat, ioat->tail + i);
819 dump_desc_dbg(ioat, desc);
820 ioat2_free_ring_ent(desc, c);
821 }
822
823 kfree(ioat->ring);
824 ioat->ring = NULL;
825 ioat->alloc_order = 0;
826 pci_pool_free(device->completion_pool, chan->completion,
827 chan->completion_dma);
828 spin_unlock_bh(&ioat->prep_lock);
829 spin_unlock_bh(&chan->cleanup_lock);
830
831 chan->last_completion = 0;
832 chan->completion_dma = 0;
833 ioat->dmacount = 0;
834}
835
836static ssize_t ring_size_show(struct dma_chan *c, char *page)
837{
838 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
839
840 return sprintf(page, "%d\n", (1 << ioat->alloc_order) & ~1);
841}
842static struct ioat_sysfs_entry ring_size_attr = __ATTR_RO(ring_size);
843
844static ssize_t ring_active_show(struct dma_chan *c, char *page)
845{
846 struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
847
848 /* ...taken outside the lock, no need to be precise */
849 return sprintf(page, "%d\n", ioat2_ring_active(ioat));
850}
851static struct ioat_sysfs_entry ring_active_attr = __ATTR_RO(ring_active);
852
853static struct attribute *ioat2_attrs[] = {
854 &ring_size_attr.attr,
855 &ring_active_attr.attr,
856 &ioat_cap_attr.attr,
857 &ioat_version_attr.attr,
858 NULL,
859};
860
861struct kobj_type ioat2_ktype = {
862 .sysfs_ops = &ioat_sysfs_ops,
863 .default_attrs = ioat2_attrs,
864};
865
866int __devinit ioat2_dma_probe(struct ioatdma_device *device, int dca)
867{
868 struct pci_dev *pdev = device->pdev;
869 struct dma_device *dma;
870 struct dma_chan *c;
871 struct ioat_chan_common *chan;
872 int err;
873
874 device->enumerate_channels = ioat2_enumerate_channels;
875 device->reset_hw = ioat2_reset_hw;
876 device->cleanup_fn = ioat2_cleanup_event;
877 device->timer_fn = ioat2_timer_event;
878 device->self_test = ioat_dma_self_test;
879 dma = &device->common;
880 dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy_lock;
881 dma->device_issue_pending = ioat2_issue_pending;
882 dma->device_alloc_chan_resources = ioat2_alloc_chan_resources;
883 dma->device_free_chan_resources = ioat2_free_chan_resources;
884 dma->device_tx_status = ioat_dma_tx_status;
885
886 err = ioat_probe(device);
887 if (err)
888 return err;
889 ioat_set_tcp_copy_break(2048);
890
891 list_for_each_entry(c, &dma->channels, device_node) {
892 chan = to_chan_common(c);
893 writel(IOAT_DCACTRL_CMPL_WRITE_ENABLE | IOAT_DMA_DCA_ANY_CPU,
894 chan->reg_base + IOAT_DCACTRL_OFFSET);
895 }
896
897 err = ioat_register(device);
898 if (err)
899 return err;
900
901 ioat_kobject_add(device, &ioat2_ktype);
902
903 if (dca)
904 device->dca = ioat2_dca_init(pdev, device->reg_base);
905
906 return err;
907}