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1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * MMU support
8 *
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 *
12 * Authors:
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
21/*
22 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
23 * so the code in this file is compiled twice, once per pte size.
24 */
25
26#if PTTYPE == 64
27 #define pt_element_t u64
28 #define guest_walker guest_walker64
29 #define FNAME(name) paging##64_##name
30 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
31 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
32 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
33 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
34 #define PT_LEVEL_BITS PT64_LEVEL_BITS
35 #ifdef CONFIG_X86_64
36 #define PT_MAX_FULL_LEVELS 4
37 #define CMPXCHG cmpxchg
38 #else
39 #define CMPXCHG cmpxchg64
40 #define PT_MAX_FULL_LEVELS 2
41 #endif
42#elif PTTYPE == 32
43 #define pt_element_t u32
44 #define guest_walker guest_walker32
45 #define FNAME(name) paging##32_##name
46 #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
47 #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
48 #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
49 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
50 #define PT_LEVEL_BITS PT32_LEVEL_BITS
51 #define PT_MAX_FULL_LEVELS 2
52 #define CMPXCHG cmpxchg
53#else
54 #error Invalid PTTYPE value
55#endif
56
57#define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
58#define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL)
59
60/*
61 * The guest_walker structure emulates the behavior of the hardware page
62 * table walker.
63 */
64struct guest_walker {
65 int level;
66 gfn_t table_gfn[PT_MAX_FULL_LEVELS];
67 pt_element_t ptes[PT_MAX_FULL_LEVELS];
68 pt_element_t prefetch_ptes[PTE_PREFETCH_NUM];
69 gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
70 unsigned pt_access;
71 unsigned pte_access;
72 gfn_t gfn;
73 struct x86_exception fault;
74};
75
76static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
77{
78 return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
79}
80
81static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
82 pt_element_t __user *ptep_user, unsigned index,
83 pt_element_t orig_pte, pt_element_t new_pte)
84{
85 int npages;
86 pt_element_t ret;
87 pt_element_t *table;
88 struct page *page;
89
90 npages = get_user_pages_fast((unsigned long)ptep_user, 1, 1, &page);
91 /* Check if the user is doing something meaningless. */
92 if (unlikely(npages != 1))
93 return -EFAULT;
94
95 table = kmap_atomic(page);
96 ret = CMPXCHG(&table[index], orig_pte, new_pte);
97 kunmap_atomic(table);
98
99 kvm_release_page_dirty(page);
100
101 return (ret != orig_pte);
102}
103
104static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte,
105 bool last)
106{
107 unsigned access;
108
109 access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
110 if (last && !is_dirty_gpte(gpte))
111 access &= ~ACC_WRITE_MASK;
112
113#if PTTYPE == 64
114 if (vcpu->arch.mmu.nx)
115 access &= ~(gpte >> PT64_NX_SHIFT);
116#endif
117 return access;
118}
119
120static bool FNAME(is_last_gpte)(struct guest_walker *walker,
121 struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
122 pt_element_t gpte)
123{
124 if (walker->level == PT_PAGE_TABLE_LEVEL)
125 return true;
126
127 if ((walker->level == PT_DIRECTORY_LEVEL) && is_large_pte(gpte) &&
128 (PTTYPE == 64 || is_pse(vcpu)))
129 return true;
130
131 if ((walker->level == PT_PDPE_LEVEL) && is_large_pte(gpte) &&
132 (mmu->root_level == PT64_ROOT_LEVEL))
133 return true;
134
135 return false;
136}
137
138/*
139 * Fetch a guest pte for a guest virtual address
140 */
141static int FNAME(walk_addr_generic)(struct guest_walker *walker,
142 struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
143 gva_t addr, u32 access)
144{
145 pt_element_t pte;
146 pt_element_t __user *uninitialized_var(ptep_user);
147 gfn_t table_gfn;
148 unsigned index, pt_access, uninitialized_var(pte_access);
149 gpa_t pte_gpa;
150 bool eperm, last_gpte;
151 int offset;
152 const int write_fault = access & PFERR_WRITE_MASK;
153 const int user_fault = access & PFERR_USER_MASK;
154 const int fetch_fault = access & PFERR_FETCH_MASK;
155 u16 errcode = 0;
156
157 trace_kvm_mmu_pagetable_walk(addr, write_fault, user_fault,
158 fetch_fault);
159retry_walk:
160 eperm = false;
161 walker->level = mmu->root_level;
162 pte = mmu->get_cr3(vcpu);
163
164#if PTTYPE == 64
165 if (walker->level == PT32E_ROOT_LEVEL) {
166 pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3);
167 trace_kvm_mmu_paging_element(pte, walker->level);
168 if (!is_present_gpte(pte))
169 goto error;
170 --walker->level;
171 }
172#endif
173 ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
174 (mmu->get_cr3(vcpu) & CR3_NONPAE_RESERVED_BITS) == 0);
175
176 pt_access = ACC_ALL;
177
178 for (;;) {
179 gfn_t real_gfn;
180 unsigned long host_addr;
181
182 index = PT_INDEX(addr, walker->level);
183
184 table_gfn = gpte_to_gfn(pte);
185 offset = index * sizeof(pt_element_t);
186 pte_gpa = gfn_to_gpa(table_gfn) + offset;
187 walker->table_gfn[walker->level - 1] = table_gfn;
188 walker->pte_gpa[walker->level - 1] = pte_gpa;
189
190 real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn),
191 PFERR_USER_MASK|PFERR_WRITE_MASK);
192 if (unlikely(real_gfn == UNMAPPED_GVA))
193 goto error;
194 real_gfn = gpa_to_gfn(real_gfn);
195
196 host_addr = gfn_to_hva(vcpu->kvm, real_gfn);
197 if (unlikely(kvm_is_error_hva(host_addr)))
198 goto error;
199
200 ptep_user = (pt_element_t __user *)((void *)host_addr + offset);
201 if (unlikely(__copy_from_user(&pte, ptep_user, sizeof(pte))))
202 goto error;
203
204 trace_kvm_mmu_paging_element(pte, walker->level);
205
206 if (unlikely(!is_present_gpte(pte)))
207 goto error;
208
209 if (unlikely(is_rsvd_bits_set(&vcpu->arch.mmu, pte,
210 walker->level))) {
211 errcode |= PFERR_RSVD_MASK | PFERR_PRESENT_MASK;
212 goto error;
213 }
214
215 if (!check_write_user_access(vcpu, write_fault, user_fault,
216 pte))
217 eperm = true;
218
219#if PTTYPE == 64
220 if (unlikely(fetch_fault && (pte & PT64_NX_MASK)))
221 eperm = true;
222#endif
223
224 last_gpte = FNAME(is_last_gpte)(walker, vcpu, mmu, pte);
225 if (last_gpte) {
226 pte_access = pt_access &
227 FNAME(gpte_access)(vcpu, pte, true);
228 /* check if the kernel is fetching from user page */
229 if (unlikely(pte_access & PT_USER_MASK) &&
230 kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))
231 if (fetch_fault && !user_fault)
232 eperm = true;
233 }
234
235 if (!eperm && unlikely(!(pte & PT_ACCESSED_MASK))) {
236 int ret;
237 trace_kvm_mmu_set_accessed_bit(table_gfn, index,
238 sizeof(pte));
239 ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index,
240 pte, pte|PT_ACCESSED_MASK);
241 if (unlikely(ret < 0))
242 goto error;
243 else if (ret)
244 goto retry_walk;
245
246 mark_page_dirty(vcpu->kvm, table_gfn);
247 pte |= PT_ACCESSED_MASK;
248 }
249
250 walker->ptes[walker->level - 1] = pte;
251
252 if (last_gpte) {
253 int lvl = walker->level;
254 gpa_t real_gpa;
255 gfn_t gfn;
256 u32 ac;
257
258 gfn = gpte_to_gfn_lvl(pte, lvl);
259 gfn += (addr & PT_LVL_OFFSET_MASK(lvl)) >> PAGE_SHIFT;
260
261 if (PTTYPE == 32 &&
262 walker->level == PT_DIRECTORY_LEVEL &&
263 is_cpuid_PSE36())
264 gfn += pse36_gfn_delta(pte);
265
266 ac = write_fault | fetch_fault | user_fault;
267
268 real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn),
269 ac);
270 if (real_gpa == UNMAPPED_GVA)
271 return 0;
272
273 walker->gfn = real_gpa >> PAGE_SHIFT;
274
275 break;
276 }
277
278 pt_access &= FNAME(gpte_access)(vcpu, pte, false);
279 --walker->level;
280 }
281
282 if (unlikely(eperm)) {
283 errcode |= PFERR_PRESENT_MASK;
284 goto error;
285 }
286
287 if (write_fault && unlikely(!is_dirty_gpte(pte))) {
288 int ret;
289
290 trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
291 ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index,
292 pte, pte|PT_DIRTY_MASK);
293 if (unlikely(ret < 0))
294 goto error;
295 else if (ret)
296 goto retry_walk;
297
298 mark_page_dirty(vcpu->kvm, table_gfn);
299 pte |= PT_DIRTY_MASK;
300 walker->ptes[walker->level - 1] = pte;
301 }
302
303 walker->pt_access = pt_access;
304 walker->pte_access = pte_access;
305 pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
306 __func__, (u64)pte, pte_access, pt_access);
307 return 1;
308
309error:
310 errcode |= write_fault | user_fault;
311 if (fetch_fault && (mmu->nx ||
312 kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)))
313 errcode |= PFERR_FETCH_MASK;
314
315 walker->fault.vector = PF_VECTOR;
316 walker->fault.error_code_valid = true;
317 walker->fault.error_code = errcode;
318 walker->fault.address = addr;
319 walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu;
320
321 trace_kvm_mmu_walker_error(walker->fault.error_code);
322 return 0;
323}
324
325static int FNAME(walk_addr)(struct guest_walker *walker,
326 struct kvm_vcpu *vcpu, gva_t addr, u32 access)
327{
328 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr,
329 access);
330}
331
332static int FNAME(walk_addr_nested)(struct guest_walker *walker,
333 struct kvm_vcpu *vcpu, gva_t addr,
334 u32 access)
335{
336 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu,
337 addr, access);
338}
339
340static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu,
341 struct kvm_mmu_page *sp, u64 *spte,
342 pt_element_t gpte)
343{
344 if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL))
345 goto no_present;
346
347 if (!is_present_gpte(gpte))
348 goto no_present;
349
350 if (!(gpte & PT_ACCESSED_MASK))
351 goto no_present;
352
353 return false;
354
355no_present:
356 drop_spte(vcpu->kvm, spte);
357 return true;
358}
359
360static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
361 u64 *spte, const void *pte)
362{
363 pt_element_t gpte;
364 unsigned pte_access;
365 pfn_t pfn;
366
367 gpte = *(const pt_element_t *)pte;
368 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte))
369 return;
370
371 pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
372 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte, true);
373 pfn = gfn_to_pfn_atomic(vcpu->kvm, gpte_to_gfn(gpte));
374 if (mmu_invalid_pfn(pfn)) {
375 kvm_release_pfn_clean(pfn);
376 return;
377 }
378
379 /*
380 * we call mmu_set_spte() with host_writable = true because that
381 * vcpu->arch.update_pte.pfn was fetched from get_user_pages(write = 1).
382 */
383 mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0,
384 NULL, PT_PAGE_TABLE_LEVEL,
385 gpte_to_gfn(gpte), pfn, true, true);
386}
387
388static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu,
389 struct guest_walker *gw, int level)
390{
391 pt_element_t curr_pte;
392 gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1];
393 u64 mask;
394 int r, index;
395
396 if (level == PT_PAGE_TABLE_LEVEL) {
397 mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1;
398 base_gpa = pte_gpa & ~mask;
399 index = (pte_gpa - base_gpa) / sizeof(pt_element_t);
400
401 r = kvm_read_guest_atomic(vcpu->kvm, base_gpa,
402 gw->prefetch_ptes, sizeof(gw->prefetch_ptes));
403 curr_pte = gw->prefetch_ptes[index];
404 } else
405 r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa,
406 &curr_pte, sizeof(curr_pte));
407
408 return r || curr_pte != gw->ptes[level - 1];
409}
410
411static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw,
412 u64 *sptep)
413{
414 struct kvm_mmu_page *sp;
415 pt_element_t *gptep = gw->prefetch_ptes;
416 u64 *spte;
417 int i;
418
419 sp = page_header(__pa(sptep));
420
421 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
422 return;
423
424 if (sp->role.direct)
425 return __direct_pte_prefetch(vcpu, sp, sptep);
426
427 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
428 spte = sp->spt + i;
429
430 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
431 pt_element_t gpte;
432 unsigned pte_access;
433 gfn_t gfn;
434 pfn_t pfn;
435
436 if (spte == sptep)
437 continue;
438
439 if (is_shadow_present_pte(*spte))
440 continue;
441
442 gpte = gptep[i];
443
444 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte))
445 continue;
446
447 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte,
448 true);
449 gfn = gpte_to_gfn(gpte);
450 pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn,
451 pte_access & ACC_WRITE_MASK);
452 if (mmu_invalid_pfn(pfn)) {
453 kvm_release_pfn_clean(pfn);
454 break;
455 }
456
457 mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0,
458 NULL, PT_PAGE_TABLE_LEVEL, gfn,
459 pfn, true, true);
460 }
461}
462
463/*
464 * Fetch a shadow pte for a specific level in the paging hierarchy.
465 */
466static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
467 struct guest_walker *gw,
468 int user_fault, int write_fault, int hlevel,
469 int *emulate, pfn_t pfn, bool map_writable,
470 bool prefault)
471{
472 unsigned access = gw->pt_access;
473 struct kvm_mmu_page *sp = NULL;
474 int top_level;
475 unsigned direct_access;
476 struct kvm_shadow_walk_iterator it;
477
478 if (!is_present_gpte(gw->ptes[gw->level - 1]))
479 return NULL;
480
481 direct_access = gw->pte_access;
482
483 top_level = vcpu->arch.mmu.root_level;
484 if (top_level == PT32E_ROOT_LEVEL)
485 top_level = PT32_ROOT_LEVEL;
486 /*
487 * Verify that the top-level gpte is still there. Since the page
488 * is a root page, it is either write protected (and cannot be
489 * changed from now on) or it is invalid (in which case, we don't
490 * really care if it changes underneath us after this point).
491 */
492 if (FNAME(gpte_changed)(vcpu, gw, top_level))
493 goto out_gpte_changed;
494
495 for (shadow_walk_init(&it, vcpu, addr);
496 shadow_walk_okay(&it) && it.level > gw->level;
497 shadow_walk_next(&it)) {
498 gfn_t table_gfn;
499
500 clear_sp_write_flooding_count(it.sptep);
501 drop_large_spte(vcpu, it.sptep);
502
503 sp = NULL;
504 if (!is_shadow_present_pte(*it.sptep)) {
505 table_gfn = gw->table_gfn[it.level - 2];
506 sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1,
507 false, access, it.sptep);
508 }
509
510 /*
511 * Verify that the gpte in the page we've just write
512 * protected is still there.
513 */
514 if (FNAME(gpte_changed)(vcpu, gw, it.level - 1))
515 goto out_gpte_changed;
516
517 if (sp)
518 link_shadow_page(it.sptep, sp);
519 }
520
521 for (;
522 shadow_walk_okay(&it) && it.level > hlevel;
523 shadow_walk_next(&it)) {
524 gfn_t direct_gfn;
525
526 clear_sp_write_flooding_count(it.sptep);
527 validate_direct_spte(vcpu, it.sptep, direct_access);
528
529 drop_large_spte(vcpu, it.sptep);
530
531 if (is_shadow_present_pte(*it.sptep))
532 continue;
533
534 direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
535
536 sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1,
537 true, direct_access, it.sptep);
538 link_shadow_page(it.sptep, sp);
539 }
540
541 clear_sp_write_flooding_count(it.sptep);
542 mmu_set_spte(vcpu, it.sptep, access, gw->pte_access,
543 user_fault, write_fault, emulate, it.level,
544 gw->gfn, pfn, prefault, map_writable);
545 FNAME(pte_prefetch)(vcpu, gw, it.sptep);
546
547 return it.sptep;
548
549out_gpte_changed:
550 if (sp)
551 kvm_mmu_put_page(sp, it.sptep);
552 kvm_release_pfn_clean(pfn);
553 return NULL;
554}
555
556/*
557 * Page fault handler. There are several causes for a page fault:
558 * - there is no shadow pte for the guest pte
559 * - write access through a shadow pte marked read only so that we can set
560 * the dirty bit
561 * - write access to a shadow pte marked read only so we can update the page
562 * dirty bitmap, when userspace requests it
563 * - mmio access; in this case we will never install a present shadow pte
564 * - normal guest page fault due to the guest pte marked not present, not
565 * writable, or not executable
566 *
567 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
568 * a negative value on error.
569 */
570static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code,
571 bool prefault)
572{
573 int write_fault = error_code & PFERR_WRITE_MASK;
574 int user_fault = error_code & PFERR_USER_MASK;
575 struct guest_walker walker;
576 u64 *sptep;
577 int emulate = 0;
578 int r;
579 pfn_t pfn;
580 int level = PT_PAGE_TABLE_LEVEL;
581 int force_pt_level;
582 unsigned long mmu_seq;
583 bool map_writable;
584
585 pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
586
587 if (unlikely(error_code & PFERR_RSVD_MASK))
588 return handle_mmio_page_fault(vcpu, addr, error_code,
589 mmu_is_nested(vcpu));
590
591 r = mmu_topup_memory_caches(vcpu);
592 if (r)
593 return r;
594
595 /*
596 * Look up the guest pte for the faulting address.
597 */
598 r = FNAME(walk_addr)(&walker, vcpu, addr, error_code);
599
600 /*
601 * The page is not mapped by the guest. Let the guest handle it.
602 */
603 if (!r) {
604 pgprintk("%s: guest page fault\n", __func__);
605 if (!prefault)
606 inject_page_fault(vcpu, &walker.fault);
607
608 return 0;
609 }
610
611 if (walker.level >= PT_DIRECTORY_LEVEL)
612 force_pt_level = mapping_level_dirty_bitmap(vcpu, walker.gfn);
613 else
614 force_pt_level = 1;
615 if (!force_pt_level) {
616 level = min(walker.level, mapping_level(vcpu, walker.gfn));
617 walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
618 }
619
620 mmu_seq = vcpu->kvm->mmu_notifier_seq;
621 smp_rmb();
622
623 if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault,
624 &map_writable))
625 return 0;
626
627 if (handle_abnormal_pfn(vcpu, mmu_is_nested(vcpu) ? 0 : addr,
628 walker.gfn, pfn, walker.pte_access, &r))
629 return r;
630
631 spin_lock(&vcpu->kvm->mmu_lock);
632 if (mmu_notifier_retry(vcpu, mmu_seq))
633 goto out_unlock;
634
635 kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT);
636 kvm_mmu_free_some_pages(vcpu);
637 if (!force_pt_level)
638 transparent_hugepage_adjust(vcpu, &walker.gfn, &pfn, &level);
639 sptep = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
640 level, &emulate, pfn, map_writable, prefault);
641 (void)sptep;
642 pgprintk("%s: shadow pte %p %llx emulate %d\n", __func__,
643 sptep, *sptep, emulate);
644
645 ++vcpu->stat.pf_fixed;
646 kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT);
647 spin_unlock(&vcpu->kvm->mmu_lock);
648
649 return emulate;
650
651out_unlock:
652 spin_unlock(&vcpu->kvm->mmu_lock);
653 kvm_release_pfn_clean(pfn);
654 return 0;
655}
656
657static gpa_t FNAME(get_level1_sp_gpa)(struct kvm_mmu_page *sp)
658{
659 int offset = 0;
660
661 WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL);
662
663 if (PTTYPE == 32)
664 offset = sp->role.quadrant << PT64_LEVEL_BITS;
665
666 return gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
667}
668
669static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
670{
671 struct kvm_shadow_walk_iterator iterator;
672 struct kvm_mmu_page *sp;
673 int level;
674 u64 *sptep;
675
676 vcpu_clear_mmio_info(vcpu, gva);
677
678 /*
679 * No need to check return value here, rmap_can_add() can
680 * help us to skip pte prefetch later.
681 */
682 mmu_topup_memory_caches(vcpu);
683
684 spin_lock(&vcpu->kvm->mmu_lock);
685 for_each_shadow_entry(vcpu, gva, iterator) {
686 level = iterator.level;
687 sptep = iterator.sptep;
688
689 sp = page_header(__pa(sptep));
690 if (is_last_spte(*sptep, level)) {
691 pt_element_t gpte;
692 gpa_t pte_gpa;
693
694 if (!sp->unsync)
695 break;
696
697 pte_gpa = FNAME(get_level1_sp_gpa)(sp);
698 pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
699
700 if (mmu_page_zap_pte(vcpu->kvm, sp, sptep))
701 kvm_flush_remote_tlbs(vcpu->kvm);
702
703 if (!rmap_can_add(vcpu))
704 break;
705
706 if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
707 sizeof(pt_element_t)))
708 break;
709
710 FNAME(update_pte)(vcpu, sp, sptep, &gpte);
711 }
712
713 if (!is_shadow_present_pte(*sptep) || !sp->unsync_children)
714 break;
715 }
716 spin_unlock(&vcpu->kvm->mmu_lock);
717}
718
719static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access,
720 struct x86_exception *exception)
721{
722 struct guest_walker walker;
723 gpa_t gpa = UNMAPPED_GVA;
724 int r;
725
726 r = FNAME(walk_addr)(&walker, vcpu, vaddr, access);
727
728 if (r) {
729 gpa = gfn_to_gpa(walker.gfn);
730 gpa |= vaddr & ~PAGE_MASK;
731 } else if (exception)
732 *exception = walker.fault;
733
734 return gpa;
735}
736
737static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr,
738 u32 access,
739 struct x86_exception *exception)
740{
741 struct guest_walker walker;
742 gpa_t gpa = UNMAPPED_GVA;
743 int r;
744
745 r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access);
746
747 if (r) {
748 gpa = gfn_to_gpa(walker.gfn);
749 gpa |= vaddr & ~PAGE_MASK;
750 } else if (exception)
751 *exception = walker.fault;
752
753 return gpa;
754}
755
756/*
757 * Using the cached information from sp->gfns is safe because:
758 * - The spte has a reference to the struct page, so the pfn for a given gfn
759 * can't change unless all sptes pointing to it are nuked first.
760 *
761 * Note:
762 * We should flush all tlbs if spte is dropped even though guest is
763 * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page
764 * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't
765 * used by guest then tlbs are not flushed, so guest is allowed to access the
766 * freed pages.
767 * And we increase kvm->tlbs_dirty to delay tlbs flush in this case.
768 */
769static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
770{
771 int i, nr_present = 0;
772 bool host_writable;
773 gpa_t first_pte_gpa;
774
775 /* direct kvm_mmu_page can not be unsync. */
776 BUG_ON(sp->role.direct);
777
778 first_pte_gpa = FNAME(get_level1_sp_gpa)(sp);
779
780 for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
781 unsigned pte_access;
782 pt_element_t gpte;
783 gpa_t pte_gpa;
784 gfn_t gfn;
785
786 if (!sp->spt[i])
787 continue;
788
789 pte_gpa = first_pte_gpa + i * sizeof(pt_element_t);
790
791 if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
792 sizeof(pt_element_t)))
793 return -EINVAL;
794
795 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) {
796 vcpu->kvm->tlbs_dirty++;
797 continue;
798 }
799
800 gfn = gpte_to_gfn(gpte);
801 pte_access = sp->role.access;
802 pte_access &= FNAME(gpte_access)(vcpu, gpte, true);
803
804 if (sync_mmio_spte(&sp->spt[i], gfn, pte_access, &nr_present))
805 continue;
806
807 if (gfn != sp->gfns[i]) {
808 drop_spte(vcpu->kvm, &sp->spt[i]);
809 vcpu->kvm->tlbs_dirty++;
810 continue;
811 }
812
813 nr_present++;
814
815 host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE;
816
817 set_spte(vcpu, &sp->spt[i], pte_access, 0, 0,
818 PT_PAGE_TABLE_LEVEL, gfn,
819 spte_to_pfn(sp->spt[i]), true, false,
820 host_writable);
821 }
822
823 return !nr_present;
824}
825
826#undef pt_element_t
827#undef guest_walker
828#undef FNAME
829#undef PT_BASE_ADDR_MASK
830#undef PT_INDEX
831#undef PT_LVL_ADDR_MASK
832#undef PT_LVL_OFFSET_MASK
833#undef PT_LEVEL_BITS
834#undef PT_MAX_FULL_LEVELS
835#undef gpte_to_gfn
836#undef gpte_to_gfn_lvl
837#undef CMPXCHG