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1/*
2 * linux/arch/unicore32/kernel/pci.c
3 *
4 * Code specific to PKUnity SoC and UniCore ISA
5 *
6 * Copyright (C) 2001-2010 GUAN Xue-tao
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * PCI bios-type initialisation for PCI machines
13 *
14 */
15#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/interrupt.h>
18#include <linux/pci.h>
19#include <linux/slab.h>
20#include <linux/init.h>
21#include <linux/io.h>
22
23static int debug_pci;
24
25#define CONFIG_CMD(bus, devfn, where) \
26 (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
27
28static int
29puv3_read_config(struct pci_bus *bus, unsigned int devfn, int where,
30 int size, u32 *value)
31{
32 writel(CONFIG_CMD(bus, devfn, where), PCICFG_ADDR);
33 switch (size) {
34 case 1:
35 *value = (readl(PCICFG_DATA) >> ((where & 3) * 8)) & 0xFF;
36 break;
37 case 2:
38 *value = (readl(PCICFG_DATA) >> ((where & 2) * 8)) & 0xFFFF;
39 break;
40 case 4:
41 *value = readl(PCICFG_DATA);
42 break;
43 }
44 return PCIBIOS_SUCCESSFUL;
45}
46
47static int
48puv3_write_config(struct pci_bus *bus, unsigned int devfn, int where,
49 int size, u32 value)
50{
51 writel(CONFIG_CMD(bus, devfn, where), PCICFG_ADDR);
52 switch (size) {
53 case 1:
54 writel((readl(PCICFG_DATA) & ~FMASK(8, (where&3)*8))
55 | FIELD(value, 8, (where&3)*8), PCICFG_DATA);
56 break;
57 case 2:
58 writel((readl(PCICFG_DATA) & ~FMASK(16, (where&2)*8))
59 | FIELD(value, 16, (where&2)*8), PCICFG_DATA);
60 break;
61 case 4:
62 writel(value, PCICFG_DATA);
63 break;
64 }
65 return PCIBIOS_SUCCESSFUL;
66}
67
68struct pci_ops pci_puv3_ops = {
69 .read = puv3_read_config,
70 .write = puv3_write_config,
71};
72
73void pci_puv3_preinit(void)
74{
75 printk(KERN_DEBUG "PCI: PKUnity PCI Controller Initializing ...\n");
76 /* config PCI bridge base */
77 writel(io_v2p(PKUNITY_PCIBRI_BASE), PCICFG_BRIBASE);
78
79 writel(0, PCIBRI_AHBCTL0);
80 writel(io_v2p(PKUNITY_PCIBRI_BASE) | PCIBRI_BARx_MEM, PCIBRI_AHBBAR0);
81 writel(0xFFFF0000, PCIBRI_AHBAMR0);
82 writel(0, PCIBRI_AHBTAR0);
83
84 writel(PCIBRI_CTLx_AT, PCIBRI_AHBCTL1);
85 writel(io_v2p(PKUNITY_PCILIO_BASE) | PCIBRI_BARx_IO, PCIBRI_AHBBAR1);
86 writel(0xFFFF0000, PCIBRI_AHBAMR1);
87 writel(0x00000000, PCIBRI_AHBTAR1);
88
89 writel(PCIBRI_CTLx_PREF, PCIBRI_AHBCTL2);
90 writel(io_v2p(PKUNITY_PCIMEM_BASE) | PCIBRI_BARx_MEM, PCIBRI_AHBBAR2);
91 writel(0xF8000000, PCIBRI_AHBAMR2);
92 writel(0, PCIBRI_AHBTAR2);
93
94 writel(io_v2p(PKUNITY_PCIAHB_BASE) | PCIBRI_BARx_MEM, PCIBRI_BAR1);
95
96 writel(PCIBRI_CTLx_AT | PCIBRI_CTLx_PREF, PCIBRI_PCICTL0);
97 writel(io_v2p(PKUNITY_PCIAHB_BASE) | PCIBRI_BARx_MEM, PCIBRI_PCIBAR0);
98 writel(0xF8000000, PCIBRI_PCIAMR0);
99 writel(PKUNITY_SDRAM_BASE, PCIBRI_PCITAR0);
100
101 writel(readl(PCIBRI_CMD) | PCIBRI_CMD_IO | PCIBRI_CMD_MEM, PCIBRI_CMD);
102}
103
104static int __init pci_puv3_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
105{
106 if (dev->bus->number == 0) {
107#ifdef CONFIG_ARCH_FPGA /* 4 pci slots */
108 if (dev->devfn == 0x00)
109 return IRQ_PCIINTA;
110 else if (dev->devfn == 0x08)
111 return IRQ_PCIINTB;
112 else if (dev->devfn == 0x10)
113 return IRQ_PCIINTC;
114 else if (dev->devfn == 0x18)
115 return IRQ_PCIINTD;
116#endif
117#ifdef CONFIG_PUV3_DB0913 /* 3 pci slots */
118 if (dev->devfn == 0x30)
119 return IRQ_PCIINTB;
120 else if (dev->devfn == 0x60)
121 return IRQ_PCIINTC;
122 else if (dev->devfn == 0x58)
123 return IRQ_PCIINTD;
124#endif
125#if defined(CONFIG_PUV3_NB0916) || defined(CONFIG_PUV3_SMW0919)
126 /* only support 2 pci devices */
127 if (dev->devfn == 0x00)
128 return IRQ_PCIINTC; /* sata */
129#endif
130 }
131 return -1;
132}
133
134/*
135 * Only first 128MB of memory can be accessed via PCI.
136 * We use GFP_DMA to allocate safe buffers to do map/unmap.
137 * This is really ugly and we need a better way of specifying
138 * DMA-capable regions of memory.
139 */
140void __init puv3_pci_adjust_zones(unsigned long *zone_size,
141 unsigned long *zhole_size)
142{
143 unsigned int sz = SZ_128M >> PAGE_SHIFT;
144
145 /*
146 * Only adjust if > 128M on current system
147 */
148 if (zone_size[0] <= sz)
149 return;
150
151 zone_size[1] = zone_size[0] - sz;
152 zone_size[0] = sz;
153 zhole_size[1] = zhole_size[0];
154 zhole_size[0] = 0;
155}
156
157void __devinit pcibios_update_irq(struct pci_dev *dev, int irq)
158{
159 if (debug_pci)
160 printk(KERN_DEBUG "PCI: Assigning IRQ %02d to %s\n",
161 irq, pci_name(dev));
162 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
163}
164
165/*
166 * If the bus contains any of these devices, then we must not turn on
167 * parity checking of any kind.
168 */
169static inline int pdev_bad_for_parity(struct pci_dev *dev)
170{
171 return 0;
172}
173
174/*
175 * pcibios_fixup_bus - Called after each bus is probed,
176 * but before its children are examined.
177 */
178void __devinit pcibios_fixup_bus(struct pci_bus *bus)
179{
180 struct pci_dev *dev;
181 u16 features = PCI_COMMAND_SERR
182 | PCI_COMMAND_PARITY
183 | PCI_COMMAND_FAST_BACK;
184
185 bus->resource[0] = &ioport_resource;
186 bus->resource[1] = &iomem_resource;
187
188 /*
189 * Walk the devices on this bus, working out what we can
190 * and can't support.
191 */
192 list_for_each_entry(dev, &bus->devices, bus_list) {
193 u16 status;
194
195 pci_read_config_word(dev, PCI_STATUS, &status);
196
197 /*
198 * If any device on this bus does not support fast back
199 * to back transfers, then the bus as a whole is not able
200 * to support them. Having fast back to back transfers
201 * on saves us one PCI cycle per transaction.
202 */
203 if (!(status & PCI_STATUS_FAST_BACK))
204 features &= ~PCI_COMMAND_FAST_BACK;
205
206 if (pdev_bad_for_parity(dev))
207 features &= ~(PCI_COMMAND_SERR
208 | PCI_COMMAND_PARITY);
209
210 switch (dev->class >> 8) {
211 case PCI_CLASS_BRIDGE_PCI:
212 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &status);
213 status |= PCI_BRIDGE_CTL_PARITY
214 | PCI_BRIDGE_CTL_MASTER_ABORT;
215 status &= ~(PCI_BRIDGE_CTL_BUS_RESET
216 | PCI_BRIDGE_CTL_FAST_BACK);
217 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, status);
218 break;
219
220 case PCI_CLASS_BRIDGE_CARDBUS:
221 pci_read_config_word(dev, PCI_CB_BRIDGE_CONTROL,
222 &status);
223 status |= PCI_CB_BRIDGE_CTL_PARITY
224 | PCI_CB_BRIDGE_CTL_MASTER_ABORT;
225 pci_write_config_word(dev, PCI_CB_BRIDGE_CONTROL,
226 status);
227 break;
228 }
229 }
230
231 /*
232 * Now walk the devices again, this time setting them up.
233 */
234 list_for_each_entry(dev, &bus->devices, bus_list) {
235 u16 cmd;
236
237 pci_read_config_word(dev, PCI_COMMAND, &cmd);
238 cmd |= features;
239 pci_write_config_word(dev, PCI_COMMAND, cmd);
240
241 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
242 L1_CACHE_BYTES >> 2);
243 }
244
245 /*
246 * Propagate the flags to the PCI bridge.
247 */
248 if (bus->self && bus->self->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
249 if (features & PCI_COMMAND_FAST_BACK)
250 bus->bridge_ctl |= PCI_BRIDGE_CTL_FAST_BACK;
251 if (features & PCI_COMMAND_PARITY)
252 bus->bridge_ctl |= PCI_BRIDGE_CTL_PARITY;
253 }
254
255 /*
256 * Report what we did for this bus
257 */
258 printk(KERN_INFO "PCI: bus%d: Fast back to back transfers %sabled\n",
259 bus->number, (features & PCI_COMMAND_FAST_BACK) ? "en" : "dis");
260}
261#ifdef CONFIG_HOTPLUG
262EXPORT_SYMBOL(pcibios_fixup_bus);
263#endif
264
265static int __init pci_common_init(void)
266{
267 struct pci_bus *puv3_bus;
268
269 pci_puv3_preinit();
270
271 puv3_bus = pci_scan_bus(0, &pci_puv3_ops, NULL);
272
273 if (!puv3_bus)
274 panic("PCI: unable to scan bus!");
275
276 pci_fixup_irqs(pci_common_swizzle, pci_puv3_map_irq);
277
278 if (!pci_has_flag(PCI_PROBE_ONLY)) {
279 /*
280 * Size the bridge windows.
281 */
282 pci_bus_size_bridges(puv3_bus);
283
284 /*
285 * Assign resources.
286 */
287 pci_bus_assign_resources(puv3_bus);
288 }
289
290 /*
291 * Tell drivers about devices found.
292 */
293 pci_bus_add_devices(puv3_bus);
294
295 return 0;
296}
297subsys_initcall(pci_common_init);
298
299char * __devinit pcibios_setup(char *str)
300{
301 if (!strcmp(str, "debug")) {
302 debug_pci = 1;
303 return NULL;
304 } else if (!strcmp(str, "firmware")) {
305 pci_add_flags(PCI_PROBE_ONLY);
306 return NULL;
307 }
308 return str;
309}
310
311void pcibios_set_master(struct pci_dev *dev)
312{
313 /* No special bus mastering setup handling */
314}
315
316/*
317 * From arch/i386/kernel/pci-i386.c:
318 *
319 * We need to avoid collisions with `mirrored' VGA ports
320 * and other strange ISA hardware, so we always want the
321 * addresses to be allocated in the 0x000-0x0ff region
322 * modulo 0x400.
323 *
324 * Why? Because some silly external IO cards only decode
325 * the low 10 bits of the IO address. The 0x00-0xff region
326 * is reserved for motherboard devices that decode all 16
327 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
328 * but we want to try to avoid allocating at 0x2900-0x2bff
329 * which might be mirrored at 0x0100-0x03ff..
330 */
331resource_size_t pcibios_align_resource(void *data, const struct resource *res,
332 resource_size_t size, resource_size_t align)
333{
334 resource_size_t start = res->start;
335
336 if (res->flags & IORESOURCE_IO && start & 0x300)
337 start = (start + 0x3ff) & ~0x3ff;
338
339 start = (start + align - 1) & ~(align - 1);
340
341 return start;
342}
343
344/**
345 * pcibios_enable_device - Enable I/O and memory.
346 * @dev: PCI device to be enabled
347 */
348int pcibios_enable_device(struct pci_dev *dev, int mask)
349{
350 u16 cmd, old_cmd;
351 int idx;
352 struct resource *r;
353
354 pci_read_config_word(dev, PCI_COMMAND, &cmd);
355 old_cmd = cmd;
356 for (idx = 0; idx < 6; idx++) {
357 /* Only set up the requested stuff */
358 if (!(mask & (1 << idx)))
359 continue;
360
361 r = dev->resource + idx;
362 if (!r->start && r->end) {
363 printk(KERN_ERR "PCI: Device %s not available because"
364 " of resource collisions\n", pci_name(dev));
365 return -EINVAL;
366 }
367 if (r->flags & IORESOURCE_IO)
368 cmd |= PCI_COMMAND_IO;
369 if (r->flags & IORESOURCE_MEM)
370 cmd |= PCI_COMMAND_MEMORY;
371 }
372
373 /*
374 * Bridges (eg, cardbus bridges) need to be fully enabled
375 */
376 if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE)
377 cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
378
379 if (cmd != old_cmd) {
380 printk("PCI: enabling device %s (%04x -> %04x)\n",
381 pci_name(dev), old_cmd, cmd);
382 pci_write_config_word(dev, PCI_COMMAND, cmd);
383 }
384 return 0;
385}
386
387int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
388 enum pci_mmap_state mmap_state, int write_combine)
389{
390 unsigned long phys;
391
392 if (mmap_state == pci_mmap_io)
393 return -EINVAL;
394
395 phys = vma->vm_pgoff;
396
397 /*
398 * Mark this as IO
399 */
400 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
401
402 if (remap_pfn_range(vma, vma->vm_start, phys,
403 vma->vm_end - vma->vm_start,
404 vma->vm_page_prot))
405 return -EAGAIN;
406
407 return 0;
408}