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1/* irq.c: UltraSparc IRQ handling/init/registry.
2 *
3 * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
6 */
7
8#include <linux/sched.h>
9#include <linux/linkage.h>
10#include <linux/ptrace.h>
11#include <linux/errno.h>
12#include <linux/kernel_stat.h>
13#include <linux/signal.h>
14#include <linux/mm.h>
15#include <linux/interrupt.h>
16#include <linux/slab.h>
17#include <linux/random.h>
18#include <linux/init.h>
19#include <linux/delay.h>
20#include <linux/proc_fs.h>
21#include <linux/seq_file.h>
22#include <linux/ftrace.h>
23#include <linux/irq.h>
24#include <linux/kmemleak.h>
25
26#include <asm/ptrace.h>
27#include <asm/processor.h>
28#include <linux/atomic.h>
29#include <asm/irq.h>
30#include <asm/io.h>
31#include <asm/iommu.h>
32#include <asm/upa.h>
33#include <asm/oplib.h>
34#include <asm/prom.h>
35#include <asm/timer.h>
36#include <asm/smp.h>
37#include <asm/starfire.h>
38#include <asm/uaccess.h>
39#include <asm/cache.h>
40#include <asm/cpudata.h>
41#include <asm/auxio.h>
42#include <asm/head.h>
43#include <asm/hypervisor.h>
44#include <asm/cacheflush.h>
45
46#include "entry.h"
47#include "cpumap.h"
48#include "kstack.h"
49
50#define NUM_IVECS (IMAP_INR + 1)
51
52struct ino_bucket *ivector_table;
53unsigned long ivector_table_pa;
54
55/* On several sun4u processors, it is illegal to mix bypass and
56 * non-bypass accesses. Therefore we access all INO buckets
57 * using bypass accesses only.
58 */
59static unsigned long bucket_get_chain_pa(unsigned long bucket_pa)
60{
61 unsigned long ret;
62
63 __asm__ __volatile__("ldxa [%1] %2, %0"
64 : "=&r" (ret)
65 : "r" (bucket_pa +
66 offsetof(struct ino_bucket,
67 __irq_chain_pa)),
68 "i" (ASI_PHYS_USE_EC));
69
70 return ret;
71}
72
73static void bucket_clear_chain_pa(unsigned long bucket_pa)
74{
75 __asm__ __volatile__("stxa %%g0, [%0] %1"
76 : /* no outputs */
77 : "r" (bucket_pa +
78 offsetof(struct ino_bucket,
79 __irq_chain_pa)),
80 "i" (ASI_PHYS_USE_EC));
81}
82
83static unsigned int bucket_get_irq(unsigned long bucket_pa)
84{
85 unsigned int ret;
86
87 __asm__ __volatile__("lduwa [%1] %2, %0"
88 : "=&r" (ret)
89 : "r" (bucket_pa +
90 offsetof(struct ino_bucket,
91 __irq)),
92 "i" (ASI_PHYS_USE_EC));
93
94 return ret;
95}
96
97static void bucket_set_irq(unsigned long bucket_pa, unsigned int irq)
98{
99 __asm__ __volatile__("stwa %0, [%1] %2"
100 : /* no outputs */
101 : "r" (irq),
102 "r" (bucket_pa +
103 offsetof(struct ino_bucket,
104 __irq)),
105 "i" (ASI_PHYS_USE_EC));
106}
107
108#define irq_work_pa(__cpu) &(trap_block[(__cpu)].irq_worklist_pa)
109
110static struct {
111 unsigned int dev_handle;
112 unsigned int dev_ino;
113 unsigned int in_use;
114} irq_table[NR_IRQS];
115static DEFINE_SPINLOCK(irq_alloc_lock);
116
117unsigned char irq_alloc(unsigned int dev_handle, unsigned int dev_ino)
118{
119 unsigned long flags;
120 unsigned char ent;
121
122 BUILD_BUG_ON(NR_IRQS >= 256);
123
124 spin_lock_irqsave(&irq_alloc_lock, flags);
125
126 for (ent = 1; ent < NR_IRQS; ent++) {
127 if (!irq_table[ent].in_use)
128 break;
129 }
130 if (ent >= NR_IRQS) {
131 printk(KERN_ERR "IRQ: Out of virtual IRQs.\n");
132 ent = 0;
133 } else {
134 irq_table[ent].dev_handle = dev_handle;
135 irq_table[ent].dev_ino = dev_ino;
136 irq_table[ent].in_use = 1;
137 }
138
139 spin_unlock_irqrestore(&irq_alloc_lock, flags);
140
141 return ent;
142}
143
144#ifdef CONFIG_PCI_MSI
145void irq_free(unsigned int irq)
146{
147 unsigned long flags;
148
149 if (irq >= NR_IRQS)
150 return;
151
152 spin_lock_irqsave(&irq_alloc_lock, flags);
153
154 irq_table[irq].in_use = 0;
155
156 spin_unlock_irqrestore(&irq_alloc_lock, flags);
157}
158#endif
159
160/*
161 * /proc/interrupts printing:
162 */
163int arch_show_interrupts(struct seq_file *p, int prec)
164{
165 int j;
166
167 seq_printf(p, "NMI: ");
168 for_each_online_cpu(j)
169 seq_printf(p, "%10u ", cpu_data(j).__nmi_count);
170 seq_printf(p, " Non-maskable interrupts\n");
171 return 0;
172}
173
174static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid)
175{
176 unsigned int tid;
177
178 if (this_is_starfire) {
179 tid = starfire_translate(imap, cpuid);
180 tid <<= IMAP_TID_SHIFT;
181 tid &= IMAP_TID_UPA;
182 } else {
183 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
184 unsigned long ver;
185
186 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
187 if ((ver >> 32UL) == __JALAPENO_ID ||
188 (ver >> 32UL) == __SERRANO_ID) {
189 tid = cpuid << IMAP_TID_SHIFT;
190 tid &= IMAP_TID_JBUS;
191 } else {
192 unsigned int a = cpuid & 0x1f;
193 unsigned int n = (cpuid >> 5) & 0x1f;
194
195 tid = ((a << IMAP_AID_SHIFT) |
196 (n << IMAP_NID_SHIFT));
197 tid &= (IMAP_AID_SAFARI |
198 IMAP_NID_SAFARI);
199 }
200 } else {
201 tid = cpuid << IMAP_TID_SHIFT;
202 tid &= IMAP_TID_UPA;
203 }
204 }
205
206 return tid;
207}
208
209struct irq_handler_data {
210 unsigned long iclr;
211 unsigned long imap;
212
213 void (*pre_handler)(unsigned int, void *, void *);
214 void *arg1;
215 void *arg2;
216};
217
218#ifdef CONFIG_SMP
219static int irq_choose_cpu(unsigned int irq, const struct cpumask *affinity)
220{
221 cpumask_t mask;
222 int cpuid;
223
224 cpumask_copy(&mask, affinity);
225 if (cpumask_equal(&mask, cpu_online_mask)) {
226 cpuid = map_to_cpu(irq);
227 } else {
228 cpumask_t tmp;
229
230 cpumask_and(&tmp, cpu_online_mask, &mask);
231 cpuid = cpumask_empty(&tmp) ? map_to_cpu(irq) : cpumask_first(&tmp);
232 }
233
234 return cpuid;
235}
236#else
237#define irq_choose_cpu(irq, affinity) \
238 real_hard_smp_processor_id()
239#endif
240
241static void sun4u_irq_enable(struct irq_data *data)
242{
243 struct irq_handler_data *handler_data = data->handler_data;
244
245 if (likely(handler_data)) {
246 unsigned long cpuid, imap, val;
247 unsigned int tid;
248
249 cpuid = irq_choose_cpu(data->irq, data->affinity);
250 imap = handler_data->imap;
251
252 tid = sun4u_compute_tid(imap, cpuid);
253
254 val = upa_readq(imap);
255 val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS |
256 IMAP_AID_SAFARI | IMAP_NID_SAFARI);
257 val |= tid | IMAP_VALID;
258 upa_writeq(val, imap);
259 upa_writeq(ICLR_IDLE, handler_data->iclr);
260 }
261}
262
263static int sun4u_set_affinity(struct irq_data *data,
264 const struct cpumask *mask, bool force)
265{
266 struct irq_handler_data *handler_data = data->handler_data;
267
268 if (likely(handler_data)) {
269 unsigned long cpuid, imap, val;
270 unsigned int tid;
271
272 cpuid = irq_choose_cpu(data->irq, mask);
273 imap = handler_data->imap;
274
275 tid = sun4u_compute_tid(imap, cpuid);
276
277 val = upa_readq(imap);
278 val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS |
279 IMAP_AID_SAFARI | IMAP_NID_SAFARI);
280 val |= tid | IMAP_VALID;
281 upa_writeq(val, imap);
282 upa_writeq(ICLR_IDLE, handler_data->iclr);
283 }
284
285 return 0;
286}
287
288/* Don't do anything. The desc->status check for IRQ_DISABLED in
289 * handler_irq() will skip the handler call and that will leave the
290 * interrupt in the sent state. The next ->enable() call will hit the
291 * ICLR register to reset the state machine.
292 *
293 * This scheme is necessary, instead of clearing the Valid bit in the
294 * IMAP register, to handle the case of IMAP registers being shared by
295 * multiple INOs (and thus ICLR registers). Since we use a different
296 * virtual IRQ for each shared IMAP instance, the generic code thinks
297 * there is only one user so it prematurely calls ->disable() on
298 * free_irq().
299 *
300 * We have to provide an explicit ->disable() method instead of using
301 * NULL to get the default. The reason is that if the generic code
302 * sees that, it also hooks up a default ->shutdown method which
303 * invokes ->mask() which we do not want. See irq_chip_set_defaults().
304 */
305static void sun4u_irq_disable(struct irq_data *data)
306{
307}
308
309static void sun4u_irq_eoi(struct irq_data *data)
310{
311 struct irq_handler_data *handler_data = data->handler_data;
312
313 if (likely(handler_data))
314 upa_writeq(ICLR_IDLE, handler_data->iclr);
315}
316
317static void sun4v_irq_enable(struct irq_data *data)
318{
319 unsigned int ino = irq_table[data->irq].dev_ino;
320 unsigned long cpuid = irq_choose_cpu(data->irq, data->affinity);
321 int err;
322
323 err = sun4v_intr_settarget(ino, cpuid);
324 if (err != HV_EOK)
325 printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): "
326 "err(%d)\n", ino, cpuid, err);
327 err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
328 if (err != HV_EOK)
329 printk(KERN_ERR "sun4v_intr_setstate(%x): "
330 "err(%d)\n", ino, err);
331 err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED);
332 if (err != HV_EOK)
333 printk(KERN_ERR "sun4v_intr_setenabled(%x): err(%d)\n",
334 ino, err);
335}
336
337static int sun4v_set_affinity(struct irq_data *data,
338 const struct cpumask *mask, bool force)
339{
340 unsigned int ino = irq_table[data->irq].dev_ino;
341 unsigned long cpuid = irq_choose_cpu(data->irq, mask);
342 int err;
343
344 err = sun4v_intr_settarget(ino, cpuid);
345 if (err != HV_EOK)
346 printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): "
347 "err(%d)\n", ino, cpuid, err);
348
349 return 0;
350}
351
352static void sun4v_irq_disable(struct irq_data *data)
353{
354 unsigned int ino = irq_table[data->irq].dev_ino;
355 int err;
356
357 err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED);
358 if (err != HV_EOK)
359 printk(KERN_ERR "sun4v_intr_setenabled(%x): "
360 "err(%d)\n", ino, err);
361}
362
363static void sun4v_irq_eoi(struct irq_data *data)
364{
365 unsigned int ino = irq_table[data->irq].dev_ino;
366 int err;
367
368 err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
369 if (err != HV_EOK)
370 printk(KERN_ERR "sun4v_intr_setstate(%x): "
371 "err(%d)\n", ino, err);
372}
373
374static void sun4v_virq_enable(struct irq_data *data)
375{
376 unsigned long cpuid, dev_handle, dev_ino;
377 int err;
378
379 cpuid = irq_choose_cpu(data->irq, data->affinity);
380
381 dev_handle = irq_table[data->irq].dev_handle;
382 dev_ino = irq_table[data->irq].dev_ino;
383
384 err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid);
385 if (err != HV_EOK)
386 printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): "
387 "err(%d)\n",
388 dev_handle, dev_ino, cpuid, err);
389 err = sun4v_vintr_set_state(dev_handle, dev_ino,
390 HV_INTR_STATE_IDLE);
391 if (err != HV_EOK)
392 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
393 "HV_INTR_STATE_IDLE): err(%d)\n",
394 dev_handle, dev_ino, err);
395 err = sun4v_vintr_set_valid(dev_handle, dev_ino,
396 HV_INTR_ENABLED);
397 if (err != HV_EOK)
398 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
399 "HV_INTR_ENABLED): err(%d)\n",
400 dev_handle, dev_ino, err);
401}
402
403static int sun4v_virt_set_affinity(struct irq_data *data,
404 const struct cpumask *mask, bool force)
405{
406 unsigned long cpuid, dev_handle, dev_ino;
407 int err;
408
409 cpuid = irq_choose_cpu(data->irq, mask);
410
411 dev_handle = irq_table[data->irq].dev_handle;
412 dev_ino = irq_table[data->irq].dev_ino;
413
414 err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid);
415 if (err != HV_EOK)
416 printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): "
417 "err(%d)\n",
418 dev_handle, dev_ino, cpuid, err);
419
420 return 0;
421}
422
423static void sun4v_virq_disable(struct irq_data *data)
424{
425 unsigned long dev_handle, dev_ino;
426 int err;
427
428 dev_handle = irq_table[data->irq].dev_handle;
429 dev_ino = irq_table[data->irq].dev_ino;
430
431 err = sun4v_vintr_set_valid(dev_handle, dev_ino,
432 HV_INTR_DISABLED);
433 if (err != HV_EOK)
434 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
435 "HV_INTR_DISABLED): err(%d)\n",
436 dev_handle, dev_ino, err);
437}
438
439static void sun4v_virq_eoi(struct irq_data *data)
440{
441 unsigned long dev_handle, dev_ino;
442 int err;
443
444 dev_handle = irq_table[data->irq].dev_handle;
445 dev_ino = irq_table[data->irq].dev_ino;
446
447 err = sun4v_vintr_set_state(dev_handle, dev_ino,
448 HV_INTR_STATE_IDLE);
449 if (err != HV_EOK)
450 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
451 "HV_INTR_STATE_IDLE): err(%d)\n",
452 dev_handle, dev_ino, err);
453}
454
455static struct irq_chip sun4u_irq = {
456 .name = "sun4u",
457 .irq_enable = sun4u_irq_enable,
458 .irq_disable = sun4u_irq_disable,
459 .irq_eoi = sun4u_irq_eoi,
460 .irq_set_affinity = sun4u_set_affinity,
461 .flags = IRQCHIP_EOI_IF_HANDLED,
462};
463
464static struct irq_chip sun4v_irq = {
465 .name = "sun4v",
466 .irq_enable = sun4v_irq_enable,
467 .irq_disable = sun4v_irq_disable,
468 .irq_eoi = sun4v_irq_eoi,
469 .irq_set_affinity = sun4v_set_affinity,
470 .flags = IRQCHIP_EOI_IF_HANDLED,
471};
472
473static struct irq_chip sun4v_virq = {
474 .name = "vsun4v",
475 .irq_enable = sun4v_virq_enable,
476 .irq_disable = sun4v_virq_disable,
477 .irq_eoi = sun4v_virq_eoi,
478 .irq_set_affinity = sun4v_virt_set_affinity,
479 .flags = IRQCHIP_EOI_IF_HANDLED,
480};
481
482static void pre_flow_handler(struct irq_data *d)
483{
484 struct irq_handler_data *handler_data = irq_data_get_irq_handler_data(d);
485 unsigned int ino = irq_table[d->irq].dev_ino;
486
487 handler_data->pre_handler(ino, handler_data->arg1, handler_data->arg2);
488}
489
490void irq_install_pre_handler(int irq,
491 void (*func)(unsigned int, void *, void *),
492 void *arg1, void *arg2)
493{
494 struct irq_handler_data *handler_data = irq_get_handler_data(irq);
495
496 handler_data->pre_handler = func;
497 handler_data->arg1 = arg1;
498 handler_data->arg2 = arg2;
499
500 __irq_set_preflow_handler(irq, pre_flow_handler);
501}
502
503unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap)
504{
505 struct ino_bucket *bucket;
506 struct irq_handler_data *handler_data;
507 unsigned int irq;
508 int ino;
509
510 BUG_ON(tlb_type == hypervisor);
511
512 ino = (upa_readq(imap) & (IMAP_IGN | IMAP_INO)) + inofixup;
513 bucket = &ivector_table[ino];
514 irq = bucket_get_irq(__pa(bucket));
515 if (!irq) {
516 irq = irq_alloc(0, ino);
517 bucket_set_irq(__pa(bucket), irq);
518 irq_set_chip_and_handler_name(irq, &sun4u_irq,
519 handle_fasteoi_irq, "IVEC");
520 }
521
522 handler_data = irq_get_handler_data(irq);
523 if (unlikely(handler_data))
524 goto out;
525
526 handler_data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
527 if (unlikely(!handler_data)) {
528 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
529 prom_halt();
530 }
531 irq_set_handler_data(irq, handler_data);
532
533 handler_data->imap = imap;
534 handler_data->iclr = iclr;
535
536out:
537 return irq;
538}
539
540static unsigned int sun4v_build_common(unsigned long sysino,
541 struct irq_chip *chip)
542{
543 struct ino_bucket *bucket;
544 struct irq_handler_data *handler_data;
545 unsigned int irq;
546
547 BUG_ON(tlb_type != hypervisor);
548
549 bucket = &ivector_table[sysino];
550 irq = bucket_get_irq(__pa(bucket));
551 if (!irq) {
552 irq = irq_alloc(0, sysino);
553 bucket_set_irq(__pa(bucket), irq);
554 irq_set_chip_and_handler_name(irq, chip, handle_fasteoi_irq,
555 "IVEC");
556 }
557
558 handler_data = irq_get_handler_data(irq);
559 if (unlikely(handler_data))
560 goto out;
561
562 handler_data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
563 if (unlikely(!handler_data)) {
564 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
565 prom_halt();
566 }
567 irq_set_handler_data(irq, handler_data);
568
569 /* Catch accidental accesses to these things. IMAP/ICLR handling
570 * is done by hypervisor calls on sun4v platforms, not by direct
571 * register accesses.
572 */
573 handler_data->imap = ~0UL;
574 handler_data->iclr = ~0UL;
575
576out:
577 return irq;
578}
579
580unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino)
581{
582 unsigned long sysino = sun4v_devino_to_sysino(devhandle, devino);
583
584 return sun4v_build_common(sysino, &sun4v_irq);
585}
586
587unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino)
588{
589 struct irq_handler_data *handler_data;
590 unsigned long hv_err, cookie;
591 struct ino_bucket *bucket;
592 unsigned int irq;
593
594 bucket = kzalloc(sizeof(struct ino_bucket), GFP_ATOMIC);
595 if (unlikely(!bucket))
596 return 0;
597
598 /* The only reference we store to the IRQ bucket is
599 * by physical address which kmemleak can't see, tell
600 * it that this object explicitly is not a leak and
601 * should be scanned.
602 */
603 kmemleak_not_leak(bucket);
604
605 __flush_dcache_range((unsigned long) bucket,
606 ((unsigned long) bucket +
607 sizeof(struct ino_bucket)));
608
609 irq = irq_alloc(devhandle, devino);
610 bucket_set_irq(__pa(bucket), irq);
611
612 irq_set_chip_and_handler_name(irq, &sun4v_virq, handle_fasteoi_irq,
613 "IVEC");
614
615 handler_data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
616 if (unlikely(!handler_data))
617 return 0;
618
619 /* In order to make the LDC channel startup sequence easier,
620 * especially wrt. locking, we do not let request_irq() enable
621 * the interrupt.
622 */
623 irq_set_status_flags(irq, IRQ_NOAUTOEN);
624 irq_set_handler_data(irq, handler_data);
625
626 /* Catch accidental accesses to these things. IMAP/ICLR handling
627 * is done by hypervisor calls on sun4v platforms, not by direct
628 * register accesses.
629 */
630 handler_data->imap = ~0UL;
631 handler_data->iclr = ~0UL;
632
633 cookie = ~__pa(bucket);
634 hv_err = sun4v_vintr_set_cookie(devhandle, devino, cookie);
635 if (hv_err) {
636 prom_printf("IRQ: Fatal, cannot set cookie for [%x:%x] "
637 "err=%lu\n", devhandle, devino, hv_err);
638 prom_halt();
639 }
640
641 return irq;
642}
643
644void ack_bad_irq(unsigned int irq)
645{
646 unsigned int ino = irq_table[irq].dev_ino;
647
648 if (!ino)
649 ino = 0xdeadbeef;
650
651 printk(KERN_CRIT "Unexpected IRQ from ino[%x] irq[%u]\n",
652 ino, irq);
653}
654
655void *hardirq_stack[NR_CPUS];
656void *softirq_stack[NR_CPUS];
657
658void __irq_entry handler_irq(int pil, struct pt_regs *regs)
659{
660 unsigned long pstate, bucket_pa;
661 struct pt_regs *old_regs;
662 void *orig_sp;
663
664 clear_softint(1 << pil);
665
666 old_regs = set_irq_regs(regs);
667 irq_enter();
668
669 /* Grab an atomic snapshot of the pending IVECs. */
670 __asm__ __volatile__("rdpr %%pstate, %0\n\t"
671 "wrpr %0, %3, %%pstate\n\t"
672 "ldx [%2], %1\n\t"
673 "stx %%g0, [%2]\n\t"
674 "wrpr %0, 0x0, %%pstate\n\t"
675 : "=&r" (pstate), "=&r" (bucket_pa)
676 : "r" (irq_work_pa(smp_processor_id())),
677 "i" (PSTATE_IE)
678 : "memory");
679
680 orig_sp = set_hardirq_stack();
681
682 while (bucket_pa) {
683 unsigned long next_pa;
684 unsigned int irq;
685
686 next_pa = bucket_get_chain_pa(bucket_pa);
687 irq = bucket_get_irq(bucket_pa);
688 bucket_clear_chain_pa(bucket_pa);
689
690 generic_handle_irq(irq);
691
692 bucket_pa = next_pa;
693 }
694
695 restore_hardirq_stack(orig_sp);
696
697 irq_exit();
698 set_irq_regs(old_regs);
699}
700
701void do_softirq(void)
702{
703 unsigned long flags;
704
705 if (in_interrupt())
706 return;
707
708 local_irq_save(flags);
709
710 if (local_softirq_pending()) {
711 void *orig_sp, *sp = softirq_stack[smp_processor_id()];
712
713 sp += THREAD_SIZE - 192 - STACK_BIAS;
714
715 __asm__ __volatile__("mov %%sp, %0\n\t"
716 "mov %1, %%sp"
717 : "=&r" (orig_sp)
718 : "r" (sp));
719 __do_softirq();
720 __asm__ __volatile__("mov %0, %%sp"
721 : : "r" (orig_sp));
722 }
723
724 local_irq_restore(flags);
725}
726
727#ifdef CONFIG_HOTPLUG_CPU
728void fixup_irqs(void)
729{
730 unsigned int irq;
731
732 for (irq = 0; irq < NR_IRQS; irq++) {
733 struct irq_desc *desc = irq_to_desc(irq);
734 struct irq_data *data = irq_desc_get_irq_data(desc);
735 unsigned long flags;
736
737 raw_spin_lock_irqsave(&desc->lock, flags);
738 if (desc->action && !irqd_is_per_cpu(data)) {
739 if (data->chip->irq_set_affinity)
740 data->chip->irq_set_affinity(data,
741 data->affinity,
742 false);
743 }
744 raw_spin_unlock_irqrestore(&desc->lock, flags);
745 }
746
747 tick_ops->disable_irq();
748}
749#endif
750
751struct sun5_timer {
752 u64 count0;
753 u64 limit0;
754 u64 count1;
755 u64 limit1;
756};
757
758static struct sun5_timer *prom_timers;
759static u64 prom_limit0, prom_limit1;
760
761static void map_prom_timers(void)
762{
763 struct device_node *dp;
764 const unsigned int *addr;
765
766 /* PROM timer node hangs out in the top level of device siblings... */
767 dp = of_find_node_by_path("/");
768 dp = dp->child;
769 while (dp) {
770 if (!strcmp(dp->name, "counter-timer"))
771 break;
772 dp = dp->sibling;
773 }
774
775 /* Assume if node is not present, PROM uses different tick mechanism
776 * which we should not care about.
777 */
778 if (!dp) {
779 prom_timers = (struct sun5_timer *) 0;
780 return;
781 }
782
783 /* If PROM is really using this, it must be mapped by him. */
784 addr = of_get_property(dp, "address", NULL);
785 if (!addr) {
786 prom_printf("PROM does not have timer mapped, trying to continue.\n");
787 prom_timers = (struct sun5_timer *) 0;
788 return;
789 }
790 prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]);
791}
792
793static void kill_prom_timer(void)
794{
795 if (!prom_timers)
796 return;
797
798 /* Save them away for later. */
799 prom_limit0 = prom_timers->limit0;
800 prom_limit1 = prom_timers->limit1;
801
802 /* Just as in sun4c PROM uses timer which ticks at IRQ 14.
803 * We turn both off here just to be paranoid.
804 */
805 prom_timers->limit0 = 0;
806 prom_timers->limit1 = 0;
807
808 /* Wheee, eat the interrupt packet too... */
809 __asm__ __volatile__(
810" mov 0x40, %%g2\n"
811" ldxa [%%g0] %0, %%g1\n"
812" ldxa [%%g2] %1, %%g1\n"
813" stxa %%g0, [%%g0] %0\n"
814" membar #Sync\n"
815 : /* no outputs */
816 : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R)
817 : "g1", "g2");
818}
819
820void notrace init_irqwork_curcpu(void)
821{
822 int cpu = hard_smp_processor_id();
823
824 trap_block[cpu].irq_worklist_pa = 0UL;
825}
826
827/* Please be very careful with register_one_mondo() and
828 * sun4v_register_mondo_queues().
829 *
830 * On SMP this gets invoked from the CPU trampoline before
831 * the cpu has fully taken over the trap table from OBP,
832 * and it's kernel stack + %g6 thread register state is
833 * not fully cooked yet.
834 *
835 * Therefore you cannot make any OBP calls, not even prom_printf,
836 * from these two routines.
837 */
838static void __cpuinit notrace register_one_mondo(unsigned long paddr, unsigned long type, unsigned long qmask)
839{
840 unsigned long num_entries = (qmask + 1) / 64;
841 unsigned long status;
842
843 status = sun4v_cpu_qconf(type, paddr, num_entries);
844 if (status != HV_EOK) {
845 prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, "
846 "err %lu\n", type, paddr, num_entries, status);
847 prom_halt();
848 }
849}
850
851void __cpuinit notrace sun4v_register_mondo_queues(int this_cpu)
852{
853 struct trap_per_cpu *tb = &trap_block[this_cpu];
854
855 register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO,
856 tb->cpu_mondo_qmask);
857 register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO,
858 tb->dev_mondo_qmask);
859 register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR,
860 tb->resum_qmask);
861 register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR,
862 tb->nonresum_qmask);
863}
864
865/* Each queue region must be a power of 2 multiple of 64 bytes in
866 * size. The base real address must be aligned to the size of the
867 * region. Thus, an 8KB queue must be 8KB aligned, for example.
868 */
869static void __init alloc_one_queue(unsigned long *pa_ptr, unsigned long qmask)
870{
871 unsigned long size = PAGE_ALIGN(qmask + 1);
872 unsigned long order = get_order(size);
873 unsigned long p;
874
875 p = __get_free_pages(GFP_KERNEL, order);
876 if (!p) {
877 prom_printf("SUN4V: Error, cannot allocate queue.\n");
878 prom_halt();
879 }
880
881 *pa_ptr = __pa(p);
882}
883
884static void __init init_cpu_send_mondo_info(struct trap_per_cpu *tb)
885{
886#ifdef CONFIG_SMP
887 unsigned long page;
888
889 BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64));
890
891 page = get_zeroed_page(GFP_KERNEL);
892 if (!page) {
893 prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n");
894 prom_halt();
895 }
896
897 tb->cpu_mondo_block_pa = __pa(page);
898 tb->cpu_list_pa = __pa(page + 64);
899#endif
900}
901
902/* Allocate mondo and error queues for all possible cpus. */
903static void __init sun4v_init_mondo_queues(void)
904{
905 int cpu;
906
907 for_each_possible_cpu(cpu) {
908 struct trap_per_cpu *tb = &trap_block[cpu];
909
910 alloc_one_queue(&tb->cpu_mondo_pa, tb->cpu_mondo_qmask);
911 alloc_one_queue(&tb->dev_mondo_pa, tb->dev_mondo_qmask);
912 alloc_one_queue(&tb->resum_mondo_pa, tb->resum_qmask);
913 alloc_one_queue(&tb->resum_kernel_buf_pa, tb->resum_qmask);
914 alloc_one_queue(&tb->nonresum_mondo_pa, tb->nonresum_qmask);
915 alloc_one_queue(&tb->nonresum_kernel_buf_pa,
916 tb->nonresum_qmask);
917 }
918}
919
920static void __init init_send_mondo_info(void)
921{
922 int cpu;
923
924 for_each_possible_cpu(cpu) {
925 struct trap_per_cpu *tb = &trap_block[cpu];
926
927 init_cpu_send_mondo_info(tb);
928 }
929}
930
931static struct irqaction timer_irq_action = {
932 .name = "timer",
933};
934
935/* Only invoked on boot processor. */
936void __init init_IRQ(void)
937{
938 unsigned long size;
939
940 map_prom_timers();
941 kill_prom_timer();
942
943 size = sizeof(struct ino_bucket) * NUM_IVECS;
944 ivector_table = kzalloc(size, GFP_KERNEL);
945 if (!ivector_table) {
946 prom_printf("Fatal error, cannot allocate ivector_table\n");
947 prom_halt();
948 }
949 __flush_dcache_range((unsigned long) ivector_table,
950 ((unsigned long) ivector_table) + size);
951
952 ivector_table_pa = __pa(ivector_table);
953
954 if (tlb_type == hypervisor)
955 sun4v_init_mondo_queues();
956
957 init_send_mondo_info();
958
959 if (tlb_type == hypervisor) {
960 /* Load up the boot cpu's entries. */
961 sun4v_register_mondo_queues(hard_smp_processor_id());
962 }
963
964 /* We need to clear any IRQ's pending in the soft interrupt
965 * registers, a spurious one could be left around from the
966 * PROM timer which we just disabled.
967 */
968 clear_softint(get_softint());
969
970 /* Now that ivector table is initialized, it is safe
971 * to receive IRQ vector traps. We will normally take
972 * one or two right now, in case some device PROM used
973 * to boot us wants to speak to us. We just ignore them.
974 */
975 __asm__ __volatile__("rdpr %%pstate, %%g1\n\t"
976 "or %%g1, %0, %%g1\n\t"
977 "wrpr %%g1, 0x0, %%pstate"
978 : /* No outputs */
979 : "i" (PSTATE_IE)
980 : "g1");
981
982 irq_to_desc(0)->action = &timer_irq_action;
983}