1/*
  2 * SH4 CPU-specific DMA definitions, used by both DMA drivers
  3 *
  4 * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
  5 *
  6 * This program is free software; you can redistribute it and/or modify
  7 * it under the terms of the GNU General Public License version 2 as
  8 * published by the Free Software Foundation.
  9 */
 10#ifndef CPU_DMA_REGISTER_H
 11#define CPU_DMA_REGISTER_H
 12
 13/* SH7751/7760/7780 DMA IRQ sources */
 14
 15#ifdef CONFIG_CPU_SH4A
 16
 17#define DMAOR_INIT	DMAOR_DME
 18
 19#if defined(CONFIG_CPU_SUBTYPE_SH7343)
 20#define CHCR_TS_LOW_MASK	0x00000018
 21#define CHCR_TS_LOW_SHIFT	3
 22#define CHCR_TS_HIGH_MASK	0
 23#define CHCR_TS_HIGH_SHIFT	0
 24#elif defined(CONFIG_CPU_SUBTYPE_SH7722) || \
 25	defined(CONFIG_CPU_SUBTYPE_SH7723) || \
 26	defined(CONFIG_CPU_SUBTYPE_SH7724) || \
 27	defined(CONFIG_CPU_SUBTYPE_SH7730) || \
 28	defined(CONFIG_CPU_SUBTYPE_SH7786)
 29#define CHCR_TS_LOW_MASK	0x00000018
 30#define CHCR_TS_LOW_SHIFT	3
 31#define CHCR_TS_HIGH_MASK	0x00300000
 32#define CHCR_TS_HIGH_SHIFT	(20 - 2)	/* 2 bits for shifted low TS */
 33#elif defined(CONFIG_CPU_SUBTYPE_SH7757) || \
 34	defined(CONFIG_CPU_SUBTYPE_SH7763) || \
 35	defined(CONFIG_CPU_SUBTYPE_SH7764) || \
 36	defined(CONFIG_CPU_SUBTYPE_SH7780) || \
 37	defined(CONFIG_CPU_SUBTYPE_SH7785)
 38#define CHCR_TS_LOW_MASK	0x00000018
 39#define CHCR_TS_LOW_SHIFT	3
 40#define CHCR_TS_HIGH_MASK	0x00100000
 41#define CHCR_TS_HIGH_SHIFT	(20 - 2)	/* 2 bits for shifted low TS */
 42#endif
 43
 44/* Transmit sizes and respective CHCR register values */
 45enum {
 46	XMIT_SZ_8BIT		= 0,
 47	XMIT_SZ_16BIT		= 1,
 48	XMIT_SZ_32BIT		= 2,
 49	XMIT_SZ_64BIT		= 7,
 50	XMIT_SZ_128BIT		= 3,
 51	XMIT_SZ_256BIT		= 4,
 52	XMIT_SZ_128BIT_BLK	= 0xb,
 53	XMIT_SZ_256BIT_BLK	= 0xc,
 54};
 55
 56/* log2(size / 8) - used to calculate number of transfers */
 57#define TS_SHIFT {			\
 58	[XMIT_SZ_8BIT]		= 0,	\
 59	[XMIT_SZ_16BIT]		= 1,	\
 60	[XMIT_SZ_32BIT]		= 2,	\
 61	[XMIT_SZ_64BIT]		= 3,	\
 62	[XMIT_SZ_128BIT]	= 4,	\
 63	[XMIT_SZ_256BIT]	= 5,	\
 64	[XMIT_SZ_128BIT_BLK]	= 4,	\
 65	[XMIT_SZ_256BIT_BLK]	= 5,	\
 66}
 67
 68#define TS_INDEX2VAL(i)	((((i) & 3) << CHCR_TS_LOW_SHIFT) | \
 69			 (((i) & 0xc) << CHCR_TS_HIGH_SHIFT))
 70
 71#else /* CONFIG_CPU_SH4A */
 72
 73#define DMAOR_INIT	(0x8000 | DMAOR_DME)
 74
 75#define CHCR_TS_LOW_MASK	0x70
 76#define CHCR_TS_LOW_SHIFT	4
 77#define CHCR_TS_HIGH_MASK	0
 78#define CHCR_TS_HIGH_SHIFT	0
 79
 80/* Transmit sizes and respective CHCR register values */
 81enum {
 82	XMIT_SZ_8BIT	= 1,
 83	XMIT_SZ_16BIT	= 2,
 84	XMIT_SZ_32BIT	= 3,
 85	XMIT_SZ_64BIT	= 0,
 86	XMIT_SZ_256BIT	= 4,
 87};
 88
 89/* log2(size / 8) - used to calculate number of transfers */
 90#define TS_SHIFT {			\
 91	[XMIT_SZ_8BIT]		= 0,	\
 92	[XMIT_SZ_16BIT]		= 1,	\
 93	[XMIT_SZ_32BIT]		= 2,	\
 94	[XMIT_SZ_64BIT]		= 3,	\
 95	[XMIT_SZ_256BIT]	= 5,	\
 96}
 97
 98#define TS_INDEX2VAL(i)	(((i) & 7) << CHCR_TS_LOW_SHIFT)
 99
100#endif /* CONFIG_CPU_SH4A */
101
102#endif