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1/*
2 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
3 *
4 * Rewrite, cleanup:
5 *
6 * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
7 * Copyright (C) 2006 Olof Johansson <olof@lixom.net>
8 *
9 * Dynamic DMA mapping support, pSeries-specific parts, both SMP and LPAR.
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 */
26
27#include <linux/init.h>
28#include <linux/types.h>
29#include <linux/slab.h>
30#include <linux/mm.h>
31#include <linux/spinlock.h>
32#include <linux/sched.h> /* for show_stack */
33#include <linux/string.h>
34#include <linux/pci.h>
35#include <linux/dma-mapping.h>
36#include <linux/crash_dump.h>
37#include <linux/memory.h>
38#include <asm/io.h>
39#include <asm/prom.h>
40#include <asm/rtas.h>
41#include <asm/iommu.h>
42#include <asm/pci-bridge.h>
43#include <asm/machdep.h>
44#include <asm/abs_addr.h>
45#include <asm/pSeries_reconfig.h>
46#include <asm/firmware.h>
47#include <asm/tce.h>
48#include <asm/ppc-pci.h>
49#include <asm/udbg.h>
50#include <asm/mmzone.h>
51
52#include "plpar_wrappers.h"
53
54
55static void tce_invalidate_pSeries_sw(struct iommu_table *tbl,
56 u64 *startp, u64 *endp)
57{
58 u64 __iomem *invalidate = (u64 __iomem *)tbl->it_index;
59 unsigned long start, end, inc;
60
61 start = __pa(startp);
62 end = __pa(endp);
63 inc = L1_CACHE_BYTES; /* invalidate a cacheline of TCEs at a time */
64
65 /* If this is non-zero, change the format. We shift the
66 * address and or in the magic from the device tree. */
67 if (tbl->it_busno) {
68 start <<= 12;
69 end <<= 12;
70 inc <<= 12;
71 start |= tbl->it_busno;
72 end |= tbl->it_busno;
73 }
74
75 end |= inc - 1; /* round up end to be different than start */
76
77 mb(); /* Make sure TCEs in memory are written */
78 while (start <= end) {
79 out_be64(invalidate, start);
80 start += inc;
81 }
82}
83
84static int tce_build_pSeries(struct iommu_table *tbl, long index,
85 long npages, unsigned long uaddr,
86 enum dma_data_direction direction,
87 struct dma_attrs *attrs)
88{
89 u64 proto_tce;
90 u64 *tcep, *tces;
91 u64 rpn;
92
93 proto_tce = TCE_PCI_READ; // Read allowed
94
95 if (direction != DMA_TO_DEVICE)
96 proto_tce |= TCE_PCI_WRITE;
97
98 tces = tcep = ((u64 *)tbl->it_base) + index;
99
100 while (npages--) {
101 /* can't move this out since we might cross MEMBLOCK boundary */
102 rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT;
103 *tcep = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
104
105 uaddr += TCE_PAGE_SIZE;
106 tcep++;
107 }
108
109 if (tbl->it_type & TCE_PCI_SWINV_CREATE)
110 tce_invalidate_pSeries_sw(tbl, tces, tcep - 1);
111 return 0;
112}
113
114
115static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages)
116{
117 u64 *tcep, *tces;
118
119 tces = tcep = ((u64 *)tbl->it_base) + index;
120
121 while (npages--)
122 *(tcep++) = 0;
123
124 if (tbl->it_type & TCE_PCI_SWINV_FREE)
125 tce_invalidate_pSeries_sw(tbl, tces, tcep - 1);
126}
127
128static unsigned long tce_get_pseries(struct iommu_table *tbl, long index)
129{
130 u64 *tcep;
131
132 tcep = ((u64 *)tbl->it_base) + index;
133
134 return *tcep;
135}
136
137static void tce_free_pSeriesLP(struct iommu_table*, long, long);
138static void tce_freemulti_pSeriesLP(struct iommu_table*, long, long);
139
140static int tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum,
141 long npages, unsigned long uaddr,
142 enum dma_data_direction direction,
143 struct dma_attrs *attrs)
144{
145 u64 rc = 0;
146 u64 proto_tce, tce;
147 u64 rpn;
148 int ret = 0;
149 long tcenum_start = tcenum, npages_start = npages;
150
151 rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT;
152 proto_tce = TCE_PCI_READ;
153 if (direction != DMA_TO_DEVICE)
154 proto_tce |= TCE_PCI_WRITE;
155
156 while (npages--) {
157 tce = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
158 rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, tce);
159
160 if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) {
161 ret = (int)rc;
162 tce_free_pSeriesLP(tbl, tcenum_start,
163 (npages_start - (npages + 1)));
164 break;
165 }
166
167 if (rc && printk_ratelimit()) {
168 printk("tce_build_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
169 printk("\tindex = 0x%llx\n", (u64)tbl->it_index);
170 printk("\ttcenum = 0x%llx\n", (u64)tcenum);
171 printk("\ttce val = 0x%llx\n", tce );
172 show_stack(current, (unsigned long *)__get_SP());
173 }
174
175 tcenum++;
176 rpn++;
177 }
178 return ret;
179}
180
181static DEFINE_PER_CPU(u64 *, tce_page);
182
183static int tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
184 long npages, unsigned long uaddr,
185 enum dma_data_direction direction,
186 struct dma_attrs *attrs)
187{
188 u64 rc = 0;
189 u64 proto_tce;
190 u64 *tcep;
191 u64 rpn;
192 long l, limit;
193 long tcenum_start = tcenum, npages_start = npages;
194 int ret = 0;
195
196 if (npages == 1) {
197 return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr,
198 direction, attrs);
199 }
200
201 tcep = __get_cpu_var(tce_page);
202
203 /* This is safe to do since interrupts are off when we're called
204 * from iommu_alloc{,_sg}()
205 */
206 if (!tcep) {
207 tcep = (u64 *)__get_free_page(GFP_ATOMIC);
208 /* If allocation fails, fall back to the loop implementation */
209 if (!tcep) {
210 return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr,
211 direction, attrs);
212 }
213 __get_cpu_var(tce_page) = tcep;
214 }
215
216 rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT;
217 proto_tce = TCE_PCI_READ;
218 if (direction != DMA_TO_DEVICE)
219 proto_tce |= TCE_PCI_WRITE;
220
221 /* We can map max one pageful of TCEs at a time */
222 do {
223 /*
224 * Set up the page with TCE data, looping through and setting
225 * the values.
226 */
227 limit = min_t(long, npages, 4096/TCE_ENTRY_SIZE);
228
229 for (l = 0; l < limit; l++) {
230 tcep[l] = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
231 rpn++;
232 }
233
234 rc = plpar_tce_put_indirect((u64)tbl->it_index,
235 (u64)tcenum << 12,
236 (u64)virt_to_abs(tcep),
237 limit);
238
239 npages -= limit;
240 tcenum += limit;
241 } while (npages > 0 && !rc);
242
243 if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) {
244 ret = (int)rc;
245 tce_freemulti_pSeriesLP(tbl, tcenum_start,
246 (npages_start - (npages + limit)));
247 return ret;
248 }
249
250 if (rc && printk_ratelimit()) {
251 printk("tce_buildmulti_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
252 printk("\tindex = 0x%llx\n", (u64)tbl->it_index);
253 printk("\tnpages = 0x%llx\n", (u64)npages);
254 printk("\ttce[0] val = 0x%llx\n", tcep[0]);
255 show_stack(current, (unsigned long *)__get_SP());
256 }
257 return ret;
258}
259
260static void tce_free_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
261{
262 u64 rc;
263
264 while (npages--) {
265 rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, 0);
266
267 if (rc && printk_ratelimit()) {
268 printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
269 printk("\tindex = 0x%llx\n", (u64)tbl->it_index);
270 printk("\ttcenum = 0x%llx\n", (u64)tcenum);
271 show_stack(current, (unsigned long *)__get_SP());
272 }
273
274 tcenum++;
275 }
276}
277
278
279static void tce_freemulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
280{
281 u64 rc;
282
283 rc = plpar_tce_stuff((u64)tbl->it_index, (u64)tcenum << 12, 0, npages);
284
285 if (rc && printk_ratelimit()) {
286 printk("tce_freemulti_pSeriesLP: plpar_tce_stuff failed\n");
287 printk("\trc = %lld\n", rc);
288 printk("\tindex = 0x%llx\n", (u64)tbl->it_index);
289 printk("\tnpages = 0x%llx\n", (u64)npages);
290 show_stack(current, (unsigned long *)__get_SP());
291 }
292}
293
294static unsigned long tce_get_pSeriesLP(struct iommu_table *tbl, long tcenum)
295{
296 u64 rc;
297 unsigned long tce_ret;
298
299 rc = plpar_tce_get((u64)tbl->it_index, (u64)tcenum << 12, &tce_ret);
300
301 if (rc && printk_ratelimit()) {
302 printk("tce_get_pSeriesLP: plpar_tce_get failed. rc=%lld\n", rc);
303 printk("\tindex = 0x%llx\n", (u64)tbl->it_index);
304 printk("\ttcenum = 0x%llx\n", (u64)tcenum);
305 show_stack(current, (unsigned long *)__get_SP());
306 }
307
308 return tce_ret;
309}
310
311/* this is compatible with cells for the device tree property */
312struct dynamic_dma_window_prop {
313 __be32 liobn; /* tce table number */
314 __be64 dma_base; /* address hi,lo */
315 __be32 tce_shift; /* ilog2(tce_page_size) */
316 __be32 window_shift; /* ilog2(tce_window_size) */
317};
318
319struct direct_window {
320 struct device_node *device;
321 const struct dynamic_dma_window_prop *prop;
322 struct list_head list;
323};
324
325/* Dynamic DMA Window support */
326struct ddw_query_response {
327 u32 windows_available;
328 u32 largest_available_block;
329 u32 page_size;
330 u32 migration_capable;
331};
332
333struct ddw_create_response {
334 u32 liobn;
335 u32 addr_hi;
336 u32 addr_lo;
337};
338
339static LIST_HEAD(direct_window_list);
340/* prevents races between memory on/offline and window creation */
341static DEFINE_SPINLOCK(direct_window_list_lock);
342/* protects initializing window twice for same device */
343static DEFINE_MUTEX(direct_window_init_mutex);
344#define DIRECT64_PROPNAME "linux,direct64-ddr-window-info"
345
346static int tce_clearrange_multi_pSeriesLP(unsigned long start_pfn,
347 unsigned long num_pfn, const void *arg)
348{
349 const struct dynamic_dma_window_prop *maprange = arg;
350 int rc;
351 u64 tce_size, num_tce, dma_offset, next;
352 u32 tce_shift;
353 long limit;
354
355 tce_shift = be32_to_cpu(maprange->tce_shift);
356 tce_size = 1ULL << tce_shift;
357 next = start_pfn << PAGE_SHIFT;
358 num_tce = num_pfn << PAGE_SHIFT;
359
360 /* round back to the beginning of the tce page size */
361 num_tce += next & (tce_size - 1);
362 next &= ~(tce_size - 1);
363
364 /* covert to number of tces */
365 num_tce |= tce_size - 1;
366 num_tce >>= tce_shift;
367
368 do {
369 /*
370 * Set up the page with TCE data, looping through and setting
371 * the values.
372 */
373 limit = min_t(long, num_tce, 512);
374 dma_offset = next + be64_to_cpu(maprange->dma_base);
375
376 rc = plpar_tce_stuff((u64)be32_to_cpu(maprange->liobn),
377 dma_offset,
378 0, limit);
379 num_tce -= limit;
380 } while (num_tce > 0 && !rc);
381
382 return rc;
383}
384
385static int tce_setrange_multi_pSeriesLP(unsigned long start_pfn,
386 unsigned long num_pfn, const void *arg)
387{
388 const struct dynamic_dma_window_prop *maprange = arg;
389 u64 *tcep, tce_size, num_tce, dma_offset, next, proto_tce, liobn;
390 u32 tce_shift;
391 u64 rc = 0;
392 long l, limit;
393
394 local_irq_disable(); /* to protect tcep and the page behind it */
395 tcep = __get_cpu_var(tce_page);
396
397 if (!tcep) {
398 tcep = (u64 *)__get_free_page(GFP_ATOMIC);
399 if (!tcep) {
400 local_irq_enable();
401 return -ENOMEM;
402 }
403 __get_cpu_var(tce_page) = tcep;
404 }
405
406 proto_tce = TCE_PCI_READ | TCE_PCI_WRITE;
407
408 liobn = (u64)be32_to_cpu(maprange->liobn);
409 tce_shift = be32_to_cpu(maprange->tce_shift);
410 tce_size = 1ULL << tce_shift;
411 next = start_pfn << PAGE_SHIFT;
412 num_tce = num_pfn << PAGE_SHIFT;
413
414 /* round back to the beginning of the tce page size */
415 num_tce += next & (tce_size - 1);
416 next &= ~(tce_size - 1);
417
418 /* covert to number of tces */
419 num_tce |= tce_size - 1;
420 num_tce >>= tce_shift;
421
422 /* We can map max one pageful of TCEs at a time */
423 do {
424 /*
425 * Set up the page with TCE data, looping through and setting
426 * the values.
427 */
428 limit = min_t(long, num_tce, 4096/TCE_ENTRY_SIZE);
429 dma_offset = next + be64_to_cpu(maprange->dma_base);
430
431 for (l = 0; l < limit; l++) {
432 tcep[l] = proto_tce | next;
433 next += tce_size;
434 }
435
436 rc = plpar_tce_put_indirect(liobn,
437 dma_offset,
438 (u64)virt_to_abs(tcep),
439 limit);
440
441 num_tce -= limit;
442 } while (num_tce > 0 && !rc);
443
444 /* error cleanup: caller will clear whole range */
445
446 local_irq_enable();
447 return rc;
448}
449
450static int tce_setrange_multi_pSeriesLP_walk(unsigned long start_pfn,
451 unsigned long num_pfn, void *arg)
452{
453 return tce_setrange_multi_pSeriesLP(start_pfn, num_pfn, arg);
454}
455
456
457#ifdef CONFIG_PCI
458static void iommu_table_setparms(struct pci_controller *phb,
459 struct device_node *dn,
460 struct iommu_table *tbl)
461{
462 struct device_node *node;
463 const unsigned long *basep, *sw_inval;
464 const u32 *sizep;
465
466 node = phb->dn;
467
468 basep = of_get_property(node, "linux,tce-base", NULL);
469 sizep = of_get_property(node, "linux,tce-size", NULL);
470 if (basep == NULL || sizep == NULL) {
471 printk(KERN_ERR "PCI_DMA: iommu_table_setparms: %s has "
472 "missing tce entries !\n", dn->full_name);
473 return;
474 }
475
476 tbl->it_base = (unsigned long)__va(*basep);
477
478 if (!is_kdump_kernel())
479 memset((void *)tbl->it_base, 0, *sizep);
480
481 tbl->it_busno = phb->bus->number;
482
483 /* Units of tce entries */
484 tbl->it_offset = phb->dma_window_base_cur >> IOMMU_PAGE_SHIFT;
485
486 /* Test if we are going over 2GB of DMA space */
487 if (phb->dma_window_base_cur + phb->dma_window_size > 0x80000000ul) {
488 udbg_printf("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
489 panic("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
490 }
491
492 phb->dma_window_base_cur += phb->dma_window_size;
493
494 /* Set the tce table size - measured in entries */
495 tbl->it_size = phb->dma_window_size >> IOMMU_PAGE_SHIFT;
496
497 tbl->it_index = 0;
498 tbl->it_blocksize = 16;
499 tbl->it_type = TCE_PCI;
500
501 sw_inval = of_get_property(node, "linux,tce-sw-invalidate-info", NULL);
502 if (sw_inval) {
503 /*
504 * This property contains information on how to
505 * invalidate the TCE entry. The first property is
506 * the base MMIO address used to invalidate entries.
507 * The second property tells us the format of the TCE
508 * invalidate (whether it needs to be shifted) and
509 * some magic routing info to add to our invalidate
510 * command.
511 */
512 tbl->it_index = (unsigned long) ioremap(sw_inval[0], 8);
513 tbl->it_busno = sw_inval[1]; /* overload this with magic */
514 tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE;
515 }
516}
517
518/*
519 * iommu_table_setparms_lpar
520 *
521 * Function: On pSeries LPAR systems, return TCE table info, given a pci bus.
522 */
523static void iommu_table_setparms_lpar(struct pci_controller *phb,
524 struct device_node *dn,
525 struct iommu_table *tbl,
526 const void *dma_window)
527{
528 unsigned long offset, size;
529
530 of_parse_dma_window(dn, dma_window, &tbl->it_index, &offset, &size);
531
532 tbl->it_busno = phb->bus->number;
533 tbl->it_base = 0;
534 tbl->it_blocksize = 16;
535 tbl->it_type = TCE_PCI;
536 tbl->it_offset = offset >> IOMMU_PAGE_SHIFT;
537 tbl->it_size = size >> IOMMU_PAGE_SHIFT;
538}
539
540static void pci_dma_bus_setup_pSeries(struct pci_bus *bus)
541{
542 struct device_node *dn;
543 struct iommu_table *tbl;
544 struct device_node *isa_dn, *isa_dn_orig;
545 struct device_node *tmp;
546 struct pci_dn *pci;
547 int children;
548
549 dn = pci_bus_to_OF_node(bus);
550
551 pr_debug("pci_dma_bus_setup_pSeries: setting up bus %s\n", dn->full_name);
552
553 if (bus->self) {
554 /* This is not a root bus, any setup will be done for the
555 * device-side of the bridge in iommu_dev_setup_pSeries().
556 */
557 return;
558 }
559 pci = PCI_DN(dn);
560
561 /* Check if the ISA bus on the system is under
562 * this PHB.
563 */
564 isa_dn = isa_dn_orig = of_find_node_by_type(NULL, "isa");
565
566 while (isa_dn && isa_dn != dn)
567 isa_dn = isa_dn->parent;
568
569 if (isa_dn_orig)
570 of_node_put(isa_dn_orig);
571
572 /* Count number of direct PCI children of the PHB. */
573 for (children = 0, tmp = dn->child; tmp; tmp = tmp->sibling)
574 children++;
575
576 pr_debug("Children: %d\n", children);
577
578 /* Calculate amount of DMA window per slot. Each window must be
579 * a power of two (due to pci_alloc_consistent requirements).
580 *
581 * Keep 256MB aside for PHBs with ISA.
582 */
583
584 if (!isa_dn) {
585 /* No ISA/IDE - just set window size and return */
586 pci->phb->dma_window_size = 0x80000000ul; /* To be divided */
587
588 while (pci->phb->dma_window_size * children > 0x80000000ul)
589 pci->phb->dma_window_size >>= 1;
590 pr_debug("No ISA/IDE, window size is 0x%llx\n",
591 pci->phb->dma_window_size);
592 pci->phb->dma_window_base_cur = 0;
593
594 return;
595 }
596
597 /* If we have ISA, then we probably have an IDE
598 * controller too. Allocate a 128MB table but
599 * skip the first 128MB to avoid stepping on ISA
600 * space.
601 */
602 pci->phb->dma_window_size = 0x8000000ul;
603 pci->phb->dma_window_base_cur = 0x8000000ul;
604
605 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
606 pci->phb->node);
607
608 iommu_table_setparms(pci->phb, dn, tbl);
609 pci->iommu_table = iommu_init_table(tbl, pci->phb->node);
610
611 /* Divide the rest (1.75GB) among the children */
612 pci->phb->dma_window_size = 0x80000000ul;
613 while (pci->phb->dma_window_size * children > 0x70000000ul)
614 pci->phb->dma_window_size >>= 1;
615
616 pr_debug("ISA/IDE, window size is 0x%llx\n", pci->phb->dma_window_size);
617}
618
619
620static void pci_dma_bus_setup_pSeriesLP(struct pci_bus *bus)
621{
622 struct iommu_table *tbl;
623 struct device_node *dn, *pdn;
624 struct pci_dn *ppci;
625 const void *dma_window = NULL;
626
627 dn = pci_bus_to_OF_node(bus);
628
629 pr_debug("pci_dma_bus_setup_pSeriesLP: setting up bus %s\n",
630 dn->full_name);
631
632 /* Find nearest ibm,dma-window, walking up the device tree */
633 for (pdn = dn; pdn != NULL; pdn = pdn->parent) {
634 dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
635 if (dma_window != NULL)
636 break;
637 }
638
639 if (dma_window == NULL) {
640 pr_debug(" no ibm,dma-window property !\n");
641 return;
642 }
643
644 ppci = PCI_DN(pdn);
645
646 pr_debug(" parent is %s, iommu_table: 0x%p\n",
647 pdn->full_name, ppci->iommu_table);
648
649 if (!ppci->iommu_table) {
650 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
651 ppci->phb->node);
652 iommu_table_setparms_lpar(ppci->phb, pdn, tbl, dma_window);
653 ppci->iommu_table = iommu_init_table(tbl, ppci->phb->node);
654 pr_debug(" created table: %p\n", ppci->iommu_table);
655 }
656}
657
658
659static void pci_dma_dev_setup_pSeries(struct pci_dev *dev)
660{
661 struct device_node *dn;
662 struct iommu_table *tbl;
663
664 pr_debug("pci_dma_dev_setup_pSeries: %s\n", pci_name(dev));
665
666 dn = dev->dev.of_node;
667
668 /* If we're the direct child of a root bus, then we need to allocate
669 * an iommu table ourselves. The bus setup code should have setup
670 * the window sizes already.
671 */
672 if (!dev->bus->self) {
673 struct pci_controller *phb = PCI_DN(dn)->phb;
674
675 pr_debug(" --> first child, no bridge. Allocating iommu table.\n");
676 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
677 phb->node);
678 iommu_table_setparms(phb, dn, tbl);
679 PCI_DN(dn)->iommu_table = iommu_init_table(tbl, phb->node);
680 set_iommu_table_base(&dev->dev, PCI_DN(dn)->iommu_table);
681 return;
682 }
683
684 /* If this device is further down the bus tree, search upwards until
685 * an already allocated iommu table is found and use that.
686 */
687
688 while (dn && PCI_DN(dn) && PCI_DN(dn)->iommu_table == NULL)
689 dn = dn->parent;
690
691 if (dn && PCI_DN(dn))
692 set_iommu_table_base(&dev->dev, PCI_DN(dn)->iommu_table);
693 else
694 printk(KERN_WARNING "iommu: Device %s has no iommu table\n",
695 pci_name(dev));
696}
697
698static int __read_mostly disable_ddw;
699
700static int __init disable_ddw_setup(char *str)
701{
702 disable_ddw = 1;
703 printk(KERN_INFO "ppc iommu: disabling ddw.\n");
704
705 return 0;
706}
707
708early_param("disable_ddw", disable_ddw_setup);
709
710static void remove_ddw(struct device_node *np)
711{
712 struct dynamic_dma_window_prop *dwp;
713 struct property *win64;
714 const u32 *ddw_avail;
715 u64 liobn;
716 int len, ret;
717
718 ddw_avail = of_get_property(np, "ibm,ddw-applicable", &len);
719 win64 = of_find_property(np, DIRECT64_PROPNAME, NULL);
720 if (!win64)
721 return;
722
723 if (!ddw_avail || len < 3 * sizeof(u32) || win64->length < sizeof(*dwp))
724 goto delprop;
725
726 dwp = win64->value;
727 liobn = (u64)be32_to_cpu(dwp->liobn);
728
729 /* clear the whole window, note the arg is in kernel pages */
730 ret = tce_clearrange_multi_pSeriesLP(0,
731 1ULL << (be32_to_cpu(dwp->window_shift) - PAGE_SHIFT), dwp);
732 if (ret)
733 pr_warning("%s failed to clear tces in window.\n",
734 np->full_name);
735 else
736 pr_debug("%s successfully cleared tces in window.\n",
737 np->full_name);
738
739 ret = rtas_call(ddw_avail[2], 1, 1, NULL, liobn);
740 if (ret)
741 pr_warning("%s: failed to remove direct window: rtas returned "
742 "%d to ibm,remove-pe-dma-window(%x) %llx\n",
743 np->full_name, ret, ddw_avail[2], liobn);
744 else
745 pr_debug("%s: successfully removed direct window: rtas returned "
746 "%d to ibm,remove-pe-dma-window(%x) %llx\n",
747 np->full_name, ret, ddw_avail[2], liobn);
748
749delprop:
750 ret = prom_remove_property(np, win64);
751 if (ret)
752 pr_warning("%s: failed to remove direct window property: %d\n",
753 np->full_name, ret);
754}
755
756static u64 find_existing_ddw(struct device_node *pdn)
757{
758 struct direct_window *window;
759 const struct dynamic_dma_window_prop *direct64;
760 u64 dma_addr = 0;
761
762 spin_lock(&direct_window_list_lock);
763 /* check if we already created a window and dupe that config if so */
764 list_for_each_entry(window, &direct_window_list, list) {
765 if (window->device == pdn) {
766 direct64 = window->prop;
767 dma_addr = direct64->dma_base;
768 break;
769 }
770 }
771 spin_unlock(&direct_window_list_lock);
772
773 return dma_addr;
774}
775
776static int find_existing_ddw_windows(void)
777{
778 int len;
779 struct device_node *pdn;
780 struct direct_window *window;
781 const struct dynamic_dma_window_prop *direct64;
782
783 if (!firmware_has_feature(FW_FEATURE_LPAR))
784 return 0;
785
786 for_each_node_with_property(pdn, DIRECT64_PROPNAME) {
787 direct64 = of_get_property(pdn, DIRECT64_PROPNAME, &len);
788 if (!direct64)
789 continue;
790
791 window = kzalloc(sizeof(*window), GFP_KERNEL);
792 if (!window || len < sizeof(struct dynamic_dma_window_prop)) {
793 kfree(window);
794 remove_ddw(pdn);
795 continue;
796 }
797
798 window->device = pdn;
799 window->prop = direct64;
800 spin_lock(&direct_window_list_lock);
801 list_add(&window->list, &direct_window_list);
802 spin_unlock(&direct_window_list_lock);
803 }
804
805 return 0;
806}
807machine_arch_initcall(pseries, find_existing_ddw_windows);
808
809static int query_ddw(struct pci_dev *dev, const u32 *ddw_avail,
810 struct ddw_query_response *query)
811{
812 struct eeh_dev *edev;
813 u32 cfg_addr;
814 u64 buid;
815 int ret;
816
817 /*
818 * Get the config address and phb buid of the PE window.
819 * Rely on eeh to retrieve this for us.
820 * Retrieve them from the pci device, not the node with the
821 * dma-window property
822 */
823 edev = pci_dev_to_eeh_dev(dev);
824 cfg_addr = edev->config_addr;
825 if (edev->pe_config_addr)
826 cfg_addr = edev->pe_config_addr;
827 buid = edev->phb->buid;
828
829 ret = rtas_call(ddw_avail[0], 3, 5, (u32 *)query,
830 cfg_addr, BUID_HI(buid), BUID_LO(buid));
831 dev_info(&dev->dev, "ibm,query-pe-dma-windows(%x) %x %x %x"
832 " returned %d\n", ddw_avail[0], cfg_addr, BUID_HI(buid),
833 BUID_LO(buid), ret);
834 return ret;
835}
836
837static int create_ddw(struct pci_dev *dev, const u32 *ddw_avail,
838 struct ddw_create_response *create, int page_shift,
839 int window_shift)
840{
841 struct eeh_dev *edev;
842 u32 cfg_addr;
843 u64 buid;
844 int ret;
845
846 /*
847 * Get the config address and phb buid of the PE window.
848 * Rely on eeh to retrieve this for us.
849 * Retrieve them from the pci device, not the node with the
850 * dma-window property
851 */
852 edev = pci_dev_to_eeh_dev(dev);
853 cfg_addr = edev->config_addr;
854 if (edev->pe_config_addr)
855 cfg_addr = edev->pe_config_addr;
856 buid = edev->phb->buid;
857
858 do {
859 /* extra outputs are LIOBN and dma-addr (hi, lo) */
860 ret = rtas_call(ddw_avail[1], 5, 4, (u32 *)create, cfg_addr,
861 BUID_HI(buid), BUID_LO(buid), page_shift, window_shift);
862 } while (rtas_busy_delay(ret));
863 dev_info(&dev->dev,
864 "ibm,create-pe-dma-window(%x) %x %x %x %x %x returned %d "
865 "(liobn = 0x%x starting addr = %x %x)\n", ddw_avail[1],
866 cfg_addr, BUID_HI(buid), BUID_LO(buid), page_shift,
867 window_shift, ret, create->liobn, create->addr_hi, create->addr_lo);
868
869 return ret;
870}
871
872/*
873 * If the PE supports dynamic dma windows, and there is space for a table
874 * that can map all pages in a linear offset, then setup such a table,
875 * and record the dma-offset in the struct device.
876 *
877 * dev: the pci device we are checking
878 * pdn: the parent pe node with the ibm,dma_window property
879 * Future: also check if we can remap the base window for our base page size
880 *
881 * returns the dma offset for use by dma_set_mask
882 */
883static u64 enable_ddw(struct pci_dev *dev, struct device_node *pdn)
884{
885 int len, ret;
886 struct ddw_query_response query;
887 struct ddw_create_response create;
888 int page_shift;
889 u64 dma_addr, max_addr;
890 struct device_node *dn;
891 const u32 *uninitialized_var(ddw_avail);
892 struct direct_window *window;
893 struct property *win64;
894 struct dynamic_dma_window_prop *ddwprop;
895
896 mutex_lock(&direct_window_init_mutex);
897
898 dma_addr = find_existing_ddw(pdn);
899 if (dma_addr != 0)
900 goto out_unlock;
901
902 /*
903 * the ibm,ddw-applicable property holds the tokens for:
904 * ibm,query-pe-dma-window
905 * ibm,create-pe-dma-window
906 * ibm,remove-pe-dma-window
907 * for the given node in that order.
908 * the property is actually in the parent, not the PE
909 */
910 ddw_avail = of_get_property(pdn, "ibm,ddw-applicable", &len);
911 if (!ddw_avail || len < 3 * sizeof(u32))
912 goto out_unlock;
913
914 /*
915 * Query if there is a second window of size to map the
916 * whole partition. Query returns number of windows, largest
917 * block assigned to PE (partition endpoint), and two bitmasks
918 * of page sizes: supported and supported for migrate-dma.
919 */
920 dn = pci_device_to_OF_node(dev);
921 ret = query_ddw(dev, ddw_avail, &query);
922 if (ret != 0)
923 goto out_unlock;
924
925 if (query.windows_available == 0) {
926 /*
927 * no additional windows are available for this device.
928 * We might be able to reallocate the existing window,
929 * trading in for a larger page size.
930 */
931 dev_dbg(&dev->dev, "no free dynamic windows");
932 goto out_unlock;
933 }
934 if (query.page_size & 4) {
935 page_shift = 24; /* 16MB */
936 } else if (query.page_size & 2) {
937 page_shift = 16; /* 64kB */
938 } else if (query.page_size & 1) {
939 page_shift = 12; /* 4kB */
940 } else {
941 dev_dbg(&dev->dev, "no supported direct page size in mask %x",
942 query.page_size);
943 goto out_unlock;
944 }
945 /* verify the window * number of ptes will map the partition */
946 /* check largest block * page size > max memory hotplug addr */
947 max_addr = memory_hotplug_max();
948 if (query.largest_available_block < (max_addr >> page_shift)) {
949 dev_dbg(&dev->dev, "can't map partiton max 0x%llx with %u "
950 "%llu-sized pages\n", max_addr, query.largest_available_block,
951 1ULL << page_shift);
952 goto out_unlock;
953 }
954 len = order_base_2(max_addr);
955 win64 = kzalloc(sizeof(struct property), GFP_KERNEL);
956 if (!win64) {
957 dev_info(&dev->dev,
958 "couldn't allocate property for 64bit dma window\n");
959 goto out_unlock;
960 }
961 win64->name = kstrdup(DIRECT64_PROPNAME, GFP_KERNEL);
962 win64->value = ddwprop = kmalloc(sizeof(*ddwprop), GFP_KERNEL);
963 win64->length = sizeof(*ddwprop);
964 if (!win64->name || !win64->value) {
965 dev_info(&dev->dev,
966 "couldn't allocate property name and value\n");
967 goto out_free_prop;
968 }
969
970 ret = create_ddw(dev, ddw_avail, &create, page_shift, len);
971 if (ret != 0)
972 goto out_free_prop;
973
974 ddwprop->liobn = cpu_to_be32(create.liobn);
975 ddwprop->dma_base = cpu_to_be64(of_read_number(&create.addr_hi, 2));
976 ddwprop->tce_shift = cpu_to_be32(page_shift);
977 ddwprop->window_shift = cpu_to_be32(len);
978
979 dev_dbg(&dev->dev, "created tce table LIOBN 0x%x for %s\n",
980 create.liobn, dn->full_name);
981
982 window = kzalloc(sizeof(*window), GFP_KERNEL);
983 if (!window)
984 goto out_clear_window;
985
986 ret = walk_system_ram_range(0, memblock_end_of_DRAM() >> PAGE_SHIFT,
987 win64->value, tce_setrange_multi_pSeriesLP_walk);
988 if (ret) {
989 dev_info(&dev->dev, "failed to map direct window for %s: %d\n",
990 dn->full_name, ret);
991 goto out_free_window;
992 }
993
994 ret = prom_add_property(pdn, win64);
995 if (ret) {
996 dev_err(&dev->dev, "unable to add dma window property for %s: %d",
997 pdn->full_name, ret);
998 goto out_free_window;
999 }
1000
1001 window->device = pdn;
1002 window->prop = ddwprop;
1003 spin_lock(&direct_window_list_lock);
1004 list_add(&window->list, &direct_window_list);
1005 spin_unlock(&direct_window_list_lock);
1006
1007 dma_addr = of_read_number(&create.addr_hi, 2);
1008 goto out_unlock;
1009
1010out_free_window:
1011 kfree(window);
1012
1013out_clear_window:
1014 remove_ddw(pdn);
1015
1016out_free_prop:
1017 kfree(win64->name);
1018 kfree(win64->value);
1019 kfree(win64);
1020
1021out_unlock:
1022 mutex_unlock(&direct_window_init_mutex);
1023 return dma_addr;
1024}
1025
1026static void pci_dma_dev_setup_pSeriesLP(struct pci_dev *dev)
1027{
1028 struct device_node *pdn, *dn;
1029 struct iommu_table *tbl;
1030 const void *dma_window = NULL;
1031 struct pci_dn *pci;
1032
1033 pr_debug("pci_dma_dev_setup_pSeriesLP: %s\n", pci_name(dev));
1034
1035 /* dev setup for LPAR is a little tricky, since the device tree might
1036 * contain the dma-window properties per-device and not necessarily
1037 * for the bus. So we need to search upwards in the tree until we
1038 * either hit a dma-window property, OR find a parent with a table
1039 * already allocated.
1040 */
1041 dn = pci_device_to_OF_node(dev);
1042 pr_debug(" node is %s\n", dn->full_name);
1043
1044 for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->iommu_table;
1045 pdn = pdn->parent) {
1046 dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
1047 if (dma_window)
1048 break;
1049 }
1050
1051 if (!pdn || !PCI_DN(pdn)) {
1052 printk(KERN_WARNING "pci_dma_dev_setup_pSeriesLP: "
1053 "no DMA window found for pci dev=%s dn=%s\n",
1054 pci_name(dev), dn? dn->full_name : "<null>");
1055 return;
1056 }
1057 pr_debug(" parent is %s\n", pdn->full_name);
1058
1059 pci = PCI_DN(pdn);
1060 if (!pci->iommu_table) {
1061 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
1062 pci->phb->node);
1063 iommu_table_setparms_lpar(pci->phb, pdn, tbl, dma_window);
1064 pci->iommu_table = iommu_init_table(tbl, pci->phb->node);
1065 pr_debug(" created table: %p\n", pci->iommu_table);
1066 } else {
1067 pr_debug(" found DMA window, table: %p\n", pci->iommu_table);
1068 }
1069
1070 set_iommu_table_base(&dev->dev, pci->iommu_table);
1071}
1072
1073static int dma_set_mask_pSeriesLP(struct device *dev, u64 dma_mask)
1074{
1075 bool ddw_enabled = false;
1076 struct device_node *pdn, *dn;
1077 struct pci_dev *pdev;
1078 const void *dma_window = NULL;
1079 u64 dma_offset;
1080
1081 if (!dev->dma_mask)
1082 return -EIO;
1083
1084 if (!dev_is_pci(dev))
1085 goto check_mask;
1086
1087 pdev = to_pci_dev(dev);
1088
1089 /* only attempt to use a new window if 64-bit DMA is requested */
1090 if (!disable_ddw && dma_mask == DMA_BIT_MASK(64)) {
1091 dn = pci_device_to_OF_node(pdev);
1092 dev_dbg(dev, "node is %s\n", dn->full_name);
1093
1094 /*
1095 * the device tree might contain the dma-window properties
1096 * per-device and not necessarily for the bus. So we need to
1097 * search upwards in the tree until we either hit a dma-window
1098 * property, OR find a parent with a table already allocated.
1099 */
1100 for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->iommu_table;
1101 pdn = pdn->parent) {
1102 dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
1103 if (dma_window)
1104 break;
1105 }
1106 if (pdn && PCI_DN(pdn)) {
1107 dma_offset = enable_ddw(pdev, pdn);
1108 if (dma_offset != 0) {
1109 dev_info(dev, "Using 64-bit direct DMA at offset %llx\n", dma_offset);
1110 set_dma_offset(dev, dma_offset);
1111 set_dma_ops(dev, &dma_direct_ops);
1112 ddw_enabled = true;
1113 }
1114 }
1115 }
1116
1117 /* fall back on iommu ops, restore table pointer with ops */
1118 if (!ddw_enabled && get_dma_ops(dev) != &dma_iommu_ops) {
1119 dev_info(dev, "Restoring 32-bit DMA via iommu\n");
1120 set_dma_ops(dev, &dma_iommu_ops);
1121 pci_dma_dev_setup_pSeriesLP(pdev);
1122 }
1123
1124check_mask:
1125 if (!dma_supported(dev, dma_mask))
1126 return -EIO;
1127
1128 *dev->dma_mask = dma_mask;
1129 return 0;
1130}
1131
1132static u64 dma_get_required_mask_pSeriesLP(struct device *dev)
1133{
1134 if (!dev->dma_mask)
1135 return 0;
1136
1137 if (!disable_ddw && dev_is_pci(dev)) {
1138 struct pci_dev *pdev = to_pci_dev(dev);
1139 struct device_node *dn;
1140
1141 dn = pci_device_to_OF_node(pdev);
1142
1143 /* search upwards for ibm,dma-window */
1144 for (; dn && PCI_DN(dn) && !PCI_DN(dn)->iommu_table;
1145 dn = dn->parent)
1146 if (of_get_property(dn, "ibm,dma-window", NULL))
1147 break;
1148 /* if there is a ibm,ddw-applicable property require 64 bits */
1149 if (dn && PCI_DN(dn) &&
1150 of_get_property(dn, "ibm,ddw-applicable", NULL))
1151 return DMA_BIT_MASK(64);
1152 }
1153
1154 return dma_iommu_ops.get_required_mask(dev);
1155}
1156
1157#else /* CONFIG_PCI */
1158#define pci_dma_bus_setup_pSeries NULL
1159#define pci_dma_dev_setup_pSeries NULL
1160#define pci_dma_bus_setup_pSeriesLP NULL
1161#define pci_dma_dev_setup_pSeriesLP NULL
1162#define dma_set_mask_pSeriesLP NULL
1163#define dma_get_required_mask_pSeriesLP NULL
1164#endif /* !CONFIG_PCI */
1165
1166static int iommu_mem_notifier(struct notifier_block *nb, unsigned long action,
1167 void *data)
1168{
1169 struct direct_window *window;
1170 struct memory_notify *arg = data;
1171 int ret = 0;
1172
1173 switch (action) {
1174 case MEM_GOING_ONLINE:
1175 spin_lock(&direct_window_list_lock);
1176 list_for_each_entry(window, &direct_window_list, list) {
1177 ret |= tce_setrange_multi_pSeriesLP(arg->start_pfn,
1178 arg->nr_pages, window->prop);
1179 /* XXX log error */
1180 }
1181 spin_unlock(&direct_window_list_lock);
1182 break;
1183 case MEM_CANCEL_ONLINE:
1184 case MEM_OFFLINE:
1185 spin_lock(&direct_window_list_lock);
1186 list_for_each_entry(window, &direct_window_list, list) {
1187 ret |= tce_clearrange_multi_pSeriesLP(arg->start_pfn,
1188 arg->nr_pages, window->prop);
1189 /* XXX log error */
1190 }
1191 spin_unlock(&direct_window_list_lock);
1192 break;
1193 default:
1194 break;
1195 }
1196 if (ret && action != MEM_CANCEL_ONLINE)
1197 return NOTIFY_BAD;
1198
1199 return NOTIFY_OK;
1200}
1201
1202static struct notifier_block iommu_mem_nb = {
1203 .notifier_call = iommu_mem_notifier,
1204};
1205
1206static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *node)
1207{
1208 int err = NOTIFY_OK;
1209 struct device_node *np = node;
1210 struct pci_dn *pci = PCI_DN(np);
1211 struct direct_window *window;
1212
1213 switch (action) {
1214 case PSERIES_RECONFIG_REMOVE:
1215 if (pci && pci->iommu_table)
1216 iommu_free_table(pci->iommu_table, np->full_name);
1217
1218 spin_lock(&direct_window_list_lock);
1219 list_for_each_entry(window, &direct_window_list, list) {
1220 if (window->device == np) {
1221 list_del(&window->list);
1222 kfree(window);
1223 break;
1224 }
1225 }
1226 spin_unlock(&direct_window_list_lock);
1227
1228 /*
1229 * Because the notifier runs after isolation of the
1230 * slot, we are guaranteed any DMA window has already
1231 * been revoked and the TCEs have been marked invalid,
1232 * so we don't need a call to remove_ddw(np). However,
1233 * if an additional notifier action is added before the
1234 * isolate call, we should update this code for
1235 * completeness with such a call.
1236 */
1237 break;
1238 default:
1239 err = NOTIFY_DONE;
1240 break;
1241 }
1242 return err;
1243}
1244
1245static struct notifier_block iommu_reconfig_nb = {
1246 .notifier_call = iommu_reconfig_notifier,
1247};
1248
1249/* These are called very early. */
1250void iommu_init_early_pSeries(void)
1251{
1252 if (of_chosen && of_get_property(of_chosen, "linux,iommu-off", NULL))
1253 return;
1254
1255 if (firmware_has_feature(FW_FEATURE_LPAR)) {
1256 if (firmware_has_feature(FW_FEATURE_MULTITCE)) {
1257 ppc_md.tce_build = tce_buildmulti_pSeriesLP;
1258 ppc_md.tce_free = tce_freemulti_pSeriesLP;
1259 } else {
1260 ppc_md.tce_build = tce_build_pSeriesLP;
1261 ppc_md.tce_free = tce_free_pSeriesLP;
1262 }
1263 ppc_md.tce_get = tce_get_pSeriesLP;
1264 ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pSeriesLP;
1265 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_pSeriesLP;
1266 ppc_md.dma_set_mask = dma_set_mask_pSeriesLP;
1267 ppc_md.dma_get_required_mask = dma_get_required_mask_pSeriesLP;
1268 } else {
1269 ppc_md.tce_build = tce_build_pSeries;
1270 ppc_md.tce_free = tce_free_pSeries;
1271 ppc_md.tce_get = tce_get_pseries;
1272 ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pSeries;
1273 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_pSeries;
1274 }
1275
1276
1277 pSeries_reconfig_notifier_register(&iommu_reconfig_nb);
1278 register_memory_notifier(&iommu_mem_nb);
1279
1280 set_pci_dma_ops(&dma_iommu_ops);
1281}
1282
1283static int __init disable_multitce(char *str)
1284{
1285 if (strcmp(str, "off") == 0 &&
1286 firmware_has_feature(FW_FEATURE_LPAR) &&
1287 firmware_has_feature(FW_FEATURE_MULTITCE)) {
1288 printk(KERN_INFO "Disabling MULTITCE firmware feature\n");
1289 ppc_md.tce_build = tce_build_pSeriesLP;
1290 ppc_md.tce_free = tce_free_pSeriesLP;
1291 powerpc_firmware_features &= ~FW_FEATURE_MULTITCE;
1292 }
1293 return 1;
1294}
1295
1296__setup("multitce=", disable_multitce);