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1/*
2 * Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org),
3 * IBM Corp.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 */
10
11#undef DEBUG
12
13#include <linux/kernel.h>
14#include <linux/pci.h>
15#include <linux/delay.h>
16#include <linux/string.h>
17#include <linux/init.h>
18#include <linux/bootmem.h>
19#include <linux/irq.h>
20
21#include <asm/sections.h>
22#include <asm/io.h>
23#include <asm/prom.h>
24#include <asm/pci-bridge.h>
25#include <asm/machdep.h>
26#include <asm/iommu.h>
27#include <asm/ppc-pci.h>
28
29#include "maple.h"
30
31#ifdef DEBUG
32#define DBG(x...) printk(x)
33#else
34#define DBG(x...)
35#endif
36
37static struct pci_controller *u3_agp, *u3_ht, *u4_pcie;
38
39static int __init fixup_one_level_bus_range(struct device_node *node, int higher)
40{
41 for (; node != 0;node = node->sibling) {
42 const int *bus_range;
43 const unsigned int *class_code;
44 int len;
45
46 /* For PCI<->PCI bridges or CardBus bridges, we go down */
47 class_code = of_get_property(node, "class-code", NULL);
48 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
49 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
50 continue;
51 bus_range = of_get_property(node, "bus-range", &len);
52 if (bus_range != NULL && len > 2 * sizeof(int)) {
53 if (bus_range[1] > higher)
54 higher = bus_range[1];
55 }
56 higher = fixup_one_level_bus_range(node->child, higher);
57 }
58 return higher;
59}
60
61/* This routine fixes the "bus-range" property of all bridges in the
62 * system since they tend to have their "last" member wrong on macs
63 *
64 * Note that the bus numbers manipulated here are OF bus numbers, they
65 * are not Linux bus numbers.
66 */
67static void __init fixup_bus_range(struct device_node *bridge)
68{
69 int *bus_range;
70 struct property *prop;
71 int len;
72
73 /* Lookup the "bus-range" property for the hose */
74 prop = of_find_property(bridge, "bus-range", &len);
75 if (prop == NULL || prop->value == NULL || len < 2 * sizeof(int)) {
76 printk(KERN_WARNING "Can't get bus-range for %s\n",
77 bridge->full_name);
78 return;
79 }
80 bus_range = prop->value;
81 bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]);
82}
83
84
85static unsigned long u3_agp_cfa0(u8 devfn, u8 off)
86{
87 return (1 << (unsigned long)PCI_SLOT(devfn)) |
88 ((unsigned long)PCI_FUNC(devfn) << 8) |
89 ((unsigned long)off & 0xFCUL);
90}
91
92static unsigned long u3_agp_cfa1(u8 bus, u8 devfn, u8 off)
93{
94 return ((unsigned long)bus << 16) |
95 ((unsigned long)devfn << 8) |
96 ((unsigned long)off & 0xFCUL) |
97 1UL;
98}
99
100static volatile void __iomem *u3_agp_cfg_access(struct pci_controller* hose,
101 u8 bus, u8 dev_fn, u8 offset)
102{
103 unsigned int caddr;
104
105 if (bus == hose->first_busno) {
106 if (dev_fn < (11 << 3))
107 return NULL;
108 caddr = u3_agp_cfa0(dev_fn, offset);
109 } else
110 caddr = u3_agp_cfa1(bus, dev_fn, offset);
111
112 /* Uninorth will return garbage if we don't read back the value ! */
113 do {
114 out_le32(hose->cfg_addr, caddr);
115 } while (in_le32(hose->cfg_addr) != caddr);
116
117 offset &= 0x07;
118 return hose->cfg_data + offset;
119}
120
121static int u3_agp_read_config(struct pci_bus *bus, unsigned int devfn,
122 int offset, int len, u32 *val)
123{
124 struct pci_controller *hose;
125 volatile void __iomem *addr;
126
127 hose = pci_bus_to_host(bus);
128 if (hose == NULL)
129 return PCIBIOS_DEVICE_NOT_FOUND;
130
131 addr = u3_agp_cfg_access(hose, bus->number, devfn, offset);
132 if (!addr)
133 return PCIBIOS_DEVICE_NOT_FOUND;
134 /*
135 * Note: the caller has already checked that offset is
136 * suitably aligned and that len is 1, 2 or 4.
137 */
138 switch (len) {
139 case 1:
140 *val = in_8(addr);
141 break;
142 case 2:
143 *val = in_le16(addr);
144 break;
145 default:
146 *val = in_le32(addr);
147 break;
148 }
149 return PCIBIOS_SUCCESSFUL;
150}
151
152static int u3_agp_write_config(struct pci_bus *bus, unsigned int devfn,
153 int offset, int len, u32 val)
154{
155 struct pci_controller *hose;
156 volatile void __iomem *addr;
157
158 hose = pci_bus_to_host(bus);
159 if (hose == NULL)
160 return PCIBIOS_DEVICE_NOT_FOUND;
161
162 addr = u3_agp_cfg_access(hose, bus->number, devfn, offset);
163 if (!addr)
164 return PCIBIOS_DEVICE_NOT_FOUND;
165 /*
166 * Note: the caller has already checked that offset is
167 * suitably aligned and that len is 1, 2 or 4.
168 */
169 switch (len) {
170 case 1:
171 out_8(addr, val);
172 break;
173 case 2:
174 out_le16(addr, val);
175 break;
176 default:
177 out_le32(addr, val);
178 break;
179 }
180 return PCIBIOS_SUCCESSFUL;
181}
182
183static struct pci_ops u3_agp_pci_ops =
184{
185 .read = u3_agp_read_config,
186 .write = u3_agp_write_config,
187};
188
189static unsigned long u3_ht_cfa0(u8 devfn, u8 off)
190{
191 return (devfn << 8) | off;
192}
193
194static unsigned long u3_ht_cfa1(u8 bus, u8 devfn, u8 off)
195{
196 return u3_ht_cfa0(devfn, off) + (bus << 16) + 0x01000000UL;
197}
198
199static volatile void __iomem *u3_ht_cfg_access(struct pci_controller* hose,
200 u8 bus, u8 devfn, u8 offset)
201{
202 if (bus == hose->first_busno) {
203 if (PCI_SLOT(devfn) == 0)
204 return NULL;
205 return hose->cfg_data + u3_ht_cfa0(devfn, offset);
206 } else
207 return hose->cfg_data + u3_ht_cfa1(bus, devfn, offset);
208}
209
210static int u3_ht_root_read_config(struct pci_controller *hose, u8 offset,
211 int len, u32 *val)
212{
213 volatile void __iomem *addr;
214
215 addr = hose->cfg_addr;
216 addr += ((offset & ~3) << 2) + (4 - len - (offset & 3));
217
218 switch (len) {
219 case 1:
220 *val = in_8(addr);
221 break;
222 case 2:
223 *val = in_be16(addr);
224 break;
225 default:
226 *val = in_be32(addr);
227 break;
228 }
229
230 return PCIBIOS_SUCCESSFUL;
231}
232
233static int u3_ht_root_write_config(struct pci_controller *hose, u8 offset,
234 int len, u32 val)
235{
236 volatile void __iomem *addr;
237
238 addr = hose->cfg_addr + ((offset & ~3) << 2) + (4 - len - (offset & 3));
239
240 if (offset >= PCI_BASE_ADDRESS_0 && offset < PCI_CAPABILITY_LIST)
241 return PCIBIOS_SUCCESSFUL;
242
243 switch (len) {
244 case 1:
245 out_8(addr, val);
246 break;
247 case 2:
248 out_be16(addr, val);
249 break;
250 default:
251 out_be32(addr, val);
252 break;
253 }
254
255 return PCIBIOS_SUCCESSFUL;
256}
257
258static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
259 int offset, int len, u32 *val)
260{
261 struct pci_controller *hose;
262 volatile void __iomem *addr;
263
264 hose = pci_bus_to_host(bus);
265 if (hose == NULL)
266 return PCIBIOS_DEVICE_NOT_FOUND;
267
268 if (bus->number == hose->first_busno && devfn == PCI_DEVFN(0, 0))
269 return u3_ht_root_read_config(hose, offset, len, val);
270
271 if (offset > 0xff)
272 return PCIBIOS_BAD_REGISTER_NUMBER;
273
274 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
275 if (!addr)
276 return PCIBIOS_DEVICE_NOT_FOUND;
277
278 /*
279 * Note: the caller has already checked that offset is
280 * suitably aligned and that len is 1, 2 or 4.
281 */
282 switch (len) {
283 case 1:
284 *val = in_8(addr);
285 break;
286 case 2:
287 *val = in_le16(addr);
288 break;
289 default:
290 *val = in_le32(addr);
291 break;
292 }
293 return PCIBIOS_SUCCESSFUL;
294}
295
296static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
297 int offset, int len, u32 val)
298{
299 struct pci_controller *hose;
300 volatile void __iomem *addr;
301
302 hose = pci_bus_to_host(bus);
303 if (hose == NULL)
304 return PCIBIOS_DEVICE_NOT_FOUND;
305
306 if (bus->number == hose->first_busno && devfn == PCI_DEVFN(0, 0))
307 return u3_ht_root_write_config(hose, offset, len, val);
308
309 if (offset > 0xff)
310 return PCIBIOS_BAD_REGISTER_NUMBER;
311
312 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
313 if (!addr)
314 return PCIBIOS_DEVICE_NOT_FOUND;
315 /*
316 * Note: the caller has already checked that offset is
317 * suitably aligned and that len is 1, 2 or 4.
318 */
319 switch (len) {
320 case 1:
321 out_8(addr, val);
322 break;
323 case 2:
324 out_le16(addr, val);
325 break;
326 default:
327 out_le32(addr, val);
328 break;
329 }
330 return PCIBIOS_SUCCESSFUL;
331}
332
333static struct pci_ops u3_ht_pci_ops =
334{
335 .read = u3_ht_read_config,
336 .write = u3_ht_write_config,
337};
338
339static unsigned int u4_pcie_cfa0(unsigned int devfn, unsigned int off)
340{
341 return (1 << PCI_SLOT(devfn)) |
342 (PCI_FUNC(devfn) << 8) |
343 ((off >> 8) << 28) |
344 (off & 0xfcu);
345}
346
347static unsigned int u4_pcie_cfa1(unsigned int bus, unsigned int devfn,
348 unsigned int off)
349{
350 return (bus << 16) |
351 (devfn << 8) |
352 ((off >> 8) << 28) |
353 (off & 0xfcu) | 1u;
354}
355
356static volatile void __iomem *u4_pcie_cfg_access(struct pci_controller* hose,
357 u8 bus, u8 dev_fn, int offset)
358{
359 unsigned int caddr;
360
361 if (bus == hose->first_busno)
362 caddr = u4_pcie_cfa0(dev_fn, offset);
363 else
364 caddr = u4_pcie_cfa1(bus, dev_fn, offset);
365
366 /* Uninorth will return garbage if we don't read back the value ! */
367 do {
368 out_le32(hose->cfg_addr, caddr);
369 } while (in_le32(hose->cfg_addr) != caddr);
370
371 offset &= 0x03;
372 return hose->cfg_data + offset;
373}
374
375static int u4_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
376 int offset, int len, u32 *val)
377{
378 struct pci_controller *hose;
379 volatile void __iomem *addr;
380
381 hose = pci_bus_to_host(bus);
382 if (hose == NULL)
383 return PCIBIOS_DEVICE_NOT_FOUND;
384 if (offset >= 0x1000)
385 return PCIBIOS_BAD_REGISTER_NUMBER;
386 addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset);
387 if (!addr)
388 return PCIBIOS_DEVICE_NOT_FOUND;
389 /*
390 * Note: the caller has already checked that offset is
391 * suitably aligned and that len is 1, 2 or 4.
392 */
393 switch (len) {
394 case 1:
395 *val = in_8(addr);
396 break;
397 case 2:
398 *val = in_le16(addr);
399 break;
400 default:
401 *val = in_le32(addr);
402 break;
403 }
404 return PCIBIOS_SUCCESSFUL;
405}
406static int u4_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
407 int offset, int len, u32 val)
408{
409 struct pci_controller *hose;
410 volatile void __iomem *addr;
411
412 hose = pci_bus_to_host(bus);
413 if (hose == NULL)
414 return PCIBIOS_DEVICE_NOT_FOUND;
415 if (offset >= 0x1000)
416 return PCIBIOS_BAD_REGISTER_NUMBER;
417 addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset);
418 if (!addr)
419 return PCIBIOS_DEVICE_NOT_FOUND;
420 /*
421 * Note: the caller has already checked that offset is
422 * suitably aligned and that len is 1, 2 or 4.
423 */
424 switch (len) {
425 case 1:
426 out_8(addr, val);
427 break;
428 case 2:
429 out_le16(addr, val);
430 break;
431 default:
432 out_le32(addr, val);
433 break;
434 }
435 return PCIBIOS_SUCCESSFUL;
436}
437
438static struct pci_ops u4_pcie_pci_ops =
439{
440 .read = u4_pcie_read_config,
441 .write = u4_pcie_write_config,
442};
443
444static void __init setup_u3_agp(struct pci_controller* hose)
445{
446 /* On G5, we move AGP up to high bus number so we don't need
447 * to reassign bus numbers for HT. If we ever have P2P bridges
448 * on AGP, we'll have to move pci_assign_all_buses to the
449 * pci_controller structure so we enable it for AGP and not for
450 * HT childs.
451 * We hard code the address because of the different size of
452 * the reg address cell, we shall fix that by killing struct
453 * reg_property and using some accessor functions instead
454 */
455 hose->first_busno = 0xf0;
456 hose->last_busno = 0xff;
457 hose->ops = &u3_agp_pci_ops;
458 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
459 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
460
461 u3_agp = hose;
462}
463
464static void __init setup_u4_pcie(struct pci_controller* hose)
465{
466 /* We currently only implement the "non-atomic" config space, to
467 * be optimised later.
468 */
469 hose->ops = &u4_pcie_pci_ops;
470 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
471 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
472
473 u4_pcie = hose;
474}
475
476static void __init setup_u3_ht(struct pci_controller* hose)
477{
478 hose->ops = &u3_ht_pci_ops;
479
480 /* We hard code the address because of the different size of
481 * the reg address cell, we shall fix that by killing struct
482 * reg_property and using some accessor functions instead
483 */
484 hose->cfg_data = ioremap(0xf2000000, 0x02000000);
485 hose->cfg_addr = ioremap(0xf8070000, 0x1000);
486
487 hose->first_busno = 0;
488 hose->last_busno = 0xef;
489
490 u3_ht = hose;
491}
492
493static int __init maple_add_bridge(struct device_node *dev)
494{
495 int len;
496 struct pci_controller *hose;
497 char* disp_name;
498 const int *bus_range;
499 int primary = 1;
500
501 DBG("Adding PCI host bridge %s\n", dev->full_name);
502
503 bus_range = of_get_property(dev, "bus-range", &len);
504 if (bus_range == NULL || len < 2 * sizeof(int)) {
505 printk(KERN_WARNING "Can't get bus-range for %s, assume bus 0\n",
506 dev->full_name);
507 }
508
509 hose = pcibios_alloc_controller(dev);
510 if (hose == NULL)
511 return -ENOMEM;
512 hose->first_busno = bus_range ? bus_range[0] : 0;
513 hose->last_busno = bus_range ? bus_range[1] : 0xff;
514
515 disp_name = NULL;
516 if (of_device_is_compatible(dev, "u3-agp")) {
517 setup_u3_agp(hose);
518 disp_name = "U3-AGP";
519 primary = 0;
520 } else if (of_device_is_compatible(dev, "u3-ht")) {
521 setup_u3_ht(hose);
522 disp_name = "U3-HT";
523 primary = 1;
524 } else if (of_device_is_compatible(dev, "u4-pcie")) {
525 setup_u4_pcie(hose);
526 disp_name = "U4-PCIE";
527 primary = 0;
528 }
529 printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number: %d->%d\n",
530 disp_name, hose->first_busno, hose->last_busno);
531
532 /* Interpret the "ranges" property */
533 /* This also maps the I/O region and sets isa_io/mem_base */
534 pci_process_bridge_OF_ranges(hose, dev, primary);
535
536 /* Fixup "bus-range" OF property */
537 fixup_bus_range(dev);
538
539 /* Check for legacy IOs */
540 isa_bridge_find_early(hose);
541
542 return 0;
543}
544
545
546void __devinit maple_pci_irq_fixup(struct pci_dev *dev)
547{
548 DBG(" -> maple_pci_irq_fixup\n");
549
550 /* Fixup IRQ for PCIe host */
551 if (u4_pcie != NULL && dev->bus->number == 0 &&
552 pci_bus_to_host(dev->bus) == u4_pcie) {
553 printk(KERN_DEBUG "Fixup U4 PCIe IRQ\n");
554 dev->irq = irq_create_mapping(NULL, 1);
555 if (dev->irq != NO_IRQ)
556 irq_set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW);
557 }
558
559 /* Hide AMD8111 IDE interrupt when in legacy mode so
560 * the driver calls pci_get_legacy_ide_irq()
561 */
562 if (dev->vendor == PCI_VENDOR_ID_AMD &&
563 dev->device == PCI_DEVICE_ID_AMD_8111_IDE &&
564 (dev->class & 5) != 5) {
565 dev->irq = NO_IRQ;
566 }
567
568 DBG(" <- maple_pci_irq_fixup\n");
569}
570
571void __init maple_pci_init(void)
572{
573 struct device_node *np, *root;
574 struct device_node *ht = NULL;
575
576 /* Probe root PCI hosts, that is on U3 the AGP host and the
577 * HyperTransport host. That one is actually "kept" around
578 * and actually added last as it's resource management relies
579 * on the AGP resources to have been setup first
580 */
581 root = of_find_node_by_path("/");
582 if (root == NULL) {
583 printk(KERN_CRIT "maple_find_bridges: can't find root of device tree\n");
584 return;
585 }
586 for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) {
587 if (!np->type)
588 continue;
589 if (strcmp(np->type, "pci") && strcmp(np->type, "ht"))
590 continue;
591 if ((of_device_is_compatible(np, "u4-pcie") ||
592 of_device_is_compatible(np, "u3-agp")) &&
593 maple_add_bridge(np) == 0)
594 of_node_get(np);
595
596 if (of_device_is_compatible(np, "u3-ht")) {
597 of_node_get(np);
598 ht = np;
599 }
600 }
601 of_node_put(root);
602
603 /* Now setup the HyperTransport host if we found any
604 */
605 if (ht && maple_add_bridge(ht) != 0)
606 of_node_put(ht);
607
608 /* Setup the linkage between OF nodes and PHBs */
609 pci_devs_phb_init();
610
611 /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We
612 * assume there is no P2P bridge on the AGP bus, which should be a
613 * safe assumptions hopefully.
614 */
615 if (u3_agp) {
616 struct device_node *np = u3_agp->dn;
617 PCI_DN(np)->busno = 0xf0;
618 for (np = np->child; np; np = np->sibling)
619 PCI_DN(np)->busno = 0xf0;
620 }
621
622 /* Tell pci.c to not change any resource allocations. */
623 pci_add_flags(PCI_PROBE_ONLY);
624}
625
626int maple_pci_get_legacy_ide_irq(struct pci_dev *pdev, int channel)
627{
628 struct device_node *np;
629 unsigned int defirq = channel ? 15 : 14;
630 unsigned int irq;
631
632 if (pdev->vendor != PCI_VENDOR_ID_AMD ||
633 pdev->device != PCI_DEVICE_ID_AMD_8111_IDE)
634 return defirq;
635
636 np = pci_device_to_OF_node(pdev);
637 if (np == NULL) {
638 printk("Failed to locate OF node for IDE %s\n",
639 pci_name(pdev));
640 return defirq;
641 }
642 irq = irq_of_parse_and_map(np, channel & 0x1);
643 if (irq == NO_IRQ) {
644 printk("Failed to map onboard IDE interrupt for channel %d\n",
645 channel);
646 return defirq;
647 }
648 return irq;
649}
650
651static void __devinit quirk_ipr_msi(struct pci_dev *dev)
652{
653 /* Something prevents MSIs from the IPR from working on Bimini,
654 * and the driver has no smarts to recover. So disable MSI
655 * on it for now. */
656
657 if (machine_is(maple)) {
658 dev->no_msi = 1;
659 dev_info(&dev->dev, "Quirk disabled MSI\n");
660 }
661}
662DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN,
663 quirk_ipr_msi);