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1/*
2 * Copyright (C) 2006-2010, 2012 Freescale Semicondutor, Inc.
3 * All rights reserved.
4 *
5 * Author: Andy Fleming <afleming@freescale.com>
6 *
7 * Based on 83xx/mpc8360e_pb.c by:
8 * Li Yang <LeoLi@freescale.com>
9 * Yin Olivia <Hong-hua.Yin@freescale.com>
10 *
11 * Description:
12 * MPC85xx MDS board specific routines.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
18 */
19
20#include <linux/stddef.h>
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/errno.h>
24#include <linux/reboot.h>
25#include <linux/pci.h>
26#include <linux/kdev_t.h>
27#include <linux/major.h>
28#include <linux/console.h>
29#include <linux/delay.h>
30#include <linux/seq_file.h>
31#include <linux/initrd.h>
32#include <linux/fsl_devices.h>
33#include <linux/of_platform.h>
34#include <linux/of_device.h>
35#include <linux/phy.h>
36#include <linux/memblock.h>
37
38#include <linux/atomic.h>
39#include <asm/time.h>
40#include <asm/io.h>
41#include <asm/machdep.h>
42#include <asm/pci-bridge.h>
43#include <asm/irq.h>
44#include <mm/mmu_decl.h>
45#include <asm/prom.h>
46#include <asm/udbg.h>
47#include <sysdev/fsl_soc.h>
48#include <sysdev/fsl_pci.h>
49#include <sysdev/simple_gpio.h>
50#include <asm/qe.h>
51#include <asm/qe_ic.h>
52#include <asm/mpic.h>
53#include <asm/swiotlb.h>
54#include <asm/fsl_guts.h>
55#include "smp.h"
56
57#include "mpc85xx.h"
58
59#undef DEBUG
60#ifdef DEBUG
61#define DBG(fmt...) udbg_printf(fmt)
62#else
63#define DBG(fmt...)
64#endif
65
66#define MV88E1111_SCR 0x10
67#define MV88E1111_SCR_125CLK 0x0010
68static int mpc8568_fixup_125_clock(struct phy_device *phydev)
69{
70 int scr;
71 int err;
72
73 /* Workaround for the 125 CLK Toggle */
74 scr = phy_read(phydev, MV88E1111_SCR);
75
76 if (scr < 0)
77 return scr;
78
79 err = phy_write(phydev, MV88E1111_SCR, scr & ~(MV88E1111_SCR_125CLK));
80
81 if (err)
82 return err;
83
84 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
85
86 if (err)
87 return err;
88
89 scr = phy_read(phydev, MV88E1111_SCR);
90
91 if (scr < 0)
92 return scr;
93
94 err = phy_write(phydev, MV88E1111_SCR, scr | 0x0008);
95
96 return err;
97}
98
99static int mpc8568_mds_phy_fixups(struct phy_device *phydev)
100{
101 int temp;
102 int err;
103
104 /* Errata */
105 err = phy_write(phydev,29, 0x0006);
106
107 if (err)
108 return err;
109
110 temp = phy_read(phydev, 30);
111
112 if (temp < 0)
113 return temp;
114
115 temp = (temp & (~0x8000)) | 0x4000;
116 err = phy_write(phydev,30, temp);
117
118 if (err)
119 return err;
120
121 err = phy_write(phydev,29, 0x000a);
122
123 if (err)
124 return err;
125
126 temp = phy_read(phydev, 30);
127
128 if (temp < 0)
129 return temp;
130
131 temp = phy_read(phydev, 30);
132
133 if (temp < 0)
134 return temp;
135
136 temp &= ~0x0020;
137
138 err = phy_write(phydev,30,temp);
139
140 if (err)
141 return err;
142
143 /* Disable automatic MDI/MDIX selection */
144 temp = phy_read(phydev, 16);
145
146 if (temp < 0)
147 return temp;
148
149 temp &= ~0x0060;
150 err = phy_write(phydev,16,temp);
151
152 return err;
153}
154
155/* ************************************************************************
156 *
157 * Setup the architecture
158 *
159 */
160#ifdef CONFIG_QUICC_ENGINE
161static void __init mpc85xx_mds_reset_ucc_phys(void)
162{
163 struct device_node *np;
164 static u8 __iomem *bcsr_regs;
165
166 /* Map BCSR area */
167 np = of_find_node_by_name(NULL, "bcsr");
168 if (!np)
169 return;
170
171 bcsr_regs = of_iomap(np, 0);
172 of_node_put(np);
173 if (!bcsr_regs)
174 return;
175
176 if (machine_is(mpc8568_mds)) {
177#define BCSR_UCC1_GETH_EN (0x1 << 7)
178#define BCSR_UCC2_GETH_EN (0x1 << 7)
179#define BCSR_UCC1_MODE_MSK (0x3 << 4)
180#define BCSR_UCC2_MODE_MSK (0x3 << 0)
181
182 /* Turn off UCC1 & UCC2 */
183 clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
184 clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
185
186 /* Mode is RGMII, all bits clear */
187 clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK |
188 BCSR_UCC2_MODE_MSK);
189
190 /* Turn UCC1 & UCC2 on */
191 setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
192 setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
193 } else if (machine_is(mpc8569_mds)) {
194#define BCSR7_UCC12_GETHnRST (0x1 << 2)
195#define BCSR8_UEM_MARVELL_RST (0x1 << 1)
196#define BCSR_UCC_RGMII (0x1 << 6)
197#define BCSR_UCC_RTBI (0x1 << 5)
198 /*
199 * U-Boot mangles interrupt polarity for Marvell PHYs,
200 * so reset built-in and UEM Marvell PHYs, this puts
201 * the PHYs into their normal state.
202 */
203 clrbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
204 setbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
205
206 setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
207 clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
208
209 for (np = NULL; (np = of_find_compatible_node(np,
210 "network",
211 "ucc_geth")) != NULL;) {
212 const unsigned int *prop;
213 int ucc_num;
214
215 prop = of_get_property(np, "cell-index", NULL);
216 if (prop == NULL)
217 continue;
218
219 ucc_num = *prop - 1;
220
221 prop = of_get_property(np, "phy-connection-type", NULL);
222 if (prop == NULL)
223 continue;
224
225 if (strcmp("rtbi", (const char *)prop) == 0)
226 clrsetbits_8(&bcsr_regs[7 + ucc_num],
227 BCSR_UCC_RGMII, BCSR_UCC_RTBI);
228 }
229 } else if (machine_is(p1021_mds)) {
230#define BCSR11_ENET_MICRST (0x1 << 5)
231 /* Reset Micrel PHY */
232 clrbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
233 setbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
234 }
235
236 iounmap(bcsr_regs);
237}
238
239static void __init mpc85xx_mds_qe_init(void)
240{
241 struct device_node *np;
242
243 np = of_find_compatible_node(NULL, NULL, "fsl,qe");
244 if (!np) {
245 np = of_find_node_by_name(NULL, "qe");
246 if (!np)
247 return;
248 }
249
250 if (!of_device_is_available(np)) {
251 of_node_put(np);
252 return;
253 }
254
255 qe_reset();
256 of_node_put(np);
257
258 np = of_find_node_by_name(NULL, "par_io");
259 if (np) {
260 struct device_node *ucc;
261
262 par_io_init(np);
263 of_node_put(np);
264
265 for_each_node_by_name(ucc, "ucc")
266 par_io_of_config(ucc);
267 }
268
269 mpc85xx_mds_reset_ucc_phys();
270
271 if (machine_is(p1021_mds)) {
272
273 struct ccsr_guts __iomem *guts;
274
275 np = of_find_node_by_name(NULL, "global-utilities");
276 if (np) {
277 guts = of_iomap(np, 0);
278 if (!guts)
279 pr_err("mpc85xx-rdb: could not map global utilities register\n");
280 else{
281 /* P1021 has pins muxed for QE and other functions. To
282 * enable QE UEC mode, we need to set bit QE0 for UCC1
283 * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
284 * and QE12 for QE MII management signals in PMUXCR
285 * register.
286 */
287 setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
288 MPC85xx_PMUXCR_QE(3) |
289 MPC85xx_PMUXCR_QE(9) |
290 MPC85xx_PMUXCR_QE(12));
291 iounmap(guts);
292 }
293 of_node_put(np);
294 }
295
296 }
297}
298
299static void __init mpc85xx_mds_qeic_init(void)
300{
301 struct device_node *np;
302
303 np = of_find_compatible_node(NULL, NULL, "fsl,qe");
304 if (!of_device_is_available(np)) {
305 of_node_put(np);
306 return;
307 }
308
309 np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
310 if (!np) {
311 np = of_find_node_by_type(NULL, "qeic");
312 if (!np)
313 return;
314 }
315
316 if (machine_is(p1021_mds))
317 qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
318 qe_ic_cascade_high_mpic);
319 else
320 qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
321 of_node_put(np);
322}
323#else
324static void __init mpc85xx_mds_qe_init(void) { }
325static void __init mpc85xx_mds_qeic_init(void) { }
326#endif /* CONFIG_QUICC_ENGINE */
327
328static void __init mpc85xx_mds_setup_arch(void)
329{
330#ifdef CONFIG_PCI
331 struct pci_controller *hose;
332 struct device_node *np;
333#endif
334 dma_addr_t max = 0xffffffff;
335
336 if (ppc_md.progress)
337 ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
338
339#ifdef CONFIG_PCI
340 for_each_node_by_type(np, "pci") {
341 if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
342 of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
343 struct resource rsrc;
344 of_address_to_resource(np, 0, &rsrc);
345 if ((rsrc.start & 0xfffff) == 0x8000)
346 fsl_add_bridge(np, 1);
347 else
348 fsl_add_bridge(np, 0);
349
350 hose = pci_find_hose_for_OF_device(np);
351 max = min(max, hose->dma_window_base_cur +
352 hose->dma_window_size);
353 }
354 }
355#endif
356
357 mpc85xx_smp_init();
358
359 mpc85xx_mds_qe_init();
360
361#ifdef CONFIG_SWIOTLB
362 if (memblock_end_of_DRAM() > max) {
363 ppc_swiotlb_enable = 1;
364 set_pci_dma_ops(&swiotlb_dma_ops);
365 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
366 }
367#endif
368}
369
370
371static int __init board_fixups(void)
372{
373 char phy_id[20];
374 char *compstrs[2] = {"fsl,gianfar-mdio", "fsl,ucc-mdio"};
375 struct device_node *mdio;
376 struct resource res;
377 int i;
378
379 for (i = 0; i < ARRAY_SIZE(compstrs); i++) {
380 mdio = of_find_compatible_node(NULL, NULL, compstrs[i]);
381
382 of_address_to_resource(mdio, 0, &res);
383 snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
384 (unsigned long long)res.start, 1);
385
386 phy_register_fixup_for_id(phy_id, mpc8568_fixup_125_clock);
387 phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
388
389 /* Register a workaround for errata */
390 snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
391 (unsigned long long)res.start, 7);
392 phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
393
394 of_node_put(mdio);
395 }
396
397 return 0;
398}
399machine_arch_initcall(mpc8568_mds, board_fixups);
400machine_arch_initcall(mpc8569_mds, board_fixups);
401
402static int __init mpc85xx_publish_devices(void)
403{
404 if (machine_is(mpc8568_mds))
405 simple_gpiochip_init("fsl,mpc8568mds-bcsr-gpio");
406 if (machine_is(mpc8569_mds))
407 simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio");
408
409 return mpc85xx_common_publish_devices();
410}
411
412machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices);
413machine_device_initcall(mpc8569_mds, mpc85xx_publish_devices);
414machine_device_initcall(p1021_mds, mpc85xx_common_publish_devices);
415
416machine_arch_initcall(mpc8568_mds, swiotlb_setup_bus_notifier);
417machine_arch_initcall(mpc8569_mds, swiotlb_setup_bus_notifier);
418machine_arch_initcall(p1021_mds, swiotlb_setup_bus_notifier);
419
420static void __init mpc85xx_mds_pic_init(void)
421{
422 struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
423 MPIC_SINGLE_DEST_CPU,
424 0, 256, " OpenPIC ");
425 BUG_ON(mpic == NULL);
426
427 mpic_init(mpic);
428 mpc85xx_mds_qeic_init();
429}
430
431static int __init mpc85xx_mds_probe(void)
432{
433 unsigned long root = of_get_flat_dt_root();
434
435 return of_flat_dt_is_compatible(root, "MPC85xxMDS");
436}
437
438define_machine(mpc8568_mds) {
439 .name = "MPC8568 MDS",
440 .probe = mpc85xx_mds_probe,
441 .setup_arch = mpc85xx_mds_setup_arch,
442 .init_IRQ = mpc85xx_mds_pic_init,
443 .get_irq = mpic_get_irq,
444 .restart = fsl_rstcr_restart,
445 .calibrate_decr = generic_calibrate_decr,
446 .progress = udbg_progress,
447#ifdef CONFIG_PCI
448 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
449#endif
450};
451
452static int __init mpc8569_mds_probe(void)
453{
454 unsigned long root = of_get_flat_dt_root();
455
456 return of_flat_dt_is_compatible(root, "fsl,MPC8569EMDS");
457}
458
459define_machine(mpc8569_mds) {
460 .name = "MPC8569 MDS",
461 .probe = mpc8569_mds_probe,
462 .setup_arch = mpc85xx_mds_setup_arch,
463 .init_IRQ = mpc85xx_mds_pic_init,
464 .get_irq = mpic_get_irq,
465 .restart = fsl_rstcr_restart,
466 .calibrate_decr = generic_calibrate_decr,
467 .progress = udbg_progress,
468#ifdef CONFIG_PCI
469 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
470#endif
471};
472
473static int __init p1021_mds_probe(void)
474{
475 unsigned long root = of_get_flat_dt_root();
476
477 return of_flat_dt_is_compatible(root, "fsl,P1021MDS");
478
479}
480
481define_machine(p1021_mds) {
482 .name = "P1021 MDS",
483 .probe = p1021_mds_probe,
484 .setup_arch = mpc85xx_mds_setup_arch,
485 .init_IRQ = mpc85xx_mds_pic_init,
486 .get_irq = mpic_get_irq,
487 .restart = fsl_rstcr_restart,
488 .calibrate_decr = generic_calibrate_decr,
489 .progress = udbg_progress,
490#ifdef CONFIG_PCI
491 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
492#endif
493};
494