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1/*
2 * Copyright (C) 2007,2008 Freescale Semiconductor, Inc. All rights reserved.
3 *
4 * Author: John Rigby <jrigby@freescale.com>
5 *
6 * Description:
7 * MPC512x Shared code
8 *
9 * This is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#include <linux/kernel.h>
16#include <linux/io.h>
17#include <linux/irq.h>
18#include <linux/of_platform.h>
19#include <linux/fsl-diu-fb.h>
20#include <linux/bootmem.h>
21#include <sysdev/fsl_soc.h>
22
23#include <asm/cacheflush.h>
24#include <asm/machdep.h>
25#include <asm/ipic.h>
26#include <asm/prom.h>
27#include <asm/time.h>
28#include <asm/mpc5121.h>
29#include <asm/mpc52xx_psc.h>
30
31#include "mpc512x.h"
32
33static struct mpc512x_reset_module __iomem *reset_module_base;
34
35static void __init mpc512x_restart_init(void)
36{
37 struct device_node *np;
38
39 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-reset");
40 if (!np)
41 return;
42
43 reset_module_base = of_iomap(np, 0);
44 of_node_put(np);
45}
46
47void mpc512x_restart(char *cmd)
48{
49 if (reset_module_base) {
50 /* Enable software reset "RSTE" */
51 out_be32(&reset_module_base->rpr, 0x52535445);
52 /* Set software hard reset */
53 out_be32(&reset_module_base->rcr, 0x2);
54 } else {
55 pr_err("Restart module not mapped.\n");
56 }
57 for (;;)
58 ;
59}
60
61struct fsl_diu_shared_fb {
62 u8 gamma[0x300]; /* 32-bit aligned! */
63 struct diu_ad ad0; /* 32-bit aligned! */
64 phys_addr_t fb_phys;
65 size_t fb_len;
66 bool in_use;
67};
68
69u32 mpc512x_get_pixel_format(enum fsl_diu_monitor_port port,
70 unsigned int bits_per_pixel)
71{
72 switch (bits_per_pixel) {
73 case 32:
74 return 0x88883316;
75 case 24:
76 return 0x88082219;
77 case 16:
78 return 0x65053118;
79 }
80 return 0x00000400;
81}
82
83void mpc512x_set_gamma_table(enum fsl_diu_monitor_port port,
84 char *gamma_table_base)
85{
86}
87
88void mpc512x_set_monitor_port(enum fsl_diu_monitor_port port)
89{
90}
91
92#define DIU_DIV_MASK 0x000000ff
93void mpc512x_set_pixel_clock(unsigned int pixclock)
94{
95 unsigned long bestval, bestfreq, speed, busfreq;
96 unsigned long minpixclock, maxpixclock, pixval;
97 struct mpc512x_ccm __iomem *ccm;
98 struct device_node *np;
99 u32 temp;
100 long err;
101 int i;
102
103 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-clock");
104 if (!np) {
105 pr_err("Can't find clock control module.\n");
106 return;
107 }
108
109 ccm = of_iomap(np, 0);
110 of_node_put(np);
111 if (!ccm) {
112 pr_err("Can't map clock control module reg.\n");
113 return;
114 }
115
116 np = of_find_node_by_type(NULL, "cpu");
117 if (np) {
118 const unsigned int *prop =
119 of_get_property(np, "bus-frequency", NULL);
120
121 of_node_put(np);
122 if (prop) {
123 busfreq = *prop;
124 } else {
125 pr_err("Can't get bus-frequency property\n");
126 return;
127 }
128 } else {
129 pr_err("Can't find 'cpu' node.\n");
130 return;
131 }
132
133 /* Pixel Clock configuration */
134 pr_debug("DIU: Bus Frequency = %lu\n", busfreq);
135 speed = busfreq * 4; /* DIU_DIV ratio is 4 * CSB_CLK / DIU_CLK */
136
137 /* Calculate the pixel clock with the smallest error */
138 /* calculate the following in steps to avoid overflow */
139 pr_debug("DIU pixclock in ps - %d\n", pixclock);
140 temp = (1000000000 / pixclock) * 1000;
141 pixclock = temp;
142 pr_debug("DIU pixclock freq - %u\n", pixclock);
143
144 temp = temp / 20; /* pixclock * 0.05 */
145 pr_debug("deviation = %d\n", temp);
146 minpixclock = pixclock - temp;
147 maxpixclock = pixclock + temp;
148 pr_debug("DIU minpixclock - %lu\n", minpixclock);
149 pr_debug("DIU maxpixclock - %lu\n", maxpixclock);
150 pixval = speed/pixclock;
151 pr_debug("DIU pixval = %lu\n", pixval);
152
153 err = LONG_MAX;
154 bestval = pixval;
155 pr_debug("DIU bestval = %lu\n", bestval);
156
157 bestfreq = 0;
158 for (i = -1; i <= 1; i++) {
159 temp = speed / (pixval+i);
160 pr_debug("DIU test pixval i=%d, pixval=%lu, temp freq. = %u\n",
161 i, pixval, temp);
162 if ((temp < minpixclock) || (temp > maxpixclock))
163 pr_debug("DIU exceeds monitor range (%lu to %lu)\n",
164 minpixclock, maxpixclock);
165 else if (abs(temp - pixclock) < err) {
166 pr_debug("Entered the else if block %d\n", i);
167 err = abs(temp - pixclock);
168 bestval = pixval + i;
169 bestfreq = temp;
170 }
171 }
172
173 pr_debug("DIU chose = %lx\n", bestval);
174 pr_debug("DIU error = %ld\n NomPixClk ", err);
175 pr_debug("DIU: Best Freq = %lx\n", bestfreq);
176 /* Modify DIU_DIV in CCM SCFR1 */
177 temp = in_be32(&ccm->scfr1);
178 pr_debug("DIU: Current value of SCFR1: 0x%08x\n", temp);
179 temp &= ~DIU_DIV_MASK;
180 temp |= (bestval & DIU_DIV_MASK);
181 out_be32(&ccm->scfr1, temp);
182 pr_debug("DIU: Modified value of SCFR1: 0x%08x\n", temp);
183 iounmap(ccm);
184}
185
186enum fsl_diu_monitor_port
187mpc512x_valid_monitor_port(enum fsl_diu_monitor_port port)
188{
189 return FSL_DIU_PORT_DVI;
190}
191
192static struct fsl_diu_shared_fb __attribute__ ((__aligned__(8))) diu_shared_fb;
193
194#if defined(CONFIG_FB_FSL_DIU) || \
195 defined(CONFIG_FB_FSL_DIU_MODULE)
196static inline void mpc512x_free_bootmem(struct page *page)
197{
198 __ClearPageReserved(page);
199 BUG_ON(PageTail(page));
200 BUG_ON(atomic_read(&page->_count) > 1);
201 atomic_set(&page->_count, 1);
202 __free_page(page);
203 totalram_pages++;
204}
205
206void mpc512x_release_bootmem(void)
207{
208 unsigned long addr = diu_shared_fb.fb_phys & PAGE_MASK;
209 unsigned long size = diu_shared_fb.fb_len;
210 unsigned long start, end;
211
212 if (diu_shared_fb.in_use) {
213 start = PFN_UP(addr);
214 end = PFN_DOWN(addr + size);
215
216 for (; start < end; start++)
217 mpc512x_free_bootmem(pfn_to_page(start));
218
219 diu_shared_fb.in_use = false;
220 }
221 diu_ops.release_bootmem = NULL;
222}
223#endif
224
225/*
226 * Check if DIU was pre-initialized. If so, perform steps
227 * needed to continue displaying through the whole boot process.
228 * Move area descriptor and gamma table elsewhere, they are
229 * destroyed by bootmem allocator otherwise. The frame buffer
230 * address range will be reserved in setup_arch() after bootmem
231 * allocator is up.
232 */
233void __init mpc512x_init_diu(void)
234{
235 struct device_node *np;
236 struct diu __iomem *diu_reg;
237 phys_addr_t desc;
238 void __iomem *vaddr;
239 unsigned long mode, pix_fmt, res, bpp;
240 unsigned long dst;
241
242 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-diu");
243 if (!np) {
244 pr_err("No DIU node\n");
245 return;
246 }
247
248 diu_reg = of_iomap(np, 0);
249 of_node_put(np);
250 if (!diu_reg) {
251 pr_err("Can't map DIU\n");
252 return;
253 }
254
255 mode = in_be32(&diu_reg->diu_mode);
256 if (mode == MFB_MODE0) {
257 pr_info("%s: DIU OFF\n", __func__);
258 goto out;
259 }
260
261 desc = in_be32(&diu_reg->desc[0]);
262 vaddr = ioremap(desc, sizeof(struct diu_ad));
263 if (!vaddr) {
264 pr_err("Can't map DIU area desc.\n");
265 goto out;
266 }
267 memcpy(&diu_shared_fb.ad0, vaddr, sizeof(struct diu_ad));
268 /* flush fb area descriptor */
269 dst = (unsigned long)&diu_shared_fb.ad0;
270 flush_dcache_range(dst, dst + sizeof(struct diu_ad) - 1);
271
272 res = in_be32(&diu_reg->disp_size);
273 pix_fmt = in_le32(vaddr);
274 bpp = ((pix_fmt >> 16) & 0x3) + 1;
275 diu_shared_fb.fb_phys = in_le32(vaddr + 4);
276 diu_shared_fb.fb_len = ((res & 0xfff0000) >> 16) * (res & 0xfff) * bpp;
277 diu_shared_fb.in_use = true;
278 iounmap(vaddr);
279
280 desc = in_be32(&diu_reg->gamma);
281 vaddr = ioremap(desc, sizeof(diu_shared_fb.gamma));
282 if (!vaddr) {
283 pr_err("Can't map DIU area desc.\n");
284 diu_shared_fb.in_use = false;
285 goto out;
286 }
287 memcpy(&diu_shared_fb.gamma, vaddr, sizeof(diu_shared_fb.gamma));
288 /* flush gamma table */
289 dst = (unsigned long)&diu_shared_fb.gamma;
290 flush_dcache_range(dst, dst + sizeof(diu_shared_fb.gamma) - 1);
291
292 iounmap(vaddr);
293 out_be32(&diu_reg->gamma, virt_to_phys(&diu_shared_fb.gamma));
294 out_be32(&diu_reg->desc[1], 0);
295 out_be32(&diu_reg->desc[2], 0);
296 out_be32(&diu_reg->desc[0], virt_to_phys(&diu_shared_fb.ad0));
297
298out:
299 iounmap(diu_reg);
300}
301
302void __init mpc512x_setup_diu(void)
303{
304 int ret;
305
306 /*
307 * We do not allocate and configure new area for bitmap buffer
308 * because it would requere copying bitmap data (splash image)
309 * and so negatively affect boot time. Instead we reserve the
310 * already configured frame buffer area so that it won't be
311 * destroyed. The starting address of the area to reserve and
312 * also it's length is passed to reserve_bootmem(). It will be
313 * freed later on first open of fbdev, when splash image is not
314 * needed any more.
315 */
316 if (diu_shared_fb.in_use) {
317 ret = reserve_bootmem(diu_shared_fb.fb_phys,
318 diu_shared_fb.fb_len,
319 BOOTMEM_EXCLUSIVE);
320 if (ret) {
321 pr_err("%s: reserve bootmem failed\n", __func__);
322 diu_shared_fb.in_use = false;
323 }
324 }
325
326#if defined(CONFIG_FB_FSL_DIU) || \
327 defined(CONFIG_FB_FSL_DIU_MODULE)
328 diu_ops.get_pixel_format = mpc512x_get_pixel_format;
329 diu_ops.set_gamma_table = mpc512x_set_gamma_table;
330 diu_ops.set_monitor_port = mpc512x_set_monitor_port;
331 diu_ops.set_pixel_clock = mpc512x_set_pixel_clock;
332 diu_ops.valid_monitor_port = mpc512x_valid_monitor_port;
333 diu_ops.release_bootmem = mpc512x_release_bootmem;
334#endif
335}
336
337void __init mpc512x_init_IRQ(void)
338{
339 struct device_node *np;
340
341 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-ipic");
342 if (!np)
343 return;
344
345 ipic_init(np, 0);
346 of_node_put(np);
347
348 /*
349 * Initialize the default interrupt mapping priorities,
350 * in case the boot rom changed something on us.
351 */
352 ipic_set_default_priority();
353}
354
355/*
356 * Nodes to do bus probe on, soc and localbus
357 */
358static struct of_device_id __initdata of_bus_ids[] = {
359 { .compatible = "fsl,mpc5121-immr", },
360 { .compatible = "fsl,mpc5121-localbus", },
361 {},
362};
363
364void __init mpc512x_declare_of_platform_devices(void)
365{
366 struct device_node *np;
367
368 if (of_platform_bus_probe(NULL, of_bus_ids, NULL))
369 printk(KERN_ERR __FILE__ ": "
370 "Error while probing of_platform bus\n");
371
372 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-nfc");
373 if (np) {
374 of_platform_device_create(np, NULL, NULL);
375 of_node_put(np);
376 }
377}
378
379#define DEFAULT_FIFO_SIZE 16
380
381static unsigned int __init get_fifo_size(struct device_node *np,
382 char *prop_name)
383{
384 const unsigned int *fp;
385
386 fp = of_get_property(np, prop_name, NULL);
387 if (fp)
388 return *fp;
389
390 pr_warning("no %s property in %s node, defaulting to %d\n",
391 prop_name, np->full_name, DEFAULT_FIFO_SIZE);
392
393 return DEFAULT_FIFO_SIZE;
394}
395
396#define FIFOC(_base) ((struct mpc512x_psc_fifo __iomem *) \
397 ((u32)(_base) + sizeof(struct mpc52xx_psc)))
398
399/* Init PSC FIFO space for TX and RX slices */
400void __init mpc512x_psc_fifo_init(void)
401{
402 struct device_node *np;
403 void __iomem *psc;
404 unsigned int tx_fifo_size;
405 unsigned int rx_fifo_size;
406 int fifobase = 0; /* current fifo address in 32 bit words */
407
408 for_each_compatible_node(np, NULL, "fsl,mpc5121-psc") {
409 tx_fifo_size = get_fifo_size(np, "fsl,tx-fifo-size");
410 rx_fifo_size = get_fifo_size(np, "fsl,rx-fifo-size");
411
412 /* size in register is in 4 byte units */
413 tx_fifo_size /= 4;
414 rx_fifo_size /= 4;
415 if (!tx_fifo_size)
416 tx_fifo_size = 1;
417 if (!rx_fifo_size)
418 rx_fifo_size = 1;
419
420 psc = of_iomap(np, 0);
421 if (!psc) {
422 pr_err("%s: Can't map %s device\n",
423 __func__, np->full_name);
424 continue;
425 }
426
427 /* FIFO space is 4KiB, check if requested size is available */
428 if ((fifobase + tx_fifo_size + rx_fifo_size) > 0x1000) {
429 pr_err("%s: no fifo space available for %s\n",
430 __func__, np->full_name);
431 iounmap(psc);
432 /*
433 * chances are that another device requests less
434 * fifo space, so we continue.
435 */
436 continue;
437 }
438
439 /* set tx and rx fifo size registers */
440 out_be32(&FIFOC(psc)->txsz, (fifobase << 16) | tx_fifo_size);
441 fifobase += tx_fifo_size;
442 out_be32(&FIFOC(psc)->rxsz, (fifobase << 16) | rx_fifo_size);
443 fifobase += rx_fifo_size;
444
445 /* reset and enable the slices */
446 out_be32(&FIFOC(psc)->txcmd, 0x80);
447 out_be32(&FIFOC(psc)->txcmd, 0x01);
448 out_be32(&FIFOC(psc)->rxcmd, 0x80);
449 out_be32(&FIFOC(psc)->rxcmd, 0x01);
450
451 iounmap(psc);
452 }
453}
454
455void __init mpc512x_init(void)
456{
457 mpc512x_declare_of_platform_devices();
458 mpc5121_clk_init();
459 mpc512x_restart_init();
460 mpc512x_psc_fifo_init();
461}