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1/*
2 * Helper routines to scan the device tree for PCI devices and busses
3 *
4 * Migrated out of PowerPC architecture pci_64.c file by Grant Likely
5 * <grant.likely@secretlab.ca> so that these routines are available for
6 * 32 bit also.
7 *
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
10 * Copyright (c) 2009 Secret Lab Technologies Ltd.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * version 2 as published by the Free Software Foundation.
15 */
16
17#include <linux/pci.h>
18#include <linux/export.h>
19#include <asm/pci-bridge.h>
20#include <asm/prom.h>
21
22/**
23 * get_int_prop - Decode a u32 from a device tree property
24 */
25static u32 get_int_prop(struct device_node *np, const char *name, u32 def)
26{
27 const u32 *prop;
28 int len;
29
30 prop = of_get_property(np, name, &len);
31 if (prop && len >= 4)
32 return *prop;
33 return def;
34}
35
36/**
37 * pci_parse_of_flags - Parse the flags cell of a device tree PCI address
38 * @addr0: value of 1st cell of a device tree PCI address.
39 * @bridge: Set this flag if the address is from a bridge 'ranges' property
40 */
41unsigned int pci_parse_of_flags(u32 addr0, int bridge)
42{
43 unsigned int flags = 0;
44
45 if (addr0 & 0x02000000) {
46 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
47 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
48 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
49 if (addr0 & 0x40000000)
50 flags |= IORESOURCE_PREFETCH
51 | PCI_BASE_ADDRESS_MEM_PREFETCH;
52 /* Note: We don't know whether the ROM has been left enabled
53 * by the firmware or not. We mark it as disabled (ie, we do
54 * not set the IORESOURCE_ROM_ENABLE flag) for now rather than
55 * do a config space read, it will be force-enabled if needed
56 */
57 if (!bridge && (addr0 & 0xff) == 0x30)
58 flags |= IORESOURCE_READONLY;
59 } else if (addr0 & 0x01000000)
60 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
61 if (flags)
62 flags |= IORESOURCE_SIZEALIGN;
63 return flags;
64}
65
66/**
67 * of_pci_parse_addrs - Parse PCI addresses assigned in the device tree node
68 * @node: device tree node for the PCI device
69 * @dev: pci_dev structure for the device
70 *
71 * This function parses the 'assigned-addresses' property of a PCI devices'
72 * device tree node and writes them into the associated pci_dev structure.
73 */
74static void of_pci_parse_addrs(struct device_node *node, struct pci_dev *dev)
75{
76 u64 base, size;
77 unsigned int flags;
78 struct pci_bus_region region;
79 struct resource *res;
80 const u32 *addrs;
81 u32 i;
82 int proplen;
83
84 addrs = of_get_property(node, "assigned-addresses", &proplen);
85 if (!addrs)
86 return;
87 pr_debug(" parse addresses (%d bytes) @ %p\n", proplen, addrs);
88 for (; proplen >= 20; proplen -= 20, addrs += 5) {
89 flags = pci_parse_of_flags(addrs[0], 0);
90 if (!flags)
91 continue;
92 base = of_read_number(&addrs[1], 2);
93 size = of_read_number(&addrs[3], 2);
94 if (!size)
95 continue;
96 i = addrs[0] & 0xff;
97 pr_debug(" base: %llx, size: %llx, i: %x\n",
98 (unsigned long long)base,
99 (unsigned long long)size, i);
100
101 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
102 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
103 } else if (i == dev->rom_base_reg) {
104 res = &dev->resource[PCI_ROM_RESOURCE];
105 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
106 } else {
107 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
108 continue;
109 }
110 res->flags = flags;
111 res->name = pci_name(dev);
112 region.start = base;
113 region.end = base + size - 1;
114 pcibios_bus_to_resource(dev, res, ®ion);
115 }
116}
117
118/**
119 * of_create_pci_dev - Given a device tree node on a pci bus, create a pci_dev
120 * @node: device tree node pointer
121 * @bus: bus the device is sitting on
122 * @devfn: PCI function number, extracted from device tree by caller.
123 */
124struct pci_dev *of_create_pci_dev(struct device_node *node,
125 struct pci_bus *bus, int devfn)
126{
127 struct pci_dev *dev;
128 const char *type;
129 struct pci_slot *slot;
130
131 dev = alloc_pci_dev();
132 if (!dev)
133 return NULL;
134 type = of_get_property(node, "device_type", NULL);
135 if (type == NULL)
136 type = "";
137
138 pr_debug(" create device, devfn: %x, type: %s\n", devfn, type);
139
140 dev->bus = bus;
141 dev->dev.of_node = of_node_get(node);
142 dev->dev.parent = bus->bridge;
143 dev->dev.bus = &pci_bus_type;
144 dev->devfn = devfn;
145 dev->multifunction = 0; /* maybe a lie? */
146 dev->needs_freset = 0; /* pcie fundamental reset required */
147 set_pcie_port_type(dev);
148
149 list_for_each_entry(slot, &dev->bus->slots, list)
150 if (PCI_SLOT(dev->devfn) == slot->number)
151 dev->slot = slot;
152
153 dev->vendor = get_int_prop(node, "vendor-id", 0xffff);
154 dev->device = get_int_prop(node, "device-id", 0xffff);
155 dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0);
156 dev->subsystem_device = get_int_prop(node, "subsystem-id", 0);
157
158 dev->cfg_size = pci_cfg_space_size(dev);
159
160 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus),
161 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
162 dev->class = get_int_prop(node, "class-code", 0);
163 dev->revision = get_int_prop(node, "revision-id", 0);
164
165 pr_debug(" class: 0x%x\n", dev->class);
166 pr_debug(" revision: 0x%x\n", dev->revision);
167
168 dev->current_state = 4; /* unknown power state */
169 dev->error_state = pci_channel_io_normal;
170 dev->dma_mask = 0xffffffff;
171
172 /* Early fixups, before probing the BARs */
173 pci_fixup_device(pci_fixup_early, dev);
174
175 if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
176 /* a PCI-PCI bridge */
177 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
178 dev->rom_base_reg = PCI_ROM_ADDRESS1;
179 set_pcie_hotplug_bridge(dev);
180 } else if (!strcmp(type, "cardbus")) {
181 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
182 } else {
183 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
184 dev->rom_base_reg = PCI_ROM_ADDRESS;
185 /* Maybe do a default OF mapping here */
186 dev->irq = NO_IRQ;
187 }
188
189 of_pci_parse_addrs(node, dev);
190
191 pr_debug(" adding to system ...\n");
192
193 pci_device_add(dev, bus);
194
195 return dev;
196}
197EXPORT_SYMBOL(of_create_pci_dev);
198
199/**
200 * of_scan_pci_bridge - Set up a PCI bridge and scan for child nodes
201 * @node: device tree node of bridge
202 * @dev: pci_dev structure for the bridge
203 *
204 * of_scan_bus() calls this routine for each PCI bridge that it finds, and
205 * this routine in turn call of_scan_bus() recusively to scan for more child
206 * devices.
207 */
208void __devinit of_scan_pci_bridge(struct pci_dev *dev)
209{
210 struct device_node *node = dev->dev.of_node;
211 struct pci_bus *bus;
212 const u32 *busrange, *ranges;
213 int len, i, mode;
214 struct pci_bus_region region;
215 struct resource *res;
216 unsigned int flags;
217 u64 size;
218
219 pr_debug("of_scan_pci_bridge(%s)\n", node->full_name);
220
221 /* parse bus-range property */
222 busrange = of_get_property(node, "bus-range", &len);
223 if (busrange == NULL || len != 8) {
224 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
225 node->full_name);
226 return;
227 }
228 ranges = of_get_property(node, "ranges", &len);
229 if (ranges == NULL) {
230 printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n",
231 node->full_name);
232 return;
233 }
234
235 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
236 if (!bus) {
237 printk(KERN_ERR "Failed to create pci bus for %s\n",
238 node->full_name);
239 return;
240 }
241
242 bus->primary = dev->bus->number;
243 bus->subordinate = busrange[1];
244 bus->bridge_ctl = 0;
245
246 /* parse ranges property */
247 /* PCI #address-cells == 3 and #size-cells == 2 always */
248 res = &dev->resource[PCI_BRIDGE_RESOURCES];
249 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
250 res->flags = 0;
251 bus->resource[i] = res;
252 ++res;
253 }
254 i = 1;
255 for (; len >= 32; len -= 32, ranges += 8) {
256 flags = pci_parse_of_flags(ranges[0], 1);
257 size = of_read_number(&ranges[6], 2);
258 if (flags == 0 || size == 0)
259 continue;
260 if (flags & IORESOURCE_IO) {
261 res = bus->resource[0];
262 if (res->flags) {
263 printk(KERN_ERR "PCI: ignoring extra I/O range"
264 " for bridge %s\n", node->full_name);
265 continue;
266 }
267 } else {
268 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
269 printk(KERN_ERR "PCI: too many memory ranges"
270 " for bridge %s\n", node->full_name);
271 continue;
272 }
273 res = bus->resource[i];
274 ++i;
275 }
276 res->flags = flags;
277 region.start = of_read_number(&ranges[1], 2);
278 region.end = region.start + size - 1;
279 pcibios_bus_to_resource(dev, res, ®ion);
280 }
281 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
282 bus->number);
283 pr_debug(" bus name: %s\n", bus->name);
284
285 mode = PCI_PROBE_NORMAL;
286 if (ppc_md.pci_probe_mode)
287 mode = ppc_md.pci_probe_mode(bus);
288 pr_debug(" probe mode: %d\n", mode);
289
290 if (mode == PCI_PROBE_DEVTREE)
291 of_scan_bus(node, bus);
292 else if (mode == PCI_PROBE_NORMAL)
293 pci_scan_child_bus(bus);
294}
295EXPORT_SYMBOL(of_scan_pci_bridge);
296
297/**
298 * __of_scan_bus - given a PCI bus node, setup bus and scan for child devices
299 * @node: device tree node for the PCI bus
300 * @bus: pci_bus structure for the PCI bus
301 * @rescan_existing: Flag indicating bus has already been set up
302 */
303static void __devinit __of_scan_bus(struct device_node *node,
304 struct pci_bus *bus, int rescan_existing)
305{
306 struct device_node *child;
307 const u32 *reg;
308 int reglen, devfn;
309 struct pci_dev *dev;
310
311 pr_debug("of_scan_bus(%s) bus no %d...\n",
312 node->full_name, bus->number);
313
314 /* Scan direct children */
315 for_each_child_of_node(node, child) {
316 pr_debug(" * %s\n", child->full_name);
317 if (!of_device_is_available(child))
318 continue;
319 reg = of_get_property(child, "reg", ®len);
320 if (reg == NULL || reglen < 20)
321 continue;
322 devfn = (reg[0] >> 8) & 0xff;
323
324 /* create a new pci_dev for this device */
325 dev = of_create_pci_dev(child, bus, devfn);
326 if (!dev)
327 continue;
328 pr_debug(" dev header type: %x\n", dev->hdr_type);
329 }
330
331 /* Apply all fixups necessary. We don't fixup the bus "self"
332 * for an existing bridge that is being rescanned
333 */
334 if (!rescan_existing)
335 pcibios_setup_bus_self(bus);
336 pcibios_setup_bus_devices(bus);
337
338 /* Now scan child busses */
339 list_for_each_entry(dev, &bus->devices, bus_list) {
340 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
341 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) {
342 of_scan_pci_bridge(dev);
343 }
344 }
345}
346
347/**
348 * of_scan_bus - given a PCI bus node, setup bus and scan for child devices
349 * @node: device tree node for the PCI bus
350 * @bus: pci_bus structure for the PCI bus
351 */
352void __devinit of_scan_bus(struct device_node *node,
353 struct pci_bus *bus)
354{
355 __of_scan_bus(node, bus, 0);
356}
357EXPORT_SYMBOL_GPL(of_scan_bus);
358
359/**
360 * of_rescan_bus - given a PCI bus node, scan for child devices
361 * @node: device tree node for the PCI bus
362 * @bus: pci_bus structure for the PCI bus
363 *
364 * Same as of_scan_bus, but for a pci_bus structure that has already been
365 * setup.
366 */
367void __devinit of_rescan_bus(struct device_node *node,
368 struct pci_bus *bus)
369{
370 __of_scan_bus(node, bus, 1);
371}
372EXPORT_SYMBOL_GPL(of_rescan_bus);
373