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1#ifndef _PARISC_PGTABLE_H
2#define _PARISC_PGTABLE_H
3
4#include <asm-generic/4level-fixup.h>
5
6#include <asm/fixmap.h>
7
8#ifndef __ASSEMBLY__
9/*
10 * we simulate an x86-style page table for the linux mm code
11 */
12
13#include <linux/bitops.h>
14#include <linux/spinlock.h>
15#include <asm/processor.h>
16#include <asm/cache.h>
17
18struct vm_area_struct;
19
20/*
21 * kern_addr_valid(ADDR) tests if ADDR is pointing to valid kernel
22 * memory. For the return value to be meaningful, ADDR must be >=
23 * PAGE_OFFSET. This operation can be relatively expensive (e.g.,
24 * require a hash-, or multi-level tree-lookup or something of that
25 * sort) but it guarantees to return TRUE only if accessing the page
26 * at that address does not cause an error. Note that there may be
27 * addresses for which kern_addr_valid() returns FALSE even though an
28 * access would not cause an error (e.g., this is typically true for
29 * memory mapped I/O regions.
30 *
31 * XXX Need to implement this for parisc.
32 */
33#define kern_addr_valid(addr) (1)
34
35/* Certain architectures need to do special things when PTEs
36 * within a page table are directly modified. Thus, the following
37 * hook is made available.
38 */
39#define set_pte(pteptr, pteval) \
40 do{ \
41 *(pteptr) = (pteval); \
42 } while(0)
43#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
44
45#endif /* !__ASSEMBLY__ */
46
47#include <asm/page.h>
48
49#define pte_ERROR(e) \
50 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
51#define pmd_ERROR(e) \
52 printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, (unsigned long)pmd_val(e))
53#define pgd_ERROR(e) \
54 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, (unsigned long)pgd_val(e))
55
56/* This is the size of the initially mapped kernel memory */
57#define KERNEL_INITIAL_ORDER 24 /* 0 to 1<<24 = 16MB */
58#define KERNEL_INITIAL_SIZE (1 << KERNEL_INITIAL_ORDER)
59
60#if defined(CONFIG_64BIT) && defined(CONFIG_PARISC_PAGE_SIZE_4KB)
61#define PT_NLEVELS 3
62#define PGD_ORDER 1 /* Number of pages per pgd */
63#define PMD_ORDER 1 /* Number of pages per pmd */
64#define PGD_ALLOC_ORDER 2 /* first pgd contains pmd */
65#else
66#define PT_NLEVELS 2
67#define PGD_ORDER 1 /* Number of pages per pgd */
68#define PGD_ALLOC_ORDER PGD_ORDER
69#endif
70
71/* Definitions for 3rd level (we use PLD here for Page Lower directory
72 * because PTE_SHIFT is used lower down to mean shift that has to be
73 * done to get usable bits out of the PTE) */
74#define PLD_SHIFT PAGE_SHIFT
75#define PLD_SIZE PAGE_SIZE
76#define BITS_PER_PTE (PAGE_SHIFT - BITS_PER_PTE_ENTRY)
77#define PTRS_PER_PTE (1UL << BITS_PER_PTE)
78
79/* Definitions for 2nd level */
80#define pgtable_cache_init() do { } while (0)
81
82#define PMD_SHIFT (PLD_SHIFT + BITS_PER_PTE)
83#define PMD_SIZE (1UL << PMD_SHIFT)
84#define PMD_MASK (~(PMD_SIZE-1))
85#if PT_NLEVELS == 3
86#define BITS_PER_PMD (PAGE_SHIFT + PMD_ORDER - BITS_PER_PMD_ENTRY)
87#else
88#define BITS_PER_PMD 0
89#endif
90#define PTRS_PER_PMD (1UL << BITS_PER_PMD)
91
92/* Definitions for 1st level */
93#define PGDIR_SHIFT (PMD_SHIFT + BITS_PER_PMD)
94#if (PGDIR_SHIFT + PAGE_SHIFT + PGD_ORDER - BITS_PER_PGD_ENTRY) > BITS_PER_LONG
95#define BITS_PER_PGD (BITS_PER_LONG - PGDIR_SHIFT)
96#else
97#define BITS_PER_PGD (PAGE_SHIFT + PGD_ORDER - BITS_PER_PGD_ENTRY)
98#endif
99#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
100#define PGDIR_MASK (~(PGDIR_SIZE-1))
101#define PTRS_PER_PGD (1UL << BITS_PER_PGD)
102#define USER_PTRS_PER_PGD PTRS_PER_PGD
103
104#ifdef CONFIG_64BIT
105#define MAX_ADDRBITS (PGDIR_SHIFT + BITS_PER_PGD)
106#define MAX_ADDRESS (1UL << MAX_ADDRBITS)
107#define SPACEID_SHIFT (MAX_ADDRBITS - 32)
108#else
109#define MAX_ADDRBITS (BITS_PER_LONG)
110#define MAX_ADDRESS (1UL << MAX_ADDRBITS)
111#define SPACEID_SHIFT 0
112#endif
113
114/* This calculates the number of initial pages we need for the initial
115 * page tables */
116#if (KERNEL_INITIAL_ORDER) >= (PMD_SHIFT)
117# define PT_INITIAL (1 << (KERNEL_INITIAL_ORDER - PMD_SHIFT))
118#else
119# define PT_INITIAL (1) /* all initial PTEs fit into one page */
120#endif
121
122/*
123 * pgd entries used up by user/kernel:
124 */
125
126#define FIRST_USER_ADDRESS 0
127
128/* NB: The tlb miss handlers make certain assumptions about the order */
129/* of the following bits, so be careful (One example, bits 25-31 */
130/* are moved together in one instruction). */
131
132#define _PAGE_READ_BIT 31 /* (0x001) read access allowed */
133#define _PAGE_WRITE_BIT 30 /* (0x002) write access allowed */
134#define _PAGE_EXEC_BIT 29 /* (0x004) execute access allowed */
135#define _PAGE_GATEWAY_BIT 28 /* (0x008) privilege promotion allowed */
136#define _PAGE_DMB_BIT 27 /* (0x010) Data Memory Break enable (B bit) */
137#define _PAGE_DIRTY_BIT 26 /* (0x020) Page Dirty (D bit) */
138#define _PAGE_FILE_BIT _PAGE_DIRTY_BIT /* overload this bit */
139#define _PAGE_REFTRAP_BIT 25 /* (0x040) Page Ref. Trap enable (T bit) */
140#define _PAGE_NO_CACHE_BIT 24 /* (0x080) Uncached Page (U bit) */
141#define _PAGE_ACCESSED_BIT 23 /* (0x100) Software: Page Accessed */
142#define _PAGE_PRESENT_BIT 22 /* (0x200) Software: translation valid */
143/* bit 21 was formerly the FLUSH bit but is now unused */
144#define _PAGE_USER_BIT 20 /* (0x800) Software: User accessible page */
145
146/* N.B. The bits are defined in terms of a 32 bit word above, so the */
147/* following macro is ok for both 32 and 64 bit. */
148
149#define xlate_pabit(x) (31 - x)
150
151/* this defines the shift to the usable bits in the PTE it is set so
152 * that the valid bits _PAGE_PRESENT_BIT and _PAGE_USER_BIT are set
153 * to zero */
154#define PTE_SHIFT xlate_pabit(_PAGE_USER_BIT)
155
156/* PFN_PTE_SHIFT defines the shift of a PTE value to access the PFN field */
157#define PFN_PTE_SHIFT 12
158
159
160/* this is how many bits may be used by the file functions */
161#define PTE_FILE_MAX_BITS (BITS_PER_LONG - PTE_SHIFT)
162
163#define pte_to_pgoff(pte) (pte_val(pte) >> PTE_SHIFT)
164#define pgoff_to_pte(off) ((pte_t) { ((off) << PTE_SHIFT) | _PAGE_FILE })
165
166#define _PAGE_READ (1 << xlate_pabit(_PAGE_READ_BIT))
167#define _PAGE_WRITE (1 << xlate_pabit(_PAGE_WRITE_BIT))
168#define _PAGE_RW (_PAGE_READ | _PAGE_WRITE)
169#define _PAGE_EXEC (1 << xlate_pabit(_PAGE_EXEC_BIT))
170#define _PAGE_GATEWAY (1 << xlate_pabit(_PAGE_GATEWAY_BIT))
171#define _PAGE_DMB (1 << xlate_pabit(_PAGE_DMB_BIT))
172#define _PAGE_DIRTY (1 << xlate_pabit(_PAGE_DIRTY_BIT))
173#define _PAGE_REFTRAP (1 << xlate_pabit(_PAGE_REFTRAP_BIT))
174#define _PAGE_NO_CACHE (1 << xlate_pabit(_PAGE_NO_CACHE_BIT))
175#define _PAGE_ACCESSED (1 << xlate_pabit(_PAGE_ACCESSED_BIT))
176#define _PAGE_PRESENT (1 << xlate_pabit(_PAGE_PRESENT_BIT))
177#define _PAGE_USER (1 << xlate_pabit(_PAGE_USER_BIT))
178#define _PAGE_FILE (1 << xlate_pabit(_PAGE_FILE_BIT))
179
180#define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_ACCESSED)
181#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
182#define _PAGE_KERNEL_RO (_PAGE_PRESENT | _PAGE_READ | _PAGE_DIRTY | _PAGE_ACCESSED)
183#define _PAGE_KERNEL_EXEC (_PAGE_KERNEL_RO | _PAGE_EXEC)
184#define _PAGE_KERNEL_RWX (_PAGE_KERNEL_EXEC | _PAGE_WRITE)
185#define _PAGE_KERNEL (_PAGE_KERNEL_RO | _PAGE_WRITE)
186
187/* The pgd/pmd contains a ptr (in phys addr space); since all pgds/pmds
188 * are page-aligned, we don't care about the PAGE_OFFSET bits, except
189 * for a few meta-information bits, so we shift the address to be
190 * able to effectively address 40/42/44-bits of physical address space
191 * depending on 4k/16k/64k PAGE_SIZE */
192#define _PxD_PRESENT_BIT 31
193#define _PxD_ATTACHED_BIT 30
194#define _PxD_VALID_BIT 29
195
196#define PxD_FLAG_PRESENT (1 << xlate_pabit(_PxD_PRESENT_BIT))
197#define PxD_FLAG_ATTACHED (1 << xlate_pabit(_PxD_ATTACHED_BIT))
198#define PxD_FLAG_VALID (1 << xlate_pabit(_PxD_VALID_BIT))
199#define PxD_FLAG_MASK (0xf)
200#define PxD_FLAG_SHIFT (4)
201#define PxD_VALUE_SHIFT (8) /* (PAGE_SHIFT-PxD_FLAG_SHIFT) */
202
203#ifndef __ASSEMBLY__
204
205#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED)
206#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_WRITE | _PAGE_ACCESSED)
207/* Others seem to make this executable, I don't know if that's correct
208 or not. The stack is mapped this way though so this is necessary
209 in the short term - dhd@linuxcare.com, 2000-08-08 */
210#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_ACCESSED)
211#define PAGE_WRITEONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITE | _PAGE_ACCESSED)
212#define PAGE_EXECREAD __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_EXEC |_PAGE_ACCESSED)
213#define PAGE_COPY PAGE_EXECREAD
214#define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_WRITE | _PAGE_EXEC |_PAGE_ACCESSED)
215#define PAGE_KERNEL __pgprot(_PAGE_KERNEL)
216#define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL_EXEC)
217#define PAGE_KERNEL_RWX __pgprot(_PAGE_KERNEL_RWX)
218#define PAGE_KERNEL_RO __pgprot(_PAGE_KERNEL_RO)
219#define PAGE_KERNEL_UNC __pgprot(_PAGE_KERNEL | _PAGE_NO_CACHE)
220#define PAGE_GATEWAY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_GATEWAY| _PAGE_READ)
221
222
223/*
224 * We could have an execute only page using "gateway - promote to priv
225 * level 3", but that is kind of silly. So, the way things are defined
226 * now, we must always have read permission for pages with execute
227 * permission. For the fun of it we'll go ahead and support write only
228 * pages.
229 */
230
231 /*xwr*/
232#define __P000 PAGE_NONE
233#define __P001 PAGE_READONLY
234#define __P010 __P000 /* copy on write */
235#define __P011 __P001 /* copy on write */
236#define __P100 PAGE_EXECREAD
237#define __P101 PAGE_EXECREAD
238#define __P110 __P100 /* copy on write */
239#define __P111 __P101 /* copy on write */
240
241#define __S000 PAGE_NONE
242#define __S001 PAGE_READONLY
243#define __S010 PAGE_WRITEONLY
244#define __S011 PAGE_SHARED
245#define __S100 PAGE_EXECREAD
246#define __S101 PAGE_EXECREAD
247#define __S110 PAGE_RWX
248#define __S111 PAGE_RWX
249
250
251extern pgd_t swapper_pg_dir[]; /* declared in init_task.c */
252
253/* initial page tables for 0-8MB for kernel */
254
255extern pte_t pg0[];
256
257/* zero page used for uninitialized stuff */
258
259extern unsigned long *empty_zero_page;
260
261/*
262 * ZERO_PAGE is a global shared page that is always zero: used
263 * for zero-mapped memory areas etc..
264 */
265
266#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
267
268#define pte_none(x) (pte_val(x) == 0)
269#define pte_present(x) (pte_val(x) & _PAGE_PRESENT)
270#define pte_clear(mm,addr,xp) do { pte_val(*(xp)) = 0; } while (0)
271
272#define pmd_flag(x) (pmd_val(x) & PxD_FLAG_MASK)
273#define pmd_address(x) ((unsigned long)(pmd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT)
274#define pgd_flag(x) (pgd_val(x) & PxD_FLAG_MASK)
275#define pgd_address(x) ((unsigned long)(pgd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT)
276
277#if PT_NLEVELS == 3
278/* The first entry of the permanent pmd is not there if it contains
279 * the gateway marker */
280#define pmd_none(x) (!pmd_val(x) || pmd_flag(x) == PxD_FLAG_ATTACHED)
281#else
282#define pmd_none(x) (!pmd_val(x))
283#endif
284#define pmd_bad(x) (!(pmd_flag(x) & PxD_FLAG_VALID))
285#define pmd_present(x) (pmd_flag(x) & PxD_FLAG_PRESENT)
286static inline void pmd_clear(pmd_t *pmd) {
287#if PT_NLEVELS == 3
288 if (pmd_flag(*pmd) & PxD_FLAG_ATTACHED)
289 /* This is the entry pointing to the permanent pmd
290 * attached to the pgd; cannot clear it */
291 __pmd_val_set(*pmd, PxD_FLAG_ATTACHED);
292 else
293#endif
294 __pmd_val_set(*pmd, 0);
295}
296
297
298
299#if PT_NLEVELS == 3
300#define pgd_page_vaddr(pgd) ((unsigned long) __va(pgd_address(pgd)))
301#define pgd_page(pgd) virt_to_page((void *)pgd_page_vaddr(pgd))
302
303/* For 64 bit we have three level tables */
304
305#define pgd_none(x) (!pgd_val(x))
306#define pgd_bad(x) (!(pgd_flag(x) & PxD_FLAG_VALID))
307#define pgd_present(x) (pgd_flag(x) & PxD_FLAG_PRESENT)
308static inline void pgd_clear(pgd_t *pgd) {
309#if PT_NLEVELS == 3
310 if(pgd_flag(*pgd) & PxD_FLAG_ATTACHED)
311 /* This is the permanent pmd attached to the pgd; cannot
312 * free it */
313 return;
314#endif
315 __pgd_val_set(*pgd, 0);
316}
317#else
318/*
319 * The "pgd_xxx()" functions here are trivial for a folded two-level
320 * setup: the pgd is never bad, and a pmd always exists (as it's folded
321 * into the pgd entry)
322 */
323static inline int pgd_none(pgd_t pgd) { return 0; }
324static inline int pgd_bad(pgd_t pgd) { return 0; }
325static inline int pgd_present(pgd_t pgd) { return 1; }
326static inline void pgd_clear(pgd_t * pgdp) { }
327#endif
328
329/*
330 * The following only work if pte_present() is true.
331 * Undefined behaviour if not..
332 */
333static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
334static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
335static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; }
336static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; }
337static inline int pte_special(pte_t pte) { return 0; }
338
339static inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~_PAGE_DIRTY; return pte; }
340static inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
341static inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) &= ~_PAGE_WRITE; return pte; }
342static inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= _PAGE_DIRTY; return pte; }
343static inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= _PAGE_ACCESSED; return pte; }
344static inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) |= _PAGE_WRITE; return pte; }
345static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
346
347/*
348 * Conversion functions: convert a page and protection to a page entry,
349 * and a page entry and page directory to the page they refer to.
350 */
351#define __mk_pte(addr,pgprot) \
352({ \
353 pte_t __pte; \
354 \
355 pte_val(__pte) = ((((addr)>>PAGE_SHIFT)<<PFN_PTE_SHIFT) + pgprot_val(pgprot)); \
356 \
357 __pte; \
358})
359
360#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
361
362static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
363{
364 pte_t pte;
365 pte_val(pte) = (pfn << PFN_PTE_SHIFT) | pgprot_val(pgprot);
366 return pte;
367}
368
369static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
370{ pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; }
371
372/* Permanent address of a page. On parisc we don't have highmem. */
373
374#define pte_pfn(x) (pte_val(x) >> PFN_PTE_SHIFT)
375
376#define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
377
378#define pmd_page_vaddr(pmd) ((unsigned long) __va(pmd_address(pmd)))
379
380#define __pmd_page(pmd) ((unsigned long) __va(pmd_address(pmd)))
381#define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd))
382
383#define pgd_index(address) ((address) >> PGDIR_SHIFT)
384
385/* to find an entry in a page-table-directory */
386#define pgd_offset(mm, address) \
387((mm)->pgd + ((address) >> PGDIR_SHIFT))
388
389/* to find an entry in a kernel page-table-directory */
390#define pgd_offset_k(address) pgd_offset(&init_mm, address)
391
392/* Find an entry in the second-level page table.. */
393
394#if PT_NLEVELS == 3
395#define pmd_offset(dir,address) \
396((pmd_t *) pgd_page_vaddr(*(dir)) + (((address)>>PMD_SHIFT) & (PTRS_PER_PMD-1)))
397#else
398#define pmd_offset(dir,addr) ((pmd_t *) dir)
399#endif
400
401/* Find an entry in the third-level page table.. */
402#define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1))
403#define pte_offset_kernel(pmd, address) \
404 ((pte_t *) pmd_page_vaddr(*(pmd)) + pte_index(address))
405#define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address)
406#define pte_unmap(pte) do { } while (0)
407
408#define pte_unmap(pte) do { } while (0)
409#define pte_unmap_nested(pte) do { } while (0)
410
411extern void paging_init (void);
412
413/* Used for deferring calls to flush_dcache_page() */
414
415#define PG_dcache_dirty PG_arch_1
416
417extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *);
418
419/* Encode and de-code a swap entry */
420
421#define __swp_type(x) ((x).val & 0x1f)
422#define __swp_offset(x) ( (((x).val >> 6) & 0x7) | \
423 (((x).val >> 8) & ~0x7) )
424#define __swp_entry(type, offset) ((swp_entry_t) { (type) | \
425 ((offset & 0x7) << 6) | \
426 ((offset & ~0x7) << 8) })
427#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
428#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
429
430static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
431{
432#ifdef CONFIG_SMP
433 if (!pte_young(*ptep))
434 return 0;
435 return test_and_clear_bit(xlate_pabit(_PAGE_ACCESSED_BIT), &pte_val(*ptep));
436#else
437 pte_t pte = *ptep;
438 if (!pte_young(pte))
439 return 0;
440 set_pte_at(vma->vm_mm, addr, ptep, pte_mkold(pte));
441 return 1;
442#endif
443}
444
445extern spinlock_t pa_dbit_lock;
446
447struct mm_struct;
448static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
449{
450 pte_t old_pte;
451
452 spin_lock(&pa_dbit_lock);
453 old_pte = *ptep;
454 pte_clear(mm,addr,ptep);
455 spin_unlock(&pa_dbit_lock);
456
457 return old_pte;
458}
459
460static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
461{
462#ifdef CONFIG_SMP
463 unsigned long new, old;
464
465 do {
466 old = pte_val(*ptep);
467 new = pte_val(pte_wrprotect(__pte (old)));
468 } while (cmpxchg((unsigned long *) ptep, old, new) != old);
469#else
470 pte_t old_pte = *ptep;
471 set_pte_at(mm, addr, ptep, pte_wrprotect(old_pte));
472#endif
473}
474
475#define pte_same(A,B) (pte_val(A) == pte_val(B))
476
477#endif /* !__ASSEMBLY__ */
478
479
480/* TLB page size encoding - see table 3-1 in parisc20.pdf */
481#define _PAGE_SIZE_ENCODING_4K 0
482#define _PAGE_SIZE_ENCODING_16K 1
483#define _PAGE_SIZE_ENCODING_64K 2
484#define _PAGE_SIZE_ENCODING_256K 3
485#define _PAGE_SIZE_ENCODING_1M 4
486#define _PAGE_SIZE_ENCODING_4M 5
487#define _PAGE_SIZE_ENCODING_16M 6
488#define _PAGE_SIZE_ENCODING_64M 7
489
490#if defined(CONFIG_PARISC_PAGE_SIZE_4KB)
491# define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_4K
492#elif defined(CONFIG_PARISC_PAGE_SIZE_16KB)
493# define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_16K
494#elif defined(CONFIG_PARISC_PAGE_SIZE_64KB)
495# define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_64K
496#endif
497
498
499#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
500 remap_pfn_range(vma, vaddr, pfn, size, prot)
501
502#define pgprot_noncached(prot) __pgprot(pgprot_val(prot) | _PAGE_NO_CACHE)
503
504/* We provide our own get_unmapped_area to provide cache coherency */
505
506#define HAVE_ARCH_UNMAPPED_AREA
507
508#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
509#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
510#define __HAVE_ARCH_PTEP_SET_WRPROTECT
511#define __HAVE_ARCH_PTE_SAME
512#include <asm-generic/pgtable.h>
513
514#endif /* _PARISC_PGTABLE_H */