Linux Audio

Check our new training course

Loading...
   1/*
   2 * debugfs interface to core/system MMRs
   3 *
   4 * Copyright 2007-2011 Analog Devices Inc.
   5 *
   6 * Licensed under the GPL-2 or later
   7 */
   8
   9#include <linux/debugfs.h>
  10#include <linux/fs.h>
  11#include <linux/kernel.h>
  12#include <linux/module.h>
  13
  14#include <asm/blackfin.h>
  15#include <asm/gpio.h>
  16#include <asm/gptimers.h>
  17#include <asm/bfin_can.h>
  18#include <asm/bfin_dma.h>
  19#include <asm/bfin_ppi.h>
  20#include <asm/bfin_serial.h>
  21#include <asm/bfin5xx_spi.h>
  22#include <asm/bfin_twi.h>
  23
  24/* Common code defines PORT_MUX on us, so redirect the MMR back locally */
  25#ifdef BFIN_PORT_MUX
  26#undef PORT_MUX
  27#define PORT_MUX BFIN_PORT_MUX
  28#endif
  29
  30#define _d(name, bits, addr, perms) debugfs_create_x##bits(name, perms, parent, (u##bits *)(addr))
  31#define d(name, bits, addr)         _d(name, bits, addr, S_IRUSR|S_IWUSR)
  32#define d_RO(name, bits, addr)      _d(name, bits, addr, S_IRUSR)
  33#define d_WO(name, bits, addr)      _d(name, bits, addr, S_IWUSR)
  34
  35#define D_RO(name, bits) d_RO(#name, bits, name)
  36#define D_WO(name, bits) d_WO(#name, bits, name)
  37#define D32(name)        d(#name, 32, name)
  38#define D16(name)        d(#name, 16, name)
  39
  40#define REGS_OFF(peri, mmr) offsetof(struct bfin_##peri##_regs, mmr)
  41#define __REGS(peri, sname, rname) \
  42	do { \
  43		struct bfin_##peri##_regs r; \
  44		void *addr = (void *)(base + REGS_OFF(peri, rname)); \
  45		strcpy(_buf, sname); \
  46		if (sizeof(r.rname) == 2) \
  47			debugfs_create_x16(buf, S_IRUSR|S_IWUSR, parent, addr); \
  48		else \
  49			debugfs_create_x32(buf, S_IRUSR|S_IWUSR, parent, addr); \
  50	} while (0)
  51#define REGS_STR_PFX(buf, pfx, num) \
  52	({ \
  53		buf + (num >= 0 ? \
  54			sprintf(buf, #pfx "%i_", num) : \
  55			sprintf(buf, #pfx "_")); \
  56	})
  57#define REGS_STR_PFX_C(buf, pfx, num) \
  58	({ \
  59		buf + (num >= 0 ? \
  60			sprintf(buf, #pfx "%c_", 'A' + num) : \
  61			sprintf(buf, #pfx "_")); \
  62	})
  63
  64/*
  65 * Core registers (not memory mapped)
  66 */
  67extern u32 last_seqstat;
  68
  69static int debug_cclk_get(void *data, u64 *val)
  70{
  71	*val = get_cclk();
  72	return 0;
  73}
  74DEFINE_SIMPLE_ATTRIBUTE(fops_debug_cclk, debug_cclk_get, NULL, "0x%08llx\n");
  75
  76static int debug_sclk_get(void *data, u64 *val)
  77{
  78	*val = get_sclk();
  79	return 0;
  80}
  81DEFINE_SIMPLE_ATTRIBUTE(fops_debug_sclk, debug_sclk_get, NULL, "0x%08llx\n");
  82
  83#define DEFINE_SYSREG(sr, pre, post) \
  84static int sysreg_##sr##_get(void *data, u64 *val) \
  85{ \
  86	unsigned long tmp; \
  87	pre; \
  88	__asm__ __volatile__("%0 = " #sr ";" : "=d"(tmp)); \
  89	*val = tmp; \
  90	return 0; \
  91} \
  92static int sysreg_##sr##_set(void *data, u64 val) \
  93{ \
  94	unsigned long tmp = val; \
  95	__asm__ __volatile__(#sr " = %0;" : : "d"(tmp)); \
  96	post; \
  97	return 0; \
  98} \
  99DEFINE_SIMPLE_ATTRIBUTE(fops_sysreg_##sr, sysreg_##sr##_get, sysreg_##sr##_set, "0x%08llx\n")
 100
 101DEFINE_SYSREG(cycles, , );
 102DEFINE_SYSREG(cycles2, __asm__ __volatile__("%0 = cycles;" : "=d"(tmp)), );
 103DEFINE_SYSREG(emudat, , );
 104DEFINE_SYSREG(seqstat, , );
 105DEFINE_SYSREG(syscfg, , CSYNC());
 106#define D_SYSREG(sr) debugfs_create_file(#sr, S_IRUSR|S_IWUSR, parent, NULL, &fops_sysreg_##sr)
 107
 108#ifndef CONFIG_BF60x
 109/*
 110 * CAN
 111 */
 112#define CAN_OFF(mmr)  REGS_OFF(can, mmr)
 113#define __CAN(uname, lname) __REGS(can, #uname, lname)
 114static void __init __maybe_unused
 115bfin_debug_mmrs_can(struct dentry *parent, unsigned long base, int num)
 116{
 117	static struct dentry *am, *mb;
 118	int i, j;
 119	char buf[32], *_buf = REGS_STR_PFX(buf, CAN, num);
 120
 121	if (!am) {
 122		am = debugfs_create_dir("am", parent);
 123		mb = debugfs_create_dir("mb", parent);
 124	}
 125
 126	__CAN(MC1, mc1);
 127	__CAN(MD1, md1);
 128	__CAN(TRS1, trs1);
 129	__CAN(TRR1, trr1);
 130	__CAN(TA1, ta1);
 131	__CAN(AA1, aa1);
 132	__CAN(RMP1, rmp1);
 133	__CAN(RML1, rml1);
 134	__CAN(MBTIF1, mbtif1);
 135	__CAN(MBRIF1, mbrif1);
 136	__CAN(MBIM1, mbim1);
 137	__CAN(RFH1, rfh1);
 138	__CAN(OPSS1, opss1);
 139
 140	__CAN(MC2, mc2);
 141	__CAN(MD2, md2);
 142	__CAN(TRS2, trs2);
 143	__CAN(TRR2, trr2);
 144	__CAN(TA2, ta2);
 145	__CAN(AA2, aa2);
 146	__CAN(RMP2, rmp2);
 147	__CAN(RML2, rml2);
 148	__CAN(MBTIF2, mbtif2);
 149	__CAN(MBRIF2, mbrif2);
 150	__CAN(MBIM2, mbim2);
 151	__CAN(RFH2, rfh2);
 152	__CAN(OPSS2, opss2);
 153
 154	__CAN(CLOCK, clock);
 155	__CAN(TIMING, timing);
 156	__CAN(DEBUG, debug);
 157	__CAN(STATUS, status);
 158	__CAN(CEC, cec);
 159	__CAN(GIS, gis);
 160	__CAN(GIM, gim);
 161	__CAN(GIF, gif);
 162	__CAN(CONTROL, control);
 163	__CAN(INTR, intr);
 164	__CAN(VERSION, version);
 165	__CAN(MBTD, mbtd);
 166	__CAN(EWR, ewr);
 167	__CAN(ESR, esr);
 168	/*__CAN(UCREG, ucreg); no longer exists */
 169	__CAN(UCCNT, uccnt);
 170	__CAN(UCRC, ucrc);
 171	__CAN(UCCNF, uccnf);
 172	__CAN(VERSION2, version2);
 173
 174	for (i = 0; i < 32; ++i) {
 175		sprintf(_buf, "AM%02iL", i);
 176		debugfs_create_x16(buf, S_IRUSR|S_IWUSR, am,
 177			(u16 *)(base + CAN_OFF(msk[i].aml)));
 178		sprintf(_buf, "AM%02iH", i);
 179		debugfs_create_x16(buf, S_IRUSR|S_IWUSR, am,
 180			(u16 *)(base + CAN_OFF(msk[i].amh)));
 181
 182		for (j = 0; j < 3; ++j) {
 183			sprintf(_buf, "MB%02i_DATA%i", i, j);
 184			debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
 185				(u16 *)(base + CAN_OFF(chl[i].data[j*2])));
 186		}
 187		sprintf(_buf, "MB%02i_LENGTH", i);
 188		debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
 189			(u16 *)(base + CAN_OFF(chl[i].dlc)));
 190		sprintf(_buf, "MB%02i_TIMESTAMP", i);
 191		debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
 192			(u16 *)(base + CAN_OFF(chl[i].tsv)));
 193		sprintf(_buf, "MB%02i_ID0", i);
 194		debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
 195			(u16 *)(base + CAN_OFF(chl[i].id0)));
 196		sprintf(_buf, "MB%02i_ID1", i);
 197		debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
 198			(u16 *)(base + CAN_OFF(chl[i].id1)));
 199	}
 200}
 201#define CAN(num) bfin_debug_mmrs_can(parent, CAN##num##_MC1, num)
 202
 203/*
 204 * DMA
 205 */
 206#define __DMA(uname, lname) __REGS(dma, #uname, lname)
 207static void __init __maybe_unused
 208bfin_debug_mmrs_dma(struct dentry *parent, unsigned long base, int num, char mdma, const char *pfx)
 209{
 210	char buf[32], *_buf;
 211
 212	if (mdma)
 213		_buf = buf + sprintf(buf, "%s_%c%i_", pfx, mdma, num);
 214	else
 215		_buf = buf + sprintf(buf, "%s%i_", pfx, num);
 216
 217	__DMA(NEXT_DESC_PTR, next_desc_ptr);
 218	__DMA(START_ADDR, start_addr);
 219	__DMA(CONFIG, config);
 220	__DMA(X_COUNT, x_count);
 221	__DMA(X_MODIFY, x_modify);
 222	__DMA(Y_COUNT, y_count);
 223	__DMA(Y_MODIFY, y_modify);
 224	__DMA(CURR_DESC_PTR, curr_desc_ptr);
 225	__DMA(CURR_ADDR, curr_addr);
 226	__DMA(IRQ_STATUS, irq_status);
 227#ifndef CONFIG_BF60x
 228	if (strcmp(pfx, "IMDMA") != 0)
 229		__DMA(PERIPHERAL_MAP, peripheral_map);
 230#endif
 231	__DMA(CURR_X_COUNT, curr_x_count);
 232	__DMA(CURR_Y_COUNT, curr_y_count);
 233}
 234#define _DMA(num, base, mdma, pfx) bfin_debug_mmrs_dma(parent, base, num, mdma, pfx "DMA")
 235#define DMA(num)  _DMA(num, DMA##num##_NEXT_DESC_PTR, 0, "")
 236#define _MDMA(num, x) \
 237	do { \
 238		_DMA(num, x##DMA_D##num##_NEXT_DESC_PTR, 'D', #x); \
 239		_DMA(num, x##DMA_S##num##_NEXT_DESC_PTR, 'S', #x); \
 240	} while (0)
 241#define MDMA(num) _MDMA(num, M)
 242#define IMDMA(num) _MDMA(num, IM)
 243
 244/*
 245 * EPPI
 246 */
 247#define __EPPI(uname, lname) __REGS(eppi, #uname, lname)
 248static void __init __maybe_unused
 249bfin_debug_mmrs_eppi(struct dentry *parent, unsigned long base, int num)
 250{
 251	char buf[32], *_buf = REGS_STR_PFX(buf, EPPI, num);
 252	__EPPI(STATUS, status);
 253	__EPPI(HCOUNT, hcount);
 254	__EPPI(HDELAY, hdelay);
 255	__EPPI(VCOUNT, vcount);
 256	__EPPI(VDELAY, vdelay);
 257	__EPPI(FRAME, frame);
 258	__EPPI(LINE, line);
 259	__EPPI(CLKDIV, clkdiv);
 260	__EPPI(CONTROL, control);
 261	__EPPI(FS1W_HBL, fs1w_hbl);
 262	__EPPI(FS1P_AVPL, fs1p_avpl);
 263	__EPPI(FS2W_LVB, fs2w_lvb);
 264	__EPPI(FS2P_LAVF, fs2p_lavf);
 265	__EPPI(CLIP, clip);
 266}
 267#define EPPI(num) bfin_debug_mmrs_eppi(parent, EPPI##num##_STATUS, num)
 268
 269/*
 270 * General Purpose Timers
 271 */
 272#define __GPTIMER(uname, lname) __REGS(gptimer, #uname, lname)
 273static void __init __maybe_unused
 274bfin_debug_mmrs_gptimer(struct dentry *parent, unsigned long base, int num)
 275{
 276	char buf[32], *_buf = REGS_STR_PFX(buf, TIMER, num);
 277	__GPTIMER(CONFIG, config);
 278	__GPTIMER(COUNTER, counter);
 279	__GPTIMER(PERIOD, period);
 280	__GPTIMER(WIDTH, width);
 281}
 282#define GPTIMER(num) bfin_debug_mmrs_gptimer(parent, TIMER##num##_CONFIG, num)
 283
 284#define GPTIMER_GROUP_OFF(mmr) REGS_OFF(gptimer_group, mmr)
 285#define __GPTIMER_GROUP(uname, lname) __REGS(gptimer_group, #uname, lname)
 286static void __init __maybe_unused
 287bfin_debug_mmrs_gptimer_group(struct dentry *parent, unsigned long base, int num)
 288{
 289	char buf[32], *_buf;
 290
 291	if (num == -1) {
 292		_buf = buf + sprintf(buf, "TIMER_");
 293		__GPTIMER_GROUP(ENABLE, enable);
 294		__GPTIMER_GROUP(DISABLE, disable);
 295		__GPTIMER_GROUP(STATUS, status);
 296	} else {
 297		/* These MMRs are a bit odd as the group # is a suffix */
 298		_buf = buf + sprintf(buf, "TIMER_ENABLE%i", num);
 299		d(buf, 16, base + GPTIMER_GROUP_OFF(enable));
 300
 301		_buf = buf + sprintf(buf, "TIMER_DISABLE%i", num);
 302		d(buf, 16, base + GPTIMER_GROUP_OFF(disable));
 303
 304		_buf = buf + sprintf(buf, "TIMER_STATUS%i", num);
 305		d(buf, 32, base + GPTIMER_GROUP_OFF(status));
 306	}
 307}
 308#define GPTIMER_GROUP(mmr, num) bfin_debug_mmrs_gptimer_group(parent, mmr, num)
 309
 310/*
 311 * Handshake MDMA
 312 */
 313#define __HMDMA(uname, lname) __REGS(hmdma, #uname, lname)
 314static void __init __maybe_unused
 315bfin_debug_mmrs_hmdma(struct dentry *parent, unsigned long base, int num)
 316{
 317	char buf[32], *_buf = REGS_STR_PFX(buf, HMDMA, num);
 318	__HMDMA(CONTROL, control);
 319	__HMDMA(ECINIT, ecinit);
 320	__HMDMA(BCINIT, bcinit);
 321	__HMDMA(ECURGENT, ecurgent);
 322	__HMDMA(ECOVERFLOW, ecoverflow);
 323	__HMDMA(ECOUNT, ecount);
 324	__HMDMA(BCOUNT, bcount);
 325}
 326#define HMDMA(num) bfin_debug_mmrs_hmdma(parent, HMDMA##num##_CONTROL, num)
 327
 328/*
 329 * Peripheral Interrupts (PINT/GPIO)
 330 */
 331#ifdef PINT0_MASK_SET
 332#define __PINT(uname, lname) __REGS(pint, #uname, lname)
 333static void __init __maybe_unused
 334bfin_debug_mmrs_pint(struct dentry *parent, unsigned long base, int num)
 335{
 336	char buf[32], *_buf = REGS_STR_PFX(buf, PINT, num);
 337	__PINT(MASK_SET, mask_set);
 338	__PINT(MASK_CLEAR, mask_clear);
 339	__PINT(REQUEST, request);
 340	__PINT(ASSIGN, assign);
 341	__PINT(EDGE_SET, edge_set);
 342	__PINT(EDGE_CLEAR, edge_clear);
 343	__PINT(INVERT_SET, invert_set);
 344	__PINT(INVERT_CLEAR, invert_clear);
 345	__PINT(PINSTATE, pinstate);
 346	__PINT(LATCH, latch);
 347}
 348#define PINT(num) bfin_debug_mmrs_pint(parent, PINT##num##_MASK_SET, num)
 349#endif
 350
 351/*
 352 * Port/GPIO
 353 */
 354#define bfin_gpio_regs gpio_port_t
 355#define __PORT(uname, lname) __REGS(gpio, #uname, lname)
 356static void __init __maybe_unused
 357bfin_debug_mmrs_port(struct dentry *parent, unsigned long base, int num)
 358{
 359	char buf[32], *_buf;
 360#ifdef __ADSPBF54x__
 361	_buf = REGS_STR_PFX_C(buf, PORT, num);
 362	__PORT(FER, port_fer);
 363	__PORT(SET, data_set);
 364	__PORT(CLEAR, data_clear);
 365	__PORT(DIR_SET, dir_set);
 366	__PORT(DIR_CLEAR, dir_clear);
 367	__PORT(INEN, inen);
 368	__PORT(MUX, port_mux);
 369#else
 370	_buf = buf + sprintf(buf, "PORT%cIO_", num);
 371	__PORT(CLEAR, data_clear);
 372	__PORT(SET, data_set);
 373	__PORT(TOGGLE, toggle);
 374	__PORT(MASKA, maska);
 375	__PORT(MASKA_CLEAR, maska_clear);
 376	__PORT(MASKA_SET, maska_set);
 377	__PORT(MASKA_TOGGLE, maska_toggle);
 378	__PORT(MASKB, maskb);
 379	__PORT(MASKB_CLEAR, maskb_clear);
 380	__PORT(MASKB_SET, maskb_set);
 381	__PORT(MASKB_TOGGLE, maskb_toggle);
 382	__PORT(DIR, dir);
 383	__PORT(POLAR, polar);
 384	__PORT(EDGE, edge);
 385	__PORT(BOTH, both);
 386	__PORT(INEN, inen);
 387#endif
 388	_buf[-1] = '\0';
 389	d(buf, 16, base + REGS_OFF(gpio, data));
 390}
 391#define PORT(base, num) bfin_debug_mmrs_port(parent, base, num)
 392
 393/*
 394 * PPI
 395 */
 396#define __PPI(uname, lname) __REGS(ppi, #uname, lname)
 397static void __init __maybe_unused
 398bfin_debug_mmrs_ppi(struct dentry *parent, unsigned long base, int num)
 399{
 400	char buf[32], *_buf = REGS_STR_PFX(buf, PPI, num);
 401	__PPI(CONTROL, control);
 402	__PPI(STATUS, status);
 403	__PPI(COUNT, count);
 404	__PPI(DELAY, delay);
 405	__PPI(FRAME, frame);
 406}
 407#define PPI(num) bfin_debug_mmrs_ppi(parent, PPI##num##_CONTROL, num)
 408
 409/*
 410 * SPI
 411 */
 412#define __SPI(uname, lname) __REGS(spi, #uname, lname)
 413static void __init __maybe_unused
 414bfin_debug_mmrs_spi(struct dentry *parent, unsigned long base, int num)
 415{
 416	char buf[32], *_buf = REGS_STR_PFX(buf, SPI, num);
 417	__SPI(CTL, ctl);
 418	__SPI(FLG, flg);
 419	__SPI(STAT, stat);
 420	__SPI(TDBR, tdbr);
 421	__SPI(RDBR, rdbr);
 422	__SPI(BAUD, baud);
 423	__SPI(SHADOW, shadow);
 424}
 425#define SPI(num) bfin_debug_mmrs_spi(parent, SPI##num##_REGBASE, num)
 426
 427/*
 428 * SPORT
 429 */
 430static inline int sport_width(void *mmr)
 431{
 432	unsigned long lmmr = (unsigned long)mmr;
 433	if ((lmmr & 0xff) == 0x10)
 434		/* SPORT#_TX has 0x10 offset -> SPORT#_TCR2 has 0x04 offset */
 435		lmmr -= 0xc;
 436	else
 437		/* SPORT#_RX has 0x18 offset -> SPORT#_RCR2 has 0x24 offset */
 438		lmmr += 0xc;
 439	/* extract SLEN field from control register 2 and add 1 */
 440	return (bfin_read16(lmmr) & 0x1f) + 1;
 441}
 442static int sport_set(void *mmr, u64 val)
 443{
 444	unsigned long flags;
 445	local_irq_save(flags);
 446	if (sport_width(mmr) <= 16)
 447		bfin_write16(mmr, val);
 448	else
 449		bfin_write32(mmr, val);
 450	local_irq_restore(flags);
 451	return 0;
 452}
 453static int sport_get(void *mmr, u64 *val)
 454{
 455	unsigned long flags;
 456	local_irq_save(flags);
 457	if (sport_width(mmr) <= 16)
 458		*val = bfin_read16(mmr);
 459	else
 460		*val = bfin_read32(mmr);
 461	local_irq_restore(flags);
 462	return 0;
 463}
 464DEFINE_SIMPLE_ATTRIBUTE(fops_sport, sport_get, sport_set, "0x%08llx\n");
 465/*DEFINE_SIMPLE_ATTRIBUTE(fops_sport_ro, sport_get, NULL, "0x%08llx\n");*/
 466DEFINE_SIMPLE_ATTRIBUTE(fops_sport_wo, NULL, sport_set, "0x%08llx\n");
 467#define SPORT_OFF(mmr) (SPORT0_##mmr - SPORT0_TCR1)
 468#define _D_SPORT(name, perms, fops) \
 469	do { \
 470		strcpy(_buf, #name); \
 471		debugfs_create_file(buf, perms, parent, (void *)(base + SPORT_OFF(name)), fops); \
 472	} while (0)
 473#define __SPORT_RW(name) _D_SPORT(name, S_IRUSR|S_IWUSR, &fops_sport)
 474#define __SPORT_RO(name) _D_SPORT(name, S_IRUSR, &fops_sport_ro)
 475#define __SPORT_WO(name) _D_SPORT(name, S_IWUSR, &fops_sport_wo)
 476#define __SPORT(name, bits) \
 477	do { \
 478		strcpy(_buf, #name); \
 479		debugfs_create_x##bits(buf, S_IRUSR|S_IWUSR, parent, (u##bits *)(base + SPORT_OFF(name))); \
 480	} while (0)
 481static void __init __maybe_unused
 482bfin_debug_mmrs_sport(struct dentry *parent, unsigned long base, int num)
 483{
 484	char buf[32], *_buf = REGS_STR_PFX(buf, SPORT, num);
 485	__SPORT(CHNL, 16);
 486	__SPORT(MCMC1, 16);
 487	__SPORT(MCMC2, 16);
 488	__SPORT(MRCS0, 32);
 489	__SPORT(MRCS1, 32);
 490	__SPORT(MRCS2, 32);
 491	__SPORT(MRCS3, 32);
 492	__SPORT(MTCS0, 32);
 493	__SPORT(MTCS1, 32);
 494	__SPORT(MTCS2, 32);
 495	__SPORT(MTCS3, 32);
 496	__SPORT(RCLKDIV, 16);
 497	__SPORT(RCR1, 16);
 498	__SPORT(RCR2, 16);
 499	__SPORT(RFSDIV, 16);
 500	__SPORT_RW(RX);
 501	__SPORT(STAT, 16);
 502	__SPORT(TCLKDIV, 16);
 503	__SPORT(TCR1, 16);
 504	__SPORT(TCR2, 16);
 505	__SPORT(TFSDIV, 16);
 506	__SPORT_WO(TX);
 507}
 508#define SPORT(num) bfin_debug_mmrs_sport(parent, SPORT##num##_TCR1, num)
 509
 510/*
 511 * TWI
 512 */
 513#define __TWI(uname, lname) __REGS(twi, #uname, lname)
 514static void __init __maybe_unused
 515bfin_debug_mmrs_twi(struct dentry *parent, unsigned long base, int num)
 516{
 517	char buf[32], *_buf = REGS_STR_PFX(buf, TWI, num);
 518	__TWI(CLKDIV, clkdiv);
 519	__TWI(CONTROL, control);
 520	__TWI(SLAVE_CTL, slave_ctl);
 521	__TWI(SLAVE_STAT, slave_stat);
 522	__TWI(SLAVE_ADDR, slave_addr);
 523	__TWI(MASTER_CTL, master_ctl);
 524	__TWI(MASTER_STAT, master_stat);
 525	__TWI(MASTER_ADDR, master_addr);
 526	__TWI(INT_STAT, int_stat);
 527	__TWI(INT_MASK, int_mask);
 528	__TWI(FIFO_CTL, fifo_ctl);
 529	__TWI(FIFO_STAT, fifo_stat);
 530	__TWI(XMT_DATA8, xmt_data8);
 531	__TWI(XMT_DATA16, xmt_data16);
 532	__TWI(RCV_DATA8, rcv_data8);
 533	__TWI(RCV_DATA16, rcv_data16);
 534}
 535#define TWI(num) bfin_debug_mmrs_twi(parent, TWI##num##_CLKDIV, num)
 536
 537/*
 538 * UART
 539 */
 540#define __UART(uname, lname) __REGS(uart, #uname, lname)
 541static void __init __maybe_unused
 542bfin_debug_mmrs_uart(struct dentry *parent, unsigned long base, int num)
 543{
 544	char buf[32], *_buf = REGS_STR_PFX(buf, UART, num);
 545#ifdef BFIN_UART_BF54X_STYLE
 546	__UART(DLL, dll);
 547	__UART(DLH, dlh);
 548	__UART(GCTL, gctl);
 549	__UART(LCR, lcr);
 550	__UART(MCR, mcr);
 551	__UART(LSR, lsr);
 552	__UART(MSR, msr);
 553	__UART(SCR, scr);
 554	__UART(IER_SET, ier_set);
 555	__UART(IER_CLEAR, ier_clear);
 556	__UART(THR, thr);
 557	__UART(RBR, rbr);
 558#else
 559	__UART(DLL, dll);
 560	__UART(THR, thr);
 561	__UART(RBR, rbr);
 562	__UART(DLH, dlh);
 563	__UART(IER, ier);
 564	__UART(IIR, iir);
 565	__UART(LCR, lcr);
 566	__UART(MCR, mcr);
 567	__UART(LSR, lsr);
 568	__UART(MSR, msr);
 569	__UART(SCR, scr);
 570	__UART(GCTL, gctl);
 571#endif
 572}
 573#define UART(num) bfin_debug_mmrs_uart(parent, UART##num##_DLL, num)
 574#endif /* CONFIG_BF60x */
 575/*
 576 * The actual debugfs generation
 577 */
 578static struct dentry *debug_mmrs_dentry;
 579
 580static int __init bfin_debug_mmrs_init(void)
 581{
 582	struct dentry *top, *parent;
 583
 584	pr_info("debug-mmrs: setting up Blackfin MMR debugfs\n");
 585
 586	top = debugfs_create_dir("blackfin", NULL);
 587	if (top == NULL)
 588		return -1;
 589
 590	parent = debugfs_create_dir("core_regs", top);
 591	debugfs_create_file("cclk", S_IRUSR, parent, NULL, &fops_debug_cclk);
 592	debugfs_create_file("sclk", S_IRUSR, parent, NULL, &fops_debug_sclk);
 593	debugfs_create_x32("last_seqstat", S_IRUSR, parent, &last_seqstat);
 594	D_SYSREG(cycles);
 595	D_SYSREG(cycles2);
 596	D_SYSREG(emudat);
 597	D_SYSREG(seqstat);
 598	D_SYSREG(syscfg);
 599
 600	/* Core MMRs */
 601	parent = debugfs_create_dir("ctimer", top);
 602	D32(TCNTL);
 603	D32(TCOUNT);
 604	D32(TPERIOD);
 605	D32(TSCALE);
 606
 607	parent = debugfs_create_dir("cec", top);
 608	D32(EVT0);
 609	D32(EVT1);
 610	D32(EVT2);
 611	D32(EVT3);
 612	D32(EVT4);
 613	D32(EVT5);
 614	D32(EVT6);
 615	D32(EVT7);
 616	D32(EVT8);
 617	D32(EVT9);
 618	D32(EVT10);
 619	D32(EVT11);
 620	D32(EVT12);
 621	D32(EVT13);
 622	D32(EVT14);
 623	D32(EVT15);
 624	D32(EVT_OVERRIDE);
 625	D32(IMASK);
 626	D32(IPEND);
 627	D32(ILAT);
 628	D32(IPRIO);
 629
 630	parent = debugfs_create_dir("debug", top);
 631	D32(DBGSTAT);
 632	D32(DSPID);
 633
 634	parent = debugfs_create_dir("mmu", top);
 635	D32(SRAM_BASE_ADDRESS);
 636	D32(DCPLB_ADDR0);
 637	D32(DCPLB_ADDR10);
 638	D32(DCPLB_ADDR11);
 639	D32(DCPLB_ADDR12);
 640	D32(DCPLB_ADDR13);
 641	D32(DCPLB_ADDR14);
 642	D32(DCPLB_ADDR15);
 643	D32(DCPLB_ADDR1);
 644	D32(DCPLB_ADDR2);
 645	D32(DCPLB_ADDR3);
 646	D32(DCPLB_ADDR4);
 647	D32(DCPLB_ADDR5);
 648	D32(DCPLB_ADDR6);
 649	D32(DCPLB_ADDR7);
 650	D32(DCPLB_ADDR8);
 651	D32(DCPLB_ADDR9);
 652	D32(DCPLB_DATA0);
 653	D32(DCPLB_DATA10);
 654	D32(DCPLB_DATA11);
 655	D32(DCPLB_DATA12);
 656	D32(DCPLB_DATA13);
 657	D32(DCPLB_DATA14);
 658	D32(DCPLB_DATA15);
 659	D32(DCPLB_DATA1);
 660	D32(DCPLB_DATA2);
 661	D32(DCPLB_DATA3);
 662	D32(DCPLB_DATA4);
 663	D32(DCPLB_DATA5);
 664	D32(DCPLB_DATA6);
 665	D32(DCPLB_DATA7);
 666	D32(DCPLB_DATA8);
 667	D32(DCPLB_DATA9);
 668	D32(DCPLB_FAULT_ADDR);
 669	D32(DCPLB_STATUS);
 670	D32(DMEM_CONTROL);
 671	D32(DTEST_COMMAND);
 672	D32(DTEST_DATA0);
 673	D32(DTEST_DATA1);
 674
 675	D32(ICPLB_ADDR0);
 676	D32(ICPLB_ADDR1);
 677	D32(ICPLB_ADDR2);
 678	D32(ICPLB_ADDR3);
 679	D32(ICPLB_ADDR4);
 680	D32(ICPLB_ADDR5);
 681	D32(ICPLB_ADDR6);
 682	D32(ICPLB_ADDR7);
 683	D32(ICPLB_ADDR8);
 684	D32(ICPLB_ADDR9);
 685	D32(ICPLB_ADDR10);
 686	D32(ICPLB_ADDR11);
 687	D32(ICPLB_ADDR12);
 688	D32(ICPLB_ADDR13);
 689	D32(ICPLB_ADDR14);
 690	D32(ICPLB_ADDR15);
 691	D32(ICPLB_DATA0);
 692	D32(ICPLB_DATA1);
 693	D32(ICPLB_DATA2);
 694	D32(ICPLB_DATA3);
 695	D32(ICPLB_DATA4);
 696	D32(ICPLB_DATA5);
 697	D32(ICPLB_DATA6);
 698	D32(ICPLB_DATA7);
 699	D32(ICPLB_DATA8);
 700	D32(ICPLB_DATA9);
 701	D32(ICPLB_DATA10);
 702	D32(ICPLB_DATA11);
 703	D32(ICPLB_DATA12);
 704	D32(ICPLB_DATA13);
 705	D32(ICPLB_DATA14);
 706	D32(ICPLB_DATA15);
 707	D32(ICPLB_FAULT_ADDR);
 708	D32(ICPLB_STATUS);
 709	D32(IMEM_CONTROL);
 710	if (!ANOMALY_05000481) {
 711		D32(ITEST_COMMAND);
 712		D32(ITEST_DATA0);
 713		D32(ITEST_DATA1);
 714	}
 715
 716	parent = debugfs_create_dir("perf", top);
 717	D32(PFCNTR0);
 718	D32(PFCNTR1);
 719	D32(PFCTL);
 720
 721	parent = debugfs_create_dir("trace", top);
 722	D32(TBUF);
 723	D32(TBUFCTL);
 724	D32(TBUFSTAT);
 725
 726	parent = debugfs_create_dir("watchpoint", top);
 727	D32(WPIACTL);
 728	D32(WPIA0);
 729	D32(WPIA1);
 730	D32(WPIA2);
 731	D32(WPIA3);
 732	D32(WPIA4);
 733	D32(WPIA5);
 734	D32(WPIACNT0);
 735	D32(WPIACNT1);
 736	D32(WPIACNT2);
 737	D32(WPIACNT3);
 738	D32(WPIACNT4);
 739	D32(WPIACNT5);
 740	D32(WPDACTL);
 741	D32(WPDA0);
 742	D32(WPDA1);
 743	D32(WPDACNT0);
 744	D32(WPDACNT1);
 745	D32(WPSTAT);
 746#ifndef CONFIG_BF60x
 747	/* System MMRs */
 748#ifdef ATAPI_CONTROL
 749	parent = debugfs_create_dir("atapi", top);
 750	D16(ATAPI_CONTROL);
 751	D16(ATAPI_DEV_ADDR);
 752	D16(ATAPI_DEV_RXBUF);
 753	D16(ATAPI_DEV_TXBUF);
 754	D16(ATAPI_DMA_TFRCNT);
 755	D16(ATAPI_INT_MASK);
 756	D16(ATAPI_INT_STATUS);
 757	D16(ATAPI_LINE_STATUS);
 758	D16(ATAPI_MULTI_TIM_0);
 759	D16(ATAPI_MULTI_TIM_1);
 760	D16(ATAPI_MULTI_TIM_2);
 761	D16(ATAPI_PIO_TFRCNT);
 762	D16(ATAPI_PIO_TIM_0);
 763	D16(ATAPI_PIO_TIM_1);
 764	D16(ATAPI_REG_TIM_0);
 765	D16(ATAPI_SM_STATE);
 766	D16(ATAPI_STATUS);
 767	D16(ATAPI_TERMINATE);
 768	D16(ATAPI_UDMAOUT_TFRCNT);
 769	D16(ATAPI_ULTRA_TIM_0);
 770	D16(ATAPI_ULTRA_TIM_1);
 771	D16(ATAPI_ULTRA_TIM_2);
 772	D16(ATAPI_ULTRA_TIM_3);
 773	D16(ATAPI_UMAIN_TFRCNT);
 774	D16(ATAPI_XFER_LEN);
 775#endif
 776
 777#if defined(CAN_MC1) || defined(CAN0_MC1) || defined(CAN1_MC1)
 778	parent = debugfs_create_dir("can", top);
 779# ifdef CAN_MC1
 780	bfin_debug_mmrs_can(parent, CAN_MC1, -1);
 781# endif
 782# ifdef CAN0_MC1
 783	CAN(0);
 784# endif
 785# ifdef CAN1_MC1
 786	CAN(1);
 787# endif
 788#endif
 789
 790#ifdef CNT_COMMAND
 791	parent = debugfs_create_dir("counter", top);
 792	D16(CNT_COMMAND);
 793	D16(CNT_CONFIG);
 794	D32(CNT_COUNTER);
 795	D16(CNT_DEBOUNCE);
 796	D16(CNT_IMASK);
 797	D32(CNT_MAX);
 798	D32(CNT_MIN);
 799	D16(CNT_STATUS);
 800#endif
 801
 802	parent = debugfs_create_dir("dmac", top);
 803#ifdef DMAC_TC_CNT
 804	D16(DMAC_TC_CNT);
 805	D16(DMAC_TC_PER);
 806#endif
 807#ifdef DMAC0_TC_CNT
 808	D16(DMAC0_TC_CNT);
 809	D16(DMAC0_TC_PER);
 810#endif
 811#ifdef DMAC1_TC_CNT
 812	D16(DMAC1_TC_CNT);
 813	D16(DMAC1_TC_PER);
 814#endif
 815#ifdef DMAC1_PERIMUX
 816	D16(DMAC1_PERIMUX);
 817#endif
 818
 819#ifdef __ADSPBF561__
 820	/* XXX: should rewrite the MMR map */
 821# define DMA0_NEXT_DESC_PTR DMA2_0_NEXT_DESC_PTR
 822# define DMA1_NEXT_DESC_PTR DMA2_1_NEXT_DESC_PTR
 823# define DMA2_NEXT_DESC_PTR DMA2_2_NEXT_DESC_PTR
 824# define DMA3_NEXT_DESC_PTR DMA2_3_NEXT_DESC_PTR
 825# define DMA4_NEXT_DESC_PTR DMA2_4_NEXT_DESC_PTR
 826# define DMA5_NEXT_DESC_PTR DMA2_5_NEXT_DESC_PTR
 827# define DMA6_NEXT_DESC_PTR DMA2_6_NEXT_DESC_PTR
 828# define DMA7_NEXT_DESC_PTR DMA2_7_NEXT_DESC_PTR
 829# define DMA8_NEXT_DESC_PTR DMA2_8_NEXT_DESC_PTR
 830# define DMA9_NEXT_DESC_PTR DMA2_9_NEXT_DESC_PTR
 831# define DMA10_NEXT_DESC_PTR DMA2_10_NEXT_DESC_PTR
 832# define DMA11_NEXT_DESC_PTR DMA2_11_NEXT_DESC_PTR
 833# define DMA12_NEXT_DESC_PTR DMA1_0_NEXT_DESC_PTR
 834# define DMA13_NEXT_DESC_PTR DMA1_1_NEXT_DESC_PTR
 835# define DMA14_NEXT_DESC_PTR DMA1_2_NEXT_DESC_PTR
 836# define DMA15_NEXT_DESC_PTR DMA1_3_NEXT_DESC_PTR
 837# define DMA16_NEXT_DESC_PTR DMA1_4_NEXT_DESC_PTR
 838# define DMA17_NEXT_DESC_PTR DMA1_5_NEXT_DESC_PTR
 839# define DMA18_NEXT_DESC_PTR DMA1_6_NEXT_DESC_PTR
 840# define DMA19_NEXT_DESC_PTR DMA1_7_NEXT_DESC_PTR
 841# define DMA20_NEXT_DESC_PTR DMA1_8_NEXT_DESC_PTR
 842# define DMA21_NEXT_DESC_PTR DMA1_9_NEXT_DESC_PTR
 843# define DMA22_NEXT_DESC_PTR DMA1_10_NEXT_DESC_PTR
 844# define DMA23_NEXT_DESC_PTR DMA1_11_NEXT_DESC_PTR
 845#endif
 846	parent = debugfs_create_dir("dma", top);
 847	DMA(0);
 848	DMA(1);
 849	DMA(1);
 850	DMA(2);
 851	DMA(3);
 852	DMA(4);
 853	DMA(5);
 854	DMA(6);
 855	DMA(7);
 856#ifdef DMA8_NEXT_DESC_PTR
 857	DMA(8);
 858	DMA(9);
 859	DMA(10);
 860	DMA(11);
 861#endif
 862#ifdef DMA12_NEXT_DESC_PTR
 863	DMA(12);
 864	DMA(13);
 865	DMA(14);
 866	DMA(15);
 867	DMA(16);
 868	DMA(17);
 869	DMA(18);
 870	DMA(19);
 871#endif
 872#ifdef DMA20_NEXT_DESC_PTR
 873	DMA(20);
 874	DMA(21);
 875	DMA(22);
 876	DMA(23);
 877#endif
 878
 879	parent = debugfs_create_dir("ebiu_amc", top);
 880	D32(EBIU_AMBCTL0);
 881	D32(EBIU_AMBCTL1);
 882	D16(EBIU_AMGCTL);
 883#ifdef EBIU_MBSCTL
 884	D16(EBIU_MBSCTL);
 885	D32(EBIU_ARBSTAT);
 886	D32(EBIU_MODE);
 887	D16(EBIU_FCTL);
 888#endif
 889
 890#ifdef EBIU_SDGCTL
 891	parent = debugfs_create_dir("ebiu_sdram", top);
 892# ifdef __ADSPBF561__
 893	D32(EBIU_SDBCTL);
 894# else
 895	D16(EBIU_SDBCTL);
 896# endif
 897	D32(EBIU_SDGCTL);
 898	D16(EBIU_SDRRC);
 899	D16(EBIU_SDSTAT);
 900#endif
 901
 902#ifdef EBIU_DDRACCT
 903	parent = debugfs_create_dir("ebiu_ddr", top);
 904	D32(EBIU_DDRACCT);
 905	D32(EBIU_DDRARCT);
 906	D32(EBIU_DDRBRC0);
 907	D32(EBIU_DDRBRC1);
 908	D32(EBIU_DDRBRC2);
 909	D32(EBIU_DDRBRC3);
 910	D32(EBIU_DDRBRC4);
 911	D32(EBIU_DDRBRC5);
 912	D32(EBIU_DDRBRC6);
 913	D32(EBIU_DDRBRC7);
 914	D32(EBIU_DDRBWC0);
 915	D32(EBIU_DDRBWC1);
 916	D32(EBIU_DDRBWC2);
 917	D32(EBIU_DDRBWC3);
 918	D32(EBIU_DDRBWC4);
 919	D32(EBIU_DDRBWC5);
 920	D32(EBIU_DDRBWC6);
 921	D32(EBIU_DDRBWC7);
 922	D32(EBIU_DDRCTL0);
 923	D32(EBIU_DDRCTL1);
 924	D32(EBIU_DDRCTL2);
 925	D32(EBIU_DDRCTL3);
 926	D32(EBIU_DDRGC0);
 927	D32(EBIU_DDRGC1);
 928	D32(EBIU_DDRGC2);
 929	D32(EBIU_DDRGC3);
 930	D32(EBIU_DDRMCCL);
 931	D32(EBIU_DDRMCEN);
 932	D32(EBIU_DDRQUE);
 933	D32(EBIU_DDRTACT);
 934	D32(EBIU_ERRADD);
 935	D16(EBIU_ERRMST);
 936	D16(EBIU_RSTCTL);
 937#endif
 938
 939#ifdef EMAC_ADDRHI
 940	parent = debugfs_create_dir("emac", top);
 941	D32(EMAC_ADDRHI);
 942	D32(EMAC_ADDRLO);
 943	D32(EMAC_FLC);
 944	D32(EMAC_HASHHI);
 945	D32(EMAC_HASHLO);
 946	D32(EMAC_MMC_CTL);
 947	D32(EMAC_MMC_RIRQE);
 948	D32(EMAC_MMC_RIRQS);
 949	D32(EMAC_MMC_TIRQE);
 950	D32(EMAC_MMC_TIRQS);
 951	D32(EMAC_OPMODE);
 952	D32(EMAC_RXC_ALIGN);
 953	D32(EMAC_RXC_ALLFRM);
 954	D32(EMAC_RXC_ALLOCT);
 955	D32(EMAC_RXC_BROAD);
 956	D32(EMAC_RXC_DMAOVF);
 957	D32(EMAC_RXC_EQ64);
 958	D32(EMAC_RXC_FCS);
 959	D32(EMAC_RXC_GE1024);
 960	D32(EMAC_RXC_LNERRI);
 961	D32(EMAC_RXC_LNERRO);
 962	D32(EMAC_RXC_LONG);
 963	D32(EMAC_RXC_LT1024);
 964	D32(EMAC_RXC_LT128);
 965	D32(EMAC_RXC_LT256);
 966	D32(EMAC_RXC_LT512);
 967	D32(EMAC_RXC_MACCTL);
 968	D32(EMAC_RXC_MULTI);
 969	D32(EMAC_RXC_OCTET);
 970	D32(EMAC_RXC_OK);
 971	D32(EMAC_RXC_OPCODE);
 972	D32(EMAC_RXC_PAUSE);
 973	D32(EMAC_RXC_SHORT);
 974	D32(EMAC_RXC_TYPED);
 975	D32(EMAC_RXC_UNICST);
 976	D32(EMAC_RX_IRQE);
 977	D32(EMAC_RX_STAT);
 978	D32(EMAC_RX_STKY);
 979	D32(EMAC_STAADD);
 980	D32(EMAC_STADAT);
 981	D32(EMAC_SYSCTL);
 982	D32(EMAC_SYSTAT);
 983	D32(EMAC_TXC_1COL);
 984	D32(EMAC_TXC_ABORT);
 985	D32(EMAC_TXC_ALLFRM);
 986	D32(EMAC_TXC_ALLOCT);
 987	D32(EMAC_TXC_BROAD);
 988	D32(EMAC_TXC_CRSERR);
 989	D32(EMAC_TXC_DEFER);
 990	D32(EMAC_TXC_DMAUND);
 991	D32(EMAC_TXC_EQ64);
 992	D32(EMAC_TXC_GE1024);
 993	D32(EMAC_TXC_GT1COL);
 994	D32(EMAC_TXC_LATECL);
 995	D32(EMAC_TXC_LT1024);
 996	D32(EMAC_TXC_LT128);
 997	D32(EMAC_TXC_LT256);
 998	D32(EMAC_TXC_LT512);
 999	D32(EMAC_TXC_MACCTL);
1000	D32(EMAC_TXC_MULTI);
1001	D32(EMAC_TXC_OCTET);
1002	D32(EMAC_TXC_OK);
1003	D32(EMAC_TXC_UNICST);
1004	D32(EMAC_TXC_XS_COL);
1005	D32(EMAC_TXC_XS_DFR);
1006	D32(EMAC_TX_IRQE);
1007	D32(EMAC_TX_STAT);
1008	D32(EMAC_TX_STKY);
1009	D32(EMAC_VLAN1);
1010	D32(EMAC_VLAN2);
1011	D32(EMAC_WKUP_CTL);
1012	D32(EMAC_WKUP_FFCMD);
1013	D32(EMAC_WKUP_FFCRC0);
1014	D32(EMAC_WKUP_FFCRC1);
1015	D32(EMAC_WKUP_FFMSK0);
1016	D32(EMAC_WKUP_FFMSK1);
1017	D32(EMAC_WKUP_FFMSK2);
1018	D32(EMAC_WKUP_FFMSK3);
1019	D32(EMAC_WKUP_FFOFF);
1020# ifdef EMAC_PTP_ACCR
1021	D32(EMAC_PTP_ACCR);
1022	D32(EMAC_PTP_ADDEND);
1023	D32(EMAC_PTP_ALARMHI);
1024	D32(EMAC_PTP_ALARMLO);
1025	D16(EMAC_PTP_CTL);
1026	D32(EMAC_PTP_FOFF);
1027	D32(EMAC_PTP_FV1);
1028	D32(EMAC_PTP_FV2);
1029	D32(EMAC_PTP_FV3);
1030	D16(EMAC_PTP_ID_OFF);
1031	D32(EMAC_PTP_ID_SNAP);
1032	D16(EMAC_PTP_IE);
1033	D16(EMAC_PTP_ISTAT);
1034	D32(EMAC_PTP_OFFSET);
1035	D32(EMAC_PTP_PPS_PERIOD);
1036	D32(EMAC_PTP_PPS_STARTHI);
1037	D32(EMAC_PTP_PPS_STARTLO);
1038	D32(EMAC_PTP_RXSNAPHI);
1039	D32(EMAC_PTP_RXSNAPLO);
1040	D32(EMAC_PTP_TIMEHI);
1041	D32(EMAC_PTP_TIMELO);
1042	D32(EMAC_PTP_TXSNAPHI);
1043	D32(EMAC_PTP_TXSNAPLO);
1044# endif
1045#endif
1046
1047#if defined(EPPI0_STATUS) || defined(EPPI1_STATUS) || defined(EPPI2_STATUS)
1048	parent = debugfs_create_dir("eppi", top);
1049# ifdef EPPI0_STATUS
1050	EPPI(0);
1051# endif
1052# ifdef EPPI1_STATUS
1053	EPPI(1);
1054# endif
1055# ifdef EPPI2_STATUS
1056	EPPI(2);
1057# endif
1058#endif
1059
1060	parent = debugfs_create_dir("gptimer", top);
1061#ifdef TIMER_ENABLE
1062	GPTIMER_GROUP(TIMER_ENABLE, -1);
1063#endif
1064#ifdef TIMER_ENABLE0
1065	GPTIMER_GROUP(TIMER_ENABLE0, 0);
1066#endif
1067#ifdef TIMER_ENABLE1
1068	GPTIMER_GROUP(TIMER_ENABLE1, 1);
1069#endif
1070	/* XXX: Should convert BF561 MMR names */
1071#ifdef TMRS4_DISABLE
1072	GPTIMER_GROUP(TMRS4_ENABLE, 0);
1073	GPTIMER_GROUP(TMRS8_ENABLE, 1);
1074#endif
1075	GPTIMER(0);
1076	GPTIMER(1);
1077	GPTIMER(2);
1078#ifdef TIMER3_CONFIG
1079	GPTIMER(3);
1080	GPTIMER(4);
1081	GPTIMER(5);
1082	GPTIMER(6);
1083	GPTIMER(7);
1084#endif
1085#ifdef TIMER8_CONFIG
1086	GPTIMER(8);
1087	GPTIMER(9);
1088	GPTIMER(10);
1089#endif
1090#ifdef TIMER11_CONFIG
1091	GPTIMER(11);
1092#endif
1093
1094#ifdef HMDMA0_CONTROL
1095	parent = debugfs_create_dir("hmdma", top);
1096	HMDMA(0);
1097	HMDMA(1);
1098#endif
1099
1100#ifdef HOST_CONTROL
1101	parent = debugfs_create_dir("hostdp", top);
1102	D16(HOST_CONTROL);
1103	D16(HOST_STATUS);
1104	D16(HOST_TIMEOUT);
1105#endif
1106
1107#ifdef IMDMA_S0_CONFIG
1108	parent = debugfs_create_dir("imdma", top);
1109	IMDMA(0);
1110	IMDMA(1);
1111#endif
1112
1113#ifdef KPAD_CTL
1114	parent = debugfs_create_dir("keypad", top);
1115	D16(KPAD_CTL);
1116	D16(KPAD_PRESCALE);
1117	D16(KPAD_MSEL);
1118	D16(KPAD_ROWCOL);
1119	D16(KPAD_STAT);
1120	D16(KPAD_SOFTEVAL);
1121#endif
1122
1123	parent = debugfs_create_dir("mdma", top);
1124	MDMA(0);
1125	MDMA(1);
1126#ifdef MDMA_D2_CONFIG
1127	MDMA(2);
1128	MDMA(3);
1129#endif
1130
1131#ifdef MXVR_CONFIG
1132	parent = debugfs_create_dir("mxvr", top);
1133	D16(MXVR_CONFIG);
1134# ifdef MXVR_PLL_CTL_0
1135	D32(MXVR_PLL_CTL_0);
1136# endif
1137	D32(MXVR_STATE_0);
1138	D32(MXVR_STATE_1);
1139	D32(MXVR_INT_STAT_0);
1140	D32(MXVR_INT_STAT_1);
1141	D32(MXVR_INT_EN_0);
1142	D32(MXVR_INT_EN_1);
1143	D16(MXVR_POSITION);
1144	D16(MXVR_MAX_POSITION);
1145	D16(MXVR_DELAY);
1146	D16(MXVR_MAX_DELAY);
1147	D32(MXVR_LADDR);
1148	D16(MXVR_GADDR);
1149	D32(MXVR_AADDR);
1150	D32(MXVR_ALLOC_0);
1151	D32(MXVR_ALLOC_1);
1152	D32(MXVR_ALLOC_2);
1153	D32(MXVR_ALLOC_3);
1154	D32(MXVR_ALLOC_4);
1155	D32(MXVR_ALLOC_5);
1156	D32(MXVR_ALLOC_6);
1157	D32(MXVR_ALLOC_7);
1158	D32(MXVR_ALLOC_8);
1159	D32(MXVR_ALLOC_9);
1160	D32(MXVR_ALLOC_10);
1161	D32(MXVR_ALLOC_11);
1162	D32(MXVR_ALLOC_12);
1163	D32(MXVR_ALLOC_13);
1164	D32(MXVR_ALLOC_14);
1165	D32(MXVR_SYNC_LCHAN_0);
1166	D32(MXVR_SYNC_LCHAN_1);
1167	D32(MXVR_SYNC_LCHAN_2);
1168	D32(MXVR_SYNC_LCHAN_3);
1169	D32(MXVR_SYNC_LCHAN_4);
1170	D32(MXVR_SYNC_LCHAN_5);
1171	D32(MXVR_SYNC_LCHAN_6);
1172	D32(MXVR_SYNC_LCHAN_7);
1173	D32(MXVR_DMA0_CONFIG);
1174	D32(MXVR_DMA0_START_ADDR);
1175	D16(MXVR_DMA0_COUNT);
1176	D32(MXVR_DMA0_CURR_ADDR);
1177	D16(MXVR_DMA0_CURR_COUNT);
1178	D32(MXVR_DMA1_CONFIG);
1179	D32(MXVR_DMA1_START_ADDR);
1180	D16(MXVR_DMA1_COUNT);
1181	D32(MXVR_DMA1_CURR_ADDR);
1182	D16(MXVR_DMA1_CURR_COUNT);
1183	D32(MXVR_DMA2_CONFIG);
1184	D32(MXVR_DMA2_START_ADDR);
1185	D16(MXVR_DMA2_COUNT);
1186	D32(MXVR_DMA2_CURR_ADDR);
1187	D16(MXVR_DMA2_CURR_COUNT);
1188	D32(MXVR_DMA3_CONFIG);
1189	D32(MXVR_DMA3_START_ADDR);
1190	D16(MXVR_DMA3_COUNT);
1191	D32(MXVR_DMA3_CURR_ADDR);
1192	D16(MXVR_DMA3_CURR_COUNT);
1193	D32(MXVR_DMA4_CONFIG);
1194	D32(MXVR_DMA4_START_ADDR);
1195	D16(MXVR_DMA4_COUNT);
1196	D32(MXVR_DMA4_CURR_ADDR);
1197	D16(MXVR_DMA4_CURR_COUNT);
1198	D32(MXVR_DMA5_CONFIG);
1199	D32(MXVR_DMA5_START_ADDR);
1200	D16(MXVR_DMA5_COUNT);
1201	D32(MXVR_DMA5_CURR_ADDR);
1202	D16(MXVR_DMA5_CURR_COUNT);
1203	D32(MXVR_DMA6_CONFIG);
1204	D32(MXVR_DMA6_START_ADDR);
1205	D16(MXVR_DMA6_COUNT);
1206	D32(MXVR_DMA6_CURR_ADDR);
1207	D16(MXVR_DMA6_CURR_COUNT);
1208	D32(MXVR_DMA7_CONFIG);
1209	D32(MXVR_DMA7_START_ADDR);
1210	D16(MXVR_DMA7_COUNT);
1211	D32(MXVR_DMA7_CURR_ADDR);
1212	D16(MXVR_DMA7_CURR_COUNT);
1213	D16(MXVR_AP_CTL);
1214	D32(MXVR_APRB_START_ADDR);
1215	D32(MXVR_APRB_CURR_ADDR);
1216	D32(MXVR_APTB_START_ADDR);
1217	D32(MXVR_APTB_CURR_ADDR);
1218	D32(MXVR_CM_CTL);
1219	D32(MXVR_CMRB_START_ADDR);
1220	D32(MXVR_CMRB_CURR_ADDR);
1221	D32(MXVR_CMTB_START_ADDR);
1222	D32(MXVR_CMTB_CURR_ADDR);
1223	D32(MXVR_RRDB_START_ADDR);
1224	D32(MXVR_RRDB_CURR_ADDR);
1225	D32(MXVR_PAT_DATA_0);
1226	D32(MXVR_PAT_EN_0);
1227	D32(MXVR_PAT_DATA_1);
1228	D32(MXVR_PAT_EN_1);
1229	D16(MXVR_FRAME_CNT_0);
1230	D16(MXVR_FRAME_CNT_1);
1231	D32(MXVR_ROUTING_0);
1232	D32(MXVR_ROUTING_1);
1233	D32(MXVR_ROUTING_2);
1234	D32(MXVR_ROUTING_3);
1235	D32(MXVR_ROUTING_4);
1236	D32(MXVR_ROUTING_5);
1237	D32(MXVR_ROUTING_6);
1238	D32(MXVR_ROUTING_7);
1239	D32(MXVR_ROUTING_8);
1240	D32(MXVR_ROUTING_9);
1241	D32(MXVR_ROUTING_10);
1242	D32(MXVR_ROUTING_11);
1243	D32(MXVR_ROUTING_12);
1244	D32(MXVR_ROUTING_13);
1245	D32(MXVR_ROUTING_14);
1246# ifdef MXVR_PLL_CTL_1
1247	D32(MXVR_PLL_CTL_1);
1248# endif
1249	D16(MXVR_BLOCK_CNT);
1250# ifdef MXVR_CLK_CTL
1251	D32(MXVR_CLK_CTL);
1252# endif
1253# ifdef MXVR_CDRPLL_CTL
1254	D32(MXVR_CDRPLL_CTL);
1255# endif
1256# ifdef MXVR_FMPLL_CTL
1257	D32(MXVR_FMPLL_CTL);
1258# endif
1259# ifdef MXVR_PIN_CTL
1260	D16(MXVR_PIN_CTL);
1261# endif
1262# ifdef MXVR_SCLK_CNT
1263	D16(MXVR_SCLK_CNT);
1264# endif
1265#endif
1266
1267#ifdef NFC_ADDR
1268	parent = debugfs_create_dir("nfc", top);
1269	D_WO(NFC_ADDR, 16);
1270	D_WO(NFC_CMD, 16);
1271	D_RO(NFC_COUNT, 16);
1272	D16(NFC_CTL);
1273	D_WO(NFC_DATA_RD, 16);
1274	D_WO(NFC_DATA_WR, 16);
1275	D_RO(NFC_ECC0, 16);
1276	D_RO(NFC_ECC1, 16);
1277	D_RO(NFC_ECC2, 16);
1278	D_RO(NFC_ECC3, 16);
1279	D16(NFC_IRQMASK);
1280	D16(NFC_IRQSTAT);
1281	D_WO(NFC_PGCTL, 16);
1282	D_RO(NFC_READ, 16);
1283	D16(NFC_RST);
1284	D_RO(NFC_STAT, 16);
1285#endif
1286
1287#ifdef OTP_CONTROL
1288	parent = debugfs_create_dir("otp", top);
1289	D16(OTP_CONTROL);
1290	D16(OTP_BEN);
1291	D16(OTP_STATUS);
1292	D32(OTP_TIMING);
1293	D32(OTP_DATA0);
1294	D32(OTP_DATA1);
1295	D32(OTP_DATA2);
1296	D32(OTP_DATA3);
1297#endif
1298
1299#ifdef PINT0_MASK_SET
1300	parent = debugfs_create_dir("pint", top);
1301	PINT(0);
1302	PINT(1);
1303	PINT(2);
1304	PINT(3);
1305#endif
1306
1307#ifdef PIXC_CTL
1308	parent = debugfs_create_dir("pixc", top);
1309	D16(PIXC_CTL);
1310	D16(PIXC_PPL);
1311	D16(PIXC_LPF);
1312	D16(PIXC_AHSTART);
1313	D16(PIXC_AHEND);
1314	D16(PIXC_AVSTART);
1315	D16(PIXC_AVEND);
1316	D16(PIXC_ATRANSP);
1317	D16(PIXC_BHSTART);
1318	D16(PIXC_BHEND);
1319	D16(PIXC_BVSTART);
1320	D16(PIXC_BVEND);
1321	D16(PIXC_BTRANSP);
1322	D16(PIXC_INTRSTAT);
1323	D32(PIXC_RYCON);
1324	D32(PIXC_GUCON);
1325	D32(PIXC_BVCON);
1326	D32(PIXC_CCBIAS);
1327	D32(PIXC_TC);
1328#endif
1329
1330	parent = debugfs_create_dir("pll", top);
1331	D16(PLL_CTL);
1332	D16(PLL_DIV);
1333	D16(PLL_LOCKCNT);
1334	D16(PLL_STAT);
1335	D16(VR_CTL);
1336	D32(CHIPID);	/* it's part of this hardware block */
1337
1338#if defined(PPI_CONTROL) || defined(PPI0_CONTROL) || defined(PPI1_CONTROL)
1339	parent = debugfs_create_dir("ppi", top);
1340# ifdef PPI_CONTROL
1341	bfin_debug_mmrs_ppi(parent, PPI_CONTROL, -1);
1342# endif
1343# ifdef PPI0_CONTROL
1344	PPI(0);
1345# endif
1346# ifdef PPI1_CONTROL
1347	PPI(1);
1348# endif
1349#endif
1350
1351#ifdef PWM_CTRL
1352	parent = debugfs_create_dir("pwm", top);
1353	D16(PWM_CTRL);
1354	D16(PWM_STAT);
1355	D16(PWM_TM);
1356	D16(PWM_DT);
1357	D16(PWM_GATE);
1358	D16(PWM_CHA);
1359	D16(PWM_CHB);
1360	D16(PWM_CHC);
1361	D16(PWM_SEG);
1362	D16(PWM_SYNCWT);
1363	D16(PWM_CHAL);
1364	D16(PWM_CHBL);
1365	D16(PWM_CHCL);
1366	D16(PWM_LSI);
1367	D16(PWM_STAT2);
1368#endif
1369
1370#ifdef RSI_CONFIG
1371	parent = debugfs_create_dir("rsi", top);
1372	D32(RSI_ARGUMENT);
1373	D16(RSI_CEATA_CONTROL);
1374	D16(RSI_CLK_CONTROL);
1375	D16(RSI_COMMAND);
1376	D16(RSI_CONFIG);
1377	D16(RSI_DATA_CNT);
1378	D16(RSI_DATA_CONTROL);
1379	D16(RSI_DATA_LGTH);
1380	D32(RSI_DATA_TIMER);
1381	D16(RSI_EMASK);
1382	D16(RSI_ESTAT);
1383	D32(RSI_FIFO);
1384	D16(RSI_FIFO_CNT);
1385	D32(RSI_MASK0);
1386	D32(RSI_MASK1);
1387	D16(RSI_PID0);
1388	D16(RSI_PID1);
1389	D16(RSI_PID2);
1390	D16(RSI_PID3);
1391	D16(RSI_PID4);
1392	D16(RSI_PID5);
1393	D16(RSI_PID6);
1394	D16(RSI_PID7);
1395	D16(RSI_PWR_CONTROL);
1396	D16(RSI_RD_WAIT_EN);
1397	D32(RSI_RESPONSE0);
1398	D32(RSI_RESPONSE1);
1399	D32(RSI_RESPONSE2);
1400	D32(RSI_RESPONSE3);
1401	D16(RSI_RESP_CMD);
1402	D32(RSI_STATUS);
1403	D_WO(RSI_STATUSCL, 16);
1404#endif
1405
1406#ifdef RTC_ALARM
1407	parent = debugfs_create_dir("rtc", top);
1408	D32(RTC_ALARM);
1409	D16(RTC_ICTL);
1410	D16(RTC_ISTAT);
1411	D16(RTC_PREN);
1412	D32(RTC_STAT);
1413	D16(RTC_SWCNT);
1414#endif
1415
1416#ifdef SDH_CFG
1417	parent = debugfs_create_dir("sdh", top);
1418	D32(SDH_ARGUMENT);
1419	D16(SDH_CFG);
1420	D16(SDH_CLK_CTL);
1421	D16(SDH_COMMAND);
1422	D_RO(SDH_DATA_CNT, 16);
1423	D16(SDH_DATA_CTL);
1424	D16(SDH_DATA_LGTH);
1425	D32(SDH_DATA_TIMER);
1426	D16(SDH_E_MASK);
1427	D16(SDH_E_STATUS);
1428	D32(SDH_FIFO);
1429	D_RO(SDH_FIFO_CNT, 16);
1430	D32(SDH_MASK0);
1431	D32(SDH_MASK1);
1432	D_RO(SDH_PID0, 16);
1433	D_RO(SDH_PID1, 16);
1434	D_RO(SDH_PID2, 16);
1435	D_RO(SDH_PID3, 16);
1436	D_RO(SDH_PID4, 16);
1437	D_RO(SDH_PID5, 16);
1438	D_RO(SDH_PID6, 16);
1439	D_RO(SDH_PID7, 16);
1440	D16(SDH_PWR_CTL);
1441	D16(SDH_RD_WAIT_EN);
1442	D_RO(SDH_RESPONSE0, 32);
1443	D_RO(SDH_RESPONSE1, 32);
1444	D_RO(SDH_RESPONSE2, 32);
1445	D_RO(SDH_RESPONSE3, 32);
1446	D_RO(SDH_RESP_CMD, 16);
1447	D_RO(SDH_STATUS, 32);
1448	D_WO(SDH_STATUS_CLR, 16);
1449#endif
1450
1451#ifdef SECURE_CONTROL
1452	parent = debugfs_create_dir("security", top);
1453	D16(SECURE_CONTROL);
1454	D16(SECURE_STATUS);
1455	D32(SECURE_SYSSWT);
1456#endif
1457
1458	parent = debugfs_create_dir("sic", top);
1459	D16(SWRST);
1460	D16(SYSCR);
1461	D16(SIC_RVECT);
1462	D32(SIC_IAR0);
1463	D32(SIC_IAR1);
1464	D32(SIC_IAR2);
1465#ifdef SIC_IAR3
1466	D32(SIC_IAR3);
1467#endif
1468#ifdef SIC_IAR4
1469	D32(SIC_IAR4);
1470	D32(SIC_IAR5);
1471	D32(SIC_IAR6);
1472#endif
1473#ifdef SIC_IAR7
1474	D32(SIC_IAR7);
1475#endif
1476#ifdef SIC_IAR8
1477	D32(SIC_IAR8);
1478	D32(SIC_IAR9);
1479	D32(SIC_IAR10);
1480	D32(SIC_IAR11);
1481#endif
1482#ifdef SIC_IMASK
1483	D32(SIC_IMASK);
1484	D32(SIC_ISR);
1485	D32(SIC_IWR);
1486#endif
1487#ifdef SIC_IMASK0
1488	D32(SIC_IMASK0);
1489	D32(SIC_IMASK1);
1490	D32(SIC_ISR0);
1491	D32(SIC_ISR1);
1492	D32(SIC_IWR0);
1493	D32(SIC_IWR1);
1494#endif
1495#ifdef SIC_IMASK2
1496	D32(SIC_IMASK2);
1497	D32(SIC_ISR2);
1498	D32(SIC_IWR2);
1499#endif
1500#ifdef SICB_RVECT
1501	D16(SICB_SWRST);
1502	D16(SICB_SYSCR);
1503	D16(SICB_RVECT);
1504	D32(SICB_IAR0);
1505	D32(SICB_IAR1);
1506	D32(SICB_IAR2);
1507	D32(SICB_IAR3);
1508	D32(SICB_IAR4);
1509	D32(SICB_IAR5);
1510	D32(SICB_IAR6);
1511	D32(SICB_IAR7);
1512	D32(SICB_IMASK0);
1513	D32(SICB_IMASK1);
1514	D32(SICB_ISR0);
1515	D32(SICB_ISR1);
1516	D32(SICB_IWR0);
1517	D32(SICB_IWR1);
1518#endif
1519
1520	parent = debugfs_create_dir("spi", top);
1521#ifdef SPI0_REGBASE
1522	SPI(0);
1523#endif
1524#ifdef SPI1_REGBASE
1525	SPI(1);
1526#endif
1527#ifdef SPI2_REGBASE
1528	SPI(2);
1529#endif
1530
1531	parent = debugfs_create_dir("sport", top);
1532#ifdef SPORT0_STAT
1533	SPORT(0);
1534#endif
1535#ifdef SPORT1_STAT
1536	SPORT(1);
1537#endif
1538#ifdef SPORT2_STAT
1539	SPORT(2);
1540#endif
1541#ifdef SPORT3_STAT
1542	SPORT(3);
1543#endif
1544
1545#if defined(TWI_CLKDIV) || defined(TWI0_CLKDIV) || defined(TWI1_CLKDIV)
1546	parent = debugfs_create_dir("twi", top);
1547# ifdef TWI_CLKDIV
1548	bfin_debug_mmrs_twi(parent, TWI_CLKDIV, -1);
1549# endif
1550# ifdef TWI0_CLKDIV
1551	TWI(0);
1552# endif
1553# ifdef TWI1_CLKDIV
1554	TWI(1);
1555# endif
1556#endif
1557
1558	parent = debugfs_create_dir("uart", top);
1559#ifdef BFIN_UART_DLL
1560	bfin_debug_mmrs_uart(parent, BFIN_UART_DLL, -1);
1561#endif
1562#ifdef UART0_DLL
1563	UART(0);
1564#endif
1565#ifdef UART1_DLL
1566	UART(1);
1567#endif
1568#ifdef UART2_DLL
1569	UART(2);
1570#endif
1571#ifdef UART3_DLL
1572	UART(3);
1573#endif
1574
1575#ifdef USB_FADDR
1576	parent = debugfs_create_dir("usb", top);
1577	D16(USB_FADDR);
1578	D16(USB_POWER);
1579	D16(USB_INTRTX);
1580	D16(USB_INTRRX);
1581	D16(USB_INTRTXE);
1582	D16(USB_INTRRXE);
1583	D16(USB_INTRUSB);
1584	D16(USB_INTRUSBE);
1585	D16(USB_FRAME);
1586	D16(USB_INDEX);
1587	D16(USB_TESTMODE);
1588	D16(USB_GLOBINTR);
1589	D16(USB_GLOBAL_CTL);
1590	D16(USB_TX_MAX_PACKET);
1591	D16(USB_CSR0);
1592	D16(USB_TXCSR);
1593	D16(USB_RX_MAX_PACKET);
1594	D16(USB_RXCSR);
1595	D16(USB_COUNT0);
1596	D16(USB_RXCOUNT);
1597	D16(USB_TXTYPE);
1598	D16(USB_NAKLIMIT0);
1599	D16(USB_TXINTERVAL);
1600	D16(USB_RXTYPE);
1601	D16(USB_RXINTERVAL);
1602	D16(USB_TXCOUNT);
1603	D16(USB_EP0_FIFO);
1604	D16(USB_EP1_FIFO);
1605	D16(USB_EP2_FIFO);
1606	D16(USB_EP3_FIFO);
1607	D16(USB_EP4_FIFO);
1608	D16(USB_EP5_FIFO);
1609	D16(USB_EP6_FIFO);
1610	D16(USB_EP7_FIFO);
1611	D16(USB_OTG_DEV_CTL);
1612	D16(USB_OTG_VBUS_IRQ);
1613	D16(USB_OTG_VBUS_MASK);
1614	D16(USB_LINKINFO);
1615	D16(USB_VPLEN);
1616	D16(USB_HS_EOF1);
1617	D16(USB_FS_EOF1);
1618	D16(USB_LS_EOF1);
1619	D16(USB_APHY_CNTRL);
1620	D16(USB_APHY_CALIB);
1621	D16(USB_APHY_CNTRL2);
1622	D16(USB_PHY_TEST);
1623	D16(USB_PLLOSC_CTRL);
1624	D16(USB_SRP_CLKDIV);
1625	D16(USB_EP_NI0_TXMAXP);
1626	D16(USB_EP_NI0_TXCSR);
1627	D16(USB_EP_NI0_RXMAXP);
1628	D16(USB_EP_NI0_RXCSR);
1629	D16(USB_EP_NI0_RXCOUNT);
1630	D16(USB_EP_NI0_TXTYPE);
1631	D16(USB_EP_NI0_TXINTERVAL);
1632	D16(USB_EP_NI0_RXTYPE);
1633	D16(USB_EP_NI0_RXINTERVAL);
1634	D16(USB_EP_NI0_TXCOUNT);
1635	D16(USB_EP_NI1_TXMAXP);
1636	D16(USB_EP_NI1_TXCSR);
1637	D16(USB_EP_NI1_RXMAXP);
1638	D16(USB_EP_NI1_RXCSR);
1639	D16(USB_EP_NI1_RXCOUNT);
1640	D16(USB_EP_NI1_TXTYPE);
1641	D16(USB_EP_NI1_TXINTERVAL);
1642	D16(USB_EP_NI1_RXTYPE);
1643	D16(USB_EP_NI1_RXINTERVAL);
1644	D16(USB_EP_NI1_TXCOUNT);
1645	D16(USB_EP_NI2_TXMAXP);
1646	D16(USB_EP_NI2_TXCSR);
1647	D16(USB_EP_NI2_RXMAXP);
1648	D16(USB_EP_NI2_RXCSR);
1649	D16(USB_EP_NI2_RXCOUNT);
1650	D16(USB_EP_NI2_TXTYPE);
1651	D16(USB_EP_NI2_TXINTERVAL);
1652	D16(USB_EP_NI2_RXTYPE);
1653	D16(USB_EP_NI2_RXINTERVAL);
1654	D16(USB_EP_NI2_TXCOUNT);
1655	D16(USB_EP_NI3_TXMAXP);
1656	D16(USB_EP_NI3_TXCSR);
1657	D16(USB_EP_NI3_RXMAXP);
1658	D16(USB_EP_NI3_RXCSR);
1659	D16(USB_EP_NI3_RXCOUNT);
1660	D16(USB_EP_NI3_TXTYPE);
1661	D16(USB_EP_NI3_TXINTERVAL);
1662	D16(USB_EP_NI3_RXTYPE);
1663	D16(USB_EP_NI3_RXINTERVAL);
1664	D16(USB_EP_NI3_TXCOUNT);
1665	D16(USB_EP_NI4_TXMAXP);
1666	D16(USB_EP_NI4_TXCSR);
1667	D16(USB_EP_NI4_RXMAXP);
1668	D16(USB_EP_NI4_RXCSR);
1669	D16(USB_EP_NI4_RXCOUNT);
1670	D16(USB_EP_NI4_TXTYPE);
1671	D16(USB_EP_NI4_TXINTERVAL);
1672	D16(USB_EP_NI4_RXTYPE);
1673	D16(USB_EP_NI4_RXINTERVAL);
1674	D16(USB_EP_NI4_TXCOUNT);
1675	D16(USB_EP_NI5_TXMAXP);
1676	D16(USB_EP_NI5_TXCSR);
1677	D16(USB_EP_NI5_RXMAXP);
1678	D16(USB_EP_NI5_RXCSR);
1679	D16(USB_EP_NI5_RXCOUNT);
1680	D16(USB_EP_NI5_TXTYPE);
1681	D16(USB_EP_NI5_TXINTERVAL);
1682	D16(USB_EP_NI5_RXTYPE);
1683	D16(USB_EP_NI5_RXINTERVAL);
1684	D16(USB_EP_NI5_TXCOUNT);
1685	D16(USB_EP_NI6_TXMAXP);
1686	D16(USB_EP_NI6_TXCSR);
1687	D16(USB_EP_NI6_RXMAXP);
1688	D16(USB_EP_NI6_RXCSR);
1689	D16(USB_EP_NI6_RXCOUNT);
1690	D16(USB_EP_NI6_TXTYPE);
1691	D16(USB_EP_NI6_TXINTERVAL);
1692	D16(USB_EP_NI6_RXTYPE);
1693	D16(USB_EP_NI6_RXINTERVAL);
1694	D16(USB_EP_NI6_TXCOUNT);
1695	D16(USB_EP_NI7_TXMAXP);
1696	D16(USB_EP_NI7_TXCSR);
1697	D16(USB_EP_NI7_RXMAXP);
1698	D16(USB_EP_NI7_RXCSR);
1699	D16(USB_EP_NI7_RXCOUNT);
1700	D16(USB_EP_NI7_TXTYPE);
1701	D16(USB_EP_NI7_TXINTERVAL);
1702	D16(USB_EP_NI7_RXTYPE);
1703	D16(USB_EP_NI7_RXINTERVAL);
1704	D16(USB_EP_NI7_TXCOUNT);
1705	D16(USB_DMA_INTERRUPT);
1706	D16(USB_DMA0CONTROL);
1707	D16(USB_DMA0ADDRLOW);
1708	D16(USB_DMA0ADDRHIGH);
1709	D16(USB_DMA0COUNTLOW);
1710	D16(USB_DMA0COUNTHIGH);
1711	D16(USB_DMA1CONTROL);
1712	D16(USB_DMA1ADDRLOW);
1713	D16(USB_DMA1ADDRHIGH);
1714	D16(USB_DMA1COUNTLOW);
1715	D16(USB_DMA1COUNTHIGH);
1716	D16(USB_DMA2CONTROL);
1717	D16(USB_DMA2ADDRLOW);
1718	D16(USB_DMA2ADDRHIGH);
1719	D16(USB_DMA2COUNTLOW);
1720	D16(USB_DMA2COUNTHIGH);
1721	D16(USB_DMA3CONTROL);
1722	D16(USB_DMA3ADDRLOW);
1723	D16(USB_DMA3ADDRHIGH);
1724	D16(USB_DMA3COUNTLOW);
1725	D16(USB_DMA3COUNTHIGH);
1726	D16(USB_DMA4CONTROL);
1727	D16(USB_DMA4ADDRLOW);
1728	D16(USB_DMA4ADDRHIGH);
1729	D16(USB_DMA4COUNTLOW);
1730	D16(USB_DMA4COUNTHIGH);
1731	D16(USB_DMA5CONTROL);
1732	D16(USB_DMA5ADDRLOW);
1733	D16(USB_DMA5ADDRHIGH);
1734	D16(USB_DMA5COUNTLOW);
1735	D16(USB_DMA5COUNTHIGH);
1736	D16(USB_DMA6CONTROL);
1737	D16(USB_DMA6ADDRLOW);
1738	D16(USB_DMA6ADDRHIGH);
1739	D16(USB_DMA6COUNTLOW);
1740	D16(USB_DMA6COUNTHIGH);
1741	D16(USB_DMA7CONTROL);
1742	D16(USB_DMA7ADDRLOW);
1743	D16(USB_DMA7ADDRHIGH);
1744	D16(USB_DMA7COUNTLOW);
1745	D16(USB_DMA7COUNTHIGH);
1746#endif
1747
1748#ifdef WDOG_CNT
1749	parent = debugfs_create_dir("watchdog", top);
1750	D32(WDOG_CNT);
1751	D16(WDOG_CTL);
1752	D32(WDOG_STAT);
1753#endif
1754#ifdef WDOGA_CNT
1755	parent = debugfs_create_dir("watchdog", top);
1756	D32(WDOGA_CNT);
1757	D16(WDOGA_CTL);
1758	D32(WDOGA_STAT);
1759	D32(WDOGB_CNT);
1760	D16(WDOGB_CTL);
1761	D32(WDOGB_STAT);
1762#endif
1763
1764	/* BF533 glue */
1765#ifdef FIO_FLAG_D
1766#define PORTFIO FIO_FLAG_D
1767#endif
1768	/* BF561 glue */
1769#ifdef FIO0_FLAG_D
1770#define PORTFIO FIO0_FLAG_D
1771#endif
1772#ifdef FIO1_FLAG_D
1773#define PORTGIO FIO1_FLAG_D
1774#endif
1775#ifdef FIO2_FLAG_D
1776#define PORTHIO FIO2_FLAG_D
1777#endif
1778	parent = debugfs_create_dir("port", top);
1779#ifdef PORTFIO
1780	PORT(PORTFIO, 'F');
1781#endif
1782#ifdef PORTGIO
1783	PORT(PORTGIO, 'G');
1784#endif
1785#ifdef PORTHIO
1786	PORT(PORTHIO, 'H');
1787#endif
1788
1789#ifdef __ADSPBF51x__
1790	D16(PORTF_FER);
1791	D16(PORTF_DRIVE);
1792	D16(PORTF_HYSTERESIS);
1793	D16(PORTF_MUX);
1794
1795	D16(PORTG_FER);
1796	D16(PORTG_DRIVE);
1797	D16(PORTG_HYSTERESIS);
1798	D16(PORTG_MUX);
1799
1800	D16(PORTH_FER);
1801	D16(PORTH_DRIVE);
1802	D16(PORTH_HYSTERESIS);
1803	D16(PORTH_MUX);
1804
1805	D16(MISCPORT_DRIVE);
1806	D16(MISCPORT_HYSTERESIS);
1807#endif	/* BF51x */
1808
1809#ifdef __ADSPBF52x__
1810	D16(PORTF_FER);
1811	D16(PORTF_DRIVE);
1812	D16(PORTF_HYSTERESIS);
1813	D16(PORTF_MUX);
1814	D16(PORTF_SLEW);
1815
1816	D16(PORTG_FER);
1817	D16(PORTG_DRIVE);
1818	D16(PORTG_HYSTERESIS);
1819	D16(PORTG_MUX);
1820	D16(PORTG_SLEW);
1821
1822	D16(PORTH_FER);
1823	D16(PORTH_DRIVE);
1824	D16(PORTH_HYSTERESIS);
1825	D16(PORTH_MUX);
1826	D16(PORTH_SLEW);
1827
1828	D16(MISCPORT_DRIVE);
1829	D16(MISCPORT_HYSTERESIS);
1830	D16(MISCPORT_SLEW);
1831#endif	/* BF52x */
1832
1833#ifdef BF537_FAMILY
1834	D16(PORTF_FER);
1835	D16(PORTG_FER);
1836	D16(PORTH_FER);
1837	D16(PORT_MUX);
1838#endif	/* BF534 BF536 BF537 */
1839
1840#ifdef BF538_FAMILY
1841	D16(PORTCIO_FER);
1842	D16(PORTCIO);
1843	D16(PORTCIO_CLEAR);
1844	D16(PORTCIO_SET);
1845	D16(PORTCIO_TOGGLE);
1846	D16(PORTCIO_DIR);
1847	D16(PORTCIO_INEN);
1848
1849	D16(PORTDIO);
1850	D16(PORTDIO_CLEAR);
1851	D16(PORTDIO_DIR);
1852	D16(PORTDIO_FER);
1853	D16(PORTDIO_INEN);
1854	D16(PORTDIO_SET);
1855	D16(PORTDIO_TOGGLE);
1856
1857	D16(PORTEIO);
1858	D16(PORTEIO_CLEAR);
1859	D16(PORTEIO_DIR);
1860	D16(PORTEIO_FER);
1861	D16(PORTEIO_INEN);
1862	D16(PORTEIO_SET);
1863	D16(PORTEIO_TOGGLE);
1864#endif	/* BF538 BF539 */
1865
1866#ifdef __ADSPBF54x__
1867	{
1868		int num;
1869		unsigned long base;
1870
1871		base = PORTA_FER;
1872		for (num = 0; num < 10; ++num) {
1873			PORT(base, num);
1874			base += sizeof(struct bfin_gpio_regs);
1875		}
1876
1877	}
1878#endif	/* BF54x */
1879#endif /* CONFIG_BF60x */
1880	debug_mmrs_dentry = top;
1881
1882	return 0;
1883}
1884module_init(bfin_debug_mmrs_init);
1885
1886static void __exit bfin_debug_mmrs_exit(void)
1887{
1888	debugfs_remove_recursive(debug_mmrs_dentry);
1889}
1890module_exit(bfin_debug_mmrs_exit);
1891
1892MODULE_LICENSE("GPL");