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1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License terms: GNU General Public License (GPL) version 2
5 */
6
7#include <linux/kernel.h>
8#include <linux/init.h>
9#include <linux/bug.h>
10#include <linux/string.h>
11#include <linux/pinctrl/machine.h>
12
13#include <asm/mach-types.h>
14#include <plat/pincfg.h>
15#include <plat/gpio-nomadik.h>
16
17#include <mach/hardware.h>
18
19#include "pins-db8500.h"
20#include "board-mop500.h"
21
22enum custom_pin_cfg_t {
23 PINS_FOR_DEFAULT,
24 PINS_FOR_U9500,
25};
26
27static enum custom_pin_cfg_t pinsfor;
28
29/* These simply sets bias for pins */
30#define BIAS(a,b) static unsigned long a[] = { b }
31
32BIAS(pd, PIN_PULL_DOWN);
33BIAS(slpm_gpio_nopull, PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
34BIAS(in_nopull, PIN_INPUT_NOPULL);
35BIAS(in_nopull_sleep_nowkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_DISABLE);
36BIAS(in_pu, PIN_INPUT_PULLUP);
37BIAS(in_pd, PIN_INPUT_PULLDOWN);
38BIAS(in_pd_slpm_in_pu, PIN_INPUT_PULLDOWN|PIN_SLPM_INPUT_PULLUP);
39BIAS(in_pu_slpm_out_lo, PIN_INPUT_PULLUP|PIN_SLPM_OUTPUT_LOW);
40BIAS(out_hi, PIN_OUTPUT_HIGH);
41BIAS(out_lo, PIN_OUTPUT_LOW);
42BIAS(out_lo_sleep_nowkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE);
43/* These also force them into GPIO mode */
44BIAS(gpio_in_pu, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED);
45BIAS(gpio_in_pd, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED);
46BIAS(gpio_in_pu_slpm_gpio_nopull, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
47BIAS(gpio_in_pd_slpm_gpio_nopull, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
48BIAS(gpio_out_hi, PIN_OUTPUT_HIGH|PIN_GPIOMODE_ENABLED);
49BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED);
50/* Sleep modes */
51BIAS(sleep_in_wkup_pdis, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
52BIAS(sleep_in_nopull_wkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_ENABLE);
53BIAS(sleep_out_hi_wkup_pdis, PIN_SLPM_OUTPUT_HIGH|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
54BIAS(sleep_out_lo_wkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE);
55BIAS(sleep_out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
56
57/* We use these to define hog settings that are always done on boot */
58#define DB8500_MUX_HOG(group,func) \
59 PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-db8500", group, func)
60#define DB8500_PIN_HOG(pin,conf) \
61 PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-db8500", pin, conf)
62
63/* These are default states associated with device and changed runtime */
64#define DB8500_MUX(group,func,dev) \
65 PIN_MAP_MUX_GROUP_DEFAULT(dev, "pinctrl-db8500", group, func)
66#define DB8500_PIN(pin,conf,dev) \
67 PIN_MAP_CONFIGS_PIN_DEFAULT(dev, "pinctrl-db8500", pin, conf)
68
69#define DB8500_PIN_SLEEP(pin,conf,dev) \
70 PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
71 pin, conf)
72
73/* Pin control settings */
74static struct pinctrl_map __initdata mop500_family_pinmap[] = {
75 /*
76 * uMSP0, mux in 4 pins, regular placement of RX/TX
77 * explicitly set the pins to no pull
78 */
79 DB8500_MUX_HOG("msp0txrx_a_1", "msp0"),
80 DB8500_MUX_HOG("msp0tfstck_a_1", "msp0"),
81 DB8500_PIN_HOG("GPIO12_AC4", in_nopull), /* TXD */
82 DB8500_PIN_HOG("GPIO15_AC3", in_nopull), /* RXD */
83 DB8500_PIN_HOG("GPIO13_AF3", in_nopull), /* TFS */
84 DB8500_PIN_HOG("GPIO14_AE3", in_nopull), /* TCK */
85 /* MSP2 for HDMI, pull down TXD, TCK, TFS */
86 DB8500_MUX_HOG("msp2_a_1", "msp2"),
87 DB8500_PIN_HOG("GPIO193_AH27", in_pd), /* TXD */
88 DB8500_PIN_HOG("GPIO194_AF27", in_pd), /* TCK */
89 DB8500_PIN_HOG("GPIO195_AG28", in_pd), /* TFS */
90 DB8500_PIN_HOG("GPIO196_AG26", out_lo), /* RXD */
91 /*
92 * LCD, set TE0 (using LCD VSI0) and D14 (touch screen interrupt) to
93 * pull-up
94 * TODO: is this really correct? Snowball doesn't have a LCD.
95 */
96 DB8500_MUX_HOG("lcdvsi0_a_1", "lcd"),
97 DB8500_PIN_HOG("GPIO68_E1", in_pu),
98 DB8500_PIN_HOG("GPIO84_C2", gpio_in_pu),
99 /*
100 * STMPE1601/tc35893 keypad IRQ GPIO 218
101 * TODO: set for snowball and HREF really??
102 */
103 DB8500_PIN_HOG("GPIO218_AH11", gpio_in_pu),
104 /*
105 * UART0, we do not mux in u0 here.
106 * uart-0 pins gpio configuration should be kept intact to prevent
107 * a glitch in tx line when the tty dev is opened. Later these pins
108 * are configured to uart mop500_pins_uart0
109 */
110 DB8500_PIN_HOG("GPIO0_AJ5", in_pu), /* CTS */
111 DB8500_PIN_HOG("GPIO1_AJ3", out_hi), /* RTS */
112 DB8500_PIN_HOG("GPIO2_AH4", in_pu), /* RXD */
113 DB8500_PIN_HOG("GPIO3_AH3", out_hi), /* TXD */
114 /*
115 * Mux in UART2 on altfunction C and set pull-ups.
116 * TODO: is this used on U8500 variants and Snowball really?
117 * The setting on GPIO31 conflicts with magnetometer use on hrefv60
118 */
119 DB8500_MUX_HOG("u2rxtx_c_1", "u2"),
120 DB8500_MUX_HOG("u2ctsrts_c_1", "u2"),
121 DB8500_PIN_HOG("GPIO29_W2", in_pu), /* RXD */
122 DB8500_PIN_HOG("GPIO30_W3", out_hi), /* TXD */
123 DB8500_PIN_HOG("GPIO31_V3", in_pu), /* CTS */
124 DB8500_PIN_HOG("GPIO32_V2", out_hi), /* RTS */
125 /*
126 * The following pin sets were known as "runtime pins" before being
127 * converted to the pinctrl model. Here we model them as "default"
128 * states.
129 */
130 /* Mux in UART0 after initialization */
131 DB8500_MUX("u0_a_1", "u0", "uart0"),
132 DB8500_PIN("GPIO0_AJ5", in_pu, "uart0"), /* CTS */
133 DB8500_PIN("GPIO1_AJ3", out_hi, "uart0"), /* RTS */
134 DB8500_PIN("GPIO2_AH4", in_pu, "uart0"), /* RXD */
135 DB8500_PIN("GPIO3_AH3", out_hi, "uart0"), /* TXD */
136 /* UART0 sleep state */
137 DB8500_PIN_SLEEP("GPIO0_AJ5", sleep_in_wkup_pdis, "uart0"),
138 DB8500_PIN_SLEEP("GPIO1_AJ3", sleep_out_hi_wkup_pdis, "uart0"),
139 DB8500_PIN_SLEEP("GPIO2_AH4", sleep_in_wkup_pdis, "uart0"),
140 DB8500_PIN_SLEEP("GPIO3_AH3", sleep_out_wkup_pdis, "uart0"),
141 /* MSP1 for ALSA codec */
142 DB8500_MUX("msp1txrx_a_1", "msp1", "ux500-msp-i2s.1"),
143 DB8500_MUX("msp1_a_1", "msp1", "ux500-msp-i2s.1"),
144 DB8500_PIN("GPIO33_AF2", out_lo_sleep_nowkup, "ux500-msp-i2s.1"),
145 DB8500_PIN("GPIO34_AE1", in_nopull_sleep_nowkup, "ux500-msp-i2s.1"),
146 DB8500_PIN("GPIO35_AE2", in_nopull_sleep_nowkup, "ux500-msp-i2s.1"),
147 DB8500_PIN("GPIO36_AG2", in_nopull_sleep_nowkup, "ux500-msp-i2s.1"),
148 /* MSP1 sleep state */
149 DB8500_PIN_SLEEP("GPIO33_AF2", sleep_out_lo_wkup, "ux500-msp-i2s.1"),
150 DB8500_PIN_SLEEP("GPIO34_AE1", sleep_in_nopull_wkup, "ux500-msp-i2s.1"),
151 DB8500_PIN_SLEEP("GPIO35_AE2", sleep_in_nopull_wkup, "ux500-msp-i2s.1"),
152 DB8500_PIN_SLEEP("GPIO36_AG2", sleep_in_nopull_wkup, "ux500-msp-i2s.1"),
153 /* Mux in LCD data lines 8 thru 11 and LCDA CLK for MCDE TVOUT */
154 DB8500_MUX("lcd_d8_d11_a_1", "lcd", "mcde-tvout"),
155 DB8500_MUX("lcdaclk_b_1", "lcda", "mcde-tvout"),
156 /* Mux in LCD VSI1 and pull it up for MCDE HDMI output */
157 DB8500_MUX("lcdvsi1_a_1", "lcd", "av8100-hdmi"),
158 /* Mux in I2C blocks, put pins into GPIO in sleepmode no pull-up */
159 DB8500_MUX("i2c0_a_1", "i2c0", "nmk-i2c.0"),
160 DB8500_PIN("GPIO147_C15", slpm_gpio_nopull, "nmk-i2c.0"),
161 DB8500_PIN("GPIO148_B16", slpm_gpio_nopull, "nmk-i2c.0"),
162 DB8500_MUX("i2c1_b_2", "i2c1", "nmk-i2c.1"),
163 DB8500_PIN("GPIO16_AD3", slpm_gpio_nopull, "nmk-i2c.1"),
164 DB8500_PIN("GPIO17_AD4", slpm_gpio_nopull, "nmk-i2c.1"),
165 DB8500_MUX("i2c2_b_2", "i2c2", "nmk-i2c.2"),
166 DB8500_PIN("GPIO10_AF5", slpm_gpio_nopull, "nmk-i2c.2"),
167 DB8500_PIN("GPIO11_AG4", slpm_gpio_nopull, "nmk-i2c.2"),
168 DB8500_MUX("i2c3_c_2", "i2c3", "nmk-i2c.3"),
169 DB8500_PIN("GPIO229_AG7", slpm_gpio_nopull, "nmk-i2c.3"),
170 DB8500_PIN("GPIO230_AF7", slpm_gpio_nopull, "nmk-i2c.3"),
171 /* Mux in SDI0 (here called MC0) used for removable MMC/SD/SDIO cards */
172 DB8500_MUX("mc0_a_1", "mc0", "sdi0"),
173 DB8500_PIN("GPIO18_AC2", out_hi, "sdi0"), /* CMDDIR */
174 DB8500_PIN("GPIO19_AC1", out_hi, "sdi0"), /* DAT0DIR */
175 DB8500_PIN("GPIO20_AB4", out_hi, "sdi0"), /* DAT2DIR */
176 DB8500_PIN("GPIO22_AA3", in_nopull, "sdi0"), /* FBCLK */
177 DB8500_PIN("GPIO23_AA4", out_lo, "sdi0"), /* CLK */
178 DB8500_PIN("GPIO24_AB2", in_pu, "sdi0"), /* CMD */
179 DB8500_PIN("GPIO25_Y4", in_pu, "sdi0"), /* DAT0 */
180 DB8500_PIN("GPIO26_Y2", in_pu, "sdi0"), /* DAT1 */
181 DB8500_PIN("GPIO27_AA2", in_pu, "sdi0"), /* DAT2 */
182 DB8500_PIN("GPIO28_AA1", in_pu, "sdi0"), /* DAT3 */
183 /* Mux in SDI1 (here called MC1) used for SDIO for CW1200 WLAN */
184 DB8500_MUX("mc1_a_1", "mc1", "sdi1"),
185 DB8500_PIN("GPIO208_AH16", out_lo, "sdi1"), /* CLK */
186 DB8500_PIN("GPIO209_AG15", in_nopull, "sdi1"), /* FBCLK */
187 DB8500_PIN("GPIO210_AJ15", in_pu, "sdi1"), /* CMD */
188 DB8500_PIN("GPIO211_AG14", in_pu, "sdi1"), /* DAT0 */
189 DB8500_PIN("GPIO212_AF13", in_pu, "sdi1"), /* DAT1 */
190 DB8500_PIN("GPIO213_AG13", in_pu, "sdi1"), /* DAT2 */
191 DB8500_PIN("GPIO214_AH15", in_pu, "sdi1"), /* DAT3 */
192 /* Mux in SDI2 (here called MC2) used for for PoP eMMC */
193 DB8500_MUX("mc2_a_1", "mc2", "sdi2"),
194 DB8500_PIN("GPIO128_A5", out_lo, "sdi2"), /* CLK */
195 DB8500_PIN("GPIO129_B4", in_pu, "sdi2"), /* CMD */
196 DB8500_PIN("GPIO130_C8", in_nopull, "sdi2"), /* FBCLK */
197 DB8500_PIN("GPIO131_A12", in_pu, "sdi2"), /* DAT0 */
198 DB8500_PIN("GPIO132_C10", in_pu, "sdi2"), /* DAT1 */
199 DB8500_PIN("GPIO133_B10", in_pu, "sdi2"), /* DAT2 */
200 DB8500_PIN("GPIO134_B9", in_pu, "sdi2"), /* DAT3 */
201 DB8500_PIN("GPIO135_A9", in_pu, "sdi2"), /* DAT4 */
202 DB8500_PIN("GPIO136_C7", in_pu, "sdi2"), /* DAT5 */
203 DB8500_PIN("GPIO137_A7", in_pu, "sdi2"), /* DAT6 */
204 DB8500_PIN("GPIO138_C5", in_pu, "sdi2"), /* DAT7 */
205 /* Mux in SDI4 (here called MC4) used for for PCB-mounted eMMC */
206 DB8500_MUX("mc4_a_1", "mc4", "sdi4"),
207 DB8500_PIN("GPIO197_AH24", in_pu, "sdi4"), /* DAT3 */
208 DB8500_PIN("GPIO198_AG25", in_pu, "sdi4"), /* DAT2 */
209 DB8500_PIN("GPIO199_AH23", in_pu, "sdi4"), /* DAT1 */
210 DB8500_PIN("GPIO200_AH26", in_pu, "sdi4"), /* DAT0 */
211 DB8500_PIN("GPIO201_AF24", in_pu, "sdi4"), /* CMD */
212 DB8500_PIN("GPIO202_AF25", in_nopull, "sdi4"), /* FBCLK */
213 DB8500_PIN("GPIO203_AE23", out_lo, "sdi4"), /* CLK */
214 DB8500_PIN("GPIO204_AF23", in_pu, "sdi4"), /* DAT7 */
215 DB8500_PIN("GPIO205_AG23", in_pu, "sdi4"), /* DAT6 */
216 DB8500_PIN("GPIO206_AG24", in_pu, "sdi4"), /* DAT5 */
217 DB8500_PIN("GPIO207_AJ23", in_pu, "sdi4"), /* DAT4 */
218 /* Mux in USB pins, drive STP high */
219 DB8500_MUX("usb_a_1", "usb", "musb-ux500.0"),
220 DB8500_PIN("GPIO257_AE29", out_hi, "musb-ux500.0"), /* STP */
221 /* Mux in SPI2 pins on the "other C1" altfunction */
222 DB8500_MUX("spi2_oc1_1", "spi2", "spi2"),
223 DB8500_PIN("GPIO216_AG12", gpio_out_hi, "spi2"), /* FRM */
224 DB8500_PIN("GPIO218_AH11", in_pd, "spi2"), /* RXD */
225 DB8500_PIN("GPIO215_AH13", out_lo, "spi2"), /* TXD */
226 DB8500_PIN("GPIO217_AH12", out_lo, "spi2"), /* CLK */
227};
228
229/*
230 * These are specifically for the MOP500 and HREFP (pre-v60) version of the
231 * board, which utilized a TC35892 GPIO expander instead of using a lot of
232 * on-chip pins as the HREFv60 and later does.
233 */
234static struct pinctrl_map __initdata mop500_pinmap[] = {
235 /* Mux in SSP0, pull down RXD pin */
236 DB8500_MUX_HOG("ssp0_a_1", "ssp0"),
237 DB8500_PIN_HOG("GPIO145_C13", pd),
238 /*
239 * XENON Flashgun on image processor GPIO (controlled from image
240 * processor firmware), mux in these image processor GPIO lines 0
241 * (XENON_FLASH_ID) and 1 (XENON_READY) on altfunction C and pull up
242 * the pins.
243 */
244 DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"),
245 DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"),
246 DB8500_PIN_HOG("GPIO6_AF6", in_pu),
247 DB8500_PIN_HOG("GPIO7_AG5", in_pu),
248 /* TC35892 IRQ, pull up the line, let the driver mux in the pin */
249 DB8500_PIN_HOG("GPIO217_AH12", gpio_in_pu),
250 /* Mux in UART1 and set the pull-ups */
251 DB8500_MUX_HOG("u1rxtx_a_1", "u1"),
252 DB8500_MUX_HOG("u1ctsrts_a_1", "u1"),
253 DB8500_PIN_HOG("GPIO4_AH6", in_pu), /* RXD */
254 DB8500_PIN_HOG("GPIO5_AG6", out_hi), /* TXD */
255 DB8500_PIN_HOG("GPIO6_AF6", in_pu), /* CTS */
256 DB8500_PIN_HOG("GPIO7_AG5", out_hi), /* RTS */
257 /*
258 * Runtime stuff: make it possible to mux in the SKE keypad
259 * and bias the pins
260 */
261 DB8500_MUX("kp_a_2", "kp", "ske"),
262 DB8500_PIN("GPIO153_B17", in_pd_slpm_in_pu, "ske"), /* I7 */
263 DB8500_PIN("GPIO154_C16", in_pd_slpm_in_pu, "ske"), /* I6 */
264 DB8500_PIN("GPIO155_C19", in_pd_slpm_in_pu, "ske"), /* I5 */
265 DB8500_PIN("GPIO156_C17", in_pd_slpm_in_pu, "ske"), /* I4 */
266 DB8500_PIN("GPIO161_D21", in_pd_slpm_in_pu, "ske"), /* I3 */
267 DB8500_PIN("GPIO162_D20", in_pd_slpm_in_pu, "ske"), /* I2 */
268 DB8500_PIN("GPIO163_C20", in_pd_slpm_in_pu, "ske"), /* I1 */
269 DB8500_PIN("GPIO164_B21", in_pd_slpm_in_pu, "ske"), /* I0 */
270 DB8500_PIN("GPIO157_A18", in_pu_slpm_out_lo, "ske"), /* O7 */
271 DB8500_PIN("GPIO158_C18", in_pu_slpm_out_lo, "ske"), /* O6 */
272 DB8500_PIN("GPIO159_B19", in_pu_slpm_out_lo, "ske"), /* O5 */
273 DB8500_PIN("GPIO160_B20", in_pu_slpm_out_lo, "ske"), /* O4 */
274 DB8500_PIN("GPIO165_C21", in_pu_slpm_out_lo, "ske"), /* O3 */
275 DB8500_PIN("GPIO166_A22", in_pu_slpm_out_lo, "ske"), /* O2 */
276 DB8500_PIN("GPIO167_B24", in_pu_slpm_out_lo, "ske"), /* O1 */
277 DB8500_PIN("GPIO168_C22", in_pu_slpm_out_lo, "ske"), /* O0 */
278 /* Mux in and drive the SDI0 DAT31DIR line high at runtime */
279 DB8500_MUX("mc0dat31dir_a_1", "mc0", "sdi0"),
280 DB8500_PIN("GPIO21_AB3", out_hi, "sdi0"),
281};
282
283/*
284 * The HREFv60 series of platforms is using available pins on the DB8500
285 * insteaf of the Toshiba I2C GPIO expander, reusing some pins like the SSP0
286 * and SSP1 ports (previously connected to the AB8500) as generic GPIO lines.
287 */
288static struct pinctrl_map __initdata hrefv60_pinmap[] = {
289 /* Drive WLAN_ENA low */
290 DB8500_PIN_HOG("GPIO85_D5", gpio_out_lo), /* WLAN_ENA */
291 /*
292 * XENON Flashgun on image processor GPIO (controlled from image
293 * processor firmware), mux in these image processor GPIO lines 0
294 * (XENON_FLASH_ID), 1 (XENON_READY) and there is an assistant
295 * LED on IP GPIO 4 (XENON_EN2) on altfunction C, that need bias
296 * from GPIO21 so pull up 0, 1 and drive 4 and GPIO21 low as output.
297 */
298 DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"),
299 DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"),
300 DB8500_MUX_HOG("ipgpio4_c_1", "ipgpio"),
301 DB8500_PIN_HOG("GPIO6_AF6", in_pu), /* XENON_FLASH_ID */
302 DB8500_PIN_HOG("GPIO7_AG5", in_pu), /* XENON_READY */
303 DB8500_PIN_HOG("GPIO21_AB3", gpio_out_lo), /* XENON_EN1 */
304 DB8500_PIN_HOG("GPIO64_F3", out_lo), /* XENON_EN2 */
305 /* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */
306 DB8500_PIN_HOG("GPIO31_V3", gpio_in_pu), /* EN1 */
307 DB8500_PIN_HOG("GPIO32_V2", gpio_in_pd), /* DRDY */
308 /*
309 * Display Interface 1 uses GPIO 65 for RST (reset).
310 * Display Interface 2 uses GPIO 66 for RST (reset).
311 * Drive DISP1 reset high (not reset), driver DISP2 reset low (reset)
312 */
313 DB8500_PIN_HOG("GPIO65_F1", gpio_out_hi), /* DISP1 NO RST */
314 DB8500_PIN_HOG("GPIO66_G3", gpio_out_lo), /* DISP2 RST */
315 /*
316 * Touch screen uses GPIO 143 for RST1, GPIO 146 for RST2 and
317 * GPIO 67 for interrupts. Pull-up the IRQ line and drive both
318 * reset signals low.
319 */
320 DB8500_PIN_HOG("GPIO143_D12", gpio_out_lo), /* TOUCH_RST1 */
321 DB8500_PIN_HOG("GPIO67_G2", gpio_in_pu), /* TOUCH_INT2 */
322 DB8500_PIN_HOG("GPIO146_D13", gpio_out_lo), /* TOUCH_RST2 */
323 /*
324 * Drive D19-D23 for the ETM PTM trace interface low,
325 * (presumably pins are unconnected therefore grounded here,
326 * the "other alt C1" setting enables these pins)
327 */
328 DB8500_PIN_HOG("GPIO70_G5", gpio_out_lo),
329 DB8500_PIN_HOG("GPIO71_G4", gpio_out_lo),
330 DB8500_PIN_HOG("GPIO72_H4", gpio_out_lo),
331 DB8500_PIN_HOG("GPIO73_H3", gpio_out_lo),
332 DB8500_PIN_HOG("GPIO74_J3", gpio_out_lo),
333 /* NAHJ CTRL on GPIO 76 to low, CTRL_INV on GPIO216 to high */
334 DB8500_PIN_HOG("GPIO76_J2", gpio_out_lo), /* CTRL */
335 DB8500_PIN_HOG("GPIO216_AG12", gpio_out_hi), /* CTRL_INV */
336 /* NFC ENA and RESET to low, pulldown IRQ line */
337 DB8500_PIN_HOG("GPIO77_H1", gpio_out_lo), /* NFC_ENA */
338 DB8500_PIN_HOG("GPIO144_B13", gpio_in_pd), /* NFC_IRQ */
339 DB8500_PIN_HOG("GPIO142_C11", gpio_out_lo), /* NFC_RESET */
340 /*
341 * SKE keyboard partly on alt A and partly on "Other alt C1"
342 * Driver KP_O1,2,3,6,7 low and pull up KP_I 0,2,3 for three
343 * rows of 6 keys, then pull up force sensing interrup and
344 * drive reset and force sensing WU low.
345 */
346 DB8500_MUX_HOG("kp_a_1", "kp"),
347 DB8500_MUX_HOG("kp_oc1_1", "kp"),
348 DB8500_PIN_HOG("GPIO90_A3", out_lo), /* KP_O1 */
349 DB8500_PIN_HOG("GPIO87_B3", out_lo), /* KP_O2 */
350 DB8500_PIN_HOG("GPIO86_C6", out_lo), /* KP_O3 */
351 DB8500_PIN_HOG("GPIO96_D8", out_lo), /* KP_O6 */
352 DB8500_PIN_HOG("GPIO94_D7", out_lo), /* KP_O7 */
353 DB8500_PIN_HOG("GPIO93_B7", in_pu), /* KP_I0 */
354 DB8500_PIN_HOG("GPIO89_E6", in_pu), /* KP_I2 */
355 DB8500_PIN_HOG("GPIO88_C4", in_pu), /* KP_I3 */
356 DB8500_PIN_HOG("GPIO91_B6", gpio_in_pu), /* FORCE_SENSING_INT */
357 DB8500_PIN_HOG("GPIO92_D6", gpio_out_lo), /* FORCE_SENSING_RST */
358 DB8500_PIN_HOG("GPIO97_D9", gpio_out_lo), /* FORCE_SENSING_WU */
359 /* DiPro Sensor interrupt */
360 DB8500_PIN_HOG("GPIO139_C9", gpio_in_pu), /* DIPRO_INT */
361 /* Audio Amplifier HF enable */
362 DB8500_PIN_HOG("GPIO149_B14", gpio_out_hi), /* VAUDIO_HF_EN, enable MAX8968 */
363 /* GBF interface, pull low to reset state */
364 DB8500_PIN_HOG("GPIO171_D23", gpio_out_lo), /* GBF_ENA_RESET */
365 /* MSP : HDTV INTERFACE GPIO line */
366 DB8500_PIN_HOG("GPIO192_AJ27", gpio_in_pd),
367 /* Accelerometer interrupt lines */
368 DB8500_PIN_HOG("GPIO82_C1", gpio_in_pu), /* ACC_INT1 */
369 DB8500_PIN_HOG("GPIO83_D3", gpio_in_pu), /* ACC_INT2 */
370 /* SD card detect GPIO pin */
371 DB8500_PIN_HOG("GPIO95_E8", gpio_in_pu),
372 /*
373 * Runtime stuff
374 * Pull up/down of some sensor GPIO pins, for proximity, HAL sensor
375 * etc.
376 */
377 DB8500_PIN("GPIO217_AH12", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"),
378 DB8500_PIN("GPIO145_C13", gpio_in_pd_slpm_gpio_nopull, "gpio-keys.0"),
379 DB8500_PIN("GPIO139_C9", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"),
380 /*
381 * Make it possible to mux in the SKE keypad and bias the pins
382 * FIXME: what's the point with this on HREFv60? KP/SKE is already
383 * muxed in at another place! Enabling this will bork.
384 */
385 DB8500_MUX("kp_a_2", "kp", "ske"),
386 DB8500_PIN("GPIO153_B17", in_pd_slpm_in_pu, "ske"), /* I7 */
387 DB8500_PIN("GPIO154_C16", in_pd_slpm_in_pu, "ske"), /* I6 */
388 DB8500_PIN("GPIO155_C19", in_pd_slpm_in_pu, "ske"), /* I5 */
389 DB8500_PIN("GPIO156_C17", in_pd_slpm_in_pu, "ske"), /* I4 */
390 DB8500_PIN("GPIO161_D21", in_pd_slpm_in_pu, "ske"), /* I3 */
391 DB8500_PIN("GPIO162_D20", in_pd_slpm_in_pu, "ske"), /* I2 */
392 DB8500_PIN("GPIO163_C20", in_pd_slpm_in_pu, "ske"), /* I1 */
393 DB8500_PIN("GPIO164_B21", in_pd_slpm_in_pu, "ske"), /* I0 */
394 DB8500_PIN("GPIO157_A18", in_pu_slpm_out_lo, "ske"), /* O7 */
395 DB8500_PIN("GPIO158_C18", in_pu_slpm_out_lo, "ske"), /* O6 */
396 DB8500_PIN("GPIO159_B19", in_pu_slpm_out_lo, "ske"), /* O5 */
397 DB8500_PIN("GPIO160_B20", in_pu_slpm_out_lo, "ske"), /* O4 */
398 DB8500_PIN("GPIO165_C21", in_pu_slpm_out_lo, "ske"), /* O3 */
399 DB8500_PIN("GPIO166_A22", in_pu_slpm_out_lo, "ske"), /* O2 */
400 DB8500_PIN("GPIO167_B24", in_pu_slpm_out_lo, "ske"), /* O1 */
401 DB8500_PIN("GPIO168_C22", in_pu_slpm_out_lo, "ske"), /* O0 */
402};
403
404static struct pinctrl_map __initdata u9500_pinmap[] = {
405 /* Mux in UART1 (just RX/TX) and set the pull-ups */
406 DB8500_MUX_HOG("u1rxtx_a_1", "u1"),
407 DB8500_PIN_HOG("GPIO4_AH6", in_pu),
408 DB8500_PIN_HOG("GPIO5_AG6", out_hi),
409 /* WLAN_IRQ line */
410 DB8500_PIN_HOG("GPIO144_B13", gpio_in_pu),
411 /* HSI */
412 DB8500_MUX_HOG("hsir_a_1", "hsi"),
413 DB8500_MUX_HOG("hsit_a_1", "hsi"),
414 DB8500_PIN_HOG("GPIO219_AG10", in_pd), /* RX FLA0 */
415 DB8500_PIN_HOG("GPIO220_AH10", in_pd), /* RX DAT0 */
416 DB8500_PIN_HOG("GPIO221_AJ11", out_lo), /* RX RDY0 */
417 DB8500_PIN_HOG("GPIO222_AJ9", out_lo), /* TX FLA0 */
418 DB8500_PIN_HOG("GPIO223_AH9", out_lo), /* TX DAT0 */
419 DB8500_PIN_HOG("GPIO224_AG9", in_pd), /* TX RDY0 */
420 DB8500_PIN_HOG("GPIO225_AG8", in_pd), /* CAWAKE0 */
421 DB8500_PIN_HOG("GPIO226_AF8", out_hi), /* ACWAKE0 */
422};
423
424static struct pinctrl_map __initdata u8500_pinmap[] = {
425 DB8500_PIN_HOG("GPIO226_AF8", gpio_out_lo), /* WLAN_PMU_EN */
426 DB8500_PIN_HOG("GPIO4_AH6", gpio_in_pu), /* WLAN_IRQ */
427};
428
429static struct pinctrl_map __initdata snowball_pinmap[] = {
430 /* Mux in SSP0 connected to AB8500, pull down RXD pin */
431 DB8500_MUX_HOG("ssp0_a_1", "ssp0"),
432 DB8500_PIN_HOG("GPIO145_C13", pd),
433 /* Always drive the MC0 DAT31DIR line high on these boards */
434 DB8500_PIN_HOG("GPIO21_AB3", out_hi),
435 /* Mux in "SM" which is used for the SMSC911x Ethernet adapter */
436 DB8500_MUX_HOG("sm_b_1", "sm"),
437 /* Drive RSTn_LAN high */
438 DB8500_PIN_HOG("GPIO141_C12", gpio_out_hi),
439 /* Accelerometer/Magnetometer */
440 DB8500_PIN_HOG("GPIO163_C20", gpio_in_pu), /* ACCEL_IRQ1 */
441 DB8500_PIN_HOG("GPIO164_B21", gpio_in_pu), /* ACCEL_IRQ2 */
442 DB8500_PIN_HOG("GPIO165_C21", gpio_in_pu), /* MAG_DRDY */
443 /* WLAN/GBF */
444 DB8500_PIN_HOG("GPIO161_D21", gpio_out_lo), /* WLAN_PMU_EN */
445 DB8500_PIN_HOG("GPIO171_D23", gpio_out_hi), /* GBF_ENA */
446 DB8500_PIN_HOG("GPIO215_AH13", gpio_out_lo), /* WLAN_ENA */
447 DB8500_PIN_HOG("GPIO216_AG12", gpio_in_pu), /* WLAN_IRQ */
448};
449
450/*
451 * passing "pinsfor=" in kernel cmdline allows for custom
452 * configuration of GPIOs on u8500 derived boards.
453 */
454static int __init early_pinsfor(char *p)
455{
456 pinsfor = PINS_FOR_DEFAULT;
457
458 if (strcmp(p, "u9500-21") == 0)
459 pinsfor = PINS_FOR_U9500;
460
461 return 0;
462}
463early_param("pinsfor", early_pinsfor);
464
465int pins_for_u9500(void)
466{
467 if (pinsfor == PINS_FOR_U9500)
468 return 1;
469
470 return 0;
471}
472
473static void __init mop500_href_family_pinmaps_init(void)
474{
475 switch (pinsfor) {
476 case PINS_FOR_U9500:
477 pinctrl_register_mappings(u9500_pinmap,
478 ARRAY_SIZE(u9500_pinmap));
479 break;
480 case PINS_FOR_DEFAULT:
481 pinctrl_register_mappings(u8500_pinmap,
482 ARRAY_SIZE(u8500_pinmap));
483 default:
484 break;
485 }
486}
487
488void __init mop500_pinmaps_init(void)
489{
490 pinctrl_register_mappings(mop500_family_pinmap,
491 ARRAY_SIZE(mop500_family_pinmap));
492 pinctrl_register_mappings(mop500_pinmap,
493 ARRAY_SIZE(mop500_pinmap));
494 mop500_href_family_pinmaps_init();
495}
496
497void __init snowball_pinmaps_init(void)
498{
499 pinctrl_register_mappings(mop500_family_pinmap,
500 ARRAY_SIZE(mop500_family_pinmap));
501 pinctrl_register_mappings(snowball_pinmap,
502 ARRAY_SIZE(snowball_pinmap));
503 pinctrl_register_mappings(u8500_pinmap,
504 ARRAY_SIZE(u8500_pinmap));
505}
506
507void __init hrefv60_pinmaps_init(void)
508{
509 pinctrl_register_mappings(mop500_family_pinmap,
510 ARRAY_SIZE(mop500_family_pinmap));
511 pinctrl_register_mappings(hrefv60_pinmap,
512 ARRAY_SIZE(hrefv60_pinmap));
513 mop500_href_family_pinmaps_init();
514}