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1/*
2 *
3 * arch/arm/mach-u300/include/mach/syscon.h
4 *
5 *
6 * Copyright (C) 2008 ST-Ericsson AB
7 *
8 * Author: Rickard Andersson <rickard.andersson@stericsson.com>
9 */
10
11#ifndef __MACH_SYSCON_H
12#define __MACH_SYSCON_H
13
14/*
15 * All register defines for SYSCON registers that concerns individual
16 * block clocks and reset lines are registered here. This is because
17 * we don't want any other file to try to fool around with this stuff.
18 */
19
20/* APP side SYSCON registers */
21/* TODO: this is incomplete. Add all from asic_syscon_map.h eventually. */
22/* CLK Control Register 16bit (R/W) */
23#define U300_SYSCON_CCR (0x0000)
24#define U300_SYSCON_CCR_I2S1_USE_VCXO (0x0040)
25#define U300_SYSCON_CCR_I2S0_USE_VCXO (0x0020)
26#define U300_SYSCON_CCR_TURN_VCXO_ON (0x0008)
27#define U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK (0x0007)
28#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER (0x04)
29#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW (0x03)
30#define U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE (0x02)
31#define U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH (0x01)
32#define U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST (0x00)
33/* CLK Status Register 16bit (R/W) */
34#define U300_SYSCON_CSR (0x0004)
35#define U300_SYSCON_CSR_PLL208_LOCK_IND (0x0002)
36#define U300_SYSCON_CSR_PLL13_LOCK_IND (0x0001)
37/* Reset lines for SLOW devices 16bit (R/W) */
38#define U300_SYSCON_RSR (0x0014)
39#ifdef CONFIG_MACH_U300_BS335
40#define U300_SYSCON_RSR_PPM_RESET_EN (0x0200)
41#endif
42#define U300_SYSCON_RSR_ACC_TMR_RESET_EN (0x0100)
43#define U300_SYSCON_RSR_APP_TMR_RESET_EN (0x0080)
44#define U300_SYSCON_RSR_RTC_RESET_EN (0x0040)
45#define U300_SYSCON_RSR_KEYPAD_RESET_EN (0x0020)
46#define U300_SYSCON_RSR_GPIO_RESET_EN (0x0010)
47#define U300_SYSCON_RSR_EH_RESET_EN (0x0008)
48#define U300_SYSCON_RSR_BTR_RESET_EN (0x0004)
49#define U300_SYSCON_RSR_UART_RESET_EN (0x0002)
50#define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN (0x0001)
51/* Reset lines for FAST devices 16bit (R/W) */
52#define U300_SYSCON_RFR (0x0018)
53#ifdef CONFIG_MACH_U300_BS335
54#define U300_SYSCON_RFR_UART1_RESET_ENABLE (0x0080)
55#endif
56#define U300_SYSCON_RFR_SPI_RESET_ENABLE (0x0040)
57#define U300_SYSCON_RFR_MMC_RESET_ENABLE (0x0020)
58#define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE (0x0010)
59#define U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE (0x0008)
60#define U300_SYSCON_RFR_I2C1_RESET_ENABLE (0x0004)
61#define U300_SYSCON_RFR_I2C0_RESET_ENABLE (0x0002)
62#define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE (0x0001)
63/* Reset lines for the rest of the peripherals 16bit (R/W) */
64#define U300_SYSCON_RRR (0x001c)
65#ifdef CONFIG_MACH_U300_BS335
66#define U300_SYSCON_RRR_CDS_RESET_EN (0x4000)
67#define U300_SYSCON_RRR_ISP_RESET_EN (0x2000)
68#endif
69#define U300_SYSCON_RRR_INTCON_RESET_EN (0x1000)
70#define U300_SYSCON_RRR_MSPRO_RESET_EN (0x0800)
71#define U300_SYSCON_RRR_XGAM_RESET_EN (0x0100)
72#define U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN (0x0080)
73#define U300_SYSCON_RRR_NANDIF_RESET_EN (0x0040)
74#define U300_SYSCON_RRR_EMIF_RESET_EN (0x0020)
75#define U300_SYSCON_RRR_DMAC_RESET_EN (0x0010)
76#define U300_SYSCON_RRR_CPU_RESET_EN (0x0008)
77#define U300_SYSCON_RRR_APEX_RESET_EN (0x0004)
78#define U300_SYSCON_RRR_AHB_RESET_EN (0x0002)
79#define U300_SYSCON_RRR_AAIF_RESET_EN (0x0001)
80/* Clock enable for SLOW peripherals 16bit (R/W) */
81#define U300_SYSCON_CESR (0x0020)
82#ifdef CONFIG_MACH_U300_BS335
83#define U300_SYSCON_CESR_PPM_CLK_EN (0x0200)
84#endif
85#define U300_SYSCON_CESR_ACC_TMR_CLK_EN (0x0100)
86#define U300_SYSCON_CESR_APP_TMR_CLK_EN (0x0080)
87#define U300_SYSCON_CESR_KEYPAD_CLK_EN (0x0040)
88#define U300_SYSCON_CESR_GPIO_CLK_EN (0x0010)
89#define U300_SYSCON_CESR_EH_CLK_EN (0x0008)
90#define U300_SYSCON_CESR_BTR_CLK_EN (0x0004)
91#define U300_SYSCON_CESR_UART_CLK_EN (0x0002)
92#define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN (0x0001)
93/* Clock enable for FAST peripherals 16bit (R/W) */
94#define U300_SYSCON_CEFR (0x0024)
95#ifdef CONFIG_MACH_U300_BS335
96#define U300_SYSCON_CEFR_UART1_CLK_EN (0x0200)
97#endif
98#define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN (0x0100)
99#define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN (0x0080)
100#define U300_SYSCON_CEFR_SPI_CLK_EN (0x0040)
101#define U300_SYSCON_CEFR_MMC_CLK_EN (0x0020)
102#define U300_SYSCON_CEFR_I2S1_CLK_EN (0x0010)
103#define U300_SYSCON_CEFR_I2S0_CLK_EN (0x0008)
104#define U300_SYSCON_CEFR_I2C1_CLK_EN (0x0004)
105#define U300_SYSCON_CEFR_I2C0_CLK_EN (0x0002)
106#define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN (0x0001)
107/* Clock enable for the rest of the peripherals 16bit (R/W) */
108#define U300_SYSCON_CERR (0x0028)
109#ifdef CONFIG_MACH_U300_BS335
110#define U300_SYSCON_CERR_CDS_CLK_EN (0x2000)
111#define U300_SYSCON_CERR_ISP_CLK_EN (0x1000)
112#endif
113#define U300_SYSCON_CERR_MSPRO_CLK_EN (0x0800)
114#define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN (0x0400)
115#define U300_SYSCON_CERR_SEMI_CLK_EN (0x0200)
116#define U300_SYSCON_CERR_XGAM_CLK_EN (0x0100)
117#define U300_SYSCON_CERR_VIDEO_ENC_CLK_EN (0x0080)
118#define U300_SYSCON_CERR_NANDIF_CLK_EN (0x0040)
119#define U300_SYSCON_CERR_EMIF_CLK_EN (0x0020)
120#define U300_SYSCON_CERR_DMAC_CLK_EN (0x0010)
121#define U300_SYSCON_CERR_CPU_CLK_EN (0x0008)
122#define U300_SYSCON_CERR_APEX_CLK_EN (0x0004)
123#define U300_SYSCON_CERR_AHB_CLK_EN (0x0002)
124#define U300_SYSCON_CERR_AAIF_CLK_EN (0x0001)
125/* Single block clock enable 16bit (-/W) */
126#define U300_SYSCON_SBCER (0x002c)
127#ifdef CONFIG_MACH_U300_BS335
128#define U300_SYSCON_SBCER_PPM_CLK_EN (0x0009)
129#endif
130#define U300_SYSCON_SBCER_ACC_TMR_CLK_EN (0x0008)
131#define U300_SYSCON_SBCER_APP_TMR_CLK_EN (0x0007)
132#define U300_SYSCON_SBCER_KEYPAD_CLK_EN (0x0006)
133#define U300_SYSCON_SBCER_GPIO_CLK_EN (0x0004)
134#define U300_SYSCON_SBCER_EH_CLK_EN (0x0003)
135#define U300_SYSCON_SBCER_BTR_CLK_EN (0x0002)
136#define U300_SYSCON_SBCER_UART_CLK_EN (0x0001)
137#define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN (0x0000)
138#ifdef CONFIG_MACH_U300_BS335
139#define U300_SYSCON_SBCER_UART1_CLK_EN (0x0019)
140#endif
141#define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN (0x0018)
142#define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN (0x0017)
143#define U300_SYSCON_SBCER_SPI_CLK_EN (0x0016)
144#define U300_SYSCON_SBCER_MMC_CLK_EN (0x0015)
145#define U300_SYSCON_SBCER_I2S1_CLK_EN (0x0014)
146#define U300_SYSCON_SBCER_I2S0_CLK_EN (0x0013)
147#define U300_SYSCON_SBCER_I2C1_CLK_EN (0x0012)
148#define U300_SYSCON_SBCER_I2C0_CLK_EN (0x0011)
149#define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN (0x0010)
150#ifdef CONFIG_MACH_U300_BS335
151#define U300_SYSCON_SBCER_CDS_CLK_EN (0x002D)
152#define U300_SYSCON_SBCER_ISP_CLK_EN (0x002C)
153#endif
154#define U300_SYSCON_SBCER_MSPRO_CLK_EN (0x002B)
155#define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN (0x002A)
156#define U300_SYSCON_SBCER_SEMI_CLK_EN (0x0029)
157#define U300_SYSCON_SBCER_XGAM_CLK_EN (0x0028)
158#define U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN (0x0027)
159#define U300_SYSCON_SBCER_NANDIF_CLK_EN (0x0026)
160#define U300_SYSCON_SBCER_EMIF_CLK_EN (0x0025)
161#define U300_SYSCON_SBCER_DMAC_CLK_EN (0x0024)
162#define U300_SYSCON_SBCER_CPU_CLK_EN (0x0023)
163#define U300_SYSCON_SBCER_APEX_CLK_EN (0x0022)
164#define U300_SYSCON_SBCER_AHB_CLK_EN (0x0021)
165#define U300_SYSCON_SBCER_AAIF_CLK_EN (0x0020)
166/* Single block clock disable 16bit (-/W) */
167#define U300_SYSCON_SBCDR (0x0030)
168/* Same values as above for SBCER */
169/* Clock force SLOW peripherals 16bit (R/W) */
170#define U300_SYSCON_CFSR (0x003c)
171#ifdef CONFIG_MACH_U300_BS335
172#define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN (0x0200)
173#endif
174#define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN (0x0100)
175#define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN (0x0080)
176#define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN (0x0020)
177#define U300_SYSCON_CFSR_GPIO_CLK_FORCE_EN (0x0010)
178#define U300_SYSCON_CFSR_EH_CLK_FORCE_EN (0x0008)
179#define U300_SYSCON_CFSR_BTR_CLK_FORCE_EN (0x0004)
180#define U300_SYSCON_CFSR_UART_CLK_FORCE_EN (0x0002)
181#define U300_SYSCON_CFSR_SLOW_BRIDGE_CLK_FORCE_EN (0x0001)
182/* Clock force FAST peripherals 16bit (R/W) */
183#define U300_SYSCON_CFFR (0x40)
184/* Values not defined. Define if you want to use them. */
185/* Clock force the rest of the peripherals 16bit (R/W) */
186#define U300_SYSCON_CFRR (0x44)
187#ifdef CONFIG_MACH_U300_BS335
188#define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN (0x2000)
189#define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN (0x1000)
190#endif
191#define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN (0x0800)
192#define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN (0x0400)
193#define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN (0x0200)
194#define U300_SYSCON_CFRR_XGAM_CLK_FORCE_EN (0x0100)
195#define U300_SYSCON_CFRR_VIDEO_ENC_CLK_FORCE_EN (0x0080)
196#define U300_SYSCON_CFRR_NANDIF_CLK_FORCE_EN (0x0040)
197#define U300_SYSCON_CFRR_EMIF_CLK_FORCE_EN (0x0020)
198#define U300_SYSCON_CFRR_DMAC_CLK_FORCE_EN (0x0010)
199#define U300_SYSCON_CFRR_CPU_CLK_FORCE_EN (0x0008)
200#define U300_SYSCON_CFRR_APEX_CLK_FORCE_EN (0x0004)
201#define U300_SYSCON_CFRR_AHB_CLK_FORCE_EN (0x0002)
202#define U300_SYSCON_CFRR_AAIF_CLK_FORCE_EN (0x0001)
203/* PLL208 Frequency Control 16bit (R/W) */
204#define U300_SYSCON_PFCR (0x48)
205#define U300_SYSCON_PFCR_DPLL_MULT_NUM (0x000F)
206/* Power Management Control 16bit (R/W) */
207#define U300_SYSCON_PMCR (0x50)
208#define U300_SYSCON_PMCR_DCON_ENABLE (0x0002)
209#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE (0x0001)
210/*
211 * All other clocking registers moved to clock.c!
212 */
213/* Reset Out 16bit (R/W) */
214#define U300_SYSCON_RCR (0x6c)
215#define U300_SYSCON_RCR_RESOUT0_RST_N_DISABLE (0x0001)
216/* EMIF Slew Rate Control 16bit (R/W) */
217#define U300_SYSCON_SRCLR (0x70)
218#define U300_SYSCON_SRCLR_MASK (0x03FF)
219#define U300_SYSCON_SRCLR_VALUE (0x03FF)
220#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_B (0x0200)
221#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_A (0x0100)
222#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_B (0x0080)
223#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_A (0x0040)
224#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_B (0x0020)
225#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_A (0x0010)
226#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_B (0x0008)
227#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_A (0x0004)
228#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_B (0x0002)
229#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_A (0x0001)
230/* EMIF Clock Control Register 16bit (R/W) */
231#define U300_SYSCON_ECCR (0x0078)
232#define U300_SYSCON_ECCR_MASK (0x000F)
233#define U300_SYSCON_ECCR_EMIF_1_STATIC_CLK_EN_N_DISABLE (0x0008)
234#define U300_SYSCON_ECCR_EMIF_1_RET_OUT_CLK_EN_N_DISABLE (0x0004)
235#define U300_SYSCON_ECCR_EMIF_MEMCLK_RET_EN_N_DISABLE (0x0002)
236#define U300_SYSCON_ECCR_EMIF_SDRCLK_RET_EN_N_DISABLE (0x0001)
237/* Step one for killing the applications system 16bit (-/W) */
238#define U300_SYSCON_KA1R (0x0080)
239#define U300_SYSCON_KA1R_MASK (0xFFFF)
240#define U300_SYSCON_KA1R_VALUE (0xFFFF)
241/* Step two for killing the application system 16bit (-/W) */
242#define U300_SYSCON_KA2R (0x0084)
243#define U300_SYSCON_KA2R_MASK (0xFFFF)
244#define U300_SYSCON_KA2R_VALUE (0xFFFF)
245/* MMC/MSPRO frequency divider register 0 16bit (R/W) */
246#define U300_SYSCON_MMF0R (0x90)
247#define U300_SYSCON_MMF0R_MASK (0x00FF)
248#define U300_SYSCON_MMF0R_FREQ_0_HIGH_MASK (0x00F0)
249#define U300_SYSCON_MMF0R_FREQ_0_LOW_MASK (0x000F)
250/* MMC/MSPRO frequency divider register 1 16bit (R/W) */
251#define U300_SYSCON_MMF1R (0x94)
252#define U300_SYSCON_MMF1R_MASK (0x00FF)
253#define U300_SYSCON_MMF1R_FREQ_1_HIGH_MASK (0x00F0)
254#define U300_SYSCON_MMF1R_FREQ_1_LOW_MASK (0x000F)
255/* AAIF control register 16 bit (R/W) */
256#define U300_SYSCON_AAIFCR (0x98)
257#define U300_SYSCON_AAIFCR_MASK (0x0003)
258#define U300_SYSCON_AAIFCR_AASW_CTRL_MASK (0x0003)
259#define U300_SYSCON_AAIFCR_AASW_CTRL_FUNCTIONAL (0x0000)
260#define U300_SYSCON_AAIFCR_AASW_CTRL_MONITORING (0x0001)
261#define U300_SYSCON_AAIFCR_AASW_CTRL_ACC_TO_EXT (0x0002)
262#define U300_SYSCON_AAIFCR_AASW_CTRL_APP_TO_EXT (0x0003)
263/* Clock control for the MMC and MSPRO blocks 16bit (R/W) */
264#define U300_SYSCON_MMCR (0x9C)
265#define U300_SYSCON_MMCR_MASK (0x0003)
266#define U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE (0x0002)
267#define U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE (0x0001)
268/* Pull up/down control (R/W) */
269#define U300_SYSCON_PUCR (0x104)
270#define U300_SYSCON_PUCR_EMIF_1_WAIT_N_PU_ENABLE (0x0200)
271#define U300_SYSCON_PUCR_EMIF_1_NFIF_READY_PU_ENABLE (0x0100)
272#define U300_SYSCON_PUCR_EMIF_1_16BIT_PU_ENABLE (0x0080)
273#define U300_SYSCON_PUCR_EMIF_1_8BIT_PU_ENABLE (0x0040)
274#define U300_SYSCON_PUCR_KEY_IN_PU_EN_MASK (0x003F)
275/* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */
276#define U300_SYSCON_S0CCR (0x120)
277#define U300_SYSCON_S0CCR_FIELD_MASK (0x43FF)
278#define U300_SYSCON_S0CCR_CLOCK_REQ (0x4000)
279#define U300_SYSCON_S0CCR_CLOCK_REQ_MONITOR (0x2000)
280#define U300_SYSCON_S0CCR_CLOCK_INV (0x0200)
281#define U300_SYSCON_S0CCR_CLOCK_FREQ_MASK (0x01E0)
282#define U300_SYSCON_S0CCR_CLOCK_SELECT_MASK (0x001E)
283#define U300_SYSCON_S0CCR_CLOCK_ENABLE (0x0001)
284#define U300_SYSCON_S0CCR_SEL_MCLK (0x8<<1)
285#define U300_SYSCON_S0CCR_SEL_ACC_FSM_CLK (0xA<<1)
286#define U300_SYSCON_S0CCR_SEL_PLL60_48_CLK (0xC<<1)
287#define U300_SYSCON_S0CCR_SEL_PLL60_60_CLK (0xD<<1)
288#define U300_SYSCON_S0CCR_SEL_ACC_PLL208_CLK (0xE<<1)
289#define U300_SYSCON_S0CCR_SEL_APP_PLL13_CLK (0x0<<1)
290#define U300_SYSCON_S0CCR_SEL_APP_FSM_CLK (0x2<<1)
291#define U300_SYSCON_S0CCR_SEL_RTC_CLK (0x4<<1)
292#define U300_SYSCON_S0CCR_SEL_APP_PLL208_CLK (0x6<<1)
293/* SYS_1_CLK_CONTROL second clock control 16 bit (R/W) */
294#define U300_SYSCON_S1CCR (0x124)
295#define U300_SYSCON_S1CCR_FIELD_MASK (0x43FF)
296#define U300_SYSCON_S1CCR_CLOCK_REQ (0x4000)
297#define U300_SYSCON_S1CCR_CLOCK_REQ_MONITOR (0x2000)
298#define U300_SYSCON_S1CCR_CLOCK_INV (0x0200)
299#define U300_SYSCON_S1CCR_CLOCK_FREQ_MASK (0x01E0)
300#define U300_SYSCON_S1CCR_CLOCK_SELECT_MASK (0x001E)
301#define U300_SYSCON_S1CCR_CLOCK_ENABLE (0x0001)
302#define U300_SYSCON_S1CCR_SEL_MCLK (0x8<<1)
303#define U300_SYSCON_S1CCR_SEL_ACC_FSM_CLK (0xA<<1)
304#define U300_SYSCON_S1CCR_SEL_PLL60_48_CLK (0xC<<1)
305#define U300_SYSCON_S1CCR_SEL_PLL60_60_CLK (0xD<<1)
306#define U300_SYSCON_S1CCR_SEL_ACC_PLL208_CLK (0xE<<1)
307#define U300_SYSCON_S1CCR_SEL_ACC_PLL13_CLK (0x0<<1)
308#define U300_SYSCON_S1CCR_SEL_APP_FSM_CLK (0x2<<1)
309#define U300_SYSCON_S1CCR_SEL_RTC_CLK (0x4<<1)
310#define U300_SYSCON_S1CCR_SEL_APP_PLL208_CLK (0x6<<1)
311/* SYS_2_CLK_CONTROL third clock contol 16 bit (R/W) */
312#define U300_SYSCON_S2CCR (0x128)
313#define U300_SYSCON_S2CCR_FIELD_MASK (0xC3FF)
314#define U300_SYSCON_S2CCR_CLK_STEAL (0x8000)
315#define U300_SYSCON_S2CCR_CLOCK_REQ (0x4000)
316#define U300_SYSCON_S2CCR_CLOCK_REQ_MONITOR (0x2000)
317#define U300_SYSCON_S2CCR_CLOCK_INV (0x0200)
318#define U300_SYSCON_S2CCR_CLOCK_FREQ_MASK (0x01E0)
319#define U300_SYSCON_S2CCR_CLOCK_SELECT_MASK (0x001E)
320#define U300_SYSCON_S2CCR_CLOCK_ENABLE (0x0001)
321#define U300_SYSCON_S2CCR_SEL_MCLK (0x8<<1)
322#define U300_SYSCON_S2CCR_SEL_ACC_FSM_CLK (0xA<<1)
323#define U300_SYSCON_S2CCR_SEL_PLL60_48_CLK (0xC<<1)
324#define U300_SYSCON_S2CCR_SEL_PLL60_60_CLK (0xD<<1)
325#define U300_SYSCON_S2CCR_SEL_ACC_PLL208_CLK (0xE<<1)
326#define U300_SYSCON_S2CCR_SEL_ACC_PLL13_CLK (0x0<<1)
327#define U300_SYSCON_S2CCR_SEL_APP_FSM_CLK (0x2<<1)
328#define U300_SYSCON_S2CCR_SEL_RTC_CLK (0x4<<1)
329#define U300_SYSCON_S2CCR_SEL_APP_PLL208_CLK (0x6<<1)
330/* SYS_MISC_CONTROL, miscellaneous 16bit (R/W) */
331#define U300_SYSCON_MCR (0x12c)
332#define U300_SYSCON_MCR_FIELD_MASK (0x00FF)
333#define U300_SYSCON_MCR_PMGEN_CR_4_MASK (0x00C0)
334#define U300_SYSCON_MCR_PMGEN_CR_4_GPIO (0x0000)
335#define U300_SYSCON_MCR_PMGEN_CR_4_SPI (0x0040)
336#define U300_SYSCON_MCR_PMGEN_CR_4_AAIF (0x00C0)
337#define U300_SYSCON_MCR_PMGEN_CR_2_MASK (0x0030)
338#define U300_SYSCON_MCR_PMGEN_CR_2_GPIO (0x0000)
339#define U300_SYSCON_MCR_PMGEN_CR_2_EMIF_1_STATIC (0x0010)
340#define U300_SYSCON_MCR_PMGEN_CR_2_DSP (0x0020)
341#define U300_SYSCON_MCR_PMGEN_CR_2_AAIF (0x0030)
342#define U300_SYSCON_MCR_PMGEN_CR_0_MASK (0x000C)
343#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M1 (0x0000)
344#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M2 (0x0004)
345#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M3 (0x0008)
346#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_0_SDRAM (0x000C)
347#define U300_SYSCON_MCR_PM1G_MODE_ENABLE (0x0002)
348#define U300_SYSCON_MCR_PMTG5_MODE_ENABLE (0x0001)
349/* SC_PLL_IRQ_CONTROL 16bit (R/W) */
350#define U300_SYSCON_PICR (0x0130)
351#define U300_SYSCON_PICR_MASK (0x00FF)
352#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_LOW_ENABLE (0x0080)
353#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_HIGH_ENABLE (0x0040)
354#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_LOW_ENABLE (0x0020)
355#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_HIGH_ENABLE (0x0010)
356#define U300_SYSCON_PICR_IRQMASK_PLL13_UNLOCK_ENABLE (0x0008)
357#define U300_SYSCON_PICR_IRQMASK_PLL13_LOCK_ENABLE (0x0004)
358#define U300_SYSCON_PICR_IRQMASK_PLL208_UNLOCK_ENABLE (0x0002)
359#define U300_SYSCON_PICR_IRQMASK_PLL208_LOCK_ENABLE (0x0001)
360/* SC_PLL_IRQ_STATUS 16 bit (R/-) */
361#define U300_SYSCON_PISR (0x0134)
362#define U300_SYSCON_PISR_MASK (0x000F)
363#define U300_SYSCON_PISR_PLL13_UNLOCK_IND (0x0008)
364#define U300_SYSCON_PISR_PLL13_LOCK_IND (0x0004)
365#define U300_SYSCON_PISR_PLL208_UNLOCK_IND (0x0002)
366#define U300_SYSCON_PISR_PLL208_LOCK_IND (0x0001)
367/* SC_PLL_IRQ_CLEAR 16 bit (-/W) */
368#define U300_SYSCON_PICLR (0x0138)
369#define U300_SYSCON_PICLR_MASK (0x000F)
370#define U300_SYSCON_PICLR_RWMASK (0x0000)
371#define U300_SYSCON_PICLR_PLL13_UNLOCK_SC (0x0008)
372#define U300_SYSCON_PICLR_PLL13_LOCK_SC (0x0004)
373#define U300_SYSCON_PICLR_PLL208_UNLOCK_SC (0x0002)
374#define U300_SYSCON_PICLR_PLL208_LOCK_SC (0x0001)
375/* CAMIF_CONTROL 16 bit (-/W) */
376#define U300_SYSCON_CICR (0x013C)
377#define U300_SYSCON_CICR_MASK (0x0FFF)
378#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_MASK (0x0F00)
379#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_PORT1 (0x0C00)
380#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_PORT0 (0x0300)
381#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_MASK (0x00F0)
382#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_PORT1 (0x00C0)
383#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_PORT0 (0x0030)
384#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_MASK (0x000F)
385#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_PORT1 (0x000C)
386#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_PORT0 (0x0003)
387/* Clock activity observability register 0 */
388#define U300_SYSCON_C0OAR (0x140)
389#define U300_SYSCON_C0OAR_MASK (0xFFFF)
390#define U300_SYSCON_C0OAR_VALUE (0xFFFF)
391#define U300_SYSCON_C0OAR_BT_H_CLK (0x8000)
392#define U300_SYSCON_C0OAR_ASPB_P_CLK (0x4000)
393#define U300_SYSCON_C0OAR_APP_SEMI_H_CLK (0x2000)
394#define U300_SYSCON_C0OAR_APP_SEMI_CLK (0x1000)
395#define U300_SYSCON_C0OAR_APP_MMC_MSPRO_CLK (0x0800)
396#define U300_SYSCON_C0OAR_APP_I2S1_CLK (0x0400)
397#define U300_SYSCON_C0OAR_APP_I2S0_CLK (0x0200)
398#define U300_SYSCON_C0OAR_APP_CPU_CLK (0x0100)
399#define U300_SYSCON_C0OAR_APP_52_CLK (0x0080)
400#define U300_SYSCON_C0OAR_APP_208_CLK (0x0040)
401#define U300_SYSCON_C0OAR_APP_104_CLK (0x0020)
402#define U300_SYSCON_C0OAR_APEX_CLK (0x0010)
403#define U300_SYSCON_C0OAR_AHPB_M_H_CLK (0x0008)
404#define U300_SYSCON_C0OAR_AHB_CLK (0x0004)
405#define U300_SYSCON_C0OAR_AFPB_P_CLK (0x0002)
406#define U300_SYSCON_C0OAR_AAIF_CLK (0x0001)
407/* Clock activity observability register 1 */
408#define U300_SYSCON_C1OAR (0x144)
409#define U300_SYSCON_C1OAR_MASK (0x3FFE)
410#define U300_SYSCON_C1OAR_VALUE (0x3FFE)
411#define U300_SYSCON_C1OAR_NFIF_F_CLK (0x2000)
412#define U300_SYSCON_C1OAR_MSPRO_CLK (0x1000)
413#define U300_SYSCON_C1OAR_MMC_P_CLK (0x0800)
414#define U300_SYSCON_C1OAR_MMC_CLK (0x0400)
415#define U300_SYSCON_C1OAR_KP_P_CLK (0x0200)
416#define U300_SYSCON_C1OAR_I2C1_P_CLK (0x0100)
417#define U300_SYSCON_C1OAR_I2C0_P_CLK (0x0080)
418#define U300_SYSCON_C1OAR_GPIO_CLK (0x0040)
419#define U300_SYSCON_C1OAR_EMIF_MPMC_CLK (0x0020)
420#define U300_SYSCON_C1OAR_EMIF_H_CLK (0x0010)
421#define U300_SYSCON_C1OAR_EVHIST_CLK (0x0008)
422#define U300_SYSCON_C1OAR_PPM_CLK (0x0004)
423#define U300_SYSCON_C1OAR_DMA_CLK (0x0002)
424/* Clock activity observability register 2 */
425#define U300_SYSCON_C2OAR (0x148)
426#define U300_SYSCON_C2OAR_MASK (0x0FFF)
427#define U300_SYSCON_C2OAR_VALUE (0x0FFF)
428#define U300_SYSCON_C2OAR_XGAM_CDI_CLK (0x0800)
429#define U300_SYSCON_C2OAR_XGAM_CLK (0x0400)
430#define U300_SYSCON_C2OAR_VC_H_CLK (0x0200)
431#define U300_SYSCON_C2OAR_VC_CLK (0x0100)
432#define U300_SYSCON_C2OAR_UA_P_CLK (0x0080)
433#define U300_SYSCON_C2OAR_TMR1_CLK (0x0040)
434#define U300_SYSCON_C2OAR_TMR0_CLK (0x0020)
435#define U300_SYSCON_C2OAR_SPI_P_CLK (0x0010)
436#define U300_SYSCON_C2OAR_PCM_I2S1_CORE_CLK (0x0008)
437#define U300_SYSCON_C2OAR_PCM_I2S1_CLK (0x0004)
438#define U300_SYSCON_C2OAR_PCM_I2S0_CORE_CLK (0x0002)
439#define U300_SYSCON_C2OAR_PCM_I2S0_CLK (0x0001)
440
441/* Chip ID register 16bit (R/-) */
442#define U300_SYSCON_CIDR (0x400)
443/* Video IRQ clear 16bit (R/W) */
444#define U300_SYSCON_VICR (0x404)
445#define U300_SYSCON_VICR_VIDEO1_IRQ_CLEAR_ENABLE (0x0002)
446#define U300_SYSCON_VICR_VIDEO0_IRQ_CLEAR_ENABLE (0x0001)
447/* SMCR */
448#define U300_SYSCON_SMCR (0x4d0)
449#define U300_SYSCON_SMCR_FIELD_MASK (0x000e)
450#define U300_SYSCON_SMCR_SEMI_SREFACK_IND (0x0008)
451#define U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE (0x0004)
452#define U300_SYSCON_SMCR_SEMI_EXT_BOOT_MODE_ENABLE (0x0002)
453/* CPU_SW_DBGEN Software Debug Enable 16bit (R/W) */
454#define U300_SYSCON_CSDR (0x4f0)
455#define U300_SYSCON_CSDR_SW_DEBUG_ENABLE (0x0001)
456/* PRINT_CONTROL Print Control 16bit (R/-) */
457#define U300_SYSCON_PCR (0x4f8)
458#define U300_SYSCON_PCR_SERV_IND (0x0001)
459/* BOOT_CONTROL 16bit (R/-) */
460#define U300_SYSCON_BCR (0x4fc)
461#define U300_SYSCON_BCR_ACC_CPU_SUBSYS_VINITHI_IND (0x0400)
462#define U300_SYSCON_BCR_APP_CPU_SUBSYS_VINITHI_IND (0x0200)
463#define U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK (0x01FC)
464#define U300_SYSCON_BCR_APP_BOOT_SERV_MASK (0x0003)
465
466
467/* CPU clock defines */
468/**
469 * CPU high frequency in MHz
470 */
471#define SYSCON_CPU_CLOCK_HIGH 208
472/**
473 * CPU medium frequency in MHz
474 */
475#define SYSCON_CPU_CLOCK_MEDIUM 52
476/**
477 * CPU low frequency in MHz
478 */
479#define SYSCON_CPU_CLOCK_LOW 13
480
481/* EMIF clock defines */
482/**
483 * EMIF high frequency in MHz
484 */
485#define SYSCON_EMIF_CLOCK_HIGH 104
486/**
487 * EMIF medium frequency in MHz
488 */
489#define SYSCON_EMIF_CLOCK_MEDIUM 52
490/**
491 * EMIF low frequency in MHz
492 */
493#define SYSCON_EMIF_CLOCK_LOW 13
494
495/* AHB clock defines */
496/**
497 * AHB high frequency in MHz
498 */
499#define SYSCON_AHB_CLOCK_HIGH 52
500/**
501 * AHB medium frequency in MHz
502 */
503#define SYSCON_AHB_CLOCK_MEDIUM 26
504/**
505 * AHB low frequency in MHz
506 */
507#define SYSCON_AHB_CLOCK_LOW 7 /* i.e 13/2=6.5MHz */
508
509enum syscon_busmaster {
510 SYSCON_BM_DMAC,
511 SYSCON_BM_XGAM,
512 SYSCON_BM_VIDEO_ENC
513};
514
515/* Selectr a resistor or a set of resistors */
516enum syscon_pull_up_down {
517 SYSCON_PU_KEY_IN_EN,
518 SYSCON_PU_EMIF_1_8_BIT_EN,
519 SYSCON_PU_EMIF_1_16_BIT_EN,
520 SYSCON_PU_EMIF_1_NFIF_READY_EN,
521 SYSCON_PU_EMIF_1_NFIF_WAIT_N_EN,
522};
523
524/*
525 * Note that this array must match the order of the array "clk_reg"
526 * in syscon.c
527 */
528enum syscon_clk {
529 SYSCON_CLKCONTROL_SLOW_BRIDGE,
530 SYSCON_CLKCONTROL_UART,
531 SYSCON_CLKCONTROL_BTR,
532 SYSCON_CLKCONTROL_EH,
533 SYSCON_CLKCONTROL_GPIO,
534 SYSCON_CLKCONTROL_KEYPAD,
535 SYSCON_CLKCONTROL_APP_TIMER,
536 SYSCON_CLKCONTROL_ACC_TIMER,
537 SYSCON_CLKCONTROL_FAST_BRIDGE,
538 SYSCON_CLKCONTROL_I2C0,
539 SYSCON_CLKCONTROL_I2C1,
540 SYSCON_CLKCONTROL_I2S0,
541 SYSCON_CLKCONTROL_I2S1,
542 SYSCON_CLKCONTROL_MMC,
543 SYSCON_CLKCONTROL_SPI,
544 SYSCON_CLKCONTROL_I2S0_CORE,
545 SYSCON_CLKCONTROL_I2S1_CORE,
546 SYSCON_CLKCONTROL_UART1,
547 SYSCON_CLKCONTROL_AAIF,
548 SYSCON_CLKCONTROL_AHB,
549 SYSCON_CLKCONTROL_APEX,
550 SYSCON_CLKCONTROL_CPU,
551 SYSCON_CLKCONTROL_DMA,
552 SYSCON_CLKCONTROL_EMIF,
553 SYSCON_CLKCONTROL_NAND_IF,
554 SYSCON_CLKCONTROL_VIDEO_ENC,
555 SYSCON_CLKCONTROL_XGAM,
556 SYSCON_CLKCONTROL_SEMI,
557 SYSCON_CLKCONTROL_AHB_SUBSYS,
558 SYSCON_CLKCONTROL_MSPRO
559};
560
561enum syscon_sysclk_mode {
562 SYSCON_SYSCLK_DISABLED,
563 SYSCON_SYSCLK_M_CLK,
564 SYSCON_SYSCLK_ACC_FSM,
565 SYSCON_SYSCLK_PLL60_48,
566 SYSCON_SYSCLK_PLL60_60,
567 SYSCON_SYSCLK_ACC_PLL208,
568 SYSCON_SYSCLK_APP_PLL13,
569 SYSCON_SYSCLK_APP_FSM,
570 SYSCON_SYSCLK_RTC,
571 SYSCON_SYSCLK_APP_PLL208
572};
573
574enum syscon_sysclk_req {
575 SYSCON_SYSCLKREQ_DISABLED,
576 SYSCON_SYSCLKREQ_ACTIVE_LOW,
577 SYSCON_SYSCLKREQ_MONITOR
578};
579
580enum syscon_clk_mode {
581 SYSCON_CLKMODE_OFF,
582 SYSCON_CLKMODE_DEFAULT,
583 SYSCON_CLKMODE_LOW,
584 SYSCON_CLKMODE_MEDIUM,
585 SYSCON_CLKMODE_HIGH,
586 SYSCON_CLKMODE_PERMANENT,
587 SYSCON_CLKMODE_ON,
588};
589
590enum syscon_call_mode {
591 SYSCON_CLKCALL_NOWAIT,
592 SYSCON_CLKCALL_WAIT,
593};
594
595int syscon_dc_on(bool keep_power_on);
596int syscon_set_busmaster_active_state(enum syscon_busmaster busmaster,
597 bool active);
598bool syscon_get_busmaster_active_state(void);
599int syscon_set_sleep_mask(enum syscon_clk,
600 bool sleep_ctrl);
601int syscon_config_sysclk(u32 sysclk,
602 enum syscon_sysclk_mode sysclkmode,
603 bool inverse,
604 u32 divisor,
605 enum syscon_sysclk_req sysclkreq);
606bool syscon_can_turn_off_semi_clock(void);
607
608/* This function is restricted to core.c */
609int syscon_request_normal_power(bool req);
610
611/* This function is restricted to be used by platform_speed.c */
612int syscon_speed_request(enum syscon_call_mode wait_mode,
613 enum syscon_clk_mode req_clk_mode);
614#endif /* __MACH_SYSCON_H */