1# SPDX-License-Identifier: GPL-2.0-only
  2#
  3# Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
  4#
  5
  6config ARC
  7	def_bool y
  8	select ARC_TIMERS
  9	select ARCH_HAS_CACHE_LINE_SIZE
 10	select ARCH_HAS_DEBUG_VM_PGTABLE
 11	select ARCH_HAS_DMA_PREP_COHERENT
 12	select ARCH_HAS_PTE_SPECIAL
 13	select ARCH_HAS_SETUP_DMA_OPS
 14	select ARCH_HAS_SYNC_DMA_FOR_CPU
 15	select ARCH_HAS_SYNC_DMA_FOR_DEVICE
 16	select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
 17	select ARCH_32BIT_OFF_T
 18	select BUILDTIME_TABLE_SORT
 19	select CLONE_BACKWARDS
 20	select COMMON_CLK
 21	select DMA_DIRECT_REMAP
 22	select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC)
 23	# for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
 24	select GENERIC_IRQ_SHOW
 25	select GENERIC_PCI_IOMAP
 26	select GENERIC_PENDING_IRQ if SMP
 27	select GENERIC_SCHED_CLOCK
 28	select GENERIC_SMP_IDLE_THREAD
 29	select GENERIC_IOREMAP
 30	select GENERIC_STRNCPY_FROM_USER if MMU
 31	select GENERIC_STRNLEN_USER if MMU
 32	select HAVE_ARCH_KGDB
 33	select HAVE_ARCH_TRACEHOOK
 34	select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARC_MMU_V4
 35	select HAVE_DEBUG_STACKOVERFLOW
 36	select HAVE_DEBUG_KMEMLEAK
 37	select HAVE_IOREMAP_PROT
 38	select HAVE_KERNEL_GZIP
 39	select HAVE_KERNEL_LZMA
 40	select HAVE_KPROBES
 41	select HAVE_KRETPROBES
 42	select HAVE_REGS_AND_STACK_ACCESS_API
 43	select HAVE_MOD_ARCH_SPECIFIC
 44	select HAVE_PERF_EVENTS
 45	select HAVE_SYSCALL_TRACEPOINTS
 46	select IRQ_DOMAIN
 47	select LOCK_MM_AND_FIND_VMA
 48	select MODULES_USE_ELF_RELA
 49	select OF
 50	select OF_EARLY_FLATTREE
 51	select PCI_SYSCALL if PCI
 52	select HAVE_ARCH_JUMP_LABEL if ISA_ARCV2 && !CPU_ENDIAN_BE32
 53	select TRACE_IRQFLAGS_SUPPORT
 54
 55config LOCKDEP_SUPPORT
 56	def_bool y
 57
 58config SCHED_OMIT_FRAME_POINTER
 59	def_bool y
 60
 61config GENERIC_CSUM
 62	def_bool y
 63
 64config ARCH_FLATMEM_ENABLE
 65	def_bool y
 66
 67config MMU
 68	def_bool y
 69
 70config NO_IOPORT_MAP
 71	def_bool y
 72
 73config GENERIC_CALIBRATE_DELAY
 74	def_bool y
 75
 76config GENERIC_HWEIGHT
 77	def_bool y
 78
 79config STACKTRACE_SUPPORT
 80	def_bool y
 81	select STACKTRACE
 82
 83menu "ARC Architecture Configuration"
 84
 85menu "ARC Platform/SoC/Board"
 86
 87source "arch/arc/plat-tb10x/Kconfig"
 88source "arch/arc/plat-axs10x/Kconfig"
 89source "arch/arc/plat-hsdk/Kconfig"
 90
 91endmenu
 92
 93choice
 94	prompt "ARC Instruction Set"
 95	default ISA_ARCV2
 96
 97config ISA_ARCOMPACT
 98	bool "ARCompact ISA"
 99	select CPU_NO_EFFICIENT_FFS
100	help
101	  The original ARC ISA of ARC600/700 cores
102
103config ISA_ARCV2
104	bool "ARC ISA v2"
105	select ARC_TIMERS_64BIT
106	help
107	  ISA for the Next Generation ARC-HS cores
108
109endchoice
110
111menu "ARC CPU Configuration"
112
113choice
114	prompt "ARC Core"
115	default ARC_CPU_770 if ISA_ARCOMPACT
116	default ARC_CPU_HS if ISA_ARCV2
117
118config ARC_CPU_770
119	bool "ARC770"
120	depends on ISA_ARCOMPACT
121	select ARC_HAS_SWAPE
122	help
123	  Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
124	  This core has a bunch of cool new features:
125	  -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
126	           Shared Address Spaces (for sharing TLB entries in MMU)
127	  -Caches: New Prog Model, Region Flush
128	  -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
129
130config ARC_CPU_HS
131	bool "ARC-HS"
132	depends on ISA_ARCV2
133	help
134	  Support for ARC HS38x Cores based on ARCv2 ISA
135	  The notable features are:
136	    - SMP configurations of up to 4 cores with coherency
137	    - Optional L2 Cache and IO-Coherency
138	    - Revised Interrupt Architecture (multiple priorites, reg banks,
139	        auto stack switch, auto regfile save/restore)
140	    - MMUv4 (PIPT dcache, Huge Pages)
141	    - Instructions for
142		* 64bit load/store: LDD, STD
143		* Hardware assisted divide/remainder: DIV, REM
144		* Function prologue/epilogue: ENTER_S, LEAVE_S
145		* IRQ enable/disable: CLRI, SETI
146		* pop count: FFS, FLS
147		* SETcc, BMSKN, XBFU...
148
149endchoice
150
151config ARC_TUNE_MCPU
152	string "Override default -mcpu compiler flag"
153	default ""
154	help
155	  Override default -mcpu=xxx compiler flag (which is set depending on
156	  the ISA version) with the specified value.
157	  NOTE: If specified flag isn't supported by current compiler the
158	  ISA default value will be used as a fallback.
159
160config CPU_BIG_ENDIAN
161	bool "Enable Big Endian Mode"
162	help
163	  Build kernel for Big Endian Mode of ARC CPU
164
165config SMP
166	bool "Symmetric Multi-Processing"
167	select ARC_MCIP if ISA_ARCV2
168	help
169	  This enables support for systems with more than one CPU.
170
171if SMP
172
173config NR_CPUS
174	int "Maximum number of CPUs (2-4096)"
175	range 2 4096
176	default "4"
177
178config ARC_SMP_HALT_ON_RESET
179	bool "Enable Halt-on-reset boot mode"
180	help
181	  In SMP configuration cores can be configured as Halt-on-reset
182	  or they could all start at same time. For Halt-on-reset, non
183	  masters are parked until Master kicks them so they can start off
184	  at designated entry point. For other case, all jump to common
185	  entry point and spin wait for Master's signal.
186
187endif #SMP
188
189config ARC_MCIP
190	bool "ARConnect Multicore IP (MCIP) Support "
191	depends on ISA_ARCV2
192	default y if SMP
193	help
194	  This IP block enables SMP in ARC-HS38 cores.
195	  It provides for cross-core interrupts, multi-core debug
196	  hardware semaphores, shared memory,....
197
198menuconfig ARC_CACHE
199	bool "Enable Cache Support"
200	default y
201
202if ARC_CACHE
203
204config ARC_CACHE_LINE_SHIFT
205	int "Cache Line Length (as power of 2)"
206	range 5 7
207	default "6"
208	help
209	  Starting with ARC700 4.9, Cache line length is configurable,
210	  This option specifies "N", with Line-len = 2 power N
211	  So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
212	  Linux only supports same line lengths for I and D caches.
213
214config ARC_HAS_ICACHE
215	bool "Use Instruction Cache"
216	default y
217
218config ARC_HAS_DCACHE
219	bool "Use Data Cache"
220	default y
221
222config ARC_CACHE_PAGES
223	bool "Per Page Cache Control"
224	default y
225	depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
226	help
227	  This can be used to over-ride the global I/D Cache Enable on a
228	  per-page basis (but only for pages accessed via MMU such as
229	  Kernel Virtual address or User Virtual Address)
230	  TLB entries have a per-page Cache Enable Bit.
231	  Note that Global I/D ENABLE + Per Page DISABLE works but corollary
232	  Global DISABLE + Per Page ENABLE won't work
233
234endif #ARC_CACHE
235
236config ARC_HAS_ICCM
237	bool "Use ICCM"
238	help
239	  Single Cycle RAMS to store Fast Path Code
240
241config ARC_ICCM_SZ
242	int "ICCM Size in KB"
243	default "64"
244	depends on ARC_HAS_ICCM
245
246config ARC_HAS_DCCM
247	bool "Use DCCM"
248	help
249	  Single Cycle RAMS to store Fast Path Data
250
251config ARC_DCCM_SZ
252	int "DCCM Size in KB"
253	default "64"
254	depends on ARC_HAS_DCCM
255
256config ARC_DCCM_BASE
257	hex "DCCM map address"
258	default "0xA0000000"
259	depends on ARC_HAS_DCCM
260
261choice
262	prompt "MMU Version"
263	default ARC_MMU_V3 if ISA_ARCOMPACT
264	default ARC_MMU_V4 if ISA_ARCV2
265
266config ARC_MMU_V3
267	bool "MMU v3"
268	depends on ISA_ARCOMPACT
269	help
270	  Introduced with ARC700 4.10: New Features
271	  Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
272	  Shared Address Spaces (SASID)
273
274config ARC_MMU_V4
275	bool "MMU v4"
276	depends on ISA_ARCV2
277
278endchoice
279
280
281choice
282	prompt "MMU Page Size"
283	default ARC_PAGE_SIZE_8K
284
285config ARC_PAGE_SIZE_8K
286	bool "8KB"
287	select HAVE_PAGE_SIZE_8KB
288	help
289	  Choose between 8k vs 16k
290
291config ARC_PAGE_SIZE_16K
292	select HAVE_PAGE_SIZE_16KB
293	bool "16KB"
294
295config ARC_PAGE_SIZE_4K
296	bool "4KB"
297	select HAVE_PAGE_SIZE_4KB
298	depends on ARC_MMU_V3 || ARC_MMU_V4
299
300endchoice
301
302choice
303	prompt "MMU Super Page Size"
304	depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
305	default ARC_HUGEPAGE_2M
306
307config ARC_HUGEPAGE_2M
308	bool "2MB"
309
310config ARC_HUGEPAGE_16M
311	bool "16MB"
312
313endchoice
314
315config PGTABLE_LEVELS
316	int "Number of Page table levels"
317	default 2
318
319config ARC_COMPACT_IRQ_LEVELS
320	depends on ISA_ARCOMPACT
321	bool "Setup Timer IRQ as high Priority"
322	# if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
323	depends on !SMP
324
325config ARC_FPU_SAVE_RESTORE
326	bool "Enable FPU state persistence across context switch"
327	help
328	  ARCompact FPU has internal registers to assist with Double precision
329	  Floating Point operations. There are control and stauts registers
330	  for floating point exceptions and rounding modes. These are
331	  preserved across task context switch when enabled.
332
333config ARC_CANT_LLSC
334	def_bool n
335
336config ARC_HAS_LLSC
337	bool "Insn: LLOCK/SCOND (efficient atomic ops)"
338	default y
339	depends on !ARC_CANT_LLSC
340
341config ARC_HAS_SWAPE
342	bool "Insn: SWAPE (endian-swap)"
343	default y
344
345if ISA_ARCV2
346
347config ARC_USE_UNALIGNED_MEM_ACCESS
348	bool "Enable unaligned access in HW"
349	default y
350	select HAVE_EFFICIENT_UNALIGNED_ACCESS
351	help
352	  The ARC HS architecture supports unaligned memory access
353	  which is disabled by default. Enable unaligned access in
354	  hardware and use software to use it
355
356config ARC_HAS_LL64
357	bool "Insn: 64bit LDD/STD"
358	help
359	  Enable gcc to generate 64-bit load/store instructions
360	  ISA mandates even/odd registers to allow encoding of two
361	  dest operands with 2 possible source operands.
362	default y
363
364config ARC_HAS_DIV_REM
365	bool "Insn: div, divu, rem, remu"
366	default y
367
368config ARC_HAS_ACCL_REGS
369	bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6 and/or DSP)"
370	default y
371	help
372	  Depending on the configuration, CPU can contain accumulator reg-pair
373	  (also referred to as r58:r59). These can also be used by gcc as GPR so
374	  kernel needs to save/restore per process
375
376config ARC_DSP_HANDLED
377	def_bool n
378
379config ARC_DSP_SAVE_RESTORE_REGS
380	def_bool n
381
382choice
383	prompt "DSP support"
384	default ARC_DSP_NONE
385	help
386	  Depending on the configuration, CPU can contain DSP registers
387	  (ACC0_GLO, ACC0_GHI, DSP_BFLY0, DSP_CTRL, DSP_FFT_CTRL).
388	  Below are options describing how to handle these registers in
389	  interrupt entry / exit and in context switch.
390
391config ARC_DSP_NONE
392	bool "No DSP extension presence in HW"
393	help
394	  No DSP extension presence in HW
395
396config ARC_DSP_KERNEL
397	bool "DSP extension in HW, no support for userspace"
398	select ARC_HAS_ACCL_REGS
399	select ARC_DSP_HANDLED
400	help
401	  DSP extension presence in HW, no support for DSP-enabled userspace
402	  applications. We don't save / restore DSP registers and only do
403	  some minimal preparations so userspace won't be able to break kernel
404
405config ARC_DSP_USERSPACE
406	bool "Support DSP for userspace apps"
407	select ARC_HAS_ACCL_REGS
408	select ARC_DSP_HANDLED
409	select ARC_DSP_SAVE_RESTORE_REGS
410	help
411	  DSP extension presence in HW, support save / restore DSP registers to
412	  run DSP-enabled userspace applications
413
414config ARC_DSP_AGU_USERSPACE
415	bool "Support DSP with AGU for userspace apps"
416	select ARC_HAS_ACCL_REGS
417	select ARC_DSP_HANDLED
418	select ARC_DSP_SAVE_RESTORE_REGS
419	help
420	  DSP and AGU extensions presence in HW, support save / restore DSP
421	  and AGU registers to run DSP-enabled userspace applications
422endchoice
423
424config ARC_IRQ_NO_AUTOSAVE
425	bool "Disable hardware autosave regfile on interrupts"
426	default n
427	help
428	  On HS cores, taken interrupt auto saves the regfile on stack.
429	  This is programmable and can be optionally disabled in which case
430	  software INTERRUPT_PROLOGUE/EPILGUE do the needed work
431
432config ARC_LPB_DISABLE
433	bool "Disable loop buffer (LPB)"
434	help
435	  On HS cores, loop buffer (LPB) is programmable in runtime and can
436	  be optionally disabled.
437
438endif # ISA_ARCV2
439
440endmenu   # "ARC CPU Configuration"
441
442config LINUX_LINK_BASE
443	hex "Kernel link address"
444	default "0x80000000"
445	help
446	  ARC700 divides the 32 bit phy address space into two equal halves
447	  -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
448	  -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
449	  Typically Linux kernel is linked at the start of untransalted addr,
450	  hence the default value of 0x8zs.
451	  However some customers have peripherals mapped at this addr, so
452	  Linux needs to be scooted a bit.
453	  If you don't know what the above means, leave this setting alone.
454	  This needs to match memory start address specified in Device Tree
455
456config LINUX_RAM_BASE
457	hex "RAM base address"
458	default LINUX_LINK_BASE
459	help
460	  By default Linux is linked at base of RAM. However in some special
461	  cases (such as HSDK), Linux can't be linked at start of DDR, hence
462	  this option.
463
464config HIGHMEM
465	bool "High Memory Support"
466	select HAVE_ARCH_PFN_VALID
467	select KMAP_LOCAL
468	help
469	  With ARC 2G:2G address split, only upper 2G is directly addressable by
470	  kernel. Enable this to potentially allow access to rest of 2G and PAE
471	  in future
472
473config ARC_HAS_PAE40
474	bool "Support for the 40-bit Physical Address Extension"
475	depends on ISA_ARCV2
476	select HIGHMEM
477	select PHYS_ADDR_T_64BIT
478	help
479	  Enable access to physical memory beyond 4G, only supported on
480	  ARC cores with 40 bit Physical Addressing support
481
482config ARC_KVADDR_SIZE
483	int "Kernel Virtual Address Space size (MB)"
484	range 0 512
485	default "256"
486	help
487	  The kernel address space is carved out of 256MB of translated address
488	  space for catering to vmalloc, modules, pkmap, fixmap. This however may
489	  not suffice vmalloc requirements of a 4K CPU EZChip system. So allow
490	  this to be stretched to 512 MB (by extending into the reserved
491	  kernel-user gutter)
492
493config ARC_CURR_IN_REG
494	bool "cache current task pointer in gp"
495	default y
496	help
497	  This reserves gp register to point to Current Task in
498	  kernel mode eliding memory access for each access
499
500
501config ARC_EMUL_UNALIGNED
502	bool "Emulate unaligned memory access (userspace only)"
503	select SYSCTL_ARCH_UNALIGN_NO_WARN
504	select SYSCTL_ARCH_UNALIGN_ALLOW
505	depends on ISA_ARCOMPACT
506	help
507	  This enables misaligned 16 & 32 bit memory access from user space.
508	  Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
509	  potential bugs in code
510
511config HZ
512	int "Timer Frequency"
513	default 100
514
515config ARC_METAWARE_HLINK
516	bool "Support for Metaware debugger assisted Host access"
517	help
518	  This options allows a Linux userland apps to directly access
519	  host file system (open/creat/read/write etc) with help from
520	  Metaware Debugger. This can come in handy for Linux-host communication
521	  when there is no real usable peripheral such as EMAC.
522
523menuconfig ARC_DBG
524	bool "ARC debugging"
525	default y
526
527if ARC_DBG
528
529config ARC_DW2_UNWIND
530	bool "Enable DWARF specific kernel stack unwind"
531	default y
532	select KALLSYMS
533	help
534	  Compiles the kernel with DWARF unwind information and can be used
535	  to get stack backtraces.
536
537	  If you say Y here the resulting kernel image will be slightly larger
538	  but not slower, and it will give very useful debugging information.
539	  If you don't debug the kernel, you can say N, but we may not be able
540	  to solve problems without frame unwind information
541
542config ARC_DBG_JUMP_LABEL
543	bool "Paranoid checks in Static Keys (jump labels) code"
544	depends on JUMP_LABEL
545	default y if STATIC_KEYS_SELFTEST
546	help
547	  Enable paranoid checks and self-test of both ARC-specific and generic
548	  part of static keys (jump labels) related code.
549endif
550
551config ARC_BUILTIN_DTB_NAME
552	string "Built in DTB"
553	help
554	  Set the name of the DTB to embed in the vmlinux binary
555	  Leaving it blank selects the minimal "skeleton" dtb
556
557endmenu	 # "ARC Architecture Configuration"
558
559config ARCH_FORCE_MAX_ORDER
560	int "Maximum zone order"
561	default "11" if ARC_HUGEPAGE_16M
562	default "10"
563
564source "kernel/power/Kconfig"