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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * PCIe host controller driver for Mobiveil PCIe Host controller
4 *
5 * Copyright (c) 2018 Mobiveil Inc.
6 * Copyright 2019-2020 NXP
7 *
8 * Author: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
9 * Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
10 */
11
12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <linux/irq.h>
15#include <linux/irqchip/chained_irq.h>
16#include <linux/irqdomain.h>
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/msi.h>
20#include <linux/of_pci.h>
21#include <linux/pci.h>
22#include <linux/platform_device.h>
23#include <linux/slab.h>
24
25#include "pcie-mobiveil.h"
26
27static bool mobiveil_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
28{
29 /* Only one device down on each root port */
30 if (pci_is_root_bus(bus) && (devfn > 0))
31 return false;
32
33 /*
34 * Do not read more than one device on the bus directly
35 * attached to RC
36 */
37 if ((bus->primary == to_pci_host_bridge(bus->bridge)->busnr) && (PCI_SLOT(devfn) > 0))
38 return false;
39
40 return true;
41}
42
43/*
44 * mobiveil_pcie_map_bus - routine to get the configuration base of either
45 * root port or endpoint
46 */
47static void __iomem *mobiveil_pcie_map_bus(struct pci_bus *bus,
48 unsigned int devfn, int where)
49{
50 struct mobiveil_pcie *pcie = bus->sysdata;
51 struct mobiveil_root_port *rp = &pcie->rp;
52 u32 value;
53
54 if (!mobiveil_pcie_valid_device(bus, devfn))
55 return NULL;
56
57 /* RC config access */
58 if (pci_is_root_bus(bus))
59 return pcie->csr_axi_slave_base + where;
60
61 /*
62 * EP config access (in Config/APIO space)
63 * Program PEX Address base (31..16 bits) with appropriate value
64 * (BDF) in PAB_AXI_AMAP_PEX_WIN_L0 Register.
65 * Relies on pci_lock serialization
66 */
67 value = bus->number << PAB_BUS_SHIFT |
68 PCI_SLOT(devfn) << PAB_DEVICE_SHIFT |
69 PCI_FUNC(devfn) << PAB_FUNCTION_SHIFT;
70
71 mobiveil_csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));
72
73 return rp->config_axi_slave_base + where;
74}
75
76static struct pci_ops mobiveil_pcie_ops = {
77 .map_bus = mobiveil_pcie_map_bus,
78 .read = pci_generic_config_read,
79 .write = pci_generic_config_write,
80};
81
82static void mobiveil_pcie_isr(struct irq_desc *desc)
83{
84 struct irq_chip *chip = irq_desc_get_chip(desc);
85 struct mobiveil_pcie *pcie = irq_desc_get_handler_data(desc);
86 struct device *dev = &pcie->pdev->dev;
87 struct mobiveil_root_port *rp = &pcie->rp;
88 struct mobiveil_msi *msi = &rp->msi;
89 u32 msi_data, msi_addr_lo, msi_addr_hi;
90 u32 intr_status, msi_status;
91 unsigned long shifted_status;
92 u32 bit, val, mask;
93
94 /*
95 * The core provides a single interrupt for both INTx/MSI messages.
96 * So we'll read both INTx and MSI status
97 */
98
99 chained_irq_enter(chip, desc);
100
101 /* read INTx status */
102 val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
103 mask = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
104 intr_status = val & mask;
105
106 /* Handle INTx */
107 if (intr_status & PAB_INTP_INTX_MASK) {
108 shifted_status = mobiveil_csr_readl(pcie,
109 PAB_INTP_AMBA_MISC_STAT);
110 shifted_status &= PAB_INTP_INTX_MASK;
111 shifted_status >>= PAB_INTX_START;
112 do {
113 for_each_set_bit(bit, &shifted_status, PCI_NUM_INTX) {
114 int ret;
115 ret = generic_handle_domain_irq(rp->intx_domain,
116 bit + 1);
117 if (ret)
118 dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n",
119 bit);
120
121 /* clear interrupt handled */
122 mobiveil_csr_writel(pcie,
123 1 << (PAB_INTX_START + bit),
124 PAB_INTP_AMBA_MISC_STAT);
125 }
126
127 shifted_status = mobiveil_csr_readl(pcie,
128 PAB_INTP_AMBA_MISC_STAT);
129 shifted_status &= PAB_INTP_INTX_MASK;
130 shifted_status >>= PAB_INTX_START;
131 } while (shifted_status != 0);
132 }
133
134 /* read extra MSI status register */
135 msi_status = readl_relaxed(pcie->apb_csr_base + MSI_STATUS_OFFSET);
136
137 /* handle MSI interrupts */
138 while (msi_status & 1) {
139 msi_data = readl_relaxed(pcie->apb_csr_base + MSI_DATA_OFFSET);
140
141 /*
142 * MSI_STATUS_OFFSET register gets updated to zero
143 * once we pop not only the MSI data but also address
144 * from MSI hardware FIFO. So keeping these following
145 * two dummy reads.
146 */
147 msi_addr_lo = readl_relaxed(pcie->apb_csr_base +
148 MSI_ADDR_L_OFFSET);
149 msi_addr_hi = readl_relaxed(pcie->apb_csr_base +
150 MSI_ADDR_H_OFFSET);
151 dev_dbg(dev, "MSI registers, data: %08x, addr: %08x:%08x\n",
152 msi_data, msi_addr_hi, msi_addr_lo);
153
154 generic_handle_domain_irq(msi->dev_domain, msi_data);
155
156 msi_status = readl_relaxed(pcie->apb_csr_base +
157 MSI_STATUS_OFFSET);
158 }
159
160 /* Clear the interrupt status */
161 mobiveil_csr_writel(pcie, intr_status, PAB_INTP_AMBA_MISC_STAT);
162 chained_irq_exit(chip, desc);
163}
164
165static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)
166{
167 struct device *dev = &pcie->pdev->dev;
168 struct platform_device *pdev = pcie->pdev;
169 struct device_node *node = dev->of_node;
170 struct mobiveil_root_port *rp = &pcie->rp;
171 struct resource *res;
172
173 /* map config resource */
174 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
175 "config_axi_slave");
176 rp->config_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
177 if (IS_ERR(rp->config_axi_slave_base))
178 return PTR_ERR(rp->config_axi_slave_base);
179 rp->ob_io_res = res;
180
181 /* map csr resource */
182 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
183 "csr_axi_slave");
184 pcie->csr_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
185 if (IS_ERR(pcie->csr_axi_slave_base))
186 return PTR_ERR(pcie->csr_axi_slave_base);
187 pcie->pcie_reg_base = res->start;
188
189 /* read the number of windows requested */
190 if (of_property_read_u32(node, "apio-wins", &pcie->apio_wins))
191 pcie->apio_wins = MAX_PIO_WINDOWS;
192
193 if (of_property_read_u32(node, "ppio-wins", &pcie->ppio_wins))
194 pcie->ppio_wins = MAX_PIO_WINDOWS;
195
196 return 0;
197}
198
199static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie)
200{
201 phys_addr_t msg_addr = pcie->pcie_reg_base;
202 struct mobiveil_msi *msi = &pcie->rp.msi;
203
204 msi->num_of_vectors = PCI_NUM_MSI;
205 msi->msi_pages_phys = (phys_addr_t)msg_addr;
206
207 writel_relaxed(lower_32_bits(msg_addr),
208 pcie->apb_csr_base + MSI_BASE_LO_OFFSET);
209 writel_relaxed(upper_32_bits(msg_addr),
210 pcie->apb_csr_base + MSI_BASE_HI_OFFSET);
211 writel_relaxed(4096, pcie->apb_csr_base + MSI_SIZE_OFFSET);
212 writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET);
213}
214
215int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit)
216{
217 struct mobiveil_root_port *rp = &pcie->rp;
218 struct pci_host_bridge *bridge = rp->bridge;
219 u32 value, pab_ctrl, type;
220 struct resource_entry *win;
221
222 pcie->ib_wins_configured = 0;
223 pcie->ob_wins_configured = 0;
224
225 if (!reinit) {
226 /* setup bus numbers */
227 value = mobiveil_csr_readl(pcie, PCI_PRIMARY_BUS);
228 value &= 0xff000000;
229 value |= 0x00ff0100;
230 mobiveil_csr_writel(pcie, value, PCI_PRIMARY_BUS);
231 }
232
233 /*
234 * program Bus Master Enable Bit in Command Register in PAB Config
235 * Space
236 */
237 value = mobiveil_csr_readl(pcie, PCI_COMMAND);
238 value |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
239 mobiveil_csr_writel(pcie, value, PCI_COMMAND);
240
241 /*
242 * program PIO Enable Bit to 1 (and PEX PIO Enable to 1) in PAB_CTRL
243 * register
244 */
245 pab_ctrl = mobiveil_csr_readl(pcie, PAB_CTRL);
246 pab_ctrl |= (1 << AMBA_PIO_ENABLE_SHIFT) | (1 << PEX_PIO_ENABLE_SHIFT);
247 mobiveil_csr_writel(pcie, pab_ctrl, PAB_CTRL);
248
249 /*
250 * program PIO Enable Bit to 1 and Config Window Enable Bit to 1 in
251 * PAB_AXI_PIO_CTRL Register
252 */
253 value = mobiveil_csr_readl(pcie, PAB_AXI_PIO_CTRL);
254 value |= APIO_EN_MASK;
255 mobiveil_csr_writel(pcie, value, PAB_AXI_PIO_CTRL);
256
257 /* Enable PCIe PIO master */
258 value = mobiveil_csr_readl(pcie, PAB_PEX_PIO_CTRL);
259 value |= 1 << PIO_ENABLE_SHIFT;
260 mobiveil_csr_writel(pcie, value, PAB_PEX_PIO_CTRL);
261
262 /*
263 * we'll program one outbound window for config reads and
264 * another default inbound window for all the upstream traffic
265 * rest of the outbound windows will be configured according to
266 * the "ranges" field defined in device tree
267 */
268
269 /* config outbound translation window */
270 program_ob_windows(pcie, WIN_NUM_0, rp->ob_io_res->start, 0,
271 CFG_WINDOW_TYPE, resource_size(rp->ob_io_res));
272
273 /* memory inbound translation window */
274 program_ib_windows(pcie, WIN_NUM_0, 0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
275
276 /* Get the I/O and memory ranges from DT */
277 resource_list_for_each_entry(win, &bridge->windows) {
278 if (resource_type(win->res) == IORESOURCE_MEM)
279 type = MEM_WINDOW_TYPE;
280 else if (resource_type(win->res) == IORESOURCE_IO)
281 type = IO_WINDOW_TYPE;
282 else
283 continue;
284
285 /* configure outbound translation window */
286 program_ob_windows(pcie, pcie->ob_wins_configured,
287 win->res->start,
288 win->res->start - win->offset,
289 type, resource_size(win->res));
290 }
291
292 /* fixup for PCIe class register */
293 value = mobiveil_csr_readl(pcie, PAB_INTP_AXI_PIO_CLASS);
294 value &= 0xff;
295 value |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8;
296 mobiveil_csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS);
297
298 return 0;
299}
300
301static void mobiveil_mask_intx_irq(struct irq_data *data)
302{
303 struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(data);
304 struct mobiveil_root_port *rp;
305 unsigned long flags;
306 u32 mask, shifted_val;
307
308 rp = &pcie->rp;
309 mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
310 raw_spin_lock_irqsave(&rp->intx_mask_lock, flags);
311 shifted_val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
312 shifted_val &= ~mask;
313 mobiveil_csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
314 raw_spin_unlock_irqrestore(&rp->intx_mask_lock, flags);
315}
316
317static void mobiveil_unmask_intx_irq(struct irq_data *data)
318{
319 struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(data);
320 struct mobiveil_root_port *rp;
321 unsigned long flags;
322 u32 shifted_val, mask;
323
324 rp = &pcie->rp;
325 mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
326 raw_spin_lock_irqsave(&rp->intx_mask_lock, flags);
327 shifted_val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
328 shifted_val |= mask;
329 mobiveil_csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
330 raw_spin_unlock_irqrestore(&rp->intx_mask_lock, flags);
331}
332
333static struct irq_chip intx_irq_chip = {
334 .name = "mobiveil_pcie:intx",
335 .irq_enable = mobiveil_unmask_intx_irq,
336 .irq_disable = mobiveil_mask_intx_irq,
337 .irq_mask = mobiveil_mask_intx_irq,
338 .irq_unmask = mobiveil_unmask_intx_irq,
339};
340
341/* routine to setup the INTx related data */
342static int mobiveil_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
343 irq_hw_number_t hwirq)
344{
345 irq_set_chip_and_handler(irq, &intx_irq_chip, handle_level_irq);
346 irq_set_chip_data(irq, domain->host_data);
347
348 return 0;
349}
350
351/* INTx domain operations structure */
352static const struct irq_domain_ops intx_domain_ops = {
353 .map = mobiveil_pcie_intx_map,
354};
355
356static struct irq_chip mobiveil_msi_irq_chip = {
357 .name = "Mobiveil PCIe MSI",
358 .irq_mask = pci_msi_mask_irq,
359 .irq_unmask = pci_msi_unmask_irq,
360};
361
362static struct msi_domain_info mobiveil_msi_domain_info = {
363 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
364 MSI_FLAG_PCI_MSIX),
365 .chip = &mobiveil_msi_irq_chip,
366};
367
368static void mobiveil_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
369{
370 struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(data);
371 phys_addr_t addr = pcie->pcie_reg_base + (data->hwirq * sizeof(int));
372
373 msg->address_lo = lower_32_bits(addr);
374 msg->address_hi = upper_32_bits(addr);
375 msg->data = data->hwirq;
376
377 dev_dbg(&pcie->pdev->dev, "msi#%d address_hi %#x address_lo %#x\n",
378 (int)data->hwirq, msg->address_hi, msg->address_lo);
379}
380
381static int mobiveil_msi_set_affinity(struct irq_data *irq_data,
382 const struct cpumask *mask, bool force)
383{
384 return -EINVAL;
385}
386
387static struct irq_chip mobiveil_msi_bottom_irq_chip = {
388 .name = "Mobiveil MSI",
389 .irq_compose_msi_msg = mobiveil_compose_msi_msg,
390 .irq_set_affinity = mobiveil_msi_set_affinity,
391};
392
393static int mobiveil_irq_msi_domain_alloc(struct irq_domain *domain,
394 unsigned int virq,
395 unsigned int nr_irqs, void *args)
396{
397 struct mobiveil_pcie *pcie = domain->host_data;
398 struct mobiveil_msi *msi = &pcie->rp.msi;
399 unsigned long bit;
400
401 WARN_ON(nr_irqs != 1);
402 mutex_lock(&msi->lock);
403
404 bit = find_first_zero_bit(msi->msi_irq_in_use, msi->num_of_vectors);
405 if (bit >= msi->num_of_vectors) {
406 mutex_unlock(&msi->lock);
407 return -ENOSPC;
408 }
409
410 set_bit(bit, msi->msi_irq_in_use);
411
412 mutex_unlock(&msi->lock);
413
414 irq_domain_set_info(domain, virq, bit, &mobiveil_msi_bottom_irq_chip,
415 domain->host_data, handle_level_irq, NULL, NULL);
416 return 0;
417}
418
419static void mobiveil_irq_msi_domain_free(struct irq_domain *domain,
420 unsigned int virq,
421 unsigned int nr_irqs)
422{
423 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
424 struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(d);
425 struct mobiveil_msi *msi = &pcie->rp.msi;
426
427 mutex_lock(&msi->lock);
428
429 if (!test_bit(d->hwirq, msi->msi_irq_in_use))
430 dev_err(&pcie->pdev->dev, "trying to free unused MSI#%lu\n",
431 d->hwirq);
432 else
433 __clear_bit(d->hwirq, msi->msi_irq_in_use);
434
435 mutex_unlock(&msi->lock);
436}
437static const struct irq_domain_ops msi_domain_ops = {
438 .alloc = mobiveil_irq_msi_domain_alloc,
439 .free = mobiveil_irq_msi_domain_free,
440};
441
442static int mobiveil_allocate_msi_domains(struct mobiveil_pcie *pcie)
443{
444 struct device *dev = &pcie->pdev->dev;
445 struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node);
446 struct mobiveil_msi *msi = &pcie->rp.msi;
447
448 mutex_init(&msi->lock);
449 msi->dev_domain = irq_domain_add_linear(NULL, msi->num_of_vectors,
450 &msi_domain_ops, pcie);
451 if (!msi->dev_domain) {
452 dev_err(dev, "failed to create IRQ domain\n");
453 return -ENOMEM;
454 }
455
456 msi->msi_domain = pci_msi_create_irq_domain(fwnode,
457 &mobiveil_msi_domain_info,
458 msi->dev_domain);
459 if (!msi->msi_domain) {
460 dev_err(dev, "failed to create MSI domain\n");
461 irq_domain_remove(msi->dev_domain);
462 return -ENOMEM;
463 }
464
465 return 0;
466}
467
468static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie)
469{
470 struct device *dev = &pcie->pdev->dev;
471 struct device_node *node = dev->of_node;
472 struct mobiveil_root_port *rp = &pcie->rp;
473
474 /* setup INTx */
475 rp->intx_domain = irq_domain_add_linear(node, PCI_NUM_INTX,
476 &intx_domain_ops, pcie);
477
478 if (!rp->intx_domain) {
479 dev_err(dev, "Failed to get a INTx IRQ domain\n");
480 return -ENOMEM;
481 }
482
483 raw_spin_lock_init(&rp->intx_mask_lock);
484
485 /* setup MSI */
486 return mobiveil_allocate_msi_domains(pcie);
487}
488
489static int mobiveil_pcie_integrated_interrupt_init(struct mobiveil_pcie *pcie)
490{
491 struct platform_device *pdev = pcie->pdev;
492 struct device *dev = &pdev->dev;
493 struct mobiveil_root_port *rp = &pcie->rp;
494 struct resource *res;
495 int ret;
496
497 /* map MSI config resource */
498 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apb_csr");
499 pcie->apb_csr_base = devm_pci_remap_cfg_resource(dev, res);
500 if (IS_ERR(pcie->apb_csr_base))
501 return PTR_ERR(pcie->apb_csr_base);
502
503 /* setup MSI hardware registers */
504 mobiveil_pcie_enable_msi(pcie);
505
506 rp->irq = platform_get_irq(pdev, 0);
507 if (rp->irq < 0)
508 return rp->irq;
509
510 /* initialize the IRQ domains */
511 ret = mobiveil_pcie_init_irq_domain(pcie);
512 if (ret) {
513 dev_err(dev, "Failed creating IRQ Domain\n");
514 return ret;
515 }
516
517 irq_set_chained_handler_and_data(rp->irq, mobiveil_pcie_isr, pcie);
518
519 /* Enable interrupts */
520 mobiveil_csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK),
521 PAB_INTP_AMBA_MISC_ENB);
522
523
524 return 0;
525}
526
527static int mobiveil_pcie_interrupt_init(struct mobiveil_pcie *pcie)
528{
529 struct mobiveil_root_port *rp = &pcie->rp;
530
531 if (rp->ops->interrupt_init)
532 return rp->ops->interrupt_init(pcie);
533
534 return mobiveil_pcie_integrated_interrupt_init(pcie);
535}
536
537static bool mobiveil_pcie_is_bridge(struct mobiveil_pcie *pcie)
538{
539 u32 header_type;
540
541 header_type = mobiveil_csr_readb(pcie, PCI_HEADER_TYPE);
542 header_type &= PCI_HEADER_TYPE_MASK;
543
544 return header_type == PCI_HEADER_TYPE_BRIDGE;
545}
546
547int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie)
548{
549 struct mobiveil_root_port *rp = &pcie->rp;
550 struct pci_host_bridge *bridge = rp->bridge;
551 struct device *dev = &pcie->pdev->dev;
552 int ret;
553
554 ret = mobiveil_pcie_parse_dt(pcie);
555 if (ret) {
556 dev_err(dev, "Parsing DT failed, ret: %x\n", ret);
557 return ret;
558 }
559
560 if (!mobiveil_pcie_is_bridge(pcie))
561 return -ENODEV;
562
563 /*
564 * configure all inbound and outbound windows and prepare the RC for
565 * config access
566 */
567 ret = mobiveil_host_init(pcie, false);
568 if (ret) {
569 dev_err(dev, "Failed to initialize host\n");
570 return ret;
571 }
572
573 ret = mobiveil_pcie_interrupt_init(pcie);
574 if (ret) {
575 dev_err(dev, "Interrupt init failed\n");
576 return ret;
577 }
578
579 /* Initialize bridge */
580 bridge->sysdata = pcie;
581 bridge->ops = &mobiveil_pcie_ops;
582
583 ret = mobiveil_bringup_link(pcie);
584 if (ret) {
585 dev_info(dev, "link bring-up failed\n");
586 return ret;
587 }
588
589 return pci_host_probe(bridge);
590}