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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright(C) 2015 Linaro Limited. All rights reserved.
4 * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
5 */
6
7#ifndef _CORESIGHT_TMC_H
8#define _CORESIGHT_TMC_H
9
10#include <linux/dma-mapping.h>
11#include <linux/idr.h>
12#include <linux/miscdevice.h>
13#include <linux/mutex.h>
14#include <linux/refcount.h>
15
16#define TMC_RSZ 0x004
17#define TMC_STS 0x00c
18#define TMC_RRD 0x010
19#define TMC_RRP 0x014
20#define TMC_RWP 0x018
21#define TMC_TRG 0x01c
22#define TMC_CTL 0x020
23#define TMC_RWD 0x024
24#define TMC_MODE 0x028
25#define TMC_LBUFLEVEL 0x02c
26#define TMC_CBUFLEVEL 0x030
27#define TMC_BUFWM 0x034
28#define TMC_RRPHI 0x038
29#define TMC_RWPHI 0x03c
30#define TMC_AXICTL 0x110
31#define TMC_DBALO 0x118
32#define TMC_DBAHI 0x11c
33#define TMC_FFSR 0x300
34#define TMC_FFCR 0x304
35#define TMC_PSCR 0x308
36#define TMC_ITMISCOP0 0xee0
37#define TMC_ITTRFLIN 0xee8
38#define TMC_ITATBDATA0 0xeec
39#define TMC_ITATBCTR2 0xef0
40#define TMC_ITATBCTR1 0xef4
41#define TMC_ITATBCTR0 0xef8
42#define TMC_AUTHSTATUS 0xfb8
43
44/* register description */
45/* TMC_CTL - 0x020 */
46#define TMC_CTL_CAPT_EN BIT(0)
47/* TMC_STS - 0x00C */
48#define TMC_STS_TMCREADY_BIT 2
49#define TMC_STS_FULL BIT(0)
50#define TMC_STS_TRIGGERED BIT(1)
51#define TMC_STS_MEMERR BIT(5)
52/*
53 * TMC_AXICTL - 0x110
54 *
55 * TMC AXICTL format for SoC-400
56 * Bits [0-1] : ProtCtrlBit0-1
57 * Bits [2-5] : CacheCtrlBits 0-3 (AXCACHE)
58 * Bit 6 : Reserved
59 * Bit 7 : ScatterGatherMode
60 * Bits [8-11] : WrBurstLen
61 * Bits [12-31] : Reserved.
62 * TMC AXICTL format for SoC-600, as above except:
63 * Bits [2-5] : AXI WCACHE
64 * Bits [16-19] : AXI RCACHE
65 * Bits [20-31] : Reserved
66 */
67#define TMC_AXICTL_CLEAR_MASK 0xfbf
68#define TMC_AXICTL_ARCACHE_MASK (0xf << 16)
69
70#define TMC_AXICTL_PROT_CTL_B0 BIT(0)
71#define TMC_AXICTL_PROT_CTL_B1 BIT(1)
72#define TMC_AXICTL_SCT_GAT_MODE BIT(7)
73#define TMC_AXICTL_WR_BURST(v) (((v) & 0xf) << 8)
74#define TMC_AXICTL_WR_BURST_16 0xf
75/* Write-back Read and Write-allocate */
76#define TMC_AXICTL_AXCACHE_OS (0xf << 2)
77#define TMC_AXICTL_ARCACHE_OS (0xf << 16)
78
79/* TMC_FFCR - 0x304 */
80#define TMC_FFCR_FLUSHMAN_BIT 6
81#define TMC_FFCR_EN_FMT BIT(0)
82#define TMC_FFCR_EN_TI BIT(1)
83#define TMC_FFCR_FON_FLIN BIT(4)
84#define TMC_FFCR_FON_TRIG_EVT BIT(5)
85#define TMC_FFCR_TRIGON_TRIGIN BIT(8)
86#define TMC_FFCR_STOP_ON_FLUSH BIT(12)
87
88
89#define TMC_DEVID_NOSCAT BIT(24)
90
91#define TMC_DEVID_AXIAW_VALID BIT(16)
92#define TMC_DEVID_AXIAW_SHIFT 17
93#define TMC_DEVID_AXIAW_MASK 0x7f
94
95#define TMC_AUTH_NSID_MASK GENMASK(1, 0)
96
97enum tmc_config_type {
98 TMC_CONFIG_TYPE_ETB,
99 TMC_CONFIG_TYPE_ETR,
100 TMC_CONFIG_TYPE_ETF,
101};
102
103enum tmc_mode {
104 TMC_MODE_CIRCULAR_BUFFER,
105 TMC_MODE_SOFTWARE_FIFO,
106 TMC_MODE_HARDWARE_FIFO,
107};
108
109enum tmc_mem_intf_width {
110 TMC_MEM_INTF_WIDTH_32BITS = 1,
111 TMC_MEM_INTF_WIDTH_64BITS = 2,
112 TMC_MEM_INTF_WIDTH_128BITS = 4,
113 TMC_MEM_INTF_WIDTH_256BITS = 8,
114};
115
116/* TMC ETR Capability bit definitions */
117#define TMC_ETR_SG (0x1U << 0)
118/* ETR has separate read/write cache encodings */
119#define TMC_ETR_AXI_ARCACHE (0x1U << 1)
120/*
121 * TMC_ETR_SAVE_RESTORE - Values of RRP/RWP/STS.Full are
122 * retained when TMC leaves Disabled state, allowing us to continue
123 * the tracing from a point where we stopped. This also implies that
124 * the RRP/RWP/STS.Full should always be programmed to the correct
125 * value. Unfortunately this is not advertised by the hardware,
126 * so we have to rely on PID of the IP to detect the functionality.
127 */
128#define TMC_ETR_SAVE_RESTORE (0x1U << 2)
129
130/* Coresight SoC-600 TMC-ETR unadvertised capabilities */
131#define CORESIGHT_SOC_600_ETR_CAPS \
132 (TMC_ETR_SAVE_RESTORE | TMC_ETR_AXI_ARCACHE)
133
134enum etr_mode {
135 ETR_MODE_FLAT, /* Uses contiguous flat buffer */
136 ETR_MODE_ETR_SG, /* Uses in-built TMC ETR SG mechanism */
137 ETR_MODE_CATU, /* Use SG mechanism in CATU */
138 ETR_MODE_AUTO, /* Use the default mechanism */
139};
140
141struct etr_buf_operations;
142
143/**
144 * struct etr_buf - Details of the buffer used by ETR
145 * refcount ; Number of sources currently using this etr_buf.
146 * @mode : Mode of the ETR buffer, contiguous, Scatter Gather etc.
147 * @full : Trace data overflow
148 * @size : Size of the buffer.
149 * @hwaddr : Address to be programmed in the TMC:DBA{LO,HI}
150 * @offset : Offset of the trace data in the buffer for consumption.
151 * @len : Available trace data @buf (may round up to the beginning).
152 * @ops : ETR buffer operations for the mode.
153 * @private : Backend specific information for the buf
154 */
155struct etr_buf {
156 refcount_t refcount;
157 enum etr_mode mode;
158 bool full;
159 ssize_t size;
160 dma_addr_t hwaddr;
161 unsigned long offset;
162 s64 len;
163 const struct etr_buf_operations *ops;
164 void *private;
165};
166
167/**
168 * struct tmc_drvdata - specifics associated to an TMC component
169 * @base: memory mapped base address for this component.
170 * @csdev: component vitals needed by the framework.
171 * @miscdev: specifics to handle "/dev/xyz.tmc" entry.
172 * @spinlock: only one at a time pls.
173 * @pid: Process ID of the process being monitored by the session
174 * that is using this component.
175 * @buf: Snapshot of the trace data for ETF/ETB.
176 * @etr_buf: details of buffer used in TMC-ETR
177 * @len: size of the available trace for ETF/ETB.
178 * @size: trace buffer size for this TMC (common for all modes).
179 * @max_burst_size: The maximum burst size that can be initiated by
180 * TMC-ETR on AXI bus.
181 * @mode: how this TMC is being used.
182 * @config_type: TMC variant, must be of type @tmc_config_type.
183 * @memwidth: width of the memory interface databus, in bytes.
184 * @trigger_cntr: amount of words to store after a trigger.
185 * @etr_caps: Bitmask of capabilities of the TMC ETR, inferred from the
186 * device configuration register (DEVID)
187 * @idr: Holds etr_bufs allocated for this ETR.
188 * @idr_mutex: Access serialisation for idr.
189 * @sysfs_buf: SYSFS buffer for ETR.
190 * @perf_buf: PERF buffer for ETR.
191 */
192struct tmc_drvdata {
193 void __iomem *base;
194 struct coresight_device *csdev;
195 struct miscdevice miscdev;
196 spinlock_t spinlock;
197 pid_t pid;
198 bool reading;
199 union {
200 char *buf; /* TMC ETB */
201 struct etr_buf *etr_buf; /* TMC ETR */
202 };
203 u32 len;
204 u32 size;
205 u32 max_burst_size;
206 u32 mode;
207 enum tmc_config_type config_type;
208 enum tmc_mem_intf_width memwidth;
209 u32 trigger_cntr;
210 u32 etr_caps;
211 enum etr_mode etr_mode;
212 struct idr idr;
213 struct mutex idr_mutex;
214 struct etr_buf *sysfs_buf;
215 struct etr_buf *perf_buf;
216};
217
218struct etr_buf_operations {
219 int (*alloc)(struct tmc_drvdata *drvdata, struct etr_buf *etr_buf,
220 int node, void **pages);
221 void (*sync)(struct etr_buf *etr_buf, u64 rrp, u64 rwp);
222 ssize_t (*get_data)(struct etr_buf *etr_buf, u64 offset, size_t len,
223 char **bufpp);
224 void (*free)(struct etr_buf *etr_buf);
225};
226
227/**
228 * struct tmc_pages - Collection of pages used for SG.
229 * @nr_pages: Number of pages in the list.
230 * @daddrs: Array of DMA'able page address.
231 * @pages: Array pages for the buffer.
232 */
233struct tmc_pages {
234 int nr_pages;
235 dma_addr_t *daddrs;
236 struct page **pages;
237};
238
239/*
240 * struct tmc_sg_table - Generic SG table for TMC
241 * @dev: Device for DMA allocations
242 * @table_vaddr: Contiguous Virtual address for PageTable
243 * @data_vaddr: Contiguous Virtual address for Data Buffer
244 * @table_daddr: DMA address of the PageTable base
245 * @node: Node for Page allocations
246 * @table_pages: List of pages & dma address for Table
247 * @data_pages: List of pages & dma address for Data
248 */
249struct tmc_sg_table {
250 struct device *dev;
251 void *table_vaddr;
252 void *data_vaddr;
253 dma_addr_t table_daddr;
254 int node;
255 struct tmc_pages table_pages;
256 struct tmc_pages data_pages;
257};
258
259/* Generic functions */
260int tmc_wait_for_tmcready(struct tmc_drvdata *drvdata);
261void tmc_flush_and_stop(struct tmc_drvdata *drvdata);
262void tmc_enable_hw(struct tmc_drvdata *drvdata);
263void tmc_disable_hw(struct tmc_drvdata *drvdata);
264u32 tmc_get_memwidth_mask(struct tmc_drvdata *drvdata);
265
266/* ETB/ETF functions */
267int tmc_read_prepare_etb(struct tmc_drvdata *drvdata);
268int tmc_read_unprepare_etb(struct tmc_drvdata *drvdata);
269extern const struct coresight_ops tmc_etb_cs_ops;
270extern const struct coresight_ops tmc_etf_cs_ops;
271
272ssize_t tmc_etb_get_sysfs_trace(struct tmc_drvdata *drvdata,
273 loff_t pos, size_t len, char **bufpp);
274/* ETR functions */
275int tmc_read_prepare_etr(struct tmc_drvdata *drvdata);
276int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata);
277void tmc_etr_disable_hw(struct tmc_drvdata *drvdata);
278extern const struct coresight_ops tmc_etr_cs_ops;
279ssize_t tmc_etr_get_sysfs_trace(struct tmc_drvdata *drvdata,
280 loff_t pos, size_t len, char **bufpp);
281
282
283#define TMC_REG_PAIR(name, lo_off, hi_off) \
284static inline u64 \
285tmc_read_##name(struct tmc_drvdata *drvdata) \
286{ \
287 return csdev_access_relaxed_read_pair(&drvdata->csdev->access, lo_off, hi_off); \
288} \
289static inline void \
290tmc_write_##name(struct tmc_drvdata *drvdata, u64 val) \
291{ \
292 csdev_access_relaxed_write_pair(&drvdata->csdev->access, val, lo_off, hi_off); \
293}
294
295TMC_REG_PAIR(rrp, TMC_RRP, TMC_RRPHI)
296TMC_REG_PAIR(rwp, TMC_RWP, TMC_RWPHI)
297TMC_REG_PAIR(dba, TMC_DBALO, TMC_DBAHI)
298
299/* Initialise the caps from unadvertised static capabilities of the device */
300static inline void tmc_etr_init_caps(struct tmc_drvdata *drvdata, u32 dev_caps)
301{
302 WARN_ON(drvdata->etr_caps);
303 drvdata->etr_caps = dev_caps;
304}
305
306static inline void tmc_etr_set_cap(struct tmc_drvdata *drvdata, u32 cap)
307{
308 drvdata->etr_caps |= cap;
309}
310
311static inline bool tmc_etr_has_cap(struct tmc_drvdata *drvdata, u32 cap)
312{
313 return !!(drvdata->etr_caps & cap);
314}
315
316struct tmc_sg_table *tmc_alloc_sg_table(struct device *dev,
317 int node,
318 int nr_tpages,
319 int nr_dpages,
320 void **pages);
321void tmc_free_sg_table(struct tmc_sg_table *sg_table);
322void tmc_sg_table_sync_table(struct tmc_sg_table *sg_table);
323void tmc_sg_table_sync_data_range(struct tmc_sg_table *table,
324 u64 offset, u64 size);
325ssize_t tmc_sg_table_get_data(struct tmc_sg_table *sg_table,
326 u64 offset, size_t len, char **bufpp);
327static inline unsigned long
328tmc_sg_table_buf_size(struct tmc_sg_table *sg_table)
329{
330 return (unsigned long)sg_table->data_pages.nr_pages << PAGE_SHIFT;
331}
332
333struct coresight_device *tmc_etr_get_catu_device(struct tmc_drvdata *drvdata);
334
335void tmc_etr_set_catu_ops(const struct etr_buf_operations *catu);
336void tmc_etr_remove_catu_ops(void);
337struct etr_buf *tmc_etr_get_buffer(struct coresight_device *csdev,
338 enum cs_mode mode, void *data);
339extern const struct attribute_group coresight_etr_group;
340
341#endif