Loading...
Note: File does not exist in v3.5.6.
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2023, Linaro Limited
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/mod_devicetable.h>
9#include <linux/module.h>
10#include <linux/platform_device.h>
11#include <linux/regmap.h>
12
13#include <dt-bindings/clock/qcom,sm6125-gpucc.h>
14
15#include "clk-alpha-pll.h"
16#include "clk-branch.h"
17#include "clk-rcg.h"
18#include "clk-regmap.h"
19#include "clk-regmap-divider.h"
20#include "clk-regmap-mux.h"
21#include "clk-regmap-phy-mux.h"
22#include "gdsc.h"
23#include "reset.h"
24
25enum {
26 DT_BI_TCXO,
27 DT_GCC_GPU_GPLL0_CLK_SRC,
28};
29
30enum {
31 P_BI_TCXO,
32 P_GPLL0_OUT_MAIN,
33 P_GPU_CC_PLL0_2X_CLK,
34 P_GPU_CC_PLL0_OUT_AUX2,
35 P_GPU_CC_PLL1_OUT_AUX,
36 P_GPU_CC_PLL1_OUT_AUX2,
37};
38
39static struct pll_vco gpu_cc_pll_vco[] = {
40 { 1000000000, 2000000000, 0 },
41 { 500000000, 1000000000, 2 },
42};
43
44/* 1020MHz configuration */
45static const struct alpha_pll_config gpu_pll0_config = {
46 .l = 0x35,
47 .config_ctl_val = 0x4001055b,
48 .alpha_hi = 0x20,
49 .alpha = 0x00,
50 .alpha_en_mask = BIT(24),
51 .vco_val = 0x0 << 20,
52 .vco_mask = 0x3 << 20,
53 .aux2_output_mask = BIT(2),
54};
55
56/* 930MHz configuration */
57static const struct alpha_pll_config gpu_pll1_config = {
58 .l = 0x30,
59 .config_ctl_val = 0x4001055b,
60 .alpha_hi = 0x70,
61 .alpha = 0x00,
62 .alpha_en_mask = BIT(24),
63 .vco_val = 0x2 << 20,
64 .vco_mask = 0x3 << 20,
65 .aux2_output_mask = BIT(2),
66};
67
68static struct clk_alpha_pll gpu_cc_pll0_out_aux2 = {
69 .offset = 0x0,
70 .vco_table = gpu_cc_pll_vco,
71 .num_vco = ARRAY_SIZE(gpu_cc_pll_vco),
72 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
73 .flags = SUPPORTS_DYNAMIC_UPDATE,
74 .clkr = {
75 .hw.init = &(struct clk_init_data){
76 .name = "gpu_cc_pll0_out_aux2",
77 .parent_data = &(const struct clk_parent_data) {
78 .index = DT_BI_TCXO,
79 },
80 .num_parents = 1,
81 .ops = &clk_alpha_pll_ops,
82 },
83 },
84};
85
86static struct clk_alpha_pll gpu_cc_pll1_out_aux2 = {
87 .offset = 0x100,
88 .vco_table = gpu_cc_pll_vco,
89 .num_vco = ARRAY_SIZE(gpu_cc_pll_vco),
90 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
91 .flags = SUPPORTS_DYNAMIC_UPDATE,
92 .clkr = {
93 .hw.init = &(struct clk_init_data){
94 .name = "gpu_cc_pll1_out_aux2",
95 .parent_data = &(const struct clk_parent_data) {
96 .index = DT_BI_TCXO,
97 },
98 .num_parents = 1,
99 .ops = &clk_alpha_pll_ops,
100 },
101 },
102};
103
104static const struct parent_map gpu_cc_parent_map_0[] = {
105 { P_BI_TCXO, 0 },
106 { P_GPLL0_OUT_MAIN, 5 },
107};
108
109static const struct clk_parent_data gpu_cc_parent_data_0[] = {
110 { .index = DT_BI_TCXO },
111 { .index = DT_GCC_GPU_GPLL0_CLK_SRC },
112};
113
114static const struct parent_map gpu_cc_parent_map_1[] = {
115 { P_BI_TCXO, 0 },
116 { P_GPU_CC_PLL0_OUT_AUX2, 2 },
117 { P_GPU_CC_PLL1_OUT_AUX2, 4 },
118};
119
120static const struct clk_parent_data gpu_cc_parent_data_1[] = {
121 { .index = DT_BI_TCXO },
122 { .hw = &gpu_cc_pll0_out_aux2.clkr.hw },
123 { .hw = &gpu_cc_pll1_out_aux2.clkr.hw },
124};
125
126static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
127 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
128 { }
129};
130
131static struct clk_rcg2 gpu_cc_gmu_clk_src = {
132 .cmd_rcgr = 0x1120,
133 .mnd_width = 0,
134 .hid_width = 5,
135 .parent_map = gpu_cc_parent_map_0,
136 .freq_tbl = ftbl_gpu_cc_gmu_clk_src,
137 .clkr.hw.init = &(struct clk_init_data){
138 .name = "gpu_cc_gmu_clk_src",
139 .parent_data = gpu_cc_parent_data_0,
140 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
141 .ops = &clk_rcg2_shared_ops,
142 },
143};
144
145static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = {
146 F(320000000, P_GPU_CC_PLL1_OUT_AUX2, 2, 0, 0),
147 F(465000000, P_GPU_CC_PLL1_OUT_AUX2, 2, 0, 0),
148 F(600000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
149 F(745000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
150 F(820000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
151 F(900000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
152 F(950000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
153 { }
154};
155
156static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = {
157 .cmd_rcgr = 0x101c,
158 .mnd_width = 0,
159 .hid_width = 5,
160 .parent_map = gpu_cc_parent_map_1,
161 .freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src,
162 .clkr.hw.init = &(struct clk_init_data){
163 .name = "gpu_cc_gx_gfx3d_clk_src",
164 .parent_data = gpu_cc_parent_data_1,
165 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
166 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
167 .ops = &clk_rcg2_ops,
168 },
169};
170
171static struct clk_branch gpu_cc_crc_ahb_clk = {
172 .halt_reg = 0x107c,
173 .halt_check = BRANCH_HALT_DELAY,
174 .clkr = {
175 .enable_reg = 0x107c,
176 .enable_mask = BIT(0),
177 .hw.init = &(struct clk_init_data){
178 .name = "gpu_cc_crc_ahb_clk",
179 .ops = &clk_branch2_ops,
180 },
181 },
182};
183
184static struct clk_branch gpu_cc_cx_apb_clk = {
185 .halt_reg = 0x1088,
186 .halt_check = BRANCH_HALT_DELAY,
187 .clkr = {
188 .enable_reg = 0x1088,
189 .enable_mask = BIT(0),
190 .hw.init = &(struct clk_init_data){
191 .name = "gpu_cc_cx_apb_clk",
192 .ops = &clk_branch2_ops,
193 },
194 },
195};
196
197static struct clk_branch gpu_cc_gx_gfx3d_clk = {
198 .halt_reg = 0x1054,
199 .halt_check = BRANCH_HALT_SKIP,
200 .clkr = {
201 .enable_reg = 0x1054,
202 .enable_mask = BIT(0),
203 .hw.init = &(struct clk_init_data){
204 .name = "gpu_cc_gx_gfx3d_clk",
205 .parent_hws = (const struct clk_hw*[]) {
206 &gpu_cc_gx_gfx3d_clk_src.clkr.hw,
207 },
208 .num_parents = 1,
209 .flags = CLK_SET_RATE_PARENT,
210 .ops = &clk_branch2_ops,
211 },
212 },
213};
214
215static struct clk_branch gpu_cc_cx_gfx3d_clk = {
216 .halt_reg = 0x10a4,
217 .halt_check = BRANCH_HALT_DELAY,
218 .clkr = {
219 .enable_reg = 0x10a4,
220 .enable_mask = BIT(0),
221 .hw.init = &(struct clk_init_data){
222 .name = "gpu_cc_cx_gfx3d_clk",
223 .parent_hws = (const struct clk_hw*[]) {
224 &gpu_cc_gx_gfx3d_clk.clkr.hw,
225 },
226 .num_parents = 1,
227 .flags = CLK_SET_RATE_PARENT,
228 .ops = &clk_branch2_ops,
229 },
230 },
231};
232
233static struct clk_branch gpu_cc_cx_gmu_clk = {
234 .halt_reg = 0x1098,
235 .halt_check = BRANCH_HALT,
236 .clkr = {
237 .enable_reg = 0x1098,
238 .enable_mask = BIT(0),
239 .hw.init = &(struct clk_init_data){
240 .name = "gpu_cc_cx_gmu_clk",
241 .parent_hws = (const struct clk_hw*[]) {
242 &gpu_cc_gmu_clk_src.clkr.hw,
243 },
244 .num_parents = 1,
245 .flags = CLK_SET_RATE_PARENT,
246 .ops = &clk_branch2_ops,
247 },
248 },
249};
250
251static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
252 .halt_reg = 0x108c,
253 .halt_check = BRANCH_HALT_DELAY,
254 .clkr = {
255 .enable_reg = 0x108c,
256 .enable_mask = BIT(0),
257 .hw.init = &(struct clk_init_data){
258 .name = "gpu_cc_cx_snoc_dvm_clk",
259 .ops = &clk_branch2_ops,
260 },
261 },
262};
263
264static struct clk_branch gpu_cc_cxo_aon_clk = {
265 .halt_reg = 0x1004,
266 .halt_check = BRANCH_HALT_DELAY,
267 .clkr = {
268 .enable_reg = 0x1004,
269 .enable_mask = BIT(0),
270 .hw.init = &(struct clk_init_data){
271 .name = "gpu_cc_cxo_aon_clk",
272 .ops = &clk_branch2_ops,
273 },
274 },
275};
276
277static struct clk_branch gpu_cc_cxo_clk = {
278 .halt_reg = 0x109c,
279 .halt_check = BRANCH_HALT,
280 .clkr = {
281 .enable_reg = 0x109c,
282 .enable_mask = BIT(0),
283 .hw.init = &(struct clk_init_data){
284 .name = "gpu_cc_cxo_clk",
285 .ops = &clk_branch2_ops,
286 },
287 },
288};
289
290static struct clk_branch gpu_cc_sleep_clk = {
291 .halt_reg = 0x1090,
292 .halt_check = BRANCH_HALT_DELAY,
293 .clkr = {
294 .enable_reg = 0x1090,
295 .enable_mask = BIT(0),
296 .hw.init = &(struct clk_init_data){
297 .name = "gpu_cc_sleep_clk",
298 .ops = &clk_branch2_ops,
299 },
300 },
301};
302
303static struct clk_branch gpu_cc_ahb_clk = {
304 .halt_reg = 0x1078,
305 .halt_check = BRANCH_HALT_DELAY,
306 .clkr = {
307 .enable_reg = 0x1078,
308 .enable_mask = BIT(0),
309 .hw.init = &(struct clk_init_data){
310 .name = "gpu_cc_ahb_clk",
311 .flags = CLK_IS_CRITICAL,
312 .ops = &clk_branch2_ops,
313 },
314 },
315};
316
317static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
318 .halt_reg = 0x5000,
319 .halt_check = BRANCH_VOTED,
320 .clkr = {
321 .enable_reg = 0x5000,
322 .enable_mask = BIT(0),
323 .hw.init = &(struct clk_init_data){
324 .name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
325 .ops = &clk_branch2_ops,
326 },
327 },
328};
329
330static struct gdsc gpu_cx_gdsc = {
331 .gdscr = 0x106c,
332 .gds_hw_ctrl = 0x1540,
333 .pd = {
334 .name = "gpu_cx_gdsc",
335 },
336 .pwrsts = PWRSTS_OFF_ON,
337 .flags = VOTABLE,
338};
339
340static struct gdsc gpu_gx_gdsc = {
341 .gdscr = 0x100c,
342 .pd = {
343 .name = "gpu_gx_gdsc",
344 },
345 .pwrsts = PWRSTS_OFF_ON,
346 .flags = VOTABLE,
347};
348
349static struct clk_regmap *gpu_cc_sm6125_clocks[] = {
350 [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
351 [GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr,
352 [GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr,
353 [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
354 [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
355 [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
356 [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
357 [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
358 [GPU_CC_PLL0_OUT_AUX2] = &gpu_cc_pll0_out_aux2.clkr,
359 [GPU_CC_PLL1_OUT_AUX2] = &gpu_cc_pll1_out_aux2.clkr,
360 [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
361 [GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr,
362 [GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr,
363 [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
364 [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
365};
366
367static struct gdsc *gpucc_sm6125_gdscs[] = {
368 [GPU_CX_GDSC] = &gpu_cx_gdsc,
369 [GPU_GX_GDSC] = &gpu_gx_gdsc,
370};
371
372static const struct regmap_config gpu_cc_sm6125_regmap_config = {
373 .reg_bits = 32,
374 .reg_stride = 4,
375 .val_bits = 32,
376 .max_register = 0x9000,
377 .fast_io = true,
378};
379
380static const struct qcom_cc_desc gpu_cc_sm6125_desc = {
381 .config = &gpu_cc_sm6125_regmap_config,
382 .clks = gpu_cc_sm6125_clocks,
383 .num_clks = ARRAY_SIZE(gpu_cc_sm6125_clocks),
384 .gdscs = gpucc_sm6125_gdscs,
385 .num_gdscs = ARRAY_SIZE(gpucc_sm6125_gdscs),
386};
387
388static const struct of_device_id gpu_cc_sm6125_match_table[] = {
389 { .compatible = "qcom,sm6125-gpucc" },
390 { }
391};
392MODULE_DEVICE_TABLE(of, gpu_cc_sm6125_match_table);
393
394static int gpu_cc_sm6125_probe(struct platform_device *pdev)
395{
396 struct regmap *regmap;
397
398 regmap = qcom_cc_map(pdev, &gpu_cc_sm6125_desc);
399 if (IS_ERR(regmap))
400 return PTR_ERR(regmap);
401
402 clk_alpha_pll_configure(&gpu_cc_pll0_out_aux2, regmap, &gpu_pll0_config);
403 clk_alpha_pll_configure(&gpu_cc_pll1_out_aux2, regmap, &gpu_pll1_config);
404
405 /* Set recommended WAKEUP/SLEEP settings for the gpu_cc_cx_gmu_clk */
406 qcom_branch_set_wakeup(regmap, gpu_cc_cx_gmu_clk, 0xf);
407 qcom_branch_set_sleep(regmap, gpu_cc_cx_gmu_clk, 0xf);
408
409 qcom_branch_set_force_mem_core(regmap, gpu_cc_gx_gfx3d_clk, true);
410 qcom_branch_set_force_periph_on(regmap, gpu_cc_gx_gfx3d_clk, true);
411
412 return qcom_cc_really_probe(pdev, &gpu_cc_sm6125_desc, regmap);
413}
414
415static struct platform_driver gpu_cc_sm6125_driver = {
416 .probe = gpu_cc_sm6125_probe,
417 .driver = {
418 .name = "gpucc-sm6125",
419 .of_match_table = gpu_cc_sm6125_match_table,
420 },
421};
422module_platform_driver(gpu_cc_sm6125_driver);
423
424MODULE_DESCRIPTION("QTI GPUCC SM6125 Driver");
425MODULE_LICENSE("GPL");