1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
   4 */
   5
   6#include <linux/clk-provider.h>
   7#include <linux/kernel.h>
   8#include <linux/module.h>
   9#include <linux/of.h>
  10#include <linux/platform_device.h>
  11#include <linux/regmap.h>
  12
  13#include <dt-bindings/clock/qcom,gcc-sc7280.h>
  14
  15#include "clk-alpha-pll.h"
  16#include "clk-branch.h"
  17#include "clk-rcg.h"
  18#include "clk-regmap-divider.h"
  19#include "clk-regmap-mux.h"
  20#include "clk-regmap-phy-mux.h"
  21#include "common.h"
  22#include "gdsc.h"
  23#include "reset.h"
  24
  25enum {
  26	P_BI_TCXO,
  27	P_GCC_GPLL0_OUT_EVEN,
  28	P_GCC_GPLL0_OUT_MAIN,
  29	P_GCC_GPLL0_OUT_ODD,
  30	P_GCC_GPLL10_OUT_MAIN,
  31	P_GCC_GPLL4_OUT_MAIN,
  32	P_GCC_GPLL9_OUT_MAIN,
  33	P_PCIE_0_PIPE_CLK,
  34	P_PCIE_1_PIPE_CLK,
  35	P_SLEEP_CLK,
  36	P_UFS_PHY_RX_SYMBOL_0_CLK,
  37	P_UFS_PHY_RX_SYMBOL_1_CLK,
  38	P_UFS_PHY_TX_SYMBOL_0_CLK,
  39	P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
  40	P_GCC_MSS_GPLL0_MAIN_DIV_CLK,
  41};
  42
  43static struct clk_alpha_pll gcc_gpll0 = {
  44	.offset = 0x0,
  45	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
  46	.clkr = {
  47		.enable_reg = 0x52010,
  48		.enable_mask = BIT(0),
  49		.hw.init = &(struct clk_init_data){
  50			.name = "gcc_gpll0",
  51			.parent_data = &(const struct clk_parent_data){
  52				.fw_name = "bi_tcxo",
  53			},
  54			.num_parents = 1,
  55			.ops = &clk_alpha_pll_fixed_lucid_ops,
  56		},
  57	},
  58};
  59
  60static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
  61	{ 0x1, 2 },
  62	{ }
  63};
  64
  65static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
  66	.offset = 0x0,
  67	.post_div_shift = 8,
  68	.post_div_table = post_div_table_gcc_gpll0_out_even,
  69	.num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
  70	.width = 4,
  71	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
  72	.clkr.hw.init = &(struct clk_init_data){
  73		.name = "gcc_gpll0_out_even",
  74		.parent_hws = (const struct clk_hw*[]){
  75			&gcc_gpll0.clkr.hw,
  76		},
  77		.num_parents = 1,
  78		.ops = &clk_alpha_pll_postdiv_lucid_ops,
  79	},
  80};
  81
  82static const struct clk_div_table post_div_table_gcc_gpll0_out_odd[] = {
  83	{ 0x3, 3 },
  84	{ }
  85};
  86
  87static struct clk_alpha_pll_postdiv gcc_gpll0_out_odd = {
  88	.offset = 0x0,
  89	.post_div_shift = 12,
  90	.post_div_table = post_div_table_gcc_gpll0_out_odd,
  91	.num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_odd),
  92	.width = 4,
  93	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
  94	.clkr.hw.init = &(struct clk_init_data){
  95		.name = "gcc_gpll0_out_odd",
  96		.parent_hws = (const struct clk_hw*[]){
  97			&gcc_gpll0.clkr.hw,
  98		},
  99		.num_parents = 1,
 100		.ops = &clk_alpha_pll_postdiv_lucid_ops,
 101	},
 102};
 103
 104static struct clk_alpha_pll gcc_gpll1 = {
 105	.offset = 0x1000,
 106	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
 107	.clkr = {
 108		.enable_reg = 0x52010,
 109		.enable_mask = BIT(1),
 110		.hw.init = &(struct clk_init_data){
 111			.name = "gcc_gpll1",
 112			.parent_data = &(const struct clk_parent_data){
 113				.fw_name = "bi_tcxo",
 114			},
 115			.num_parents = 1,
 116			.ops = &clk_alpha_pll_fixed_lucid_ops,
 117		},
 118	},
 119};
 120
 121static struct clk_alpha_pll gcc_gpll10 = {
 122	.offset = 0x1e000,
 123	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
 124	.clkr = {
 125		.enable_reg = 0x52010,
 126		.enable_mask = BIT(9),
 127		.hw.init = &(struct clk_init_data){
 128			.name = "gcc_gpll10",
 129			.parent_data = &(const struct clk_parent_data){
 130				.fw_name = "bi_tcxo",
 131			},
 132			.num_parents = 1,
 133			.ops = &clk_alpha_pll_fixed_lucid_ops,
 134		},
 135	},
 136};
 137
 138static struct clk_alpha_pll gcc_gpll4 = {
 139	.offset = 0x76000,
 140	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
 141	.clkr = {
 142		.enable_reg = 0x52010,
 143		.enable_mask = BIT(4),
 144		.hw.init = &(struct clk_init_data){
 145			.name = "gcc_gpll4",
 146			.parent_data = &(const struct clk_parent_data){
 147				.fw_name = "bi_tcxo",
 148			},
 149			.num_parents = 1,
 150			.ops = &clk_alpha_pll_fixed_lucid_ops,
 151		},
 152	},
 153};
 154
 155static struct clk_alpha_pll gcc_gpll9 = {
 156	.offset = 0x1c000,
 157	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
 158	.clkr = {
 159		.enable_reg = 0x52010,
 160		.enable_mask = BIT(8),
 161		.hw.init = &(struct clk_init_data){
 162			.name = "gcc_gpll9",
 163			.parent_data = &(const struct clk_parent_data){
 164				.fw_name = "bi_tcxo",
 165			},
 166			.num_parents = 1,
 167			.ops = &clk_alpha_pll_fixed_lucid_ops,
 168		},
 169	},
 170};
 171
 172static struct clk_branch gcc_mss_gpll0_main_div_clk_src = {
 173	.halt_check = BRANCH_HALT_DELAY,
 174	.clkr = {
 175		.enable_reg = 0x52000,
 176		.enable_mask = BIT(17),
 177		.hw.init = &(struct clk_init_data){
 178			.name = "gcc_mss_gpll0_main_div_clk_src",
 179			.parent_hws = (const struct clk_hw*[]){
 180				&gcc_gpll0_out_even.clkr.hw,
 181			},
 182			.num_parents = 1,
 183			.flags = CLK_SET_RATE_PARENT,
 184			.ops = &clk_branch2_ops,
 185		},
 186	},
 187};
 188
 189static const struct parent_map gcc_parent_map_0[] = {
 190	{ P_BI_TCXO, 0 },
 191	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 192	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 193};
 194
 195static const struct clk_parent_data gcc_parent_data_0[] = {
 196	{ .fw_name = "bi_tcxo" },
 197	{ .hw = &gcc_gpll0.clkr.hw },
 198	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 199};
 200
 201static const struct parent_map gcc_parent_map_1[] = {
 202	{ P_BI_TCXO, 0 },
 203	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 204	{ P_GCC_GPLL0_OUT_ODD, 3 },
 205	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 206};
 207
 208static const struct clk_parent_data gcc_parent_data_1[] = {
 209	{ .fw_name = "bi_tcxo" },
 210	{ .hw = &gcc_gpll0.clkr.hw },
 211	{ .hw = &gcc_gpll0_out_odd.clkr.hw },
 212	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 213};
 214
 215static const struct parent_map gcc_parent_map_2[] = {
 216	{ P_BI_TCXO, 0 },
 217	{ P_SLEEP_CLK, 5 },
 218};
 219
 220static const struct clk_parent_data gcc_parent_data_2[] = {
 221	{ .fw_name = "bi_tcxo" },
 222	{ .fw_name = "sleep_clk" },
 223};
 224
 225static const struct parent_map gcc_parent_map_3[] = {
 226	{ P_BI_TCXO, 0 },
 227};
 228
 229static const struct clk_parent_data gcc_parent_data_3[] = {
 230	{ .fw_name = "bi_tcxo" },
 231};
 232
 233static const struct parent_map gcc_parent_map_4[] = {
 234	{ P_BI_TCXO, 0 },
 235	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 236	{ P_GCC_GPLL0_OUT_ODD, 3 },
 237	{ P_SLEEP_CLK, 5 },
 238	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 239};
 240
 241static const struct clk_parent_data gcc_parent_data_4[] = {
 242	{ .fw_name = "bi_tcxo" },
 243	{ .hw = &gcc_gpll0.clkr.hw },
 244	{ .hw = &gcc_gpll0_out_odd.clkr.hw },
 245	{ .fw_name = "sleep_clk" },
 246	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 247};
 248
 249static const struct parent_map gcc_parent_map_5[] = {
 250	{ P_BI_TCXO, 0 },
 251	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 252};
 253
 254static const struct clk_parent_data gcc_parent_data_5[] = {
 255	{ .fw_name = "bi_tcxo" },
 256	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 257};
 258
 259static const struct parent_map gcc_parent_map_8[] = {
 260	{ P_BI_TCXO, 0 },
 261	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 262	{ P_GCC_GPLL0_OUT_ODD, 3 },
 263	{ P_GCC_GPLL10_OUT_MAIN, 5 },
 264	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 265};
 266
 267static const struct clk_parent_data gcc_parent_data_8[] = {
 268	{ .fw_name = "bi_tcxo" },
 269	{ .hw = &gcc_gpll0.clkr.hw },
 270	{ .hw = &gcc_gpll0_out_odd.clkr.hw },
 271	{ .hw = &gcc_gpll10.clkr.hw },
 272	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 273};
 274
 275static const struct parent_map gcc_parent_map_9[] = {
 276	{ P_BI_TCXO, 0 },
 277	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 278	{ P_GCC_GPLL9_OUT_MAIN, 2 },
 279	{ P_GCC_GPLL0_OUT_ODD, 3 },
 280	{ P_GCC_GPLL4_OUT_MAIN, 5 },
 281	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 282};
 283
 284static const struct clk_parent_data gcc_parent_data_9[] = {
 285	{ .fw_name = "bi_tcxo" },
 286	{ .hw = &gcc_gpll0.clkr.hw },
 287	{ .hw = &gcc_gpll9.clkr.hw },
 288	{ .hw = &gcc_gpll0_out_odd.clkr.hw },
 289	{ .hw = &gcc_gpll4.clkr.hw },
 290	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 291};
 292
 293static const struct parent_map gcc_parent_map_10[] = {
 294	{ P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
 295	{ P_BI_TCXO, 2 },
 296};
 297
 298static const struct clk_parent_data gcc_parent_data_10[] = {
 299	{ .fw_name = "ufs_phy_rx_symbol_0_clk" },
 300	{ .fw_name = "bi_tcxo" },
 301};
 302
 303static const struct parent_map gcc_parent_map_11[] = {
 304	{ P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
 305	{ P_BI_TCXO, 2 },
 306};
 307
 308static const struct clk_parent_data gcc_parent_data_11[] = {
 309	{ .fw_name = "ufs_phy_rx_symbol_1_clk" },
 310	{ .fw_name = "bi_tcxo" },
 311};
 312
 313static const struct parent_map gcc_parent_map_12[] = {
 314	{ P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
 315	{ P_BI_TCXO, 2 },
 316};
 317
 318static const struct clk_parent_data gcc_parent_data_12[] = {
 319	{ .fw_name = "ufs_phy_tx_symbol_0_clk" },
 320	{ .fw_name = "bi_tcxo" },
 321};
 322
 323static const struct parent_map gcc_parent_map_13[] = {
 324	{ P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
 325	{ P_BI_TCXO, 2 },
 326};
 327
 328static const struct clk_parent_data gcc_parent_data_13[] = {
 329	{ .fw_name = "usb3_phy_wrapper_gcc_usb30_pipe_clk" },
 330	{ .fw_name = "bi_tcxo" },
 331};
 332
 333static const struct parent_map gcc_parent_map_14[] = {
 334	{ P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
 335	{ P_BI_TCXO, 2 },
 336};
 337
 338static const struct clk_parent_data gcc_parent_data_14[] = {
 339	{ .fw_name = "usb3_phy_wrapper_gcc_usb30_pipe_clk" },
 340	{ .fw_name = "bi_tcxo" },
 341};
 342
 343static const struct parent_map gcc_parent_map_15[] = {
 344	{ P_BI_TCXO, 0 },
 345	{ P_GCC_MSS_GPLL0_MAIN_DIV_CLK, 1 },
 346};
 347
 348static const struct clk_parent_data gcc_parent_data_15[] = {
 349	{ .fw_name = "bi_tcxo" },
 350	{ .hw = &gcc_mss_gpll0_main_div_clk_src.clkr.hw },
 351};
 352
 353static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {
 354	.reg = 0x6b054,
 355	.clkr = {
 356		.hw.init = &(struct clk_init_data){
 357			.name = "gcc_pcie_0_pipe_clk_src",
 358			.parent_data = &(const struct clk_parent_data){
 359				.fw_name = "pcie_0_pipe_clk",
 360				.name = "pcie_0_pipe_clk",
 361			},
 362			.num_parents = 1,
 363			.ops = &clk_regmap_phy_mux_ops,
 364		},
 365	},
 366};
 367
 368static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = {
 369	.reg = 0x8d054,
 370	.clkr = {
 371		.hw.init = &(struct clk_init_data){
 372			.name = "gcc_pcie_1_pipe_clk_src",
 373			.parent_data = &(const struct clk_parent_data){
 374				.fw_name = "pcie_1_pipe_clk",
 375				.name = "pcie_1_pipe_clk",
 376			},
 377			.num_parents = 1,
 378			.ops = &clk_regmap_phy_mux_ops,
 379		},
 380	},
 381};
 382
 383static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
 384	.reg = 0x77058,
 385	.shift = 0,
 386	.width = 2,
 387	.parent_map = gcc_parent_map_10,
 388	.clkr = {
 389		.hw.init = &(struct clk_init_data){
 390			.name = "gcc_ufs_phy_rx_symbol_0_clk_src",
 391			.parent_data = gcc_parent_data_10,
 392			.num_parents = ARRAY_SIZE(gcc_parent_data_10),
 393			.ops = &clk_regmap_mux_closest_ops,
 394		},
 395	},
 396};
 397
 398static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
 399	.reg = 0x770c8,
 400	.shift = 0,
 401	.width = 2,
 402	.parent_map = gcc_parent_map_11,
 403	.clkr = {
 404		.hw.init = &(struct clk_init_data){
 405			.name = "gcc_ufs_phy_rx_symbol_1_clk_src",
 406			.parent_data = gcc_parent_data_11,
 407			.num_parents = ARRAY_SIZE(gcc_parent_data_11),
 408			.ops = &clk_regmap_mux_closest_ops,
 409		},
 410	},
 411};
 412
 413static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
 414	.reg = 0x77048,
 415	.shift = 0,
 416	.width = 2,
 417	.parent_map = gcc_parent_map_12,
 418	.clkr = {
 419		.hw.init = &(struct clk_init_data){
 420			.name = "gcc_ufs_phy_tx_symbol_0_clk_src",
 421			.parent_data = gcc_parent_data_12,
 422			.num_parents = ARRAY_SIZE(gcc_parent_data_12),
 423			.ops = &clk_regmap_mux_closest_ops,
 424		},
 425	},
 426};
 427
 428static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
 429	.reg = 0xf060,
 430	.shift = 0,
 431	.width = 2,
 432	.parent_map = gcc_parent_map_13,
 433	.clkr = {
 434		.hw.init = &(struct clk_init_data){
 435			.name = "gcc_usb3_prim_phy_pipe_clk_src",
 436			.parent_data = gcc_parent_data_13,
 437			.num_parents = ARRAY_SIZE(gcc_parent_data_13),
 438			.ops = &clk_regmap_mux_closest_ops,
 439		},
 440	},
 441};
 442
 443static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = {
 444	.reg = 0x9e060,
 445	.shift = 0,
 446	.width = 2,
 447	.parent_map = gcc_parent_map_14,
 448	.clkr = {
 449		.hw.init = &(struct clk_init_data){
 450			.name = "gcc_usb3_sec_phy_pipe_clk_src",
 451			.parent_data = gcc_parent_data_14,
 452			.num_parents = ARRAY_SIZE(gcc_parent_data_14),
 453			.ops = &clk_regmap_mux_closest_ops,
 454		},
 455	},
 456};
 457
 458static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
 459	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
 460	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
 461	F(200000000, P_GCC_GPLL0_OUT_ODD, 1, 0, 0),
 462	{ }
 463};
 464
 465static struct clk_rcg2 gcc_gp1_clk_src = {
 466	.cmd_rcgr = 0x64004,
 467	.mnd_width = 16,
 468	.hid_width = 5,
 469	.parent_map = gcc_parent_map_4,
 470	.freq_tbl = ftbl_gcc_gp1_clk_src,
 471	.clkr.hw.init = &(struct clk_init_data){
 472		.name = "gcc_gp1_clk_src",
 473		.parent_data = gcc_parent_data_4,
 474		.num_parents = ARRAY_SIZE(gcc_parent_data_4),
 475		.ops = &clk_rcg2_ops,
 476	},
 477};
 478
 479static struct clk_rcg2 gcc_gp2_clk_src = {
 480	.cmd_rcgr = 0x65004,
 481	.mnd_width = 16,
 482	.hid_width = 5,
 483	.parent_map = gcc_parent_map_4,
 484	.freq_tbl = ftbl_gcc_gp1_clk_src,
 485	.clkr.hw.init = &(struct clk_init_data){
 486		.name = "gcc_gp2_clk_src",
 487		.parent_data = gcc_parent_data_4,
 488		.num_parents = ARRAY_SIZE(gcc_parent_data_4),
 489		.ops = &clk_rcg2_ops,
 490	},
 491};
 492
 493static struct clk_rcg2 gcc_gp3_clk_src = {
 494	.cmd_rcgr = 0x66004,
 495	.mnd_width = 16,
 496	.hid_width = 5,
 497	.parent_map = gcc_parent_map_4,
 498	.freq_tbl = ftbl_gcc_gp1_clk_src,
 499	.clkr.hw.init = &(struct clk_init_data){
 500		.name = "gcc_gp3_clk_src",
 501		.parent_data = gcc_parent_data_4,
 502		.num_parents = ARRAY_SIZE(gcc_parent_data_4),
 503		.ops = &clk_rcg2_ops,
 504	},
 505};
 506
 507static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
 508	F(9600000, P_BI_TCXO, 2, 0, 0),
 509	F(19200000, P_BI_TCXO, 1, 0, 0),
 510	{ }
 511};
 512
 513static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
 514	.cmd_rcgr = 0x6b058,
 515	.mnd_width = 16,
 516	.hid_width = 5,
 517	.parent_map = gcc_parent_map_2,
 518	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 519	.clkr.hw.init = &(struct clk_init_data){
 520		.name = "gcc_pcie_0_aux_clk_src",
 521		.parent_data = gcc_parent_data_2,
 522		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
 523		.ops = &clk_rcg2_ops,
 524	},
 525};
 526
 527static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
 528	F(19200000, P_BI_TCXO, 1, 0, 0),
 529	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
 530	{ }
 531};
 532
 533static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
 534	.cmd_rcgr = 0x6b03c,
 535	.mnd_width = 0,
 536	.hid_width = 5,
 537	.parent_map = gcc_parent_map_0,
 538	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
 539	.clkr.hw.init = &(struct clk_init_data){
 540		.name = "gcc_pcie_0_phy_rchng_clk_src",
 541		.parent_data = gcc_parent_data_0,
 542		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 543		.ops = &clk_rcg2_ops,
 544	},
 545};
 546
 547static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
 548	.cmd_rcgr = 0x8d058,
 549	.mnd_width = 16,
 550	.hid_width = 5,
 551	.parent_map = gcc_parent_map_2,
 552	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 553	.clkr.hw.init = &(struct clk_init_data){
 554		.name = "gcc_pcie_1_aux_clk_src",
 555		.parent_data = gcc_parent_data_2,
 556		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
 557		.ops = &clk_rcg2_ops,
 558	},
 559};
 560
 561static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
 562	.cmd_rcgr = 0x8d03c,
 563	.mnd_width = 0,
 564	.hid_width = 5,
 565	.parent_map = gcc_parent_map_0,
 566	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
 567	.clkr.hw.init = &(struct clk_init_data){
 568		.name = "gcc_pcie_1_phy_rchng_clk_src",
 569		.parent_data = gcc_parent_data_0,
 570		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 571		.flags = CLK_SET_RATE_PARENT,
 572		.ops = &clk_rcg2_ops,
 573	},
 574};
 575
 576static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
 577	F(60000000, P_GCC_GPLL0_OUT_EVEN, 5, 0, 0),
 578	{ }
 579};
 580
 581static struct clk_rcg2 gcc_pdm2_clk_src = {
 582	.cmd_rcgr = 0x33010,
 583	.mnd_width = 0,
 584	.hid_width = 5,
 585	.parent_map = gcc_parent_map_0,
 586	.freq_tbl = ftbl_gcc_pdm2_clk_src,
 587	.clkr.hw.init = &(struct clk_init_data){
 588		.name = "gcc_pdm2_clk_src",
 589		.parent_data = gcc_parent_data_0,
 590		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 591		.flags = CLK_SET_RATE_PARENT,
 592		.ops = &clk_rcg2_ops,
 593	},
 594};
 595
 596static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
 597	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
 598	F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
 599	F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
 600	F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
 601	{ }
 602};
 603
 604static struct clk_rcg2 gcc_qspi_core_clk_src = {
 605	.cmd_rcgr = 0x4b00c,
 606	.mnd_width = 0,
 607	.hid_width = 5,
 608	.parent_map = gcc_parent_map_0,
 609	.freq_tbl = ftbl_gcc_qspi_core_clk_src,
 610	.clkr.hw.init = &(struct clk_init_data){
 611		.name = "gcc_qspi_core_clk_src",
 612		.parent_data = gcc_parent_data_0,
 613		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 614		.ops = &clk_rcg2_floor_ops,
 615	},
 616};
 617
 618static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
 619	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
 620	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
 621	F(19200000, P_BI_TCXO, 1, 0, 0),
 622	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
 623	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
 624	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
 625	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
 626	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
 627	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
 628	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
 629	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
 630	F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
 631	F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
 632	F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
 633	F(120000000, P_GCC_GPLL0_OUT_EVEN, 2.5, 0, 0),
 634	{ }
 635};
 636
 637static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
 638	.name = "gcc_qupv3_wrap0_s0_clk_src",
 639	.parent_data = gcc_parent_data_0,
 640	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 641	.ops = &clk_rcg2_ops,
 642};
 643
 644static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
 645	.cmd_rcgr = 0x17010,
 646	.mnd_width = 16,
 647	.hid_width = 5,
 648	.parent_map = gcc_parent_map_0,
 649	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 650	.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
 651};
 652
 653static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
 654	.name = "gcc_qupv3_wrap0_s1_clk_src",
 655	.parent_data = gcc_parent_data_0,
 656	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 657	.ops = &clk_rcg2_ops,
 658};
 659
 660static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
 661	.cmd_rcgr = 0x17140,
 662	.mnd_width = 16,
 663	.hid_width = 5,
 664	.parent_map = gcc_parent_map_0,
 665	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 666	.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
 667};
 668
 669static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = {
 670	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
 671	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
 672	F(19200000, P_BI_TCXO, 1, 0, 0),
 673	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
 674	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
 675	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
 676	F(52174000, P_GCC_GPLL0_OUT_MAIN, 1, 2, 23),
 677	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
 678	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
 679	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
 680	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
 681	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
 682	{ }
 683};
 684
 685static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
 686	.name = "gcc_qupv3_wrap0_s2_clk_src",
 687	.parent_data = gcc_parent_data_0,
 688	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 689	.ops = &clk_rcg2_ops,
 690};
 691
 692static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
 693	.cmd_rcgr = 0x17270,
 694	.mnd_width = 16,
 695	.hid_width = 5,
 696	.parent_map = gcc_parent_map_0,
 697	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 698	.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
 699};
 700
 701static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
 702	.name = "gcc_qupv3_wrap0_s3_clk_src",
 703	.parent_data = gcc_parent_data_0,
 704	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 705	.ops = &clk_rcg2_ops,
 706};
 707
 708static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
 709	.cmd_rcgr = 0x173a0,
 710	.mnd_width = 16,
 711	.hid_width = 5,
 712	.parent_map = gcc_parent_map_0,
 713	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 714	.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
 715};
 716
 717static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
 718	.name = "gcc_qupv3_wrap0_s4_clk_src",
 719	.parent_data = gcc_parent_data_0,
 720	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 721	.ops = &clk_rcg2_ops,
 722};
 723
 724static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
 725	.cmd_rcgr = 0x174d0,
 726	.mnd_width = 16,
 727	.hid_width = 5,
 728	.parent_map = gcc_parent_map_0,
 729	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 730	.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
 731};
 732
 733static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
 734	.name = "gcc_qupv3_wrap0_s5_clk_src",
 735	.parent_data = gcc_parent_data_0,
 736	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 737	.ops = &clk_rcg2_ops,
 738};
 739
 740static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
 741	.cmd_rcgr = 0x17600,
 742	.mnd_width = 16,
 743	.hid_width = 5,
 744	.parent_map = gcc_parent_map_0,
 745	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 746	.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
 747};
 748
 749static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
 750	.name = "gcc_qupv3_wrap0_s6_clk_src",
 751	.parent_data = gcc_parent_data_0,
 752	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 753	.ops = &clk_rcg2_ops,
 754};
 755
 756static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
 757	.cmd_rcgr = 0x17730,
 758	.mnd_width = 16,
 759	.hid_width = 5,
 760	.parent_map = gcc_parent_map_0,
 761	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 762	.clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
 763};
 764
 765static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
 766	.name = "gcc_qupv3_wrap0_s7_clk_src",
 767	.parent_data = gcc_parent_data_0,
 768	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 769	.ops = &clk_rcg2_ops,
 770};
 771
 772static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
 773	.cmd_rcgr = 0x17860,
 774	.mnd_width = 16,
 775	.hid_width = 5,
 776	.parent_map = gcc_parent_map_0,
 777	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 778	.clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
 779};
 780
 781static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
 782	.name = "gcc_qupv3_wrap1_s0_clk_src",
 783	.parent_data = gcc_parent_data_0,
 784	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 785	.ops = &clk_rcg2_ops,
 786};
 787
 788static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
 789	.cmd_rcgr = 0x18010,
 790	.mnd_width = 16,
 791	.hid_width = 5,
 792	.parent_map = gcc_parent_map_0,
 793	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 794	.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
 795};
 796
 797static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
 798	.name = "gcc_qupv3_wrap1_s1_clk_src",
 799	.parent_data = gcc_parent_data_0,
 800	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 801	.ops = &clk_rcg2_ops,
 802};
 803
 804static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
 805	.cmd_rcgr = 0x18140,
 806	.mnd_width = 16,
 807	.hid_width = 5,
 808	.parent_map = gcc_parent_map_0,
 809	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 810	.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
 811};
 812
 813static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
 814	.name = "gcc_qupv3_wrap1_s2_clk_src",
 815	.parent_data = gcc_parent_data_0,
 816	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 817	.ops = &clk_rcg2_ops,
 818};
 819
 820static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
 821	.cmd_rcgr = 0x18270,
 822	.mnd_width = 16,
 823	.hid_width = 5,
 824	.parent_map = gcc_parent_map_0,
 825	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 826	.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
 827};
 828
 829static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
 830	.name = "gcc_qupv3_wrap1_s3_clk_src",
 831	.parent_data = gcc_parent_data_0,
 832	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 833	.ops = &clk_rcg2_ops,
 834};
 835
 836static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
 837	.cmd_rcgr = 0x183a0,
 838	.mnd_width = 16,
 839	.hid_width = 5,
 840	.parent_map = gcc_parent_map_0,
 841	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 842	.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
 843};
 844
 845static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
 846	.name = "gcc_qupv3_wrap1_s4_clk_src",
 847	.parent_data = gcc_parent_data_0,
 848	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 849	.ops = &clk_rcg2_ops,
 850};
 851
 852static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
 853	.cmd_rcgr = 0x184d0,
 854	.mnd_width = 16,
 855	.hid_width = 5,
 856	.parent_map = gcc_parent_map_0,
 857	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 858	.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
 859};
 860
 861static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
 862	.name = "gcc_qupv3_wrap1_s5_clk_src",
 863	.parent_data = gcc_parent_data_0,
 864	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 865	.ops = &clk_rcg2_ops,
 866};
 867
 868static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
 869	.cmd_rcgr = 0x18600,
 870	.mnd_width = 16,
 871	.hid_width = 5,
 872	.parent_map = gcc_parent_map_0,
 873	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 874	.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
 875};
 876
 877static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
 878	.name = "gcc_qupv3_wrap1_s6_clk_src",
 879	.parent_data = gcc_parent_data_0,
 880	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 881	.ops = &clk_rcg2_ops,
 882};
 883
 884static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
 885	.cmd_rcgr = 0x18730,
 886	.mnd_width = 16,
 887	.hid_width = 5,
 888	.parent_map = gcc_parent_map_0,
 889	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 890	.clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
 891};
 892
 893static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
 894	.name = "gcc_qupv3_wrap1_s7_clk_src",
 895	.parent_data = gcc_parent_data_0,
 896	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 897	.ops = &clk_rcg2_ops,
 898};
 899
 900static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
 901	.cmd_rcgr = 0x18860,
 902	.mnd_width = 16,
 903	.hid_width = 5,
 904	.parent_map = gcc_parent_map_0,
 905	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 906	.clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init,
 907};
 908
 909static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
 910	F(144000, P_BI_TCXO, 16, 3, 25),
 911	F(400000, P_BI_TCXO, 12, 1, 4),
 912	F(19200000, P_BI_TCXO, 1, 0, 0),
 913	F(20000000, P_GCC_GPLL0_OUT_EVEN, 5, 1, 3),
 914	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
 915	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
 916	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
 917	F(192000000, P_GCC_GPLL10_OUT_MAIN, 2, 0, 0),
 918	F(384000000, P_GCC_GPLL10_OUT_MAIN, 1, 0, 0),
 919	{ }
 920};
 921
 922static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
 923	.cmd_rcgr = 0x7500c,
 924	.mnd_width = 8,
 925	.hid_width = 5,
 926	.parent_map = gcc_parent_map_8,
 927	.freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
 928	.clkr.hw.init = &(struct clk_init_data){
 929		.name = "gcc_sdcc1_apps_clk_src",
 930		.parent_data = gcc_parent_data_8,
 931		.num_parents = ARRAY_SIZE(gcc_parent_data_8),
 932		.ops = &clk_rcg2_floor_ops,
 933	},
 934};
 935
 936static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
 937	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
 938	F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
 939	F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0),
 940	{ }
 941};
 942
 943static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
 944	.cmd_rcgr = 0x7502c,
 945	.mnd_width = 0,
 946	.hid_width = 5,
 947	.parent_map = gcc_parent_map_1,
 948	.freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
 949	.clkr.hw.init = &(struct clk_init_data){
 950		.name = "gcc_sdcc1_ice_core_clk_src",
 951		.parent_data = gcc_parent_data_1,
 952		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
 953		.ops = &clk_rcg2_floor_ops,
 954	},
 955};
 956
 957static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
 958	F(400000, P_BI_TCXO, 12, 1, 4),
 959	F(19200000, P_BI_TCXO, 1, 0, 0),
 960	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
 961	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
 962	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
 963	F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
 964	{ }
 965};
 966
 967static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
 968	.cmd_rcgr = 0x1400c,
 969	.mnd_width = 8,
 970	.hid_width = 5,
 971	.parent_map = gcc_parent_map_9,
 972	.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
 973	.clkr.hw.init = &(struct clk_init_data){
 974		.name = "gcc_sdcc2_apps_clk_src",
 975		.parent_data = gcc_parent_data_9,
 976		.num_parents = ARRAY_SIZE(gcc_parent_data_9),
 977		.flags = CLK_OPS_PARENT_ENABLE,
 978		.ops = &clk_rcg2_floor_ops,
 979	},
 980};
 981
 982static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
 983	F(400000, P_BI_TCXO, 12, 1, 4),
 984	F(19200000, P_BI_TCXO, 1, 0, 0),
 985	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
 986	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
 987	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
 988	{ }
 989};
 990
 991static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
 992	.cmd_rcgr = 0x1600c,
 993	.mnd_width = 8,
 994	.hid_width = 5,
 995	.parent_map = gcc_parent_map_1,
 996	.freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
 997	.clkr.hw.init = &(struct clk_init_data){
 998		.name = "gcc_sdcc4_apps_clk_src",
 999		.parent_data = gcc_parent_data_1,
1000		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1001		.ops = &clk_rcg2_floor_ops,
1002	},
1003};
1004
1005static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
1006	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1007	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1008	F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
1009	F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0),
1010	{ }
1011};
1012
1013static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
1014	.cmd_rcgr = 0x77024,
1015	.mnd_width = 8,
1016	.hid_width = 5,
1017	.parent_map = gcc_parent_map_0,
1018	.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
1019	.clkr.hw.init = &(struct clk_init_data){
1020		.name = "gcc_ufs_phy_axi_clk_src",
1021		.parent_data = gcc_parent_data_0,
1022		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1023		.ops = &clk_rcg2_ops,
1024	},
1025};
1026
1027static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
1028	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1029	F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
1030	F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0),
1031	{ }
1032};
1033
1034static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
1035	.cmd_rcgr = 0x7706c,
1036	.mnd_width = 0,
1037	.hid_width = 5,
1038	.parent_map = gcc_parent_map_0,
1039	.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
1040	.clkr.hw.init = &(struct clk_init_data){
1041		.name = "gcc_ufs_phy_ice_core_clk_src",
1042		.parent_data = gcc_parent_data_0,
1043		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1044		.ops = &clk_rcg2_ops,
1045	},
1046};
1047
1048static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
1049	.cmd_rcgr = 0x770a0,
1050	.mnd_width = 0,
1051	.hid_width = 5,
1052	.parent_map = gcc_parent_map_3,
1053	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1054	.clkr.hw.init = &(struct clk_init_data){
1055		.name = "gcc_ufs_phy_phy_aux_clk_src",
1056		.parent_data = gcc_parent_data_3,
1057		.num_parents = ARRAY_SIZE(gcc_parent_data_3),
1058		.ops = &clk_rcg2_ops,
1059	},
1060};
1061
1062static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
1063	.cmd_rcgr = 0x77084,
1064	.mnd_width = 0,
1065	.hid_width = 5,
1066	.parent_map = gcc_parent_map_0,
1067	.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
1068	.clkr.hw.init = &(struct clk_init_data){
1069		.name = "gcc_ufs_phy_unipro_core_clk_src",
1070		.parent_data = gcc_parent_data_0,
1071		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1072		.ops = &clk_rcg2_ops,
1073	},
1074};
1075
1076static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
1077	F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
1078	F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
1079	F(200000000, P_GCC_GPLL0_OUT_ODD, 1, 0, 0),
1080	F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
1081	{ }
1082};
1083
1084static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1085	.cmd_rcgr = 0xf020,
1086	.mnd_width = 8,
1087	.hid_width = 5,
1088	.parent_map = gcc_parent_map_1,
1089	.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1090	.clkr.hw.init = &(struct clk_init_data){
1091		.name = "gcc_usb30_prim_master_clk_src",
1092		.parent_data = gcc_parent_data_1,
1093		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1094		.ops = &clk_rcg2_ops,
1095	},
1096};
1097
1098static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
1099	F(19200000, P_BI_TCXO, 1, 0, 0),
1100	{ }
1101};
1102
1103static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1104	.cmd_rcgr = 0xf038,
1105	.mnd_width = 0,
1106	.hid_width = 5,
1107	.parent_map = gcc_parent_map_3,
1108	.freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1109	.clkr.hw.init = &(struct clk_init_data){
1110		.name = "gcc_usb30_prim_mock_utmi_clk_src",
1111		.parent_data = gcc_parent_data_3,
1112		.num_parents = ARRAY_SIZE(gcc_parent_data_3),
1113		.ops = &clk_rcg2_ops,
1114	},
1115};
1116
1117static const struct freq_tbl ftbl_gcc_usb30_sec_master_clk_src[] = {
1118	F(60000000, P_GCC_GPLL0_OUT_EVEN, 5, 0, 0),
1119	F(120000000, P_GCC_GPLL0_OUT_EVEN, 2.5, 0, 0),
1120	{ }
1121};
1122
1123static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
1124	.cmd_rcgr = 0x9e020,
1125	.mnd_width = 8,
1126	.hid_width = 5,
1127	.parent_map = gcc_parent_map_5,
1128	.freq_tbl = ftbl_gcc_usb30_sec_master_clk_src,
1129	.clkr.hw.init = &(struct clk_init_data){
1130		.name = "gcc_usb30_sec_master_clk_src",
1131		.parent_data = gcc_parent_data_5,
1132		.num_parents = ARRAY_SIZE(gcc_parent_data_5),
1133		.ops = &clk_rcg2_ops,
1134	},
1135};
1136
1137static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
1138	.cmd_rcgr = 0x9e038,
1139	.mnd_width = 0,
1140	.hid_width = 5,
1141	.parent_map = gcc_parent_map_3,
1142	.freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1143	.clkr.hw.init = &(struct clk_init_data){
1144		.name = "gcc_usb30_sec_mock_utmi_clk_src",
1145		.parent_data = gcc_parent_data_3,
1146		.num_parents = ARRAY_SIZE(gcc_parent_data_3),
1147		.ops = &clk_rcg2_ops,
1148	},
1149};
1150
1151static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1152	.cmd_rcgr = 0xf064,
1153	.mnd_width = 0,
1154	.hid_width = 5,
1155	.parent_map = gcc_parent_map_2,
1156	.freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1157	.clkr.hw.init = &(struct clk_init_data){
1158		.name = "gcc_usb3_prim_phy_aux_clk_src",
1159		.parent_data = gcc_parent_data_2,
1160		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
1161		.ops = &clk_rcg2_ops,
1162	},
1163};
1164
1165static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
1166	.cmd_rcgr = 0x9e064,
1167	.mnd_width = 0,
1168	.hid_width = 5,
1169	.parent_map = gcc_parent_map_2,
1170	.freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1171	.clkr.hw.init = &(struct clk_init_data){
1172		.name = "gcc_usb3_sec_phy_aux_clk_src",
1173		.parent_data = gcc_parent_data_2,
1174		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
1175		.ops = &clk_rcg2_ops,
1176	},
1177};
1178
1179static const struct freq_tbl ftbl_gcc_sec_ctrl_clk_src[] = {
1180	F(4800000, P_BI_TCXO, 4, 0, 0),
1181	F(19200000, P_BI_TCXO, 1, 0, 0),
1182	{ }
1183};
1184
1185static struct clk_rcg2 gcc_sec_ctrl_clk_src = {
1186	.cmd_rcgr = 0x3d02c,
1187	.mnd_width = 0,
1188	.hid_width = 5,
1189	.parent_map = gcc_parent_map_3,
1190	.freq_tbl = ftbl_gcc_sec_ctrl_clk_src,
1191	.clkr.hw.init = &(struct clk_init_data){
1192		.name = "gcc_sec_ctrl_clk_src",
1193		.parent_data = gcc_parent_data_3,
1194		.num_parents = ARRAY_SIZE(gcc_parent_data_3),
1195		.ops = &clk_rcg2_ops,
1196	},
1197};
1198
1199static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
1200	.reg = 0xf050,
1201	.shift = 0,
1202	.width = 4,
1203	.clkr.hw.init = &(struct clk_init_data) {
1204		.name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
1205		.parent_hws = (const struct clk_hw*[]){
1206			&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
1207		},
1208		.num_parents = 1,
1209		.flags = CLK_SET_RATE_PARENT,
1210		.ops = &clk_regmap_div_ro_ops,
1211	},
1212};
1213
1214static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = {
1215	.reg = 0x9e050,
1216	.shift = 0,
1217	.width = 4,
1218	.clkr.hw.init = &(struct clk_init_data) {
1219		.name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src",
1220		.parent_hws = (const struct clk_hw*[]){
1221			&gcc_usb30_sec_mock_utmi_clk_src.clkr.hw,
1222		},
1223		.num_parents = 1,
1224		.flags = CLK_SET_RATE_PARENT,
1225		.ops = &clk_regmap_div_ro_ops,
1226	},
1227};
1228
1229static struct clk_branch gcc_pcie_clkref_en = {
1230	.halt_reg = 0x8c004,
1231	.halt_check = BRANCH_HALT,
1232	.clkr = {
1233		.enable_reg = 0x8c004,
1234		.enable_mask = BIT(0),
1235		.hw.init = &(struct clk_init_data){
1236			.name = "gcc_pcie_clkref_en",
1237			.ops = &clk_branch2_ops,
1238		},
1239	},
1240};
1241
1242static struct clk_branch gcc_edp_clkref_en = {
1243	.halt_reg = 0x8c008,
1244	.halt_check = BRANCH_HALT,
1245	.clkr = {
1246		.enable_reg = 0x8c008,
1247		.enable_mask = BIT(0),
1248		.hw.init = &(struct clk_init_data){
1249			.name = "gcc_edp_clkref_en",
1250			.ops = &clk_branch2_ops,
1251		},
1252	},
1253};
1254
1255static struct clk_branch gcc_aggre_noc_pcie_0_axi_clk = {
1256	.halt_reg = 0x6b080,
1257	.halt_check = BRANCH_HALT_SKIP,
1258	.hwcg_reg = 0x6b080,
1259	.hwcg_bit = 1,
1260	.clkr = {
1261		.enable_reg = 0x52000,
1262		.enable_mask = BIT(12),
1263		.hw.init = &(struct clk_init_data){
1264			.name = "gcc_aggre_noc_pcie_0_axi_clk",
1265			.ops = &clk_branch2_ops,
1266		},
1267	},
1268};
1269
1270static struct clk_branch gcc_aggre_noc_pcie_1_axi_clk = {
1271	.halt_reg = 0x8d084,
1272	.halt_check = BRANCH_HALT_SKIP,
1273	.hwcg_reg = 0x8d084,
1274	.hwcg_bit = 1,
1275	.clkr = {
1276		.enable_reg = 0x52000,
1277		.enable_mask = BIT(11),
1278		.hw.init = &(struct clk_init_data){
1279			.name = "gcc_aggre_noc_pcie_1_axi_clk",
1280			.ops = &clk_branch2_ops,
1281		},
1282	},
1283};
1284
1285static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
1286	.halt_reg = 0x90010,
1287	.halt_check = BRANCH_HALT_VOTED,
1288	.hwcg_reg = 0x90010,
1289	.hwcg_bit = 1,
1290	.clkr = {
1291		.enable_reg = 0x52000,
1292		.enable_mask = BIT(18),
1293		.hw.init = &(struct clk_init_data){
1294			.name = "gcc_aggre_noc_pcie_tbu_clk",
1295			.ops = &clk_branch2_ops,
1296		},
1297	},
1298};
1299
1300static struct clk_branch gcc_aggre_noc_pcie_center_sf_axi_clk = {
1301	.halt_reg = 0x8d088,
1302	.halt_check = BRANCH_HALT_VOTED,
1303	.hwcg_reg = 0x8d088,
1304	.hwcg_bit = 1,
1305	.clkr = {
1306		.enable_reg = 0x52008,
1307		.enable_mask = BIT(28),
1308		.hw.init = &(struct clk_init_data){
1309			.name = "gcc_aggre_noc_pcie_center_sf_axi_clk",
1310			.ops = &clk_branch2_ops,
1311		},
1312	},
1313};
1314
1315static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1316	.halt_reg = 0x770cc,
1317	.halt_check = BRANCH_HALT_VOTED,
1318	.hwcg_reg = 0x770cc,
1319	.hwcg_bit = 1,
1320	.clkr = {
1321		.enable_reg = 0x770cc,
1322		.enable_mask = BIT(0),
1323		.hw.init = &(struct clk_init_data){
1324			.name = "gcc_aggre_ufs_phy_axi_clk",
1325			.parent_hws = (const struct clk_hw*[]){
1326				&gcc_ufs_phy_axi_clk_src.clkr.hw,
1327			},
1328			.num_parents = 1,
1329			.flags = CLK_SET_RATE_PARENT,
1330			.ops = &clk_branch2_ops,
1331		},
1332	},
1333};
1334
1335static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1336	.halt_reg = 0xf080,
1337	.halt_check = BRANCH_HALT_VOTED,
1338	.hwcg_reg = 0xf080,
1339	.hwcg_bit = 1,
1340	.clkr = {
1341		.enable_reg = 0xf080,
1342		.enable_mask = BIT(0),
1343		.hw.init = &(struct clk_init_data){
1344			.name = "gcc_aggre_usb3_prim_axi_clk",
1345			.parent_hws = (const struct clk_hw*[]){
1346				&gcc_usb30_prim_master_clk_src.clkr.hw,
1347			},
1348			.num_parents = 1,
1349			.flags = CLK_SET_RATE_PARENT,
1350			.ops = &clk_branch2_ops,
1351		},
1352	},
1353};
1354
1355static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
1356	.halt_reg = 0x9e080,
1357	.halt_check = BRANCH_HALT_VOTED,
1358	.hwcg_reg = 0x9e080,
1359	.hwcg_bit = 1,
1360	.clkr = {
1361		.enable_reg = 0x9e080,
1362		.enable_mask = BIT(0),
1363		.hw.init = &(struct clk_init_data){
1364			.name = "gcc_aggre_usb3_sec_axi_clk",
1365			.parent_hws = (const struct clk_hw*[]){
1366				&gcc_usb30_sec_master_clk_src.clkr.hw,
1367			},
1368			.num_parents = 1,
1369			.flags = CLK_SET_RATE_PARENT,
1370			.ops = &clk_branch2_ops,
1371		},
1372	},
1373};
1374
1375static struct clk_branch gcc_camera_hf_axi_clk = {
1376	.halt_reg = 0x26010,
1377	.halt_check = BRANCH_HALT_SKIP,
1378	.hwcg_reg = 0x26010,
1379	.hwcg_bit = 1,
1380	.clkr = {
1381		.enable_reg = 0x26010,
1382		.enable_mask = BIT(0),
1383		.hw.init = &(struct clk_init_data){
1384			.name = "gcc_camera_hf_axi_clk",
1385			.ops = &clk_branch2_ops,
1386		},
1387	},
1388};
1389
1390static struct clk_branch gcc_camera_sf_axi_clk = {
1391	.halt_reg = 0x2601c,
1392	.halt_check = BRANCH_HALT_SKIP,
1393	.hwcg_reg = 0x2601c,
1394	.hwcg_bit = 1,
1395	.clkr = {
1396		.enable_reg = 0x2601c,
1397		.enable_mask = BIT(0),
1398		.hw.init = &(struct clk_init_data){
1399			.name = "gcc_camera_sf_axi_clk",
1400			.ops = &clk_branch2_ops,
1401		},
1402	},
1403};
1404
1405static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1406	.halt_reg = 0xf07c,
1407	.halt_check = BRANCH_HALT_VOTED,
1408	.hwcg_reg = 0xf07c,
1409	.hwcg_bit = 1,
1410	.clkr = {
1411		.enable_reg = 0xf07c,
1412		.enable_mask = BIT(0),
1413		.hw.init = &(struct clk_init_data){
1414			.name = "gcc_cfg_noc_usb3_prim_axi_clk",
1415			.parent_hws = (const struct clk_hw*[]){
1416				&gcc_usb30_prim_master_clk_src.clkr.hw,
1417			},
1418			.num_parents = 1,
1419			.flags = CLK_SET_RATE_PARENT,
1420			.ops = &clk_branch2_ops,
1421		},
1422	},
1423};
1424
1425static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
1426	.halt_reg = 0x9e07c,
1427	.halt_check = BRANCH_HALT_VOTED,
1428	.hwcg_reg = 0x9e07c,
1429	.hwcg_bit = 1,
1430	.clkr = {
1431		.enable_reg = 0x9e07c,
1432		.enable_mask = BIT(0),
1433		.hw.init = &(struct clk_init_data){
1434			.name = "gcc_cfg_noc_usb3_sec_axi_clk",
1435			.parent_hws = (const struct clk_hw*[]){
1436				&gcc_usb30_sec_master_clk_src.clkr.hw,
1437			},
1438			.num_parents = 1,
1439			.flags = CLK_SET_RATE_PARENT,
1440			.ops = &clk_branch2_ops,
1441		},
1442	},
1443};
1444
1445static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1446	.halt_reg = 0x71154,
1447	.halt_check = BRANCH_HALT_SKIP,
1448	.hwcg_reg = 0x71154,
1449	.hwcg_bit = 1,
1450	.clkr = {
1451		.enable_reg = 0x71154,
1452		.enable_mask = BIT(0),
1453		.hw.init = &(struct clk_init_data){
1454			.name = "gcc_ddrss_gpu_axi_clk",
1455			.ops = &clk_branch2_aon_ops,
1456		},
1457	},
1458};
1459
1460static struct clk_branch gcc_ddrss_pcie_sf_clk = {
1461	.halt_reg = 0x8d080,
1462	.halt_check = BRANCH_HALT_SKIP,
1463	.hwcg_reg = 0x8d080,
1464	.hwcg_bit = 1,
1465	.clkr = {
1466		.enable_reg = 0x52000,
1467		.enable_mask = BIT(19),
1468		.hw.init = &(struct clk_init_data){
1469			.name = "gcc_ddrss_pcie_sf_clk",
1470			.ops = &clk_branch2_ops,
1471		},
1472	},
1473};
1474
1475static struct clk_branch gcc_disp_gpll0_clk_src = {
1476	.halt_check = BRANCH_HALT_DELAY,
1477	.clkr = {
1478		.enable_reg = 0x52000,
1479		.enable_mask = BIT(7),
1480		.hw.init = &(struct clk_init_data){
1481			.name = "gcc_disp_gpll0_clk_src",
1482			.parent_hws = (const struct clk_hw*[]){
1483				&gcc_gpll0.clkr.hw,
1484			},
1485			.num_parents = 1,
1486			.flags = CLK_SET_RATE_PARENT,
1487			.ops = &clk_branch2_ops,
1488		},
1489	},
1490};
1491
1492static struct clk_branch gcc_disp_hf_axi_clk = {
1493	.halt_reg = 0x2700c,
1494	.halt_check = BRANCH_HALT_SKIP,
1495	.hwcg_reg = 0x2700c,
1496	.hwcg_bit = 1,
1497	.clkr = {
1498		.enable_reg = 0x2700c,
1499		.enable_mask = BIT(0),
1500		.hw.init = &(struct clk_init_data){
1501			.name = "gcc_disp_hf_axi_clk",
1502			.ops = &clk_branch2_ops,
1503		},
1504	},
1505};
1506
1507static struct clk_branch gcc_disp_sf_axi_clk = {
1508	.halt_reg = 0x27014,
1509	.halt_check = BRANCH_HALT_SKIP,
1510	.hwcg_reg = 0x27014,
1511	.hwcg_bit = 1,
1512	.clkr = {
1513		.enable_reg = 0x27014,
1514		.enable_mask = BIT(0),
1515		.hw.init = &(struct clk_init_data){
1516			.name = "gcc_disp_sf_axi_clk",
1517			.ops = &clk_branch2_ops,
1518		},
1519	},
1520};
1521
1522static struct clk_branch gcc_gp1_clk = {
1523	.halt_reg = 0x64000,
1524	.halt_check = BRANCH_HALT,
1525	.clkr = {
1526		.enable_reg = 0x64000,
1527		.enable_mask = BIT(0),
1528		.hw.init = &(struct clk_init_data){
1529			.name = "gcc_gp1_clk",
1530			.parent_hws = (const struct clk_hw*[]){
1531				&gcc_gp1_clk_src.clkr.hw,
1532			},
1533			.num_parents = 1,
1534			.flags = CLK_SET_RATE_PARENT,
1535			.ops = &clk_branch2_ops,
1536		},
1537	},
1538};
1539
1540static struct clk_branch gcc_gp2_clk = {
1541	.halt_reg = 0x65000,
1542	.halt_check = BRANCH_HALT,
1543	.clkr = {
1544		.enable_reg = 0x65000,
1545		.enable_mask = BIT(0),
1546		.hw.init = &(struct clk_init_data){
1547			.name = "gcc_gp2_clk",
1548			.parent_hws = (const struct clk_hw*[]){
1549				&gcc_gp2_clk_src.clkr.hw,
1550			},
1551			.num_parents = 1,
1552			.flags = CLK_SET_RATE_PARENT,
1553			.ops = &clk_branch2_ops,
1554		},
1555	},
1556};
1557
1558static struct clk_branch gcc_gp3_clk = {
1559	.halt_reg = 0x66000,
1560	.halt_check = BRANCH_HALT,
1561	.clkr = {
1562		.enable_reg = 0x66000,
1563		.enable_mask = BIT(0),
1564		.hw.init = &(struct clk_init_data){
1565			.name = "gcc_gp3_clk",
1566			.parent_hws = (const struct clk_hw*[]){
1567				&gcc_gp3_clk_src.clkr.hw,
1568			},
1569			.num_parents = 1,
1570			.flags = CLK_SET_RATE_PARENT,
1571			.ops = &clk_branch2_ops,
1572		},
1573	},
1574};
1575
1576static struct clk_branch gcc_gpu_gpll0_clk_src = {
1577	.halt_check = BRANCH_HALT_DELAY,
1578	.clkr = {
1579		.enable_reg = 0x52000,
1580		.enable_mask = BIT(15),
1581		.hw.init = &(struct clk_init_data){
1582			.name = "gcc_gpu_gpll0_clk_src",
1583			.parent_hws = (const struct clk_hw*[]){
1584				&gcc_gpll0.clkr.hw,
1585			},
1586			.num_parents = 1,
1587			.flags = CLK_SET_RATE_PARENT,
1588			.ops = &clk_branch2_ops,
1589		},
1590	},
1591};
1592
1593static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1594	.halt_check = BRANCH_HALT_DELAY,
1595	.clkr = {
1596		.enable_reg = 0x52000,
1597		.enable_mask = BIT(16),
1598		.hw.init = &(struct clk_init_data){
1599			.name = "gcc_gpu_gpll0_div_clk_src",
1600			.parent_hws = (const struct clk_hw*[]){
1601				&gcc_gpll0_out_even.clkr.hw,
1602			},
1603			.num_parents = 1,
1604			.flags = CLK_SET_RATE_PARENT,
1605			.ops = &clk_branch2_ops,
1606		},
1607	},
1608};
1609
1610static struct clk_branch gcc_gpu_iref_en = {
1611	.halt_reg = 0x8c014,
1612	.halt_check = BRANCH_HALT,
1613	.clkr = {
1614		.enable_reg = 0x8c014,
1615		.enable_mask = BIT(0),
1616		.hw.init = &(struct clk_init_data){
1617			.name = "gcc_gpu_iref_en",
1618			.ops = &clk_branch2_ops,
1619		},
1620	},
1621};
1622
1623static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1624	.halt_reg = 0x7100c,
1625	.halt_check = BRANCH_HALT_VOTED,
1626	.hwcg_reg = 0x7100c,
1627	.hwcg_bit = 1,
1628	.clkr = {
1629		.enable_reg = 0x7100c,
1630		.enable_mask = BIT(0),
1631		.hw.init = &(struct clk_init_data){
1632			.name = "gcc_gpu_memnoc_gfx_clk",
1633			.ops = &clk_branch2_aon_ops,
1634		},
1635	},
1636};
1637
1638static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1639	.halt_reg = 0x71018,
1640	.halt_check = BRANCH_HALT,
1641	.clkr = {
1642		.enable_reg = 0x71018,
1643		.enable_mask = BIT(0),
1644		.hw.init = &(struct clk_init_data){
1645			.name = "gcc_gpu_snoc_dvm_gfx_clk",
1646			.ops = &clk_branch2_aon_ops,
1647		},
1648	},
1649};
1650
1651static struct clk_branch gcc_pcie0_phy_rchng_clk = {
1652	.halt_reg = 0x6b038,
1653	.halt_check = BRANCH_HALT_VOTED,
1654	.clkr = {
1655		.enable_reg = 0x52000,
1656		.enable_mask = BIT(22),
1657		.hw.init = &(struct clk_init_data){
1658			.name = "gcc_pcie0_phy_rchng_clk",
1659			.parent_hws = (const struct clk_hw*[]){
1660				&gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
1661			},
1662			.num_parents = 1,
1663			.flags = CLK_SET_RATE_PARENT,
1664			.ops = &clk_branch2_ops,
1665		},
1666	},
1667};
1668
1669static struct clk_branch gcc_pcie1_phy_rchng_clk = {
1670	.halt_reg = 0x8d038,
1671	.halt_check = BRANCH_HALT_VOTED,
1672	.clkr = {
1673		.enable_reg = 0x52000,
1674		.enable_mask = BIT(23),
1675		.hw.init = &(struct clk_init_data){
1676			.name = "gcc_pcie1_phy_rchng_clk",
1677			.parent_hws = (const struct clk_hw*[]){
1678				&gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
1679			},
1680			.num_parents = 1,
1681			.flags = CLK_SET_RATE_PARENT,
1682			.ops = &clk_branch2_ops,
1683		},
1684	},
1685};
1686
1687static struct clk_branch gcc_pcie_0_aux_clk = {
1688	.halt_reg = 0x6b028,
1689	.halt_check = BRANCH_HALT_VOTED,
1690	.clkr = {
1691		.enable_reg = 0x52008,
1692		.enable_mask = BIT(3),
1693		.hw.init = &(struct clk_init_data){
1694			.name = "gcc_pcie_0_aux_clk",
1695			.parent_hws = (const struct clk_hw*[]){
1696				&gcc_pcie_0_aux_clk_src.clkr.hw,
1697			},
1698			.num_parents = 1,
1699			.flags = CLK_SET_RATE_PARENT,
1700			.ops = &clk_branch2_ops,
1701		},
1702	},
1703};
1704
1705static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1706	.halt_reg = 0x6b024,
1707	.halt_check = BRANCH_HALT_VOTED,
1708	.hwcg_reg = 0x6b024,
1709	.hwcg_bit = 1,
1710	.clkr = {
1711		.enable_reg = 0x52008,
1712		.enable_mask = BIT(2),
1713		.hw.init = &(struct clk_init_data){
1714			.name = "gcc_pcie_0_cfg_ahb_clk",
1715			.ops = &clk_branch2_ops,
1716		},
1717	},
1718};
1719
1720static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1721	.halt_reg = 0x6b01c,
1722	.halt_check = BRANCH_HALT_SKIP,
1723	.clkr = {
1724		.enable_reg = 0x52008,
1725		.enable_mask = BIT(1),
1726		.hw.init = &(struct clk_init_data){
1727			.name = "gcc_pcie_0_mstr_axi_clk",
1728			.ops = &clk_branch2_ops,
1729		},
1730	},
1731};
1732
1733static struct clk_branch gcc_pcie_0_pipe_clk = {
1734	.halt_reg = 0x6b030,
1735	.halt_check = BRANCH_HALT_SKIP,
1736	.clkr = {
1737		.enable_reg = 0x52008,
1738		.enable_mask = BIT(4),
1739		.hw.init = &(struct clk_init_data){
1740			.name = "gcc_pcie_0_pipe_clk",
1741			.parent_hws = (const struct clk_hw*[]){
1742				&gcc_pcie_0_pipe_clk_src.clkr.hw,
1743			},
1744			.num_parents = 1,
1745			.flags = CLK_SET_RATE_PARENT,
1746			.ops = &clk_branch2_ops,
1747		},
1748	},
1749};
1750
1751static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1752	.halt_reg = 0x6b014,
1753	.halt_check = BRANCH_HALT_VOTED,
1754	.clkr = {
1755		.enable_reg = 0x52008,
1756		.enable_mask = BIT(0),
1757		.hw.init = &(struct clk_init_data){
1758			.name = "gcc_pcie_0_slv_axi_clk",
1759			.ops = &clk_branch2_ops,
1760		},
1761	},
1762};
1763
1764static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
1765	.halt_reg = 0x6b010,
1766	.halt_check = BRANCH_HALT_VOTED,
1767	.clkr = {
1768		.enable_reg = 0x52008,
1769		.enable_mask = BIT(5),
1770		.hw.init = &(struct clk_init_data){
1771			.name = "gcc_pcie_0_slv_q2a_axi_clk",
1772			.ops = &clk_branch2_ops,
1773		},
1774	},
1775};
1776
1777static struct clk_branch gcc_pcie_1_aux_clk = {
1778	.halt_reg = 0x8d028,
1779	.halt_check = BRANCH_HALT_VOTED,
1780	.clkr = {
1781		.enable_reg = 0x52000,
1782		.enable_mask = BIT(29),
1783		.hw.init = &(struct clk_init_data){
1784			.name = "gcc_pcie_1_aux_clk",
1785			.parent_hws = (const struct clk_hw*[]){
1786				&gcc_pcie_1_aux_clk_src.clkr.hw,
1787			},
1788			.num_parents = 1,
1789			.flags = CLK_SET_RATE_PARENT,
1790			.ops = &clk_branch2_ops,
1791		},
1792	},
1793};
1794
1795static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1796	.halt_reg = 0x8d024,
1797	.halt_check = BRANCH_HALT_VOTED,
1798	.hwcg_reg = 0x8d024,
1799	.hwcg_bit = 1,
1800	.clkr = {
1801		.enable_reg = 0x52000,
1802		.enable_mask = BIT(28),
1803		.hw.init = &(struct clk_init_data){
1804			.name = "gcc_pcie_1_cfg_ahb_clk",
1805			.ops = &clk_branch2_ops,
1806		},
1807	},
1808};
1809
1810static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1811	.halt_reg = 0x8d01c,
1812	.halt_check = BRANCH_HALT_SKIP,
1813	.clkr = {
1814		.enable_reg = 0x52000,
1815		.enable_mask = BIT(27),
1816		.hw.init = &(struct clk_init_data){
1817			.name = "gcc_pcie_1_mstr_axi_clk",
1818			.ops = &clk_branch2_ops,
1819		},
1820	},
1821};
1822
1823static struct clk_branch gcc_pcie_1_pipe_clk = {
1824	.halt_reg = 0x8d030,
1825	.halt_check = BRANCH_HALT_SKIP,
1826	.clkr = {
1827		.enable_reg = 0x52000,
1828		.enable_mask = BIT(30),
1829		.hw.init = &(struct clk_init_data){
1830			.name = "gcc_pcie_1_pipe_clk",
1831			.parent_hws = (const struct clk_hw*[]){
1832				&gcc_pcie_1_pipe_clk_src.clkr.hw,
1833			},
1834			.num_parents = 1,
1835			.flags = CLK_SET_RATE_PARENT,
1836			.ops = &clk_branch2_ops,
1837		},
1838	},
1839};
1840
1841static struct clk_branch gcc_pcie_1_slv_axi_clk = {
1842	.halt_reg = 0x8d014,
1843	.halt_check = BRANCH_HALT_VOTED,
1844	.clkr = {
1845		.enable_reg = 0x52000,
1846		.enable_mask = BIT(26),
1847		.hw.init = &(struct clk_init_data){
1848			.name = "gcc_pcie_1_slv_axi_clk",
1849			.ops = &clk_branch2_ops,
1850		},
1851	},
1852};
1853
1854static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
1855	.halt_reg = 0x8d010,
1856	.halt_check = BRANCH_HALT_VOTED,
1857	.clkr = {
1858		.enable_reg = 0x52000,
1859		.enable_mask = BIT(25),
1860		.hw.init = &(struct clk_init_data){
1861			.name = "gcc_pcie_1_slv_q2a_axi_clk",
1862			.ops = &clk_branch2_ops,
1863		},
1864	},
1865};
1866
1867static struct clk_branch gcc_pcie_throttle_core_clk = {
1868	.halt_reg = 0x90018,
1869	.halt_check = BRANCH_HALT_SKIP,
1870	.hwcg_reg = 0x90018,
1871	.hwcg_bit = 1,
1872	.clkr = {
1873		.enable_reg = 0x52000,
1874		.enable_mask = BIT(20),
1875		.hw.init = &(struct clk_init_data){
1876			.name = "gcc_pcie_throttle_core_clk",
1877			.ops = &clk_branch2_ops,
1878		},
1879	},
1880};
1881
1882static struct clk_branch gcc_pdm2_clk = {
1883	.halt_reg = 0x3300c,
1884	.halt_check = BRANCH_HALT,
1885	.clkr = {
1886		.enable_reg = 0x3300c,
1887		.enable_mask = BIT(0),
1888		.hw.init = &(struct clk_init_data){
1889			.name = "gcc_pdm2_clk",
1890			.parent_hws = (const struct clk_hw*[]){
1891				&gcc_pdm2_clk_src.clkr.hw,
1892			},
1893			.num_parents = 1,
1894			.flags = CLK_SET_RATE_PARENT,
1895			.ops = &clk_branch2_ops,
1896		},
1897	},
1898};
1899
1900static struct clk_branch gcc_pdm_ahb_clk = {
1901	.halt_reg = 0x33004,
1902	.halt_check = BRANCH_HALT_VOTED,
1903	.hwcg_reg = 0x33004,
1904	.hwcg_bit = 1,
1905	.clkr = {
1906		.enable_reg = 0x33004,
1907		.enable_mask = BIT(0),
1908		.hw.init = &(struct clk_init_data){
1909			.name = "gcc_pdm_ahb_clk",
1910			.ops = &clk_branch2_ops,
1911		},
1912	},
1913};
1914
1915static struct clk_branch gcc_pdm_xo4_clk = {
1916	.halt_reg = 0x33008,
1917	.halt_check = BRANCH_HALT,
1918	.clkr = {
1919		.enable_reg = 0x33008,
1920		.enable_mask = BIT(0),
1921		.hw.init = &(struct clk_init_data){
1922			.name = "gcc_pdm_xo4_clk",
1923			.ops = &clk_branch2_ops,
1924		},
1925	},
1926};
1927
1928static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
1929	.halt_reg = 0x26008,
1930	.halt_check = BRANCH_HALT_VOTED,
1931	.hwcg_reg = 0x26008,
1932	.hwcg_bit = 1,
1933	.clkr = {
1934		.enable_reg = 0x26008,
1935		.enable_mask = BIT(0),
1936		.hw.init = &(struct clk_init_data){
1937			.name = "gcc_qmip_camera_nrt_ahb_clk",
1938			.ops = &clk_branch2_ops,
1939		},
1940	},
1941};
1942
1943static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
1944	.halt_reg = 0x2600c,
1945	.halt_check = BRANCH_HALT_VOTED,
1946	.hwcg_reg = 0x2600c,
1947	.hwcg_bit = 1,
1948	.clkr = {
1949		.enable_reg = 0x2600c,
1950		.enable_mask = BIT(0),
1951		.hw.init = &(struct clk_init_data){
1952			.name = "gcc_qmip_camera_rt_ahb_clk",
1953			.ops = &clk_branch2_ops,
1954		},
1955	},
1956};
1957
1958static struct clk_branch gcc_qmip_disp_ahb_clk = {
1959	.halt_reg = 0x27008,
1960	.halt_check = BRANCH_HALT_VOTED,
1961	.clkr = {
1962		.enable_reg = 0x27008,
1963		.enable_mask = BIT(0),
1964		.hw.init = &(struct clk_init_data){
1965			.name = "gcc_qmip_disp_ahb_clk",
1966			.ops = &clk_branch2_ops,
1967		},
1968	},
1969};
1970
1971static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
1972	.halt_reg = 0x28008,
1973	.halt_check = BRANCH_HALT_VOTED,
1974	.hwcg_reg = 0x28008,
1975	.hwcg_bit = 1,
1976	.clkr = {
1977		.enable_reg = 0x28008,
1978		.enable_mask = BIT(0),
1979		.hw.init = &(struct clk_init_data){
1980			.name = "gcc_qmip_video_vcodec_ahb_clk",
1981			.ops = &clk_branch2_ops,
1982		},
1983	},
1984};
1985
1986static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
1987	.halt_reg = 0x4b004,
1988	.halt_check = BRANCH_HALT,
1989	.hwcg_reg = 0x4b004,
1990	.hwcg_bit = 1,
1991	.clkr = {
1992		.enable_reg = 0x4b004,
1993		.enable_mask = BIT(0),
1994		.hw.init = &(struct clk_init_data){
1995			.name = "gcc_qspi_cnoc_periph_ahb_clk",
1996			.ops = &clk_branch2_ops,
1997		},
1998	},
1999};
2000
2001static struct clk_branch gcc_qspi_core_clk = {
2002	.halt_reg = 0x4b008,
2003	.halt_check = BRANCH_HALT,
2004	.clkr = {
2005		.enable_reg = 0x4b008,
2006		.enable_mask = BIT(0),
2007		.hw.init = &(struct clk_init_data){
2008			.name = "gcc_qspi_core_clk",
2009			.parent_hws = (const struct clk_hw*[]){
2010				&gcc_qspi_core_clk_src.clkr.hw,
2011			},
2012			.num_parents = 1,
2013			.flags = CLK_SET_RATE_PARENT,
2014			.ops = &clk_branch2_ops,
2015		},
2016	},
2017};
2018
2019static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
2020	.halt_reg = 0x23008,
2021	.halt_check = BRANCH_HALT_VOTED,
2022	.clkr = {
2023		.enable_reg = 0x52008,
2024		.enable_mask = BIT(9),
2025		.hw.init = &(struct clk_init_data){
2026			.name = "gcc_qupv3_wrap0_core_2x_clk",
2027			.ops = &clk_branch2_ops,
2028		},
2029	},
2030};
2031
2032static struct clk_branch gcc_qupv3_wrap0_core_clk = {
2033	.halt_reg = 0x23000,
2034	.halt_check = BRANCH_HALT_VOTED,
2035	.clkr = {
2036		.enable_reg = 0x52008,
2037		.enable_mask = BIT(8),
2038		.hw.init = &(struct clk_init_data){
2039			.name = "gcc_qupv3_wrap0_core_clk",
2040			.ops = &clk_branch2_ops,
2041		},
2042	},
2043};
2044
2045static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
2046	.halt_reg = 0x1700c,
2047	.halt_check = BRANCH_HALT_VOTED,
2048	.clkr = {
2049		.enable_reg = 0x52008,
2050		.enable_mask = BIT(10),
2051		.hw.init = &(struct clk_init_data){
2052			.name = "gcc_qupv3_wrap0_s0_clk",
2053			.parent_hws = (const struct clk_hw*[]){
2054				&gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
2055			},
2056			.num_parents = 1,
2057			.flags = CLK_SET_RATE_PARENT,
2058			.ops = &clk_branch2_ops,
2059		},
2060	},
2061};
2062
2063static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
2064	.halt_reg = 0x1713c,
2065	.halt_check = BRANCH_HALT_VOTED,
2066	.clkr = {
2067		.enable_reg = 0x52008,
2068		.enable_mask = BIT(11),
2069		.hw.init = &(struct clk_init_data){
2070			.name = "gcc_qupv3_wrap0_s1_clk",
2071			.parent_hws = (const struct clk_hw*[]){
2072				&gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
2073			},
2074			.num_parents = 1,
2075			.flags = CLK_SET_RATE_PARENT,
2076			.ops = &clk_branch2_ops,
2077		},
2078	},
2079};
2080
2081static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
2082	.halt_reg = 0x1726c,
2083	.halt_check = BRANCH_HALT_VOTED,
2084	.clkr = {
2085		.enable_reg = 0x52008,
2086		.enable_mask = BIT(12),
2087		.hw.init = &(struct clk_init_data){
2088			.name = "gcc_qupv3_wrap0_s2_clk",
2089			.parent_hws = (const struct clk_hw*[]){
2090				&gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
2091			},
2092			.num_parents = 1,
2093			.flags = CLK_SET_RATE_PARENT,
2094			.ops = &clk_branch2_ops,
2095		},
2096	},
2097};
2098
2099static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
2100	.halt_reg = 0x1739c,
2101	.halt_check = BRANCH_HALT_VOTED,
2102	.clkr = {
2103		.enable_reg = 0x52008,
2104		.enable_mask = BIT(13),
2105		.hw.init = &(struct clk_init_data){
2106			.name = "gcc_qupv3_wrap0_s3_clk",
2107			.parent_hws = (const struct clk_hw*[]){
2108				&gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
2109			},
2110			.num_parents = 1,
2111			.flags = CLK_SET_RATE_PARENT,
2112			.ops = &clk_branch2_ops,
2113		},
2114	},
2115};
2116
2117static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2118	.halt_reg = 0x174cc,
2119	.halt_check = BRANCH_HALT_VOTED,
2120	.clkr = {
2121		.enable_reg = 0x52008,
2122		.enable_mask = BIT(14),
2123		.hw.init = &(struct clk_init_data){
2124			.name = "gcc_qupv3_wrap0_s4_clk",
2125			.parent_hws = (const struct clk_hw*[]){
2126				&gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
2127			},
2128			.num_parents = 1,
2129			.flags = CLK_SET_RATE_PARENT,
2130			.ops = &clk_branch2_ops,
2131		},
2132	},
2133};
2134
2135static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2136	.halt_reg = 0x175fc,
2137	.halt_check = BRANCH_HALT_VOTED,
2138	.clkr = {
2139		.enable_reg = 0x52008,
2140		.enable_mask = BIT(15),
2141		.hw.init = &(struct clk_init_data){
2142			.name = "gcc_qupv3_wrap0_s5_clk",
2143			.parent_hws = (const struct clk_hw*[]){
2144				&gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
2145			},
2146			.num_parents = 1,
2147			.flags = CLK_SET_RATE_PARENT,
2148			.ops = &clk_branch2_ops,
2149		},
2150	},
2151};
2152
2153static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
2154	.halt_reg = 0x1772c,
2155	.halt_check = BRANCH_HALT_VOTED,
2156	.clkr = {
2157		.enable_reg = 0x52008,
2158		.enable_mask = BIT(16),
2159		.hw.init = &(struct clk_init_data){
2160			.name = "gcc_qupv3_wrap0_s6_clk",
2161			.parent_hws = (const struct clk_hw*[]){
2162				&gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
2163			},
2164			.num_parents = 1,
2165			.flags = CLK_SET_RATE_PARENT,
2166			.ops = &clk_branch2_ops,
2167		},
2168	},
2169};
2170
2171static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
2172	.halt_reg = 0x1785c,
2173	.halt_check = BRANCH_HALT_VOTED,
2174	.clkr = {
2175		.enable_reg = 0x52008,
2176		.enable_mask = BIT(17),
2177		.hw.init = &(struct clk_init_data){
2178			.name = "gcc_qupv3_wrap0_s7_clk",
2179			.parent_hws = (const struct clk_hw*[]){
2180				&gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
2181			},
2182			.num_parents = 1,
2183			.flags = CLK_SET_RATE_PARENT,
2184			.ops = &clk_branch2_ops,
2185		},
2186	},
2187};
2188
2189static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
2190	.halt_reg = 0x23140,
2191	.halt_check = BRANCH_HALT_VOTED,
2192	.clkr = {
2193		.enable_reg = 0x52008,
2194		.enable_mask = BIT(18),
2195		.hw.init = &(struct clk_init_data){
2196			.name = "gcc_qupv3_wrap1_core_2x_clk",
2197			.ops = &clk_branch2_ops,
2198		},
2199	},
2200};
2201
2202static struct clk_branch gcc_qupv3_wrap1_core_clk = {
2203	.halt_reg = 0x23138,
2204	.halt_check = BRANCH_HALT_VOTED,
2205	.clkr = {
2206		.enable_reg = 0x52008,
2207		.enable_mask = BIT(19),
2208		.hw.init = &(struct clk_init_data){
2209			.name = "gcc_qupv3_wrap1_core_clk",
2210			.ops = &clk_branch2_ops,
2211		},
2212	},
2213};
2214
2215static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
2216	.halt_reg = 0x1800c,
2217	.halt_check = BRANCH_HALT_VOTED,
2218	.clkr = {
2219		.enable_reg = 0x52008,
2220		.enable_mask = BIT(22),
2221		.hw.init = &(struct clk_init_data){
2222			.name = "gcc_qupv3_wrap1_s0_clk",
2223			.parent_hws = (const struct clk_hw*[]){
2224				&gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
2225			},
2226			.num_parents = 1,
2227			.flags = CLK_SET_RATE_PARENT,
2228			.ops = &clk_branch2_ops,
2229		},
2230	},
2231};
2232
2233static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
2234	.halt_reg = 0x1813c,
2235	.halt_check = BRANCH_HALT_VOTED,
2236	.clkr = {
2237		.enable_reg = 0x52008,
2238		.enable_mask = BIT(23),
2239		.hw.init = &(struct clk_init_data){
2240			.name = "gcc_qupv3_wrap1_s1_clk",
2241			.parent_hws = (const struct clk_hw*[]){
2242				&gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
2243			},
2244			.num_parents = 1,
2245			.flags = CLK_SET_RATE_PARENT,
2246			.ops = &clk_branch2_ops,
2247		},
2248	},
2249};
2250
2251static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
2252	.halt_reg = 0x1826c,
2253	.halt_check = BRANCH_HALT_VOTED,
2254	.clkr = {
2255		.enable_reg = 0x52008,
2256		.enable_mask = BIT(24),
2257		.hw.init = &(struct clk_init_data){
2258			.name = "gcc_qupv3_wrap1_s2_clk",
2259			.parent_hws = (const struct clk_hw*[]){
2260				&gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
2261			},
2262			.num_parents = 1,
2263			.flags = CLK_SET_RATE_PARENT,
2264			.ops = &clk_branch2_ops,
2265		},
2266	},
2267};
2268
2269static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
2270	.halt_reg = 0x1839c,
2271	.halt_check = BRANCH_HALT_VOTED,
2272	.clkr = {
2273		.enable_reg = 0x52008,
2274		.enable_mask = BIT(25),
2275		.hw.init = &(struct clk_init_data){
2276			.name = "gcc_qupv3_wrap1_s3_clk",
2277			.parent_hws = (const struct clk_hw*[]){
2278				&gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
2279			},
2280			.num_parents = 1,
2281			.flags = CLK_SET_RATE_PARENT,
2282			.ops = &clk_branch2_ops,
2283		},
2284	},
2285};
2286
2287static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
2288	.halt_reg = 0x184cc,
2289	.halt_check = BRANCH_HALT_VOTED,
2290	.clkr = {
2291		.enable_reg = 0x52008,
2292		.enable_mask = BIT(26),
2293		.hw.init = &(struct clk_init_data){
2294			.name = "gcc_qupv3_wrap1_s4_clk",
2295			.parent_hws = (const struct clk_hw*[]){
2296				&gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
2297			},
2298			.num_parents = 1,
2299			.flags = CLK_SET_RATE_PARENT,
2300			.ops = &clk_branch2_ops,
2301		},
2302	},
2303};
2304
2305static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
2306	.halt_reg = 0x185fc,
2307	.halt_check = BRANCH_HALT_VOTED,
2308	.clkr = {
2309		.enable_reg = 0x52008,
2310		.enable_mask = BIT(27),
2311		.hw.init = &(struct clk_init_data){
2312			.name = "gcc_qupv3_wrap1_s5_clk",
2313			.parent_hws = (const struct clk_hw*[]){
2314				&gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
2315			},
2316			.num_parents = 1,
2317			.flags = CLK_SET_RATE_PARENT,
2318			.ops = &clk_branch2_ops,
2319		},
2320	},
2321};
2322
2323static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
2324	.halt_reg = 0x1872c,
2325	.halt_check = BRANCH_HALT_VOTED,
2326	.clkr = {
2327		.enable_reg = 0x52000,
2328		.enable_mask = BIT(13),
2329		.hw.init = &(struct clk_init_data){
2330			.name = "gcc_qupv3_wrap1_s6_clk",
2331			.parent_hws = (const struct clk_hw*[]){
2332				&gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
2333			},
2334			.num_parents = 1,
2335			.flags = CLK_SET_RATE_PARENT,
2336			.ops = &clk_branch2_ops,
2337		},
2338	},
2339};
2340
2341static struct clk_branch gcc_qupv3_wrap1_s7_clk = {
2342	.halt_reg = 0x1885c,
2343	.halt_check = BRANCH_HALT_VOTED,
2344	.clkr = {
2345		.enable_reg = 0x52000,
2346		.enable_mask = BIT(14),
2347		.hw.init = &(struct clk_init_data){
2348			.name = "gcc_qupv3_wrap1_s7_clk",
2349			.parent_hws = (const struct clk_hw*[]){
2350				&gcc_qupv3_wrap1_s7_clk_src.clkr.hw,
2351			},
2352			.num_parents = 1,
2353			.flags = CLK_SET_RATE_PARENT,
2354			.ops = &clk_branch2_ops,
2355		},
2356	},
2357};
2358
2359static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
2360	.halt_reg = 0x17004,
2361	.halt_check = BRANCH_HALT_VOTED,
2362	.hwcg_reg = 0x17004,
2363	.hwcg_bit = 1,
2364	.clkr = {
2365		.enable_reg = 0x52008,
2366		.enable_mask = BIT(6),
2367		.hw.init = &(struct clk_init_data){
2368			.name = "gcc_qupv3_wrap_0_m_ahb_clk",
2369			.ops = &clk_branch2_ops,
2370		},
2371	},
2372};
2373
2374static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
2375	.halt_reg = 0x17008,
2376	.halt_check = BRANCH_HALT_VOTED,
2377	.hwcg_reg = 0x17008,
2378	.hwcg_bit = 1,
2379	.clkr = {
2380		.enable_reg = 0x52008,
2381		.enable_mask = BIT(7),
2382		.hw.init = &(struct clk_init_data){
2383			.name = "gcc_qupv3_wrap_0_s_ahb_clk",
2384			.ops = &clk_branch2_ops,
2385		},
2386	},
2387};
2388
2389static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
2390	.halt_reg = 0x18004,
2391	.halt_check = BRANCH_HALT_VOTED,
2392	.hwcg_reg = 0x18004,
2393	.hwcg_bit = 1,
2394	.clkr = {
2395		.enable_reg = 0x52008,
2396		.enable_mask = BIT(20),
2397		.hw.init = &(struct clk_init_data){
2398			.name = "gcc_qupv3_wrap_1_m_ahb_clk",
2399			.ops = &clk_branch2_ops,
2400		},
2401	},
2402};
2403
2404static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
2405	.halt_reg = 0x18008,
2406	.halt_check = BRANCH_HALT_VOTED,
2407	.hwcg_reg = 0x18008,
2408	.hwcg_bit = 1,
2409	.clkr = {
2410		.enable_reg = 0x52008,
2411		.enable_mask = BIT(21),
2412		.hw.init = &(struct clk_init_data){
2413			.name = "gcc_qupv3_wrap_1_s_ahb_clk",
2414			.ops = &clk_branch2_ops,
2415		},
2416	},
2417};
2418
2419static struct clk_branch gcc_sdcc1_ahb_clk = {
2420	.halt_reg = 0x75004,
2421	.halt_check = BRANCH_HALT,
2422	.clkr = {
2423		.enable_reg = 0x75004,
2424		.enable_mask = BIT(0),
2425		.hw.init = &(struct clk_init_data){
2426			.name = "gcc_sdcc1_ahb_clk",
2427			.ops = &clk_branch2_ops,
2428		},
2429	},
2430};
2431
2432static struct clk_branch gcc_sdcc1_apps_clk = {
2433	.halt_reg = 0x75008,
2434	.halt_check = BRANCH_HALT,
2435	.clkr = {
2436		.enable_reg = 0x75008,
2437		.enable_mask = BIT(0),
2438		.hw.init = &(struct clk_init_data){
2439			.name = "gcc_sdcc1_apps_clk",
2440			.parent_hws = (const struct clk_hw*[]){
2441				&gcc_sdcc1_apps_clk_src.clkr.hw,
2442			},
2443			.num_parents = 1,
2444			.flags = CLK_SET_RATE_PARENT,
2445			.ops = &clk_branch2_ops,
2446		},
2447	},
2448};
2449
2450static struct clk_branch gcc_sdcc1_ice_core_clk = {
2451	.halt_reg = 0x75024,
2452	.halt_check = BRANCH_HALT_VOTED,
2453	.hwcg_reg = 0x75024,
2454	.hwcg_bit = 1,
2455	.clkr = {
2456		.enable_reg = 0x75024,
2457		.enable_mask = BIT(0),
2458		.hw.init = &(struct clk_init_data){
2459			.name = "gcc_sdcc1_ice_core_clk",
2460			.parent_hws = (const struct clk_hw*[]){
2461				&gcc_sdcc1_ice_core_clk_src.clkr.hw,
2462			},
2463			.num_parents = 1,
2464			.flags = CLK_SET_RATE_PARENT,
2465			.ops = &clk_branch2_ops,
2466		},
2467	},
2468};
2469
2470static struct clk_branch gcc_sdcc2_ahb_clk = {
2471	.halt_reg = 0x14008,
2472	.halt_check = BRANCH_HALT,
2473	.clkr = {
2474		.enable_reg = 0x14008,
2475		.enable_mask = BIT(0),
2476		.hw.init = &(struct clk_init_data){
2477			.name = "gcc_sdcc2_ahb_clk",
2478			.ops = &clk_branch2_ops,
2479		},
2480	},
2481};
2482
2483static struct clk_branch gcc_sdcc2_apps_clk = {
2484	.halt_reg = 0x14004,
2485	.halt_check = BRANCH_HALT,
2486	.clkr = {
2487		.enable_reg = 0x14004,
2488		.enable_mask = BIT(0),
2489		.hw.init = &(struct clk_init_data){
2490			.name = "gcc_sdcc2_apps_clk",
2491			.parent_hws = (const struct clk_hw*[]){
2492				&gcc_sdcc2_apps_clk_src.clkr.hw,
2493			},
2494			.num_parents = 1,
2495			.flags = CLK_SET_RATE_PARENT,
2496			.ops = &clk_branch2_ops,
2497		},
2498	},
2499};
2500
2501static struct clk_branch gcc_sdcc4_ahb_clk = {
2502	.halt_reg = 0x16008,
2503	.halt_check = BRANCH_HALT,
2504	.clkr = {
2505		.enable_reg = 0x16008,
2506		.enable_mask = BIT(0),
2507		.hw.init = &(struct clk_init_data){
2508			.name = "gcc_sdcc4_ahb_clk",
2509			.ops = &clk_branch2_ops,
2510		},
2511	},
2512};
2513
2514static struct clk_branch gcc_sdcc4_apps_clk = {
2515	.halt_reg = 0x16004,
2516	.halt_check = BRANCH_HALT,
2517	.clkr = {
2518		.enable_reg = 0x16004,
2519		.enable_mask = BIT(0),
2520		.hw.init = &(struct clk_init_data){
2521			.name = "gcc_sdcc4_apps_clk",
2522			.parent_hws = (const struct clk_hw*[]){
2523				&gcc_sdcc4_apps_clk_src.clkr.hw,
2524			},
2525			.num_parents = 1,
2526			.flags = CLK_SET_RATE_PARENT,
2527			.ops = &clk_branch2_ops,
2528		},
2529	},
2530};
2531
2532static struct clk_branch gcc_throttle_pcie_ahb_clk = {
2533	.halt_reg = 0x9001c,
2534	.halt_check = BRANCH_HALT,
2535	.clkr = {
2536		.enable_reg = 0x9001c,
2537		.enable_mask = BIT(0),
2538		.hw.init = &(struct clk_init_data){
2539			.name = "gcc_throttle_pcie_ahb_clk",
2540			.ops = &clk_branch2_ops,
2541		},
2542	},
2543};
2544
2545static struct clk_branch gcc_titan_nrt_throttle_core_clk = {
2546	.halt_reg = 0x26024,
2547	.halt_check = BRANCH_HALT_SKIP,
2548	.hwcg_reg = 0x26024,
2549	.hwcg_bit = 1,
2550	.clkr = {
2551		.enable_reg = 0x26024,
2552		.enable_mask = BIT(0),
2553		.hw.init = &(struct clk_init_data){
2554			.name = "gcc_titan_nrt_throttle_core_clk",
2555			.ops = &clk_branch2_ops,
2556		},
2557	},
2558};
2559
2560static struct clk_branch gcc_titan_rt_throttle_core_clk = {
2561	.halt_reg = 0x26018,
2562	.halt_check = BRANCH_HALT_SKIP,
2563	.hwcg_reg = 0x26018,
2564	.hwcg_bit = 1,
2565	.clkr = {
2566		.enable_reg = 0x26018,
2567		.enable_mask = BIT(0),
2568		.hw.init = &(struct clk_init_data){
2569			.name = "gcc_titan_rt_throttle_core_clk",
2570			.ops = &clk_branch2_ops,
2571		},
2572	},
2573};
2574
2575static struct clk_branch gcc_ufs_1_clkref_en = {
2576	.halt_reg = 0x8c000,
2577	.halt_check = BRANCH_HALT,
2578	.clkr = {
2579		.enable_reg = 0x8c000,
2580		.enable_mask = BIT(0),
2581		.hw.init = &(struct clk_init_data){
2582			.name = "gcc_ufs_1_clkref_en",
2583			.ops = &clk_branch2_ops,
2584		},
2585	},
2586};
2587
2588static struct clk_branch gcc_ufs_phy_ahb_clk = {
2589	.halt_reg = 0x77018,
2590	.halt_check = BRANCH_HALT_VOTED,
2591	.hwcg_reg = 0x77018,
2592	.hwcg_bit = 1,
2593	.clkr = {
2594		.enable_reg = 0x77018,
2595		.enable_mask = BIT(0),
2596		.hw.init = &(struct clk_init_data){
2597			.name = "gcc_ufs_phy_ahb_clk",
2598			.ops = &clk_branch2_ops,
2599		},
2600	},
2601};
2602
2603static struct clk_branch gcc_ufs_phy_axi_clk = {
2604	.halt_reg = 0x77010,
2605	.halt_check = BRANCH_HALT_VOTED,
2606	.hwcg_reg = 0x77010,
2607	.hwcg_bit = 1,
2608	.clkr = {
2609		.enable_reg = 0x77010,
2610		.enable_mask = BIT(0),
2611		.hw.init = &(struct clk_init_data){
2612			.name = "gcc_ufs_phy_axi_clk",
2613			.parent_hws = (const struct clk_hw*[]){
2614				&gcc_ufs_phy_axi_clk_src.clkr.hw,
2615			},
2616			.num_parents = 1,
2617			.flags = CLK_SET_RATE_PARENT,
2618			.ops = &clk_branch2_ops,
2619		},
2620	},
2621};
2622
2623static struct clk_branch gcc_ufs_phy_ice_core_clk = {
2624	.halt_reg = 0x77064,
2625	.halt_check = BRANCH_HALT_VOTED,
2626	.hwcg_reg = 0x77064,
2627	.hwcg_bit = 1,
2628	.clkr = {
2629		.enable_reg = 0x77064,
2630		.enable_mask = BIT(0),
2631		.hw.init = &(struct clk_init_data){
2632			.name = "gcc_ufs_phy_ice_core_clk",
2633			.parent_hws = (const struct clk_hw*[]){
2634				&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
2635			},
2636			.num_parents = 1,
2637			.flags = CLK_SET_RATE_PARENT,
2638			.ops = &clk_branch2_ops,
2639		},
2640	},
2641};
2642
2643static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
2644	.halt_reg = 0x7709c,
2645	.halt_check = BRANCH_HALT_VOTED,
2646	.hwcg_reg = 0x7709c,
2647	.hwcg_bit = 1,
2648	.clkr = {
2649		.enable_reg = 0x7709c,
2650		.enable_mask = BIT(0),
2651		.hw.init = &(struct clk_init_data){
2652			.name = "gcc_ufs_phy_phy_aux_clk",
2653			.parent_hws = (const struct clk_hw*[]){
2654				&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
2655			},
2656			.num_parents = 1,
2657			.flags = CLK_SET_RATE_PARENT,
2658			.ops = &clk_branch2_ops,
2659		},
2660	},
2661};
2662
2663static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
2664	.halt_reg = 0x77020,
2665	.halt_check = BRANCH_HALT_DELAY,
2666	.clkr = {
2667		.enable_reg = 0x77020,
2668		.enable_mask = BIT(0),
2669		.hw.init = &(struct clk_init_data){
2670			.name = "gcc_ufs_phy_rx_symbol_0_clk",
2671			.parent_hws = (const struct clk_hw*[]){
2672				&gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
2673			},
2674			.num_parents = 1,
2675			.flags = CLK_SET_RATE_PARENT,
2676			.ops = &clk_branch2_ops,
2677		},
2678	},
2679};
2680
2681static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
2682	.halt_reg = 0x770b8,
2683	.halt_check = BRANCH_HALT_DELAY,
2684	.clkr = {
2685		.enable_reg = 0x770b8,
2686		.enable_mask = BIT(0),
2687		.hw.init = &(struct clk_init_data){
2688			.name = "gcc_ufs_phy_rx_symbol_1_clk",
2689			.parent_hws = (const struct clk_hw*[]){
2690				&gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
2691			},
2692			.num_parents = 1,
2693			.flags = CLK_SET_RATE_PARENT,
2694			.ops = &clk_branch2_ops,
2695		},
2696	},
2697};
2698
2699static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
2700	.halt_reg = 0x7701c,
2701	.halt_check = BRANCH_HALT_DELAY,
2702	.clkr = {
2703		.enable_reg = 0x7701c,
2704		.enable_mask = BIT(0),
2705		.hw.init = &(struct clk_init_data){
2706			.name = "gcc_ufs_phy_tx_symbol_0_clk",
2707			.parent_hws = (const struct clk_hw*[]){
2708				&gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
2709			},
2710			.num_parents = 1,
2711			.flags = CLK_SET_RATE_PARENT,
2712			.ops = &clk_branch2_ops,
2713		},
2714	},
2715};
2716
2717static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
2718	.halt_reg = 0x7705c,
2719	.halt_check = BRANCH_HALT_VOTED,
2720	.hwcg_reg = 0x7705c,
2721	.hwcg_bit = 1,
2722	.clkr = {
2723		.enable_reg = 0x7705c,
2724		.enable_mask = BIT(0),
2725		.hw.init = &(struct clk_init_data){
2726			.name = "gcc_ufs_phy_unipro_core_clk",
2727			.parent_hws = (const struct clk_hw*[]){
2728				&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
2729			},
2730			.num_parents = 1,
2731			.flags = CLK_SET_RATE_PARENT,
2732			.ops = &clk_branch2_ops,
2733		},
2734	},
2735};
2736
2737static struct clk_branch gcc_usb30_prim_master_clk = {
2738	.halt_reg = 0xf010,
2739	.halt_check = BRANCH_HALT,
2740	.clkr = {
2741		.enable_reg = 0xf010,
2742		.enable_mask = BIT(0),
2743		.hw.init = &(struct clk_init_data){
2744			.name = "gcc_usb30_prim_master_clk",
2745			.parent_hws = (const struct clk_hw*[]){
2746				&gcc_usb30_prim_master_clk_src.clkr.hw,
2747			},
2748			.num_parents = 1,
2749			.flags = CLK_SET_RATE_PARENT,
2750			.ops = &clk_branch2_ops,
2751		},
2752	},
2753};
2754
2755static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
2756	.halt_reg = 0xf01c,
2757	.halt_check = BRANCH_HALT,
2758	.clkr = {
2759		.enable_reg = 0xf01c,
2760		.enable_mask = BIT(0),
2761		.hw.init = &(struct clk_init_data){
2762			.name = "gcc_usb30_prim_mock_utmi_clk",
2763			.parent_hws = (const struct clk_hw*[]) {
2764				&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
2765			},
2766			.num_parents = 1,
2767			.flags = CLK_SET_RATE_PARENT,
2768			.ops = &clk_branch2_ops,
2769		},
2770	},
2771};
2772
2773static struct clk_branch gcc_usb30_prim_sleep_clk = {
2774	.halt_reg = 0xf018,
2775	.halt_check = BRANCH_HALT,
2776	.clkr = {
2777		.enable_reg = 0xf018,
2778		.enable_mask = BIT(0),
2779		.hw.init = &(struct clk_init_data){
2780			.name = "gcc_usb30_prim_sleep_clk",
2781			.ops = &clk_branch2_ops,
2782		},
2783	},
2784};
2785
2786static struct clk_branch gcc_usb30_sec_master_clk = {
2787	.halt_reg = 0x9e010,
2788	.halt_check = BRANCH_HALT,
2789	.clkr = {
2790		.enable_reg = 0x9e010,
2791		.enable_mask = BIT(0),
2792		.hw.init = &(struct clk_init_data){
2793			.name = "gcc_usb30_sec_master_clk",
2794			.parent_hws = (const struct clk_hw*[]){
2795				&gcc_usb30_sec_master_clk_src.clkr.hw,
2796			},
2797			.num_parents = 1,
2798			.flags = CLK_SET_RATE_PARENT,
2799			.ops = &clk_branch2_ops,
2800		},
2801	},
2802};
2803
2804static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
2805	.halt_reg = 0x9e01c,
2806	.halt_check = BRANCH_HALT,
2807	.clkr = {
2808		.enable_reg = 0x9e01c,
2809		.enable_mask = BIT(0),
2810		.hw.init = &(struct clk_init_data){
2811			.name = "gcc_usb30_sec_mock_utmi_clk",
2812			.parent_hws = (const struct clk_hw*[]) {
2813				&gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw,
2814			},
2815			.num_parents = 1,
2816			.flags = CLK_SET_RATE_PARENT,
2817			.ops = &clk_branch2_ops,
2818		},
2819	},
2820};
2821
2822static struct clk_branch gcc_usb30_sec_sleep_clk = {
2823	.halt_reg = 0x9e018,
2824	.halt_check = BRANCH_HALT,
2825	.clkr = {
2826		.enable_reg = 0x9e018,
2827		.enable_mask = BIT(0),
2828		.hw.init = &(struct clk_init_data){
2829			.name = "gcc_usb30_sec_sleep_clk",
2830			.ops = &clk_branch2_ops,
2831		},
2832	},
2833};
2834
2835static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
2836	.halt_reg = 0xf054,
2837	.halt_check = BRANCH_HALT,
2838	.clkr = {
2839		.enable_reg = 0xf054,
2840		.enable_mask = BIT(0),
2841		.hw.init = &(struct clk_init_data){
2842			.name = "gcc_usb3_prim_phy_aux_clk",
2843			.parent_hws = (const struct clk_hw*[]){
2844				&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2845			},
2846			.num_parents = 1,
2847			.flags = CLK_SET_RATE_PARENT,
2848			.ops = &clk_branch2_ops,
2849		},
2850	},
2851};
2852
2853static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
2854	.halt_reg = 0xf058,
2855	.halt_check = BRANCH_HALT,
2856	.clkr = {
2857		.enable_reg = 0xf058,
2858		.enable_mask = BIT(0),
2859		.hw.init = &(struct clk_init_data){
2860			.name = "gcc_usb3_prim_phy_com_aux_clk",
2861			.parent_hws = (const struct clk_hw*[]){
2862				&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2863			},
2864			.num_parents = 1,
2865			.flags = CLK_SET_RATE_PARENT,
2866			.ops = &clk_branch2_ops,
2867		},
2868	},
2869};
2870
2871static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
2872	.halt_reg = 0xf05c,
2873	.halt_check = BRANCH_HALT_DELAY,
2874	.hwcg_reg = 0xf05c,
2875	.hwcg_bit = 1,
2876	.clkr = {
2877		.enable_reg = 0xf05c,
2878		.enable_mask = BIT(0),
2879		.hw.init = &(struct clk_init_data){
2880			.name = "gcc_usb3_prim_phy_pipe_clk",
2881			.parent_hws = (const struct clk_hw*[]){
2882				&gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
2883			},
2884			.num_parents = 1,
2885			.flags = CLK_SET_RATE_PARENT,
2886			.ops = &clk_branch2_ops,
2887		},
2888	},
2889};
2890
2891static struct clk_branch gcc_cfg_noc_lpass_clk = {
2892	.halt_reg = 0x47020,
2893	.halt_check = BRANCH_HALT,
2894	.clkr = {
2895		.enable_reg = 0x47020,
2896		.enable_mask = BIT(0),
2897		.hw.init = &(struct clk_init_data){
2898			.name = "gcc_cfg_noc_lpass_clk",
2899			.ops = &clk_branch2_aon_ops,
2900		},
2901	},
2902};
2903static struct clk_branch gcc_mss_cfg_ahb_clk = {
2904	.halt_reg = 0x8a000,
2905	.halt_check = BRANCH_HALT,
2906	.clkr = {
2907		.enable_reg = 0x8a000,
2908		.enable_mask = BIT(0),
2909		.hw.init = &(struct clk_init_data){
2910			.name = "gcc_mss_cfg_ahb_clk",
2911			.ops = &clk_branch2_ops,
2912		},
2913	},
2914};
2915
2916static struct clk_branch gcc_mss_offline_axi_clk = {
2917	.halt_reg = 0x8a004,
2918	.halt_check = BRANCH_HALT_DELAY,
2919	.clkr = {
2920		.enable_reg = 0x8a004,
2921		.enable_mask = BIT(0),
2922		.hw.init = &(struct clk_init_data){
2923			.name = "gcc_mss_offline_axi_clk",
2924			.ops = &clk_branch2_ops,
2925		},
2926	},
2927};
2928
2929static struct clk_branch gcc_mss_snoc_axi_clk = {
2930	.halt_reg = 0x8a154,
2931	.halt_check = BRANCH_HALT_DELAY,
2932	.clkr = {
2933		.enable_reg = 0x8a154,
2934		.enable_mask = BIT(0),
2935		.hw.init = &(struct clk_init_data){
2936			.name = "gcc_mss_snoc_axi_clk",
2937			.ops = &clk_branch2_ops,
2938		},
2939	},
2940};
2941
2942static struct clk_branch gcc_mss_q6_memnoc_axi_clk = {
2943	.halt_reg = 0x8a158,
2944	.halt_check = BRANCH_HALT,
2945	.clkr = {
2946		.enable_reg = 0x8a158,
2947		.enable_mask = BIT(0),
2948		.hw.init = &(struct clk_init_data){
2949			.name = "gcc_mss_q6_memnoc_axi_clk",
2950			.ops = &clk_branch2_ops,
2951		},
2952	},
2953};
2954
2955static struct clk_regmap_mux gcc_mss_q6ss_boot_clk_src = {
2956	.reg = 0x8a2a4,
2957	.shift = 0,
2958	.width = 1,
2959	.parent_map = gcc_parent_map_15,
2960	.clkr = {
2961		.hw.init = &(struct clk_init_data){
2962			.name = "gcc_mss_q6ss_boot_clk_src",
2963			.parent_data = gcc_parent_data_15,
2964			.num_parents = ARRAY_SIZE(gcc_parent_data_15),
2965			.ops = &clk_regmap_mux_closest_ops,
2966		},
2967	},
2968};
2969
2970static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
2971	.halt_reg = 0x9e054,
2972	.halt_check = BRANCH_HALT,
2973	.clkr = {
2974		.enable_reg = 0x9e054,
2975		.enable_mask = BIT(0),
2976		.hw.init = &(struct clk_init_data){
2977			.name = "gcc_usb3_sec_phy_aux_clk",
2978			.parent_hws = (const struct clk_hw*[]){
2979				&gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
2980			},
2981			.num_parents = 1,
2982			.flags = CLK_SET_RATE_PARENT,
2983			.ops = &clk_branch2_ops,
2984		},
2985	},
2986};
2987
2988static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
2989	.halt_reg = 0x9e058,
2990	.halt_check = BRANCH_HALT,
2991	.clkr = {
2992		.enable_reg = 0x9e058,
2993		.enable_mask = BIT(0),
2994		.hw.init = &(struct clk_init_data){
2995			.name = "gcc_usb3_sec_phy_com_aux_clk",
2996			.parent_hws = (const struct clk_hw*[]){
2997				&gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
2998			},
2999			.num_parents = 1,
3000			.flags = CLK_SET_RATE_PARENT,
3001			.ops = &clk_branch2_ops,
3002		},
3003	},
3004};
3005
3006static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
3007	.halt_reg = 0x9e05c,
3008	.halt_check = BRANCH_HALT_SKIP,
3009	.hwcg_reg = 0x9e05c,
3010	.hwcg_bit = 1,
3011	.clkr = {
3012		.enable_reg = 0x9e05c,
3013		.enable_mask = BIT(0),
3014		.hw.init = &(struct clk_init_data){
3015			.name = "gcc_usb3_sec_phy_pipe_clk",
3016			.parent_hws = (const struct clk_hw*[]){
3017				&gcc_usb3_sec_phy_pipe_clk_src.clkr.hw,
3018			},
3019			.num_parents = 1,
3020			.flags = CLK_SET_RATE_PARENT,
3021			.ops = &clk_branch2_ops,
3022		},
3023	},
3024};
3025
3026static struct clk_branch gcc_video_axi0_clk = {
3027	.halt_reg = 0x2800c,
3028	.halt_check = BRANCH_HALT_SKIP,
3029	.hwcg_reg = 0x2800c,
3030	.hwcg_bit = 1,
3031	.clkr = {
3032		.enable_reg = 0x2800c,
3033		.enable_mask = BIT(0),
3034		.hw.init = &(struct clk_init_data){
3035			.name = "gcc_video_axi0_clk",
3036			.ops = &clk_branch2_ops,
3037		},
3038	},
3039};
3040
3041static struct clk_branch gcc_video_mvp_throttle_core_clk = {
3042	.halt_reg = 0x28010,
3043	.halt_check = BRANCH_HALT_SKIP,
3044	.hwcg_reg = 0x28010,
3045	.hwcg_bit = 1,
3046	.clkr = {
3047		.enable_reg = 0x28010,
3048		.enable_mask = BIT(0),
3049		.hw.init = &(struct clk_init_data){
3050			.name = "gcc_video_mvp_throttle_core_clk",
3051			.ops = &clk_branch2_ops,
3052		},
3053	},
3054};
3055
3056static struct clk_branch gcc_wpss_ahb_clk = {
3057	.halt_reg = 0x9d154,
3058	.halt_check = BRANCH_HALT,
3059	.clkr = {
3060		.enable_reg = 0x9d154,
3061		.enable_mask = BIT(0),
3062		.hw.init = &(struct clk_init_data){
3063			.name = "gcc_wpss_ahb_clk",
3064			.ops = &clk_branch2_ops,
3065		},
3066	},
3067};
3068
3069static struct clk_branch gcc_wpss_ahb_bdg_mst_clk = {
3070	.halt_reg = 0x9d158,
3071	.halt_check = BRANCH_HALT,
3072	.clkr = {
3073		.enable_reg = 0x9d158,
3074		.enable_mask = BIT(0),
3075		.hw.init = &(struct clk_init_data){
3076			.name = "gcc_wpss_ahb_bdg_mst_clk",
3077			.ops = &clk_branch2_ops,
3078		},
3079	},
3080};
3081
3082static struct clk_branch gcc_wpss_rscp_clk = {
3083	.halt_reg = 0x9d16c,
3084	.halt_check = BRANCH_HALT,
3085	.clkr = {
3086		.enable_reg = 0x9d16c,
3087		.enable_mask = BIT(0),
3088		.hw.init = &(struct clk_init_data){
3089			.name = "gcc_wpss_rscp_clk",
3090			.ops = &clk_branch2_ops,
3091		},
3092	},
3093};
3094
3095static struct gdsc gcc_pcie_0_gdsc = {
3096	.gdscr = 0x6b004,
3097	.pd = {
3098		.name = "gcc_pcie_0_gdsc",
3099	},
3100	.pwrsts = PWRSTS_OFF_ON,
3101	.flags = VOTABLE,
3102};
3103
3104static struct gdsc gcc_pcie_1_gdsc = {
3105	.gdscr = 0x8d004,
3106	.pd = {
3107		.name = "gcc_pcie_1_gdsc",
3108	},
3109	.pwrsts = PWRSTS_RET_ON,
3110	.flags = VOTABLE,
3111};
3112
3113static struct gdsc gcc_ufs_phy_gdsc = {
3114	.gdscr = 0x77004,
3115	.pd = {
3116		.name = "gcc_ufs_phy_gdsc",
3117	},
3118	.pwrsts = PWRSTS_OFF_ON,
3119	.flags = VOTABLE,
3120};
3121
3122static struct gdsc gcc_usb30_prim_gdsc = {
3123	.gdscr = 0xf004,
3124	.pd = {
3125		.name = "gcc_usb30_prim_gdsc",
3126	},
3127	.pwrsts = PWRSTS_RET_ON,
3128	.flags = VOTABLE,
3129};
3130
3131static struct gdsc gcc_usb30_sec_gdsc = {
3132	.gdscr = 0x9e004,
3133	.pd = {
3134		.name = "gcc_usb30_sec_gdsc",
3135	},
3136	.pwrsts = PWRSTS_RET_ON,
3137	.flags = VOTABLE,
3138};
3139
3140static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
3141	.gdscr = 0x7d050,
3142	.pd = {
3143		.name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
3144	},
3145	.pwrsts = PWRSTS_OFF_ON,
3146	.flags = VOTABLE,
3147};
3148
3149static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {
3150	.gdscr = 0x7d058,
3151	.pd = {
3152		.name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",
3153	},
3154	.pwrsts = PWRSTS_OFF_ON,
3155	.flags = VOTABLE,
3156};
3157
3158static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc = {
3159	.gdscr = 0x7d054,
3160	.pd = {
3161		.name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc",
3162	},
3163	.pwrsts = PWRSTS_OFF_ON,
3164	.flags = VOTABLE,
3165};
3166
3167static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = {
3168	.gdscr = 0x7d05c,
3169	.pd = {
3170		.name = "hlos1_vote_turing_mmu_tbu0_gdsc",
3171	},
3172	.pwrsts = PWRSTS_OFF_ON,
3173	.flags = VOTABLE,
3174};
3175
3176static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = {
3177	.gdscr = 0x7d060,
3178	.pd = {
3179		.name = "hlos1_vote_turing_mmu_tbu1_gdsc",
3180	},
3181	.pwrsts = PWRSTS_OFF_ON,
3182	.flags = VOTABLE,
3183};
3184
3185static struct clk_regmap *gcc_sc7280_clocks[] = {
3186	[GCC_AGGRE_NOC_PCIE_0_AXI_CLK] = &gcc_aggre_noc_pcie_0_axi_clk.clkr,
3187	[GCC_AGGRE_NOC_PCIE_1_AXI_CLK] = &gcc_aggre_noc_pcie_1_axi_clk.clkr,
3188	[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
3189	[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
3190	[GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
3191	[GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
3192	[GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
3193	[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
3194	[GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
3195	[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
3196	[GCC_DDRSS_PCIE_SF_CLK] = &gcc_ddrss_pcie_sf_clk.clkr,
3197	[GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
3198	[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
3199	[GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,
3200	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3201	[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3202	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3203	[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3204	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3205	[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
3206	[GCC_GPLL0] = &gcc_gpll0.clkr,
3207	[GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
3208	[GCC_GPLL0_OUT_ODD] = &gcc_gpll0_out_odd.clkr,
3209	[GCC_GPLL1] = &gcc_gpll1.clkr,
3210	[GCC_GPLL10] = &gcc_gpll10.clkr,
3211	[GCC_GPLL4] = &gcc_gpll4.clkr,
3212	[GCC_GPLL9] = &gcc_gpll9.clkr,
3213	[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
3214	[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
3215	[GCC_GPU_IREF_EN] = &gcc_gpu_iref_en.clkr,
3216	[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
3217	[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
3218	[GCC_PCIE0_PHY_RCHNG_CLK] = &gcc_pcie0_phy_rchng_clk.clkr,
3219	[GCC_PCIE1_PHY_RCHNG_CLK] = &gcc_pcie1_phy_rchng_clk.clkr,
3220	[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3221	[GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
3222	[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3223	[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3224	[GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
3225	[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3226	[GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
3227	[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3228	[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
3229	[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3230	[GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
3231	[GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3232	[GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3233	[GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,
3234	[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3235	[GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr,
3236	[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3237	[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
3238	[GCC_PCIE_THROTTLE_CORE_CLK] = &gcc_pcie_throttle_core_clk.clkr,
3239	[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3240	[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3241	[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3242	[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3243	[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
3244	[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
3245	[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3246	[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
3247	[GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
3248	[GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
3249	[GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
3250	[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
3251	[GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
3252	[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
3253	[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
3254	[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
3255	[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
3256	[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
3257	[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
3258	[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
3259	[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
3260	[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
3261	[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
3262	[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
3263	[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
3264	[GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
3265	[GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
3266	[GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
3267	[GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
3268	[GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
3269	[GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
3270	[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
3271	[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
3272	[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
3273	[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
3274	[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
3275	[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
3276	[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
3277	[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
3278	[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
3279	[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
3280	[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
3281	[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
3282	[GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
3283	[GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
3284	[GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
3285	[GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
3286	[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
3287	[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
3288	[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
3289	[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
3290	[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3291	[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3292	[GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
3293	[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
3294	[GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
3295	[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3296	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3297	[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
3298	[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3299	[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3300	[GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
3301	[GCC_THROTTLE_PCIE_AHB_CLK] = &gcc_throttle_pcie_ahb_clk.clkr,
3302	[GCC_TITAN_NRT_THROTTLE_CORE_CLK] =
3303		&gcc_titan_nrt_throttle_core_clk.clkr,
3304	[GCC_TITAN_RT_THROTTLE_CORE_CLK] = &gcc_titan_rt_throttle_core_clk.clkr,
3305	[GCC_UFS_1_CLKREF_EN] = &gcc_ufs_1_clkref_en.clkr,
3306	[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
3307	[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
3308	[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
3309	[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
3310	[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
3311	[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
3312	[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
3313	[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
3314	[GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] =
3315		&gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
3316	[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
3317	[GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] =
3318		&gcc_ufs_phy_rx_symbol_1_clk_src.clkr,
3319	[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
3320	[GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] =
3321		&gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
3322	[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
3323	[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
3324		&gcc_ufs_phy_unipro_core_clk_src.clkr,
3325	[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
3326	[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
3327	[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
3328	[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
3329		&gcc_usb30_prim_mock_utmi_clk_src.clkr,
3330	[GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] =
3331		&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
3332	[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
3333	[GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
3334	[GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
3335	[GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
3336	[GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] =
3337			&gcc_usb30_sec_mock_utmi_clk_src.clkr,
3338	[GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] =
3339			&gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr,
3340	[GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
3341	[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
3342	[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
3343	[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
3344	[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
3345	[GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
3346	[GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
3347	[GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
3348	[GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
3349	[GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
3350	[GCC_USB3_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb3_sec_phy_pipe_clk_src.clkr,
3351	[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
3352	[GCC_VIDEO_MVP_THROTTLE_CORE_CLK] =
3353			&gcc_video_mvp_throttle_core_clk.clkr,
3354	[GCC_CFG_NOC_LPASS_CLK] = &gcc_cfg_noc_lpass_clk.clkr,
3355	[GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC] = &gcc_mss_gpll0_main_div_clk_src.clkr,
3356	[GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
3357	[GCC_MSS_OFFLINE_AXI_CLK] = &gcc_mss_offline_axi_clk.clkr,
3358	[GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
3359	[GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr,
3360	[GCC_MSS_Q6SS_BOOT_CLK_SRC] = &gcc_mss_q6ss_boot_clk_src.clkr,
3361	[GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
3362	[GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK] =
3363				&gcc_aggre_noc_pcie_center_sf_axi_clk.clkr,
3364	[GCC_PCIE_CLKREF_EN] = &gcc_pcie_clkref_en.clkr,
3365	[GCC_EDP_CLKREF_EN] = &gcc_edp_clkref_en.clkr,
3366	[GCC_SEC_CTRL_CLK_SRC] = &gcc_sec_ctrl_clk_src.clkr,
3367	[GCC_WPSS_AHB_CLK] = &gcc_wpss_ahb_clk.clkr,
3368	[GCC_WPSS_AHB_BDG_MST_CLK] = &gcc_wpss_ahb_bdg_mst_clk.clkr,
3369	[GCC_WPSS_RSCP_CLK] = &gcc_wpss_rscp_clk.clkr,
3370};
3371
3372static struct gdsc *gcc_sc7280_gdscs[] = {
3373	[GCC_PCIE_0_GDSC] = &gcc_pcie_0_gdsc,
3374	[GCC_PCIE_1_GDSC] = &gcc_pcie_1_gdsc,
3375	[GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc,
3376	[GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc,
3377	[GCC_USB30_SEC_GDSC] = &gcc_usb30_sec_gdsc,
3378	[HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
3379	[HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
3380	[HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc,
3381	[HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc,
3382	[HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc,
3383};
3384
3385static const struct qcom_reset_map gcc_sc7280_resets[] = {
3386	[GCC_PCIE_0_BCR] = { 0x6b000 },
3387	[GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3388	[GCC_PCIE_1_BCR] = { 0x8d000 },
3389	[GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3390	[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3391	[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3392	[GCC_SDCC1_BCR] = { 0x75000 },
3393	[GCC_SDCC2_BCR] = { 0x14000 },
3394	[GCC_SDCC4_BCR] = { 0x16000 },
3395	[GCC_UFS_PHY_BCR] = { 0x77000 },
3396	[GCC_USB30_PRIM_BCR] = { 0xf000 },
3397	[GCC_USB30_SEC_BCR] = { 0x9e000 },
3398	[GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3399	[GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3400	[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
3401	[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3402};
3403
3404static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
3405	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
3406	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
3407	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
3408	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
3409	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
3410	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
3411	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
3412	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
3413	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
3414	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
3415	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
3416	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
3417	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
3418	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
3419	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
3420	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src),
3421};
3422
3423static const struct regmap_config gcc_sc7280_regmap_config = {
3424	.reg_bits = 32,
3425	.reg_stride = 4,
3426	.val_bits = 32,
3427	.max_register = 0x9f128,
3428	.fast_io = true,
3429};
3430
3431static const struct qcom_cc_desc gcc_sc7280_desc = {
3432	.config = &gcc_sc7280_regmap_config,
3433	.clks = gcc_sc7280_clocks,
3434	.num_clks = ARRAY_SIZE(gcc_sc7280_clocks),
3435	.resets = gcc_sc7280_resets,
3436	.num_resets = ARRAY_SIZE(gcc_sc7280_resets),
3437	.gdscs = gcc_sc7280_gdscs,
3438	.num_gdscs = ARRAY_SIZE(gcc_sc7280_gdscs),
3439};
3440
3441static const struct of_device_id gcc_sc7280_match_table[] = {
3442	{ .compatible = "qcom,gcc-sc7280" },
3443	{ }
3444};
3445MODULE_DEVICE_TABLE(of, gcc_sc7280_match_table);
3446
3447static int gcc_sc7280_probe(struct platform_device *pdev)
3448{
3449	struct regmap *regmap;
3450	int ret;
3451
3452	regmap = qcom_cc_map(pdev, &gcc_sc7280_desc);
3453	if (IS_ERR(regmap))
3454		return PTR_ERR(regmap);
3455
3456	/*
3457	 * Keep the clocks always-ON
3458	 * GCC_CAMERA_AHB_CLK/XO_CLK, GCC_DISP_AHB_CLK/XO_CLK
3459	 * GCC_VIDEO_AHB_CLK/XO_CLK, GCC_GPU_CFG_AHB_CLK
3460	 */
3461	regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0));
3462	regmap_update_bits(regmap, 0x26028, BIT(0), BIT(0));
3463	regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0));
3464	regmap_update_bits(regmap, 0x2701C, BIT(0), BIT(0));
3465	regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0));
3466	regmap_update_bits(regmap, 0x28014, BIT(0), BIT(0));
3467	regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
3468	regmap_update_bits(regmap, 0x7100C, BIT(13), BIT(13));
3469
3470	ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
3471			ARRAY_SIZE(gcc_dfs_clocks));
3472	if (ret)
3473		return ret;
3474
3475	return qcom_cc_really_probe(pdev, &gcc_sc7280_desc, regmap);
3476}
3477
3478static struct platform_driver gcc_sc7280_driver = {
3479	.probe = gcc_sc7280_probe,
3480	.driver = {
3481		.name = "gcc-sc7280",
3482		.of_match_table = gcc_sc7280_match_table,
3483	},
3484};
3485
3486static int __init gcc_sc7280_init(void)
3487{
3488	return platform_driver_register(&gcc_sc7280_driver);
3489}
3490subsys_initcall(gcc_sc7280_init);
3491
3492static void __exit gcc_sc7280_exit(void)
3493{
3494	platform_driver_unregister(&gcc_sc7280_driver);
3495}
3496module_exit(gcc_sc7280_exit);
3497
3498MODULE_DESCRIPTION("QTI GCC SC7280 Driver");
3499MODULE_LICENSE("GPL v2");