Loading...
Note: File does not exist in v3.5.6.
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/kernel.h>
7#include <linux/bitops.h>
8#include <linux/err.h>
9#include <linux/platform_device.h>
10#include <linux/property.h>
11#include <linux/module.h>
12#include <linux/of.h>
13#include <linux/of_platform.h>
14#include <linux/clk-provider.h>
15#include <linux/regmap.h>
16#include <linux/reset-controller.h>
17
18#include <dt-bindings/clock/qcom,gcc-msm8960.h>
19#include <dt-bindings/reset/qcom,gcc-msm8960.h>
20
21#include "common.h"
22#include "clk-regmap.h"
23#include "clk-pll.h"
24#include "clk-rcg.h"
25#include "clk-branch.h"
26#include "clk-hfpll.h"
27#include "reset.h"
28
29static struct clk_pll pll3 = {
30 .l_reg = 0x3164,
31 .m_reg = 0x3168,
32 .n_reg = 0x316c,
33 .config_reg = 0x3174,
34 .mode_reg = 0x3160,
35 .status_reg = 0x3178,
36 .status_bit = 16,
37 .clkr.hw.init = &(struct clk_init_data){
38 .name = "pll3",
39 .parent_data = &(const struct clk_parent_data){
40 .fw_name = "pxo", .name = "pxo_board",
41 },
42 .num_parents = 1,
43 .ops = &clk_pll_ops,
44 },
45};
46
47static struct clk_regmap pll4_vote = {
48 .enable_reg = 0x34c0,
49 .enable_mask = BIT(4),
50 .hw.init = &(struct clk_init_data){
51 .name = "pll4_vote",
52 .parent_data = &(const struct clk_parent_data){
53 .fw_name = "pll4", .name = "pll4",
54 },
55 .num_parents = 1,
56 .ops = &clk_pll_vote_ops,
57 },
58};
59
60static struct clk_pll pll8 = {
61 .l_reg = 0x3144,
62 .m_reg = 0x3148,
63 .n_reg = 0x314c,
64 .config_reg = 0x3154,
65 .mode_reg = 0x3140,
66 .status_reg = 0x3158,
67 .status_bit = 16,
68 .clkr.hw.init = &(struct clk_init_data){
69 .name = "pll8",
70 .parent_data = &(const struct clk_parent_data){
71 .fw_name = "pxo", .name = "pxo_board",
72 },
73 .num_parents = 1,
74 .ops = &clk_pll_ops,
75 },
76};
77
78static struct clk_regmap pll8_vote = {
79 .enable_reg = 0x34c0,
80 .enable_mask = BIT(8),
81 .hw.init = &(struct clk_init_data){
82 .name = "pll8_vote",
83 .parent_hws = (const struct clk_hw*[]){
84 &pll8.clkr.hw
85 },
86 .num_parents = 1,
87 .ops = &clk_pll_vote_ops,
88 },
89};
90
91static struct hfpll_data hfpll0_data = {
92 .mode_reg = 0x3200,
93 .l_reg = 0x3208,
94 .m_reg = 0x320c,
95 .n_reg = 0x3210,
96 .config_reg = 0x3204,
97 .status_reg = 0x321c,
98 .config_val = 0x7845c665,
99 .droop_reg = 0x3214,
100 .droop_val = 0x0108c000,
101 .min_rate = 600000000UL,
102 .max_rate = 1800000000UL,
103};
104
105static struct clk_hfpll hfpll0 = {
106 .d = &hfpll0_data,
107 .clkr.hw.init = &(struct clk_init_data){
108 .parent_data = &(const struct clk_parent_data){
109 .fw_name = "pxo", .name = "pxo_board",
110 },
111 .num_parents = 1,
112 .name = "hfpll0",
113 .ops = &clk_ops_hfpll,
114 .flags = CLK_IGNORE_UNUSED,
115 },
116 .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
117};
118
119static struct hfpll_data hfpll1_8064_data = {
120 .mode_reg = 0x3240,
121 .l_reg = 0x3248,
122 .m_reg = 0x324c,
123 .n_reg = 0x3250,
124 .config_reg = 0x3244,
125 .status_reg = 0x325c,
126 .config_val = 0x7845c665,
127 .droop_reg = 0x3254,
128 .droop_val = 0x0108c000,
129 .min_rate = 600000000UL,
130 .max_rate = 1800000000UL,
131};
132
133static struct hfpll_data hfpll1_data = {
134 .mode_reg = 0x3300,
135 .l_reg = 0x3308,
136 .m_reg = 0x330c,
137 .n_reg = 0x3310,
138 .config_reg = 0x3304,
139 .status_reg = 0x331c,
140 .config_val = 0x7845c665,
141 .droop_reg = 0x3314,
142 .droop_val = 0x0108c000,
143 .min_rate = 600000000UL,
144 .max_rate = 1800000000UL,
145};
146
147static struct clk_hfpll hfpll1 = {
148 .d = &hfpll1_data,
149 .clkr.hw.init = &(struct clk_init_data){
150 .parent_data = &(const struct clk_parent_data){
151 .fw_name = "pxo", .name = "pxo_board",
152 },
153 .num_parents = 1,
154 .name = "hfpll1",
155 .ops = &clk_ops_hfpll,
156 .flags = CLK_IGNORE_UNUSED,
157 },
158 .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
159};
160
161static struct hfpll_data hfpll2_data = {
162 .mode_reg = 0x3280,
163 .l_reg = 0x3288,
164 .m_reg = 0x328c,
165 .n_reg = 0x3290,
166 .config_reg = 0x3284,
167 .status_reg = 0x329c,
168 .config_val = 0x7845c665,
169 .droop_reg = 0x3294,
170 .droop_val = 0x0108c000,
171 .min_rate = 600000000UL,
172 .max_rate = 1800000000UL,
173};
174
175static struct clk_hfpll hfpll2 = {
176 .d = &hfpll2_data,
177 .clkr.hw.init = &(struct clk_init_data){
178 .parent_data = &(const struct clk_parent_data){
179 .fw_name = "pxo", .name = "pxo_board",
180 },
181 .num_parents = 1,
182 .name = "hfpll2",
183 .ops = &clk_ops_hfpll,
184 .flags = CLK_IGNORE_UNUSED,
185 },
186 .lock = __SPIN_LOCK_UNLOCKED(hfpll2.lock),
187};
188
189static struct hfpll_data hfpll3_data = {
190 .mode_reg = 0x32c0,
191 .l_reg = 0x32c8,
192 .m_reg = 0x32cc,
193 .n_reg = 0x32d0,
194 .config_reg = 0x32c4,
195 .status_reg = 0x32dc,
196 .config_val = 0x7845c665,
197 .droop_reg = 0x32d4,
198 .droop_val = 0x0108c000,
199 .min_rate = 600000000UL,
200 .max_rate = 1800000000UL,
201};
202
203static struct clk_hfpll hfpll3 = {
204 .d = &hfpll3_data,
205 .clkr.hw.init = &(struct clk_init_data){
206 .parent_data = &(const struct clk_parent_data){
207 .fw_name = "pxo", .name = "pxo_board",
208 },
209 .num_parents = 1,
210 .name = "hfpll3",
211 .ops = &clk_ops_hfpll,
212 .flags = CLK_IGNORE_UNUSED,
213 },
214 .lock = __SPIN_LOCK_UNLOCKED(hfpll3.lock),
215};
216
217static struct hfpll_data hfpll_l2_8064_data = {
218 .mode_reg = 0x3300,
219 .l_reg = 0x3308,
220 .m_reg = 0x330c,
221 .n_reg = 0x3310,
222 .config_reg = 0x3304,
223 .status_reg = 0x331c,
224 .config_val = 0x7845c665,
225 .droop_reg = 0x3314,
226 .droop_val = 0x0108c000,
227 .min_rate = 600000000UL,
228 .max_rate = 1800000000UL,
229};
230
231static struct hfpll_data hfpll_l2_data = {
232 .mode_reg = 0x3400,
233 .l_reg = 0x3408,
234 .m_reg = 0x340c,
235 .n_reg = 0x3410,
236 .config_reg = 0x3404,
237 .status_reg = 0x341c,
238 .config_val = 0x7845c665,
239 .droop_reg = 0x3414,
240 .droop_val = 0x0108c000,
241 .min_rate = 600000000UL,
242 .max_rate = 1800000000UL,
243};
244
245static struct clk_hfpll hfpll_l2 = {
246 .d = &hfpll_l2_data,
247 .clkr.hw.init = &(struct clk_init_data){
248 .parent_data = &(const struct clk_parent_data){
249 .fw_name = "pxo", .name = "pxo_board",
250 },
251 .num_parents = 1,
252 .name = "hfpll_l2",
253 .ops = &clk_ops_hfpll,
254 .flags = CLK_IGNORE_UNUSED,
255 },
256 .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
257};
258
259static struct clk_pll pll14 = {
260 .l_reg = 0x31c4,
261 .m_reg = 0x31c8,
262 .n_reg = 0x31cc,
263 .config_reg = 0x31d4,
264 .mode_reg = 0x31c0,
265 .status_reg = 0x31d8,
266 .status_bit = 16,
267 .clkr.hw.init = &(struct clk_init_data){
268 .name = "pll14",
269 .parent_data = &(const struct clk_parent_data){
270 .fw_name = "pxo", .name = "pxo_board",
271 },
272 .num_parents = 1,
273 .ops = &clk_pll_ops,
274 },
275};
276
277static struct clk_regmap pll14_vote = {
278 .enable_reg = 0x34c0,
279 .enable_mask = BIT(14),
280 .hw.init = &(struct clk_init_data){
281 .name = "pll14_vote",
282 .parent_hws = (const struct clk_hw*[]){
283 &pll14.clkr.hw
284 },
285 .num_parents = 1,
286 .ops = &clk_pll_vote_ops,
287 },
288};
289
290enum {
291 P_PXO,
292 P_PLL8,
293 P_PLL3,
294 P_CXO,
295};
296
297static const struct parent_map gcc_pxo_pll8_map[] = {
298 { P_PXO, 0 },
299 { P_PLL8, 3 }
300};
301
302static const struct clk_parent_data gcc_pxo_pll8[] = {
303 { .fw_name = "pxo", .name = "pxo_board" },
304 { .hw = &pll8_vote.hw },
305};
306
307static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
308 { P_PXO, 0 },
309 { P_PLL8, 3 },
310 { P_CXO, 5 }
311};
312
313static const struct clk_parent_data gcc_pxo_pll8_cxo[] = {
314 { .fw_name = "pxo", .name = "pxo_board" },
315 { .hw = &pll8_vote.hw },
316 { .fw_name = "cxo", .name = "cxo_board" },
317};
318
319static const struct parent_map gcc_pxo_pll8_pll3_map[] = {
320 { P_PXO, 0 },
321 { P_PLL8, 3 },
322 { P_PLL3, 6 }
323};
324
325static const struct clk_parent_data gcc_pxo_pll8_pll3[] = {
326 { .fw_name = "pxo", .name = "pxo_board" },
327 { .hw = &pll8_vote.hw },
328 { .hw = &pll3.clkr.hw },
329};
330
331static struct freq_tbl clk_tbl_gsbi_uart[] = {
332 { 1843200, P_PLL8, 2, 6, 625 },
333 { 3686400, P_PLL8, 2, 12, 625 },
334 { 7372800, P_PLL8, 2, 24, 625 },
335 { 14745600, P_PLL8, 2, 48, 625 },
336 { 16000000, P_PLL8, 4, 1, 6 },
337 { 24000000, P_PLL8, 4, 1, 4 },
338 { 32000000, P_PLL8, 4, 1, 3 },
339 { 40000000, P_PLL8, 1, 5, 48 },
340 { 46400000, P_PLL8, 1, 29, 240 },
341 { 48000000, P_PLL8, 4, 1, 2 },
342 { 51200000, P_PLL8, 1, 2, 15 },
343 { 56000000, P_PLL8, 1, 7, 48 },
344 { 58982400, P_PLL8, 1, 96, 625 },
345 { 64000000, P_PLL8, 2, 1, 3 },
346 { }
347};
348
349static struct clk_rcg gsbi1_uart_src = {
350 .ns_reg = 0x29d4,
351 .md_reg = 0x29d0,
352 .mn = {
353 .mnctr_en_bit = 8,
354 .mnctr_reset_bit = 7,
355 .mnctr_mode_shift = 5,
356 .n_val_shift = 16,
357 .m_val_shift = 16,
358 .width = 16,
359 },
360 .p = {
361 .pre_div_shift = 3,
362 .pre_div_width = 2,
363 },
364 .s = {
365 .src_sel_shift = 0,
366 .parent_map = gcc_pxo_pll8_map,
367 },
368 .freq_tbl = clk_tbl_gsbi_uart,
369 .clkr = {
370 .enable_reg = 0x29d4,
371 .enable_mask = BIT(11),
372 .hw.init = &(struct clk_init_data){
373 .name = "gsbi1_uart_src",
374 .parent_data = gcc_pxo_pll8,
375 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
376 .ops = &clk_rcg_ops,
377 .flags = CLK_SET_PARENT_GATE,
378 },
379 },
380};
381
382static struct clk_branch gsbi1_uart_clk = {
383 .halt_reg = 0x2fcc,
384 .halt_bit = 10,
385 .clkr = {
386 .enable_reg = 0x29d4,
387 .enable_mask = BIT(9),
388 .hw.init = &(struct clk_init_data){
389 .name = "gsbi1_uart_clk",
390 .parent_hws = (const struct clk_hw*[]){
391 &gsbi1_uart_src.clkr.hw
392 },
393 .num_parents = 1,
394 .ops = &clk_branch_ops,
395 .flags = CLK_SET_RATE_PARENT,
396 },
397 },
398};
399
400static struct clk_rcg gsbi2_uart_src = {
401 .ns_reg = 0x29f4,
402 .md_reg = 0x29f0,
403 .mn = {
404 .mnctr_en_bit = 8,
405 .mnctr_reset_bit = 7,
406 .mnctr_mode_shift = 5,
407 .n_val_shift = 16,
408 .m_val_shift = 16,
409 .width = 16,
410 },
411 .p = {
412 .pre_div_shift = 3,
413 .pre_div_width = 2,
414 },
415 .s = {
416 .src_sel_shift = 0,
417 .parent_map = gcc_pxo_pll8_map,
418 },
419 .freq_tbl = clk_tbl_gsbi_uart,
420 .clkr = {
421 .enable_reg = 0x29f4,
422 .enable_mask = BIT(11),
423 .hw.init = &(struct clk_init_data){
424 .name = "gsbi2_uart_src",
425 .parent_data = gcc_pxo_pll8,
426 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
427 .ops = &clk_rcg_ops,
428 .flags = CLK_SET_PARENT_GATE,
429 },
430 },
431};
432
433static struct clk_branch gsbi2_uart_clk = {
434 .halt_reg = 0x2fcc,
435 .halt_bit = 6,
436 .clkr = {
437 .enable_reg = 0x29f4,
438 .enable_mask = BIT(9),
439 .hw.init = &(struct clk_init_data){
440 .name = "gsbi2_uart_clk",
441 .parent_hws = (const struct clk_hw*[]){
442 &gsbi2_uart_src.clkr.hw
443 },
444 .num_parents = 1,
445 .ops = &clk_branch_ops,
446 .flags = CLK_SET_RATE_PARENT,
447 },
448 },
449};
450
451static struct clk_rcg gsbi3_uart_src = {
452 .ns_reg = 0x2a14,
453 .md_reg = 0x2a10,
454 .mn = {
455 .mnctr_en_bit = 8,
456 .mnctr_reset_bit = 7,
457 .mnctr_mode_shift = 5,
458 .n_val_shift = 16,
459 .m_val_shift = 16,
460 .width = 16,
461 },
462 .p = {
463 .pre_div_shift = 3,
464 .pre_div_width = 2,
465 },
466 .s = {
467 .src_sel_shift = 0,
468 .parent_map = gcc_pxo_pll8_map,
469 },
470 .freq_tbl = clk_tbl_gsbi_uart,
471 .clkr = {
472 .enable_reg = 0x2a14,
473 .enable_mask = BIT(11),
474 .hw.init = &(struct clk_init_data){
475 .name = "gsbi3_uart_src",
476 .parent_data = gcc_pxo_pll8,
477 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
478 .ops = &clk_rcg_ops,
479 .flags = CLK_SET_PARENT_GATE,
480 },
481 },
482};
483
484static struct clk_branch gsbi3_uart_clk = {
485 .halt_reg = 0x2fcc,
486 .halt_bit = 2,
487 .clkr = {
488 .enable_reg = 0x2a14,
489 .enable_mask = BIT(9),
490 .hw.init = &(struct clk_init_data){
491 .name = "gsbi3_uart_clk",
492 .parent_hws = (const struct clk_hw*[]){
493 &gsbi3_uart_src.clkr.hw
494 },
495 .num_parents = 1,
496 .ops = &clk_branch_ops,
497 .flags = CLK_SET_RATE_PARENT,
498 },
499 },
500};
501
502static struct clk_rcg gsbi4_uart_src = {
503 .ns_reg = 0x2a34,
504 .md_reg = 0x2a30,
505 .mn = {
506 .mnctr_en_bit = 8,
507 .mnctr_reset_bit = 7,
508 .mnctr_mode_shift = 5,
509 .n_val_shift = 16,
510 .m_val_shift = 16,
511 .width = 16,
512 },
513 .p = {
514 .pre_div_shift = 3,
515 .pre_div_width = 2,
516 },
517 .s = {
518 .src_sel_shift = 0,
519 .parent_map = gcc_pxo_pll8_map,
520 },
521 .freq_tbl = clk_tbl_gsbi_uart,
522 .clkr = {
523 .enable_reg = 0x2a34,
524 .enable_mask = BIT(11),
525 .hw.init = &(struct clk_init_data){
526 .name = "gsbi4_uart_src",
527 .parent_data = gcc_pxo_pll8,
528 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
529 .ops = &clk_rcg_ops,
530 .flags = CLK_SET_PARENT_GATE,
531 },
532 },
533};
534
535static struct clk_branch gsbi4_uart_clk = {
536 .halt_reg = 0x2fd0,
537 .halt_bit = 26,
538 .clkr = {
539 .enable_reg = 0x2a34,
540 .enable_mask = BIT(9),
541 .hw.init = &(struct clk_init_data){
542 .name = "gsbi4_uart_clk",
543 .parent_hws = (const struct clk_hw*[]){
544 &gsbi4_uart_src.clkr.hw
545 },
546 .num_parents = 1,
547 .ops = &clk_branch_ops,
548 .flags = CLK_SET_RATE_PARENT,
549 },
550 },
551};
552
553static struct clk_rcg gsbi5_uart_src = {
554 .ns_reg = 0x2a54,
555 .md_reg = 0x2a50,
556 .mn = {
557 .mnctr_en_bit = 8,
558 .mnctr_reset_bit = 7,
559 .mnctr_mode_shift = 5,
560 .n_val_shift = 16,
561 .m_val_shift = 16,
562 .width = 16,
563 },
564 .p = {
565 .pre_div_shift = 3,
566 .pre_div_width = 2,
567 },
568 .s = {
569 .src_sel_shift = 0,
570 .parent_map = gcc_pxo_pll8_map,
571 },
572 .freq_tbl = clk_tbl_gsbi_uart,
573 .clkr = {
574 .enable_reg = 0x2a54,
575 .enable_mask = BIT(11),
576 .hw.init = &(struct clk_init_data){
577 .name = "gsbi5_uart_src",
578 .parent_data = gcc_pxo_pll8,
579 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
580 .ops = &clk_rcg_ops,
581 .flags = CLK_SET_PARENT_GATE,
582 },
583 },
584};
585
586static struct clk_branch gsbi5_uart_clk = {
587 .halt_reg = 0x2fd0,
588 .halt_bit = 22,
589 .clkr = {
590 .enable_reg = 0x2a54,
591 .enable_mask = BIT(9),
592 .hw.init = &(struct clk_init_data){
593 .name = "gsbi5_uart_clk",
594 .parent_hws = (const struct clk_hw*[]){
595 &gsbi5_uart_src.clkr.hw
596 },
597 .num_parents = 1,
598 .ops = &clk_branch_ops,
599 .flags = CLK_SET_RATE_PARENT,
600 },
601 },
602};
603
604static struct clk_rcg gsbi6_uart_src = {
605 .ns_reg = 0x2a74,
606 .md_reg = 0x2a70,
607 .mn = {
608 .mnctr_en_bit = 8,
609 .mnctr_reset_bit = 7,
610 .mnctr_mode_shift = 5,
611 .n_val_shift = 16,
612 .m_val_shift = 16,
613 .width = 16,
614 },
615 .p = {
616 .pre_div_shift = 3,
617 .pre_div_width = 2,
618 },
619 .s = {
620 .src_sel_shift = 0,
621 .parent_map = gcc_pxo_pll8_map,
622 },
623 .freq_tbl = clk_tbl_gsbi_uart,
624 .clkr = {
625 .enable_reg = 0x2a74,
626 .enable_mask = BIT(11),
627 .hw.init = &(struct clk_init_data){
628 .name = "gsbi6_uart_src",
629 .parent_data = gcc_pxo_pll8,
630 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
631 .ops = &clk_rcg_ops,
632 .flags = CLK_SET_PARENT_GATE,
633 },
634 },
635};
636
637static struct clk_branch gsbi6_uart_clk = {
638 .halt_reg = 0x2fd0,
639 .halt_bit = 18,
640 .clkr = {
641 .enable_reg = 0x2a74,
642 .enable_mask = BIT(9),
643 .hw.init = &(struct clk_init_data){
644 .name = "gsbi6_uart_clk",
645 .parent_hws = (const struct clk_hw*[]){
646 &gsbi6_uart_src.clkr.hw
647 },
648 .num_parents = 1,
649 .ops = &clk_branch_ops,
650 .flags = CLK_SET_RATE_PARENT,
651 },
652 },
653};
654
655static struct clk_rcg gsbi7_uart_src = {
656 .ns_reg = 0x2a94,
657 .md_reg = 0x2a90,
658 .mn = {
659 .mnctr_en_bit = 8,
660 .mnctr_reset_bit = 7,
661 .mnctr_mode_shift = 5,
662 .n_val_shift = 16,
663 .m_val_shift = 16,
664 .width = 16,
665 },
666 .p = {
667 .pre_div_shift = 3,
668 .pre_div_width = 2,
669 },
670 .s = {
671 .src_sel_shift = 0,
672 .parent_map = gcc_pxo_pll8_map,
673 },
674 .freq_tbl = clk_tbl_gsbi_uart,
675 .clkr = {
676 .enable_reg = 0x2a94,
677 .enable_mask = BIT(11),
678 .hw.init = &(struct clk_init_data){
679 .name = "gsbi7_uart_src",
680 .parent_data = gcc_pxo_pll8,
681 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
682 .ops = &clk_rcg_ops,
683 .flags = CLK_SET_PARENT_GATE,
684 },
685 },
686};
687
688static struct clk_branch gsbi7_uart_clk = {
689 .halt_reg = 0x2fd0,
690 .halt_bit = 14,
691 .clkr = {
692 .enable_reg = 0x2a94,
693 .enable_mask = BIT(9),
694 .hw.init = &(struct clk_init_data){
695 .name = "gsbi7_uart_clk",
696 .parent_hws = (const struct clk_hw*[]){
697 &gsbi7_uart_src.clkr.hw
698 },
699 .num_parents = 1,
700 .ops = &clk_branch_ops,
701 .flags = CLK_SET_RATE_PARENT,
702 },
703 },
704};
705
706static struct clk_rcg gsbi8_uart_src = {
707 .ns_reg = 0x2ab4,
708 .md_reg = 0x2ab0,
709 .mn = {
710 .mnctr_en_bit = 8,
711 .mnctr_reset_bit = 7,
712 .mnctr_mode_shift = 5,
713 .n_val_shift = 16,
714 .m_val_shift = 16,
715 .width = 16,
716 },
717 .p = {
718 .pre_div_shift = 3,
719 .pre_div_width = 2,
720 },
721 .s = {
722 .src_sel_shift = 0,
723 .parent_map = gcc_pxo_pll8_map,
724 },
725 .freq_tbl = clk_tbl_gsbi_uart,
726 .clkr = {
727 .enable_reg = 0x2ab4,
728 .enable_mask = BIT(11),
729 .hw.init = &(struct clk_init_data){
730 .name = "gsbi8_uart_src",
731 .parent_data = gcc_pxo_pll8,
732 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
733 .ops = &clk_rcg_ops,
734 .flags = CLK_SET_PARENT_GATE,
735 },
736 },
737};
738
739static struct clk_branch gsbi8_uart_clk = {
740 .halt_reg = 0x2fd0,
741 .halt_bit = 10,
742 .clkr = {
743 .enable_reg = 0x2ab4,
744 .enable_mask = BIT(9),
745 .hw.init = &(struct clk_init_data){
746 .name = "gsbi8_uart_clk",
747 .parent_hws = (const struct clk_hw*[]){
748 &gsbi8_uart_src.clkr.hw
749 },
750 .num_parents = 1,
751 .ops = &clk_branch_ops,
752 .flags = CLK_SET_RATE_PARENT,
753 },
754 },
755};
756
757static struct clk_rcg gsbi9_uart_src = {
758 .ns_reg = 0x2ad4,
759 .md_reg = 0x2ad0,
760 .mn = {
761 .mnctr_en_bit = 8,
762 .mnctr_reset_bit = 7,
763 .mnctr_mode_shift = 5,
764 .n_val_shift = 16,
765 .m_val_shift = 16,
766 .width = 16,
767 },
768 .p = {
769 .pre_div_shift = 3,
770 .pre_div_width = 2,
771 },
772 .s = {
773 .src_sel_shift = 0,
774 .parent_map = gcc_pxo_pll8_map,
775 },
776 .freq_tbl = clk_tbl_gsbi_uart,
777 .clkr = {
778 .enable_reg = 0x2ad4,
779 .enable_mask = BIT(11),
780 .hw.init = &(struct clk_init_data){
781 .name = "gsbi9_uart_src",
782 .parent_data = gcc_pxo_pll8,
783 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
784 .ops = &clk_rcg_ops,
785 .flags = CLK_SET_PARENT_GATE,
786 },
787 },
788};
789
790static struct clk_branch gsbi9_uart_clk = {
791 .halt_reg = 0x2fd0,
792 .halt_bit = 6,
793 .clkr = {
794 .enable_reg = 0x2ad4,
795 .enable_mask = BIT(9),
796 .hw.init = &(struct clk_init_data){
797 .name = "gsbi9_uart_clk",
798 .parent_hws = (const struct clk_hw*[]){
799 &gsbi9_uart_src.clkr.hw
800 },
801 .num_parents = 1,
802 .ops = &clk_branch_ops,
803 .flags = CLK_SET_RATE_PARENT,
804 },
805 },
806};
807
808static struct clk_rcg gsbi10_uart_src = {
809 .ns_reg = 0x2af4,
810 .md_reg = 0x2af0,
811 .mn = {
812 .mnctr_en_bit = 8,
813 .mnctr_reset_bit = 7,
814 .mnctr_mode_shift = 5,
815 .n_val_shift = 16,
816 .m_val_shift = 16,
817 .width = 16,
818 },
819 .p = {
820 .pre_div_shift = 3,
821 .pre_div_width = 2,
822 },
823 .s = {
824 .src_sel_shift = 0,
825 .parent_map = gcc_pxo_pll8_map,
826 },
827 .freq_tbl = clk_tbl_gsbi_uart,
828 .clkr = {
829 .enable_reg = 0x2af4,
830 .enable_mask = BIT(11),
831 .hw.init = &(struct clk_init_data){
832 .name = "gsbi10_uart_src",
833 .parent_data = gcc_pxo_pll8,
834 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
835 .ops = &clk_rcg_ops,
836 .flags = CLK_SET_PARENT_GATE,
837 },
838 },
839};
840
841static struct clk_branch gsbi10_uart_clk = {
842 .halt_reg = 0x2fd0,
843 .halt_bit = 2,
844 .clkr = {
845 .enable_reg = 0x2af4,
846 .enable_mask = BIT(9),
847 .hw.init = &(struct clk_init_data){
848 .name = "gsbi10_uart_clk",
849 .parent_hws = (const struct clk_hw*[]){
850 &gsbi10_uart_src.clkr.hw
851 },
852 .num_parents = 1,
853 .ops = &clk_branch_ops,
854 .flags = CLK_SET_RATE_PARENT,
855 },
856 },
857};
858
859static struct clk_rcg gsbi11_uart_src = {
860 .ns_reg = 0x2b14,
861 .md_reg = 0x2b10,
862 .mn = {
863 .mnctr_en_bit = 8,
864 .mnctr_reset_bit = 7,
865 .mnctr_mode_shift = 5,
866 .n_val_shift = 16,
867 .m_val_shift = 16,
868 .width = 16,
869 },
870 .p = {
871 .pre_div_shift = 3,
872 .pre_div_width = 2,
873 },
874 .s = {
875 .src_sel_shift = 0,
876 .parent_map = gcc_pxo_pll8_map,
877 },
878 .freq_tbl = clk_tbl_gsbi_uart,
879 .clkr = {
880 .enable_reg = 0x2b14,
881 .enable_mask = BIT(11),
882 .hw.init = &(struct clk_init_data){
883 .name = "gsbi11_uart_src",
884 .parent_data = gcc_pxo_pll8,
885 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
886 .ops = &clk_rcg_ops,
887 .flags = CLK_SET_PARENT_GATE,
888 },
889 },
890};
891
892static struct clk_branch gsbi11_uart_clk = {
893 .halt_reg = 0x2fd4,
894 .halt_bit = 17,
895 .clkr = {
896 .enable_reg = 0x2b14,
897 .enable_mask = BIT(9),
898 .hw.init = &(struct clk_init_data){
899 .name = "gsbi11_uart_clk",
900 .parent_hws = (const struct clk_hw*[]){
901 &gsbi11_uart_src.clkr.hw
902 },
903 .num_parents = 1,
904 .ops = &clk_branch_ops,
905 .flags = CLK_SET_RATE_PARENT,
906 },
907 },
908};
909
910static struct clk_rcg gsbi12_uart_src = {
911 .ns_reg = 0x2b34,
912 .md_reg = 0x2b30,
913 .mn = {
914 .mnctr_en_bit = 8,
915 .mnctr_reset_bit = 7,
916 .mnctr_mode_shift = 5,
917 .n_val_shift = 16,
918 .m_val_shift = 16,
919 .width = 16,
920 },
921 .p = {
922 .pre_div_shift = 3,
923 .pre_div_width = 2,
924 },
925 .s = {
926 .src_sel_shift = 0,
927 .parent_map = gcc_pxo_pll8_map,
928 },
929 .freq_tbl = clk_tbl_gsbi_uart,
930 .clkr = {
931 .enable_reg = 0x2b34,
932 .enable_mask = BIT(11),
933 .hw.init = &(struct clk_init_data){
934 .name = "gsbi12_uart_src",
935 .parent_data = gcc_pxo_pll8,
936 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
937 .ops = &clk_rcg_ops,
938 .flags = CLK_SET_PARENT_GATE,
939 },
940 },
941};
942
943static struct clk_branch gsbi12_uart_clk = {
944 .halt_reg = 0x2fd4,
945 .halt_bit = 13,
946 .clkr = {
947 .enable_reg = 0x2b34,
948 .enable_mask = BIT(9),
949 .hw.init = &(struct clk_init_data){
950 .name = "gsbi12_uart_clk",
951 .parent_hws = (const struct clk_hw*[]){
952 &gsbi12_uart_src.clkr.hw
953 },
954 .num_parents = 1,
955 .ops = &clk_branch_ops,
956 .flags = CLK_SET_RATE_PARENT,
957 },
958 },
959};
960
961static struct freq_tbl clk_tbl_gsbi_qup[] = {
962 { 1100000, P_PXO, 1, 2, 49 },
963 { 5400000, P_PXO, 1, 1, 5 },
964 { 10800000, P_PXO, 1, 2, 5 },
965 { 15060000, P_PLL8, 1, 2, 51 },
966 { 24000000, P_PLL8, 4, 1, 4 },
967 { 25600000, P_PLL8, 1, 1, 15 },
968 { 27000000, P_PXO, 1, 0, 0 },
969 { 48000000, P_PLL8, 4, 1, 2 },
970 { 51200000, P_PLL8, 1, 2, 15 },
971 { }
972};
973
974static struct clk_rcg gsbi1_qup_src = {
975 .ns_reg = 0x29cc,
976 .md_reg = 0x29c8,
977 .mn = {
978 .mnctr_en_bit = 8,
979 .mnctr_reset_bit = 7,
980 .mnctr_mode_shift = 5,
981 .n_val_shift = 16,
982 .m_val_shift = 16,
983 .width = 8,
984 },
985 .p = {
986 .pre_div_shift = 3,
987 .pre_div_width = 2,
988 },
989 .s = {
990 .src_sel_shift = 0,
991 .parent_map = gcc_pxo_pll8_map,
992 },
993 .freq_tbl = clk_tbl_gsbi_qup,
994 .clkr = {
995 .enable_reg = 0x29cc,
996 .enable_mask = BIT(11),
997 .hw.init = &(struct clk_init_data){
998 .name = "gsbi1_qup_src",
999 .parent_data = gcc_pxo_pll8,
1000 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1001 .ops = &clk_rcg_ops,
1002 .flags = CLK_SET_PARENT_GATE,
1003 },
1004 },
1005};
1006
1007static struct clk_branch gsbi1_qup_clk = {
1008 .halt_reg = 0x2fcc,
1009 .halt_bit = 9,
1010 .clkr = {
1011 .enable_reg = 0x29cc,
1012 .enable_mask = BIT(9),
1013 .hw.init = &(struct clk_init_data){
1014 .name = "gsbi1_qup_clk",
1015 .parent_hws = (const struct clk_hw*[]){
1016 &gsbi1_qup_src.clkr.hw
1017 },
1018 .num_parents = 1,
1019 .ops = &clk_branch_ops,
1020 .flags = CLK_SET_RATE_PARENT,
1021 },
1022 },
1023};
1024
1025static struct clk_rcg gsbi2_qup_src = {
1026 .ns_reg = 0x29ec,
1027 .md_reg = 0x29e8,
1028 .mn = {
1029 .mnctr_en_bit = 8,
1030 .mnctr_reset_bit = 7,
1031 .mnctr_mode_shift = 5,
1032 .n_val_shift = 16,
1033 .m_val_shift = 16,
1034 .width = 8,
1035 },
1036 .p = {
1037 .pre_div_shift = 3,
1038 .pre_div_width = 2,
1039 },
1040 .s = {
1041 .src_sel_shift = 0,
1042 .parent_map = gcc_pxo_pll8_map,
1043 },
1044 .freq_tbl = clk_tbl_gsbi_qup,
1045 .clkr = {
1046 .enable_reg = 0x29ec,
1047 .enable_mask = BIT(11),
1048 .hw.init = &(struct clk_init_data){
1049 .name = "gsbi2_qup_src",
1050 .parent_data = gcc_pxo_pll8,
1051 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1052 .ops = &clk_rcg_ops,
1053 .flags = CLK_SET_PARENT_GATE,
1054 },
1055 },
1056};
1057
1058static struct clk_branch gsbi2_qup_clk = {
1059 .halt_reg = 0x2fcc,
1060 .halt_bit = 4,
1061 .clkr = {
1062 .enable_reg = 0x29ec,
1063 .enable_mask = BIT(9),
1064 .hw.init = &(struct clk_init_data){
1065 .name = "gsbi2_qup_clk",
1066 .parent_hws = (const struct clk_hw*[]){
1067 &gsbi2_qup_src.clkr.hw
1068 },
1069 .num_parents = 1,
1070 .ops = &clk_branch_ops,
1071 .flags = CLK_SET_RATE_PARENT,
1072 },
1073 },
1074};
1075
1076static struct clk_rcg gsbi3_qup_src = {
1077 .ns_reg = 0x2a0c,
1078 .md_reg = 0x2a08,
1079 .mn = {
1080 .mnctr_en_bit = 8,
1081 .mnctr_reset_bit = 7,
1082 .mnctr_mode_shift = 5,
1083 .n_val_shift = 16,
1084 .m_val_shift = 16,
1085 .width = 8,
1086 },
1087 .p = {
1088 .pre_div_shift = 3,
1089 .pre_div_width = 2,
1090 },
1091 .s = {
1092 .src_sel_shift = 0,
1093 .parent_map = gcc_pxo_pll8_map,
1094 },
1095 .freq_tbl = clk_tbl_gsbi_qup,
1096 .clkr = {
1097 .enable_reg = 0x2a0c,
1098 .enable_mask = BIT(11),
1099 .hw.init = &(struct clk_init_data){
1100 .name = "gsbi3_qup_src",
1101 .parent_data = gcc_pxo_pll8,
1102 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1103 .ops = &clk_rcg_ops,
1104 .flags = CLK_SET_PARENT_GATE,
1105 },
1106 },
1107};
1108
1109static struct clk_branch gsbi3_qup_clk = {
1110 .halt_reg = 0x2fcc,
1111 .halt_bit = 0,
1112 .clkr = {
1113 .enable_reg = 0x2a0c,
1114 .enable_mask = BIT(9),
1115 .hw.init = &(struct clk_init_data){
1116 .name = "gsbi3_qup_clk",
1117 .parent_hws = (const struct clk_hw*[]){
1118 &gsbi3_qup_src.clkr.hw
1119 },
1120 .num_parents = 1,
1121 .ops = &clk_branch_ops,
1122 .flags = CLK_SET_RATE_PARENT,
1123 },
1124 },
1125};
1126
1127static struct clk_rcg gsbi4_qup_src = {
1128 .ns_reg = 0x2a2c,
1129 .md_reg = 0x2a28,
1130 .mn = {
1131 .mnctr_en_bit = 8,
1132 .mnctr_reset_bit = 7,
1133 .mnctr_mode_shift = 5,
1134 .n_val_shift = 16,
1135 .m_val_shift = 16,
1136 .width = 8,
1137 },
1138 .p = {
1139 .pre_div_shift = 3,
1140 .pre_div_width = 2,
1141 },
1142 .s = {
1143 .src_sel_shift = 0,
1144 .parent_map = gcc_pxo_pll8_map,
1145 },
1146 .freq_tbl = clk_tbl_gsbi_qup,
1147 .clkr = {
1148 .enable_reg = 0x2a2c,
1149 .enable_mask = BIT(11),
1150 .hw.init = &(struct clk_init_data){
1151 .name = "gsbi4_qup_src",
1152 .parent_data = gcc_pxo_pll8,
1153 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1154 .ops = &clk_rcg_ops,
1155 .flags = CLK_SET_PARENT_GATE,
1156 },
1157 },
1158};
1159
1160static struct clk_branch gsbi4_qup_clk = {
1161 .halt_reg = 0x2fd0,
1162 .halt_bit = 24,
1163 .clkr = {
1164 .enable_reg = 0x2a2c,
1165 .enable_mask = BIT(9),
1166 .hw.init = &(struct clk_init_data){
1167 .name = "gsbi4_qup_clk",
1168 .parent_hws = (const struct clk_hw*[]){
1169 &gsbi4_qup_src.clkr.hw
1170 },
1171 .num_parents = 1,
1172 .ops = &clk_branch_ops,
1173 .flags = CLK_SET_RATE_PARENT,
1174 },
1175 },
1176};
1177
1178static struct clk_rcg gsbi5_qup_src = {
1179 .ns_reg = 0x2a4c,
1180 .md_reg = 0x2a48,
1181 .mn = {
1182 .mnctr_en_bit = 8,
1183 .mnctr_reset_bit = 7,
1184 .mnctr_mode_shift = 5,
1185 .n_val_shift = 16,
1186 .m_val_shift = 16,
1187 .width = 8,
1188 },
1189 .p = {
1190 .pre_div_shift = 3,
1191 .pre_div_width = 2,
1192 },
1193 .s = {
1194 .src_sel_shift = 0,
1195 .parent_map = gcc_pxo_pll8_map,
1196 },
1197 .freq_tbl = clk_tbl_gsbi_qup,
1198 .clkr = {
1199 .enable_reg = 0x2a4c,
1200 .enable_mask = BIT(11),
1201 .hw.init = &(struct clk_init_data){
1202 .name = "gsbi5_qup_src",
1203 .parent_data = gcc_pxo_pll8,
1204 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1205 .ops = &clk_rcg_ops,
1206 .flags = CLK_SET_PARENT_GATE,
1207 },
1208 },
1209};
1210
1211static struct clk_branch gsbi5_qup_clk = {
1212 .halt_reg = 0x2fd0,
1213 .halt_bit = 20,
1214 .clkr = {
1215 .enable_reg = 0x2a4c,
1216 .enable_mask = BIT(9),
1217 .hw.init = &(struct clk_init_data){
1218 .name = "gsbi5_qup_clk",
1219 .parent_hws = (const struct clk_hw*[]){
1220 &gsbi5_qup_src.clkr.hw
1221 },
1222 .num_parents = 1,
1223 .ops = &clk_branch_ops,
1224 .flags = CLK_SET_RATE_PARENT,
1225 },
1226 },
1227};
1228
1229static struct clk_rcg gsbi6_qup_src = {
1230 .ns_reg = 0x2a6c,
1231 .md_reg = 0x2a68,
1232 .mn = {
1233 .mnctr_en_bit = 8,
1234 .mnctr_reset_bit = 7,
1235 .mnctr_mode_shift = 5,
1236 .n_val_shift = 16,
1237 .m_val_shift = 16,
1238 .width = 8,
1239 },
1240 .p = {
1241 .pre_div_shift = 3,
1242 .pre_div_width = 2,
1243 },
1244 .s = {
1245 .src_sel_shift = 0,
1246 .parent_map = gcc_pxo_pll8_map,
1247 },
1248 .freq_tbl = clk_tbl_gsbi_qup,
1249 .clkr = {
1250 .enable_reg = 0x2a6c,
1251 .enable_mask = BIT(11),
1252 .hw.init = &(struct clk_init_data){
1253 .name = "gsbi6_qup_src",
1254 .parent_data = gcc_pxo_pll8,
1255 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1256 .ops = &clk_rcg_ops,
1257 .flags = CLK_SET_PARENT_GATE,
1258 },
1259 },
1260};
1261
1262static struct clk_branch gsbi6_qup_clk = {
1263 .halt_reg = 0x2fd0,
1264 .halt_bit = 16,
1265 .clkr = {
1266 .enable_reg = 0x2a6c,
1267 .enable_mask = BIT(9),
1268 .hw.init = &(struct clk_init_data){
1269 .name = "gsbi6_qup_clk",
1270 .parent_hws = (const struct clk_hw*[]){
1271 &gsbi6_qup_src.clkr.hw
1272 },
1273 .num_parents = 1,
1274 .ops = &clk_branch_ops,
1275 .flags = CLK_SET_RATE_PARENT,
1276 },
1277 },
1278};
1279
1280static struct clk_rcg gsbi7_qup_src = {
1281 .ns_reg = 0x2a8c,
1282 .md_reg = 0x2a88,
1283 .mn = {
1284 .mnctr_en_bit = 8,
1285 .mnctr_reset_bit = 7,
1286 .mnctr_mode_shift = 5,
1287 .n_val_shift = 16,
1288 .m_val_shift = 16,
1289 .width = 8,
1290 },
1291 .p = {
1292 .pre_div_shift = 3,
1293 .pre_div_width = 2,
1294 },
1295 .s = {
1296 .src_sel_shift = 0,
1297 .parent_map = gcc_pxo_pll8_map,
1298 },
1299 .freq_tbl = clk_tbl_gsbi_qup,
1300 .clkr = {
1301 .enable_reg = 0x2a8c,
1302 .enable_mask = BIT(11),
1303 .hw.init = &(struct clk_init_data){
1304 .name = "gsbi7_qup_src",
1305 .parent_data = gcc_pxo_pll8,
1306 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1307 .ops = &clk_rcg_ops,
1308 .flags = CLK_SET_PARENT_GATE,
1309 },
1310 },
1311};
1312
1313static struct clk_branch gsbi7_qup_clk = {
1314 .halt_reg = 0x2fd0,
1315 .halt_bit = 12,
1316 .clkr = {
1317 .enable_reg = 0x2a8c,
1318 .enable_mask = BIT(9),
1319 .hw.init = &(struct clk_init_data){
1320 .name = "gsbi7_qup_clk",
1321 .parent_hws = (const struct clk_hw*[]){
1322 &gsbi7_qup_src.clkr.hw
1323 },
1324 .num_parents = 1,
1325 .ops = &clk_branch_ops,
1326 .flags = CLK_SET_RATE_PARENT,
1327 },
1328 },
1329};
1330
1331static struct clk_rcg gsbi8_qup_src = {
1332 .ns_reg = 0x2aac,
1333 .md_reg = 0x2aa8,
1334 .mn = {
1335 .mnctr_en_bit = 8,
1336 .mnctr_reset_bit = 7,
1337 .mnctr_mode_shift = 5,
1338 .n_val_shift = 16,
1339 .m_val_shift = 16,
1340 .width = 8,
1341 },
1342 .p = {
1343 .pre_div_shift = 3,
1344 .pre_div_width = 2,
1345 },
1346 .s = {
1347 .src_sel_shift = 0,
1348 .parent_map = gcc_pxo_pll8_map,
1349 },
1350 .freq_tbl = clk_tbl_gsbi_qup,
1351 .clkr = {
1352 .enable_reg = 0x2aac,
1353 .enable_mask = BIT(11),
1354 .hw.init = &(struct clk_init_data){
1355 .name = "gsbi8_qup_src",
1356 .parent_data = gcc_pxo_pll8,
1357 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1358 .ops = &clk_rcg_ops,
1359 .flags = CLK_SET_PARENT_GATE,
1360 },
1361 },
1362};
1363
1364static struct clk_branch gsbi8_qup_clk = {
1365 .halt_reg = 0x2fd0,
1366 .halt_bit = 8,
1367 .clkr = {
1368 .enable_reg = 0x2aac,
1369 .enable_mask = BIT(9),
1370 .hw.init = &(struct clk_init_data){
1371 .name = "gsbi8_qup_clk",
1372 .parent_hws = (const struct clk_hw*[]){
1373 &gsbi8_qup_src.clkr.hw
1374 },
1375 .num_parents = 1,
1376 .ops = &clk_branch_ops,
1377 .flags = CLK_SET_RATE_PARENT,
1378 },
1379 },
1380};
1381
1382static struct clk_rcg gsbi9_qup_src = {
1383 .ns_reg = 0x2acc,
1384 .md_reg = 0x2ac8,
1385 .mn = {
1386 .mnctr_en_bit = 8,
1387 .mnctr_reset_bit = 7,
1388 .mnctr_mode_shift = 5,
1389 .n_val_shift = 16,
1390 .m_val_shift = 16,
1391 .width = 8,
1392 },
1393 .p = {
1394 .pre_div_shift = 3,
1395 .pre_div_width = 2,
1396 },
1397 .s = {
1398 .src_sel_shift = 0,
1399 .parent_map = gcc_pxo_pll8_map,
1400 },
1401 .freq_tbl = clk_tbl_gsbi_qup,
1402 .clkr = {
1403 .enable_reg = 0x2acc,
1404 .enable_mask = BIT(11),
1405 .hw.init = &(struct clk_init_data){
1406 .name = "gsbi9_qup_src",
1407 .parent_data = gcc_pxo_pll8,
1408 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1409 .ops = &clk_rcg_ops,
1410 .flags = CLK_SET_PARENT_GATE,
1411 },
1412 },
1413};
1414
1415static struct clk_branch gsbi9_qup_clk = {
1416 .halt_reg = 0x2fd0,
1417 .halt_bit = 4,
1418 .clkr = {
1419 .enable_reg = 0x2acc,
1420 .enable_mask = BIT(9),
1421 .hw.init = &(struct clk_init_data){
1422 .name = "gsbi9_qup_clk",
1423 .parent_hws = (const struct clk_hw*[]){
1424 &gsbi9_qup_src.clkr.hw
1425 },
1426 .num_parents = 1,
1427 .ops = &clk_branch_ops,
1428 .flags = CLK_SET_RATE_PARENT,
1429 },
1430 },
1431};
1432
1433static struct clk_rcg gsbi10_qup_src = {
1434 .ns_reg = 0x2aec,
1435 .md_reg = 0x2ae8,
1436 .mn = {
1437 .mnctr_en_bit = 8,
1438 .mnctr_reset_bit = 7,
1439 .mnctr_mode_shift = 5,
1440 .n_val_shift = 16,
1441 .m_val_shift = 16,
1442 .width = 8,
1443 },
1444 .p = {
1445 .pre_div_shift = 3,
1446 .pre_div_width = 2,
1447 },
1448 .s = {
1449 .src_sel_shift = 0,
1450 .parent_map = gcc_pxo_pll8_map,
1451 },
1452 .freq_tbl = clk_tbl_gsbi_qup,
1453 .clkr = {
1454 .enable_reg = 0x2aec,
1455 .enable_mask = BIT(11),
1456 .hw.init = &(struct clk_init_data){
1457 .name = "gsbi10_qup_src",
1458 .parent_data = gcc_pxo_pll8,
1459 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1460 .ops = &clk_rcg_ops,
1461 .flags = CLK_SET_PARENT_GATE,
1462 },
1463 },
1464};
1465
1466static struct clk_branch gsbi10_qup_clk = {
1467 .halt_reg = 0x2fd0,
1468 .halt_bit = 0,
1469 .clkr = {
1470 .enable_reg = 0x2aec,
1471 .enable_mask = BIT(9),
1472 .hw.init = &(struct clk_init_data){
1473 .name = "gsbi10_qup_clk",
1474 .parent_hws = (const struct clk_hw*[]){
1475 &gsbi10_qup_src.clkr.hw
1476 },
1477 .num_parents = 1,
1478 .ops = &clk_branch_ops,
1479 .flags = CLK_SET_RATE_PARENT,
1480 },
1481 },
1482};
1483
1484static struct clk_rcg gsbi11_qup_src = {
1485 .ns_reg = 0x2b0c,
1486 .md_reg = 0x2b08,
1487 .mn = {
1488 .mnctr_en_bit = 8,
1489 .mnctr_reset_bit = 7,
1490 .mnctr_mode_shift = 5,
1491 .n_val_shift = 16,
1492 .m_val_shift = 16,
1493 .width = 8,
1494 },
1495 .p = {
1496 .pre_div_shift = 3,
1497 .pre_div_width = 2,
1498 },
1499 .s = {
1500 .src_sel_shift = 0,
1501 .parent_map = gcc_pxo_pll8_map,
1502 },
1503 .freq_tbl = clk_tbl_gsbi_qup,
1504 .clkr = {
1505 .enable_reg = 0x2b0c,
1506 .enable_mask = BIT(11),
1507 .hw.init = &(struct clk_init_data){
1508 .name = "gsbi11_qup_src",
1509 .parent_data = gcc_pxo_pll8,
1510 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1511 .ops = &clk_rcg_ops,
1512 .flags = CLK_SET_PARENT_GATE,
1513 },
1514 },
1515};
1516
1517static struct clk_branch gsbi11_qup_clk = {
1518 .halt_reg = 0x2fd4,
1519 .halt_bit = 15,
1520 .clkr = {
1521 .enable_reg = 0x2b0c,
1522 .enable_mask = BIT(9),
1523 .hw.init = &(struct clk_init_data){
1524 .name = "gsbi11_qup_clk",
1525 .parent_hws = (const struct clk_hw*[]){
1526 &gsbi11_qup_src.clkr.hw
1527 },
1528 .num_parents = 1,
1529 .ops = &clk_branch_ops,
1530 .flags = CLK_SET_RATE_PARENT,
1531 },
1532 },
1533};
1534
1535static struct clk_rcg gsbi12_qup_src = {
1536 .ns_reg = 0x2b2c,
1537 .md_reg = 0x2b28,
1538 .mn = {
1539 .mnctr_en_bit = 8,
1540 .mnctr_reset_bit = 7,
1541 .mnctr_mode_shift = 5,
1542 .n_val_shift = 16,
1543 .m_val_shift = 16,
1544 .width = 8,
1545 },
1546 .p = {
1547 .pre_div_shift = 3,
1548 .pre_div_width = 2,
1549 },
1550 .s = {
1551 .src_sel_shift = 0,
1552 .parent_map = gcc_pxo_pll8_map,
1553 },
1554 .freq_tbl = clk_tbl_gsbi_qup,
1555 .clkr = {
1556 .enable_reg = 0x2b2c,
1557 .enable_mask = BIT(11),
1558 .hw.init = &(struct clk_init_data){
1559 .name = "gsbi12_qup_src",
1560 .parent_data = gcc_pxo_pll8,
1561 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1562 .ops = &clk_rcg_ops,
1563 .flags = CLK_SET_PARENT_GATE,
1564 },
1565 },
1566};
1567
1568static struct clk_branch gsbi12_qup_clk = {
1569 .halt_reg = 0x2fd4,
1570 .halt_bit = 11,
1571 .clkr = {
1572 .enable_reg = 0x2b2c,
1573 .enable_mask = BIT(9),
1574 .hw.init = &(struct clk_init_data){
1575 .name = "gsbi12_qup_clk",
1576 .parent_hws = (const struct clk_hw*[]){
1577 &gsbi12_qup_src.clkr.hw
1578 },
1579 .num_parents = 1,
1580 .ops = &clk_branch_ops,
1581 .flags = CLK_SET_RATE_PARENT,
1582 },
1583 },
1584};
1585
1586static const struct freq_tbl clk_tbl_gp[] = {
1587 { 9600000, P_CXO, 2, 0, 0 },
1588 { 13500000, P_PXO, 2, 0, 0 },
1589 { 19200000, P_CXO, 1, 0, 0 },
1590 { 27000000, P_PXO, 1, 0, 0 },
1591 { 64000000, P_PLL8, 2, 1, 3 },
1592 { 76800000, P_PLL8, 1, 1, 5 },
1593 { 96000000, P_PLL8, 4, 0, 0 },
1594 { 128000000, P_PLL8, 3, 0, 0 },
1595 { 192000000, P_PLL8, 2, 0, 0 },
1596 { }
1597};
1598
1599static struct clk_rcg gp0_src = {
1600 .ns_reg = 0x2d24,
1601 .md_reg = 0x2d00,
1602 .mn = {
1603 .mnctr_en_bit = 8,
1604 .mnctr_reset_bit = 7,
1605 .mnctr_mode_shift = 5,
1606 .n_val_shift = 16,
1607 .m_val_shift = 16,
1608 .width = 8,
1609 },
1610 .p = {
1611 .pre_div_shift = 3,
1612 .pre_div_width = 2,
1613 },
1614 .s = {
1615 .src_sel_shift = 0,
1616 .parent_map = gcc_pxo_pll8_cxo_map,
1617 },
1618 .freq_tbl = clk_tbl_gp,
1619 .clkr = {
1620 .enable_reg = 0x2d24,
1621 .enable_mask = BIT(11),
1622 .hw.init = &(struct clk_init_data){
1623 .name = "gp0_src",
1624 .parent_data = gcc_pxo_pll8_cxo,
1625 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
1626 .ops = &clk_rcg_ops,
1627 .flags = CLK_SET_PARENT_GATE,
1628 },
1629 }
1630};
1631
1632static struct clk_branch gp0_clk = {
1633 .halt_reg = 0x2fd8,
1634 .halt_bit = 7,
1635 .clkr = {
1636 .enable_reg = 0x2d24,
1637 .enable_mask = BIT(9),
1638 .hw.init = &(struct clk_init_data){
1639 .name = "gp0_clk",
1640 .parent_hws = (const struct clk_hw*[]){
1641 &gp0_src.clkr.hw
1642 },
1643 .num_parents = 1,
1644 .ops = &clk_branch_ops,
1645 .flags = CLK_SET_RATE_PARENT,
1646 },
1647 },
1648};
1649
1650static struct clk_rcg gp1_src = {
1651 .ns_reg = 0x2d44,
1652 .md_reg = 0x2d40,
1653 .mn = {
1654 .mnctr_en_bit = 8,
1655 .mnctr_reset_bit = 7,
1656 .mnctr_mode_shift = 5,
1657 .n_val_shift = 16,
1658 .m_val_shift = 16,
1659 .width = 8,
1660 },
1661 .p = {
1662 .pre_div_shift = 3,
1663 .pre_div_width = 2,
1664 },
1665 .s = {
1666 .src_sel_shift = 0,
1667 .parent_map = gcc_pxo_pll8_cxo_map,
1668 },
1669 .freq_tbl = clk_tbl_gp,
1670 .clkr = {
1671 .enable_reg = 0x2d44,
1672 .enable_mask = BIT(11),
1673 .hw.init = &(struct clk_init_data){
1674 .name = "gp1_src",
1675 .parent_data = gcc_pxo_pll8_cxo,
1676 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
1677 .ops = &clk_rcg_ops,
1678 .flags = CLK_SET_RATE_GATE,
1679 },
1680 }
1681};
1682
1683static struct clk_branch gp1_clk = {
1684 .halt_reg = 0x2fd8,
1685 .halt_bit = 6,
1686 .clkr = {
1687 .enable_reg = 0x2d44,
1688 .enable_mask = BIT(9),
1689 .hw.init = &(struct clk_init_data){
1690 .name = "gp1_clk",
1691 .parent_hws = (const struct clk_hw*[]){
1692 &gp1_src.clkr.hw
1693 },
1694 .num_parents = 1,
1695 .ops = &clk_branch_ops,
1696 .flags = CLK_SET_RATE_PARENT,
1697 },
1698 },
1699};
1700
1701static struct clk_rcg gp2_src = {
1702 .ns_reg = 0x2d64,
1703 .md_reg = 0x2d60,
1704 .mn = {
1705 .mnctr_en_bit = 8,
1706 .mnctr_reset_bit = 7,
1707 .mnctr_mode_shift = 5,
1708 .n_val_shift = 16,
1709 .m_val_shift = 16,
1710 .width = 8,
1711 },
1712 .p = {
1713 .pre_div_shift = 3,
1714 .pre_div_width = 2,
1715 },
1716 .s = {
1717 .src_sel_shift = 0,
1718 .parent_map = gcc_pxo_pll8_cxo_map,
1719 },
1720 .freq_tbl = clk_tbl_gp,
1721 .clkr = {
1722 .enable_reg = 0x2d64,
1723 .enable_mask = BIT(11),
1724 .hw.init = &(struct clk_init_data){
1725 .name = "gp2_src",
1726 .parent_data = gcc_pxo_pll8_cxo,
1727 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
1728 .ops = &clk_rcg_ops,
1729 .flags = CLK_SET_RATE_GATE,
1730 },
1731 }
1732};
1733
1734static struct clk_branch gp2_clk = {
1735 .halt_reg = 0x2fd8,
1736 .halt_bit = 5,
1737 .clkr = {
1738 .enable_reg = 0x2d64,
1739 .enable_mask = BIT(9),
1740 .hw.init = &(struct clk_init_data){
1741 .name = "gp2_clk",
1742 .parent_hws = (const struct clk_hw*[]){
1743 &gp2_src.clkr.hw
1744 },
1745 .num_parents = 1,
1746 .ops = &clk_branch_ops,
1747 .flags = CLK_SET_RATE_PARENT,
1748 },
1749 },
1750};
1751
1752static struct clk_branch pmem_clk = {
1753 .hwcg_reg = 0x25a0,
1754 .hwcg_bit = 6,
1755 .halt_reg = 0x2fc8,
1756 .halt_bit = 20,
1757 .clkr = {
1758 .enable_reg = 0x25a0,
1759 .enable_mask = BIT(4),
1760 .hw.init = &(struct clk_init_data){
1761 .name = "pmem_clk",
1762 .ops = &clk_branch_ops,
1763 },
1764 },
1765};
1766
1767static struct clk_rcg prng_src = {
1768 .ns_reg = 0x2e80,
1769 .p = {
1770 .pre_div_shift = 3,
1771 .pre_div_width = 4,
1772 },
1773 .s = {
1774 .src_sel_shift = 0,
1775 .parent_map = gcc_pxo_pll8_map,
1776 },
1777 .clkr = {
1778 .hw.init = &(struct clk_init_data){
1779 .name = "prng_src",
1780 .parent_data = gcc_pxo_pll8,
1781 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1782 .ops = &clk_rcg_ops,
1783 },
1784 },
1785};
1786
1787static struct clk_branch prng_clk = {
1788 .halt_reg = 0x2fd8,
1789 .halt_check = BRANCH_HALT_VOTED,
1790 .halt_bit = 10,
1791 .clkr = {
1792 .enable_reg = 0x3080,
1793 .enable_mask = BIT(10),
1794 .hw.init = &(struct clk_init_data){
1795 .name = "prng_clk",
1796 .parent_hws = (const struct clk_hw*[]){
1797 &prng_src.clkr.hw
1798 },
1799 .num_parents = 1,
1800 .ops = &clk_branch_ops,
1801 },
1802 },
1803};
1804
1805static const struct freq_tbl clk_tbl_sdc[] = {
1806 { 144000, P_PXO, 3, 2, 125 },
1807 { 400000, P_PLL8, 4, 1, 240 },
1808 { 16000000, P_PLL8, 4, 1, 6 },
1809 { 17070000, P_PLL8, 1, 2, 45 },
1810 { 20210000, P_PLL8, 1, 1, 19 },
1811 { 24000000, P_PLL8, 4, 1, 4 },
1812 { 48000000, P_PLL8, 4, 1, 2 },
1813 { 64000000, P_PLL8, 3, 1, 2 },
1814 { 96000000, P_PLL8, 4, 0, 0 },
1815 { 192000000, P_PLL8, 2, 0, 0 },
1816 { }
1817};
1818
1819static struct clk_rcg sdc1_src = {
1820 .ns_reg = 0x282c,
1821 .md_reg = 0x2828,
1822 .mn = {
1823 .mnctr_en_bit = 8,
1824 .mnctr_reset_bit = 7,
1825 .mnctr_mode_shift = 5,
1826 .n_val_shift = 16,
1827 .m_val_shift = 16,
1828 .width = 8,
1829 },
1830 .p = {
1831 .pre_div_shift = 3,
1832 .pre_div_width = 2,
1833 },
1834 .s = {
1835 .src_sel_shift = 0,
1836 .parent_map = gcc_pxo_pll8_map,
1837 },
1838 .freq_tbl = clk_tbl_sdc,
1839 .clkr = {
1840 .enable_reg = 0x282c,
1841 .enable_mask = BIT(11),
1842 .hw.init = &(struct clk_init_data){
1843 .name = "sdc1_src",
1844 .parent_data = gcc_pxo_pll8,
1845 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1846 .ops = &clk_rcg_ops,
1847 },
1848 }
1849};
1850
1851static struct clk_branch sdc1_clk = {
1852 .halt_reg = 0x2fc8,
1853 .halt_bit = 6,
1854 .clkr = {
1855 .enable_reg = 0x282c,
1856 .enable_mask = BIT(9),
1857 .hw.init = &(struct clk_init_data){
1858 .name = "sdc1_clk",
1859 .parent_hws = (const struct clk_hw*[]){
1860 &sdc1_src.clkr.hw
1861 },
1862 .num_parents = 1,
1863 .ops = &clk_branch_ops,
1864 .flags = CLK_SET_RATE_PARENT,
1865 },
1866 },
1867};
1868
1869static struct clk_rcg sdc2_src = {
1870 .ns_reg = 0x284c,
1871 .md_reg = 0x2848,
1872 .mn = {
1873 .mnctr_en_bit = 8,
1874 .mnctr_reset_bit = 7,
1875 .mnctr_mode_shift = 5,
1876 .n_val_shift = 16,
1877 .m_val_shift = 16,
1878 .width = 8,
1879 },
1880 .p = {
1881 .pre_div_shift = 3,
1882 .pre_div_width = 2,
1883 },
1884 .s = {
1885 .src_sel_shift = 0,
1886 .parent_map = gcc_pxo_pll8_map,
1887 },
1888 .freq_tbl = clk_tbl_sdc,
1889 .clkr = {
1890 .enable_reg = 0x284c,
1891 .enable_mask = BIT(11),
1892 .hw.init = &(struct clk_init_data){
1893 .name = "sdc2_src",
1894 .parent_data = gcc_pxo_pll8,
1895 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1896 .ops = &clk_rcg_ops,
1897 },
1898 }
1899};
1900
1901static struct clk_branch sdc2_clk = {
1902 .halt_reg = 0x2fc8,
1903 .halt_bit = 5,
1904 .clkr = {
1905 .enable_reg = 0x284c,
1906 .enable_mask = BIT(9),
1907 .hw.init = &(struct clk_init_data){
1908 .name = "sdc2_clk",
1909 .parent_hws = (const struct clk_hw*[]){
1910 &sdc2_src.clkr.hw
1911 },
1912 .num_parents = 1,
1913 .ops = &clk_branch_ops,
1914 .flags = CLK_SET_RATE_PARENT,
1915 },
1916 },
1917};
1918
1919static struct clk_rcg sdc3_src = {
1920 .ns_reg = 0x286c,
1921 .md_reg = 0x2868,
1922 .mn = {
1923 .mnctr_en_bit = 8,
1924 .mnctr_reset_bit = 7,
1925 .mnctr_mode_shift = 5,
1926 .n_val_shift = 16,
1927 .m_val_shift = 16,
1928 .width = 8,
1929 },
1930 .p = {
1931 .pre_div_shift = 3,
1932 .pre_div_width = 2,
1933 },
1934 .s = {
1935 .src_sel_shift = 0,
1936 .parent_map = gcc_pxo_pll8_map,
1937 },
1938 .freq_tbl = clk_tbl_sdc,
1939 .clkr = {
1940 .enable_reg = 0x286c,
1941 .enable_mask = BIT(11),
1942 .hw.init = &(struct clk_init_data){
1943 .name = "sdc3_src",
1944 .parent_data = gcc_pxo_pll8,
1945 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1946 .ops = &clk_rcg_ops,
1947 },
1948 }
1949};
1950
1951static struct clk_branch sdc3_clk = {
1952 .halt_reg = 0x2fc8,
1953 .halt_bit = 4,
1954 .clkr = {
1955 .enable_reg = 0x286c,
1956 .enable_mask = BIT(9),
1957 .hw.init = &(struct clk_init_data){
1958 .name = "sdc3_clk",
1959 .parent_hws = (const struct clk_hw*[]){
1960 &sdc3_src.clkr.hw
1961 },
1962 .num_parents = 1,
1963 .ops = &clk_branch_ops,
1964 .flags = CLK_SET_RATE_PARENT,
1965 },
1966 },
1967};
1968
1969static struct clk_rcg sdc4_src = {
1970 .ns_reg = 0x288c,
1971 .md_reg = 0x2888,
1972 .mn = {
1973 .mnctr_en_bit = 8,
1974 .mnctr_reset_bit = 7,
1975 .mnctr_mode_shift = 5,
1976 .n_val_shift = 16,
1977 .m_val_shift = 16,
1978 .width = 8,
1979 },
1980 .p = {
1981 .pre_div_shift = 3,
1982 .pre_div_width = 2,
1983 },
1984 .s = {
1985 .src_sel_shift = 0,
1986 .parent_map = gcc_pxo_pll8_map,
1987 },
1988 .freq_tbl = clk_tbl_sdc,
1989 .clkr = {
1990 .enable_reg = 0x288c,
1991 .enable_mask = BIT(11),
1992 .hw.init = &(struct clk_init_data){
1993 .name = "sdc4_src",
1994 .parent_data = gcc_pxo_pll8,
1995 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1996 .ops = &clk_rcg_ops,
1997 },
1998 }
1999};
2000
2001static struct clk_branch sdc4_clk = {
2002 .halt_reg = 0x2fc8,
2003 .halt_bit = 3,
2004 .clkr = {
2005 .enable_reg = 0x288c,
2006 .enable_mask = BIT(9),
2007 .hw.init = &(struct clk_init_data){
2008 .name = "sdc4_clk",
2009 .parent_hws = (const struct clk_hw*[]){
2010 &sdc4_src.clkr.hw
2011 },
2012 .num_parents = 1,
2013 .ops = &clk_branch_ops,
2014 .flags = CLK_SET_RATE_PARENT,
2015 },
2016 },
2017};
2018
2019static struct clk_rcg sdc5_src = {
2020 .ns_reg = 0x28ac,
2021 .md_reg = 0x28a8,
2022 .mn = {
2023 .mnctr_en_bit = 8,
2024 .mnctr_reset_bit = 7,
2025 .mnctr_mode_shift = 5,
2026 .n_val_shift = 16,
2027 .m_val_shift = 16,
2028 .width = 8,
2029 },
2030 .p = {
2031 .pre_div_shift = 3,
2032 .pre_div_width = 2,
2033 },
2034 .s = {
2035 .src_sel_shift = 0,
2036 .parent_map = gcc_pxo_pll8_map,
2037 },
2038 .freq_tbl = clk_tbl_sdc,
2039 .clkr = {
2040 .enable_reg = 0x28ac,
2041 .enable_mask = BIT(11),
2042 .hw.init = &(struct clk_init_data){
2043 .name = "sdc5_src",
2044 .parent_data = gcc_pxo_pll8,
2045 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
2046 .ops = &clk_rcg_ops,
2047 },
2048 }
2049};
2050
2051static struct clk_branch sdc5_clk = {
2052 .halt_reg = 0x2fc8,
2053 .halt_bit = 2,
2054 .clkr = {
2055 .enable_reg = 0x28ac,
2056 .enable_mask = BIT(9),
2057 .hw.init = &(struct clk_init_data){
2058 .name = "sdc5_clk",
2059 .parent_hws = (const struct clk_hw*[]){
2060 &sdc5_src.clkr.hw
2061 },
2062 .num_parents = 1,
2063 .ops = &clk_branch_ops,
2064 .flags = CLK_SET_RATE_PARENT,
2065 },
2066 },
2067};
2068
2069static const struct freq_tbl clk_tbl_tsif_ref[] = {
2070 { 105000, P_PXO, 1, 1, 256 },
2071 { }
2072};
2073
2074static struct clk_rcg tsif_ref_src = {
2075 .ns_reg = 0x2710,
2076 .md_reg = 0x270c,
2077 .mn = {
2078 .mnctr_en_bit = 8,
2079 .mnctr_reset_bit = 7,
2080 .mnctr_mode_shift = 5,
2081 .n_val_shift = 16,
2082 .m_val_shift = 16,
2083 .width = 16,
2084 },
2085 .p = {
2086 .pre_div_shift = 3,
2087 .pre_div_width = 2,
2088 },
2089 .s = {
2090 .src_sel_shift = 0,
2091 .parent_map = gcc_pxo_pll8_map,
2092 },
2093 .freq_tbl = clk_tbl_tsif_ref,
2094 .clkr = {
2095 .enable_reg = 0x2710,
2096 .enable_mask = BIT(11),
2097 .hw.init = &(struct clk_init_data){
2098 .name = "tsif_ref_src",
2099 .parent_data = gcc_pxo_pll8,
2100 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
2101 .ops = &clk_rcg_ops,
2102 .flags = CLK_SET_RATE_GATE,
2103 },
2104 }
2105};
2106
2107static struct clk_branch tsif_ref_clk = {
2108 .halt_reg = 0x2fd4,
2109 .halt_bit = 5,
2110 .clkr = {
2111 .enable_reg = 0x2710,
2112 .enable_mask = BIT(9),
2113 .hw.init = &(struct clk_init_data){
2114 .name = "tsif_ref_clk",
2115 .parent_hws = (const struct clk_hw*[]){
2116 &tsif_ref_src.clkr.hw
2117 },
2118 .num_parents = 1,
2119 .ops = &clk_branch_ops,
2120 .flags = CLK_SET_RATE_PARENT,
2121 },
2122 },
2123};
2124
2125static const struct freq_tbl clk_tbl_usb[] = {
2126 { 60000000, P_PLL8, 1, 5, 32 },
2127 { }
2128};
2129
2130static struct clk_rcg usb_hs1_xcvr_src = {
2131 .ns_reg = 0x290c,
2132 .md_reg = 0x2908,
2133 .mn = {
2134 .mnctr_en_bit = 8,
2135 .mnctr_reset_bit = 7,
2136 .mnctr_mode_shift = 5,
2137 .n_val_shift = 16,
2138 .m_val_shift = 16,
2139 .width = 8,
2140 },
2141 .p = {
2142 .pre_div_shift = 3,
2143 .pre_div_width = 2,
2144 },
2145 .s = {
2146 .src_sel_shift = 0,
2147 .parent_map = gcc_pxo_pll8_map,
2148 },
2149 .freq_tbl = clk_tbl_usb,
2150 .clkr = {
2151 .enable_reg = 0x290c,
2152 .enable_mask = BIT(11),
2153 .hw.init = &(struct clk_init_data){
2154 .name = "usb_hs1_xcvr_src",
2155 .parent_data = gcc_pxo_pll8,
2156 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
2157 .ops = &clk_rcg_ops,
2158 .flags = CLK_SET_RATE_GATE,
2159 },
2160 }
2161};
2162
2163static struct clk_branch usb_hs1_xcvr_clk = {
2164 .halt_reg = 0x2fc8,
2165 .halt_bit = 0,
2166 .clkr = {
2167 .enable_reg = 0x290c,
2168 .enable_mask = BIT(9),
2169 .hw.init = &(struct clk_init_data){
2170 .name = "usb_hs1_xcvr_clk",
2171 .parent_hws = (const struct clk_hw*[]){
2172 &usb_hs1_xcvr_src.clkr.hw
2173 },
2174 .num_parents = 1,
2175 .ops = &clk_branch_ops,
2176 .flags = CLK_SET_RATE_PARENT,
2177 },
2178 },
2179};
2180
2181static struct clk_rcg usb_hs3_xcvr_src = {
2182 .ns_reg = 0x370c,
2183 .md_reg = 0x3708,
2184 .mn = {
2185 .mnctr_en_bit = 8,
2186 .mnctr_reset_bit = 7,
2187 .mnctr_mode_shift = 5,
2188 .n_val_shift = 16,
2189 .m_val_shift = 16,
2190 .width = 8,
2191 },
2192 .p = {
2193 .pre_div_shift = 3,
2194 .pre_div_width = 2,
2195 },
2196 .s = {
2197 .src_sel_shift = 0,
2198 .parent_map = gcc_pxo_pll8_map,
2199 },
2200 .freq_tbl = clk_tbl_usb,
2201 .clkr = {
2202 .enable_reg = 0x370c,
2203 .enable_mask = BIT(11),
2204 .hw.init = &(struct clk_init_data){
2205 .name = "usb_hs3_xcvr_src",
2206 .parent_data = gcc_pxo_pll8,
2207 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
2208 .ops = &clk_rcg_ops,
2209 .flags = CLK_SET_RATE_GATE,
2210 },
2211 }
2212};
2213
2214static struct clk_branch usb_hs3_xcvr_clk = {
2215 .halt_reg = 0x2fc8,
2216 .halt_bit = 30,
2217 .clkr = {
2218 .enable_reg = 0x370c,
2219 .enable_mask = BIT(9),
2220 .hw.init = &(struct clk_init_data){
2221 .name = "usb_hs3_xcvr_clk",
2222 .parent_hws = (const struct clk_hw*[]){
2223 &usb_hs3_xcvr_src.clkr.hw
2224 },
2225 .num_parents = 1,
2226 .ops = &clk_branch_ops,
2227 .flags = CLK_SET_RATE_PARENT,
2228 },
2229 },
2230};
2231
2232static struct clk_rcg usb_hs4_xcvr_src = {
2233 .ns_reg = 0x372c,
2234 .md_reg = 0x3728,
2235 .mn = {
2236 .mnctr_en_bit = 8,
2237 .mnctr_reset_bit = 7,
2238 .mnctr_mode_shift = 5,
2239 .n_val_shift = 16,
2240 .m_val_shift = 16,
2241 .width = 8,
2242 },
2243 .p = {
2244 .pre_div_shift = 3,
2245 .pre_div_width = 2,
2246 },
2247 .s = {
2248 .src_sel_shift = 0,
2249 .parent_map = gcc_pxo_pll8_map,
2250 },
2251 .freq_tbl = clk_tbl_usb,
2252 .clkr = {
2253 .enable_reg = 0x372c,
2254 .enable_mask = BIT(11),
2255 .hw.init = &(struct clk_init_data){
2256 .name = "usb_hs4_xcvr_src",
2257 .parent_data = gcc_pxo_pll8,
2258 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
2259 .ops = &clk_rcg_ops,
2260 .flags = CLK_SET_RATE_GATE,
2261 },
2262 }
2263};
2264
2265static struct clk_branch usb_hs4_xcvr_clk = {
2266 .halt_reg = 0x2fc8,
2267 .halt_bit = 2,
2268 .clkr = {
2269 .enable_reg = 0x372c,
2270 .enable_mask = BIT(9),
2271 .hw.init = &(struct clk_init_data){
2272 .name = "usb_hs4_xcvr_clk",
2273 .parent_hws = (const struct clk_hw*[]){
2274 &usb_hs4_xcvr_src.clkr.hw
2275 },
2276 .num_parents = 1,
2277 .ops = &clk_branch_ops,
2278 .flags = CLK_SET_RATE_PARENT,
2279 },
2280 },
2281};
2282
2283static struct clk_rcg usb_hsic_xcvr_fs_src = {
2284 .ns_reg = 0x2928,
2285 .md_reg = 0x2924,
2286 .mn = {
2287 .mnctr_en_bit = 8,
2288 .mnctr_reset_bit = 7,
2289 .mnctr_mode_shift = 5,
2290 .n_val_shift = 16,
2291 .m_val_shift = 16,
2292 .width = 8,
2293 },
2294 .p = {
2295 .pre_div_shift = 3,
2296 .pre_div_width = 2,
2297 },
2298 .s = {
2299 .src_sel_shift = 0,
2300 .parent_map = gcc_pxo_pll8_map,
2301 },
2302 .freq_tbl = clk_tbl_usb,
2303 .clkr = {
2304 .enable_reg = 0x2928,
2305 .enable_mask = BIT(11),
2306 .hw.init = &(struct clk_init_data){
2307 .name = "usb_hsic_xcvr_fs_src",
2308 .parent_data = gcc_pxo_pll8,
2309 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
2310 .ops = &clk_rcg_ops,
2311 .flags = CLK_SET_RATE_GATE,
2312 },
2313 }
2314};
2315
2316static struct clk_branch usb_hsic_xcvr_fs_clk = {
2317 .halt_reg = 0x2fc8,
2318 .halt_bit = 2,
2319 .clkr = {
2320 .enable_reg = 0x2928,
2321 .enable_mask = BIT(9),
2322 .hw.init = &(struct clk_init_data){
2323 .name = "usb_hsic_xcvr_fs_clk",
2324 .parent_hws = (const struct clk_hw*[]){
2325 &usb_hsic_xcvr_fs_src.clkr.hw,
2326 },
2327 .num_parents = 1,
2328 .ops = &clk_branch_ops,
2329 .flags = CLK_SET_RATE_PARENT,
2330 },
2331 },
2332};
2333
2334static struct clk_branch usb_hsic_system_clk = {
2335 .halt_reg = 0x2fcc,
2336 .halt_bit = 24,
2337 .clkr = {
2338 .enable_reg = 0x292c,
2339 .enable_mask = BIT(4),
2340 .hw.init = &(struct clk_init_data){
2341 .parent_hws = (const struct clk_hw*[]){
2342 &usb_hsic_xcvr_fs_src.clkr.hw,
2343 },
2344 .num_parents = 1,
2345 .name = "usb_hsic_system_clk",
2346 .ops = &clk_branch_ops,
2347 .flags = CLK_SET_RATE_PARENT,
2348 },
2349 },
2350};
2351
2352static struct clk_branch usb_hsic_hsic_clk = {
2353 .halt_reg = 0x2fcc,
2354 .halt_bit = 19,
2355 .clkr = {
2356 .enable_reg = 0x2b44,
2357 .enable_mask = BIT(0),
2358 .hw.init = &(struct clk_init_data){
2359 .parent_hws = (const struct clk_hw*[]){
2360 &pll14_vote.hw
2361 },
2362 .num_parents = 1,
2363 .name = "usb_hsic_hsic_clk",
2364 .ops = &clk_branch_ops,
2365 },
2366 },
2367};
2368
2369static struct clk_branch usb_hsic_hsio_cal_clk = {
2370 .halt_reg = 0x2fcc,
2371 .halt_bit = 23,
2372 .clkr = {
2373 .enable_reg = 0x2b48,
2374 .enable_mask = BIT(0),
2375 .hw.init = &(struct clk_init_data){
2376 .name = "usb_hsic_hsio_cal_clk",
2377 .ops = &clk_branch_ops,
2378 },
2379 },
2380};
2381
2382static struct clk_rcg usb_fs1_xcvr_fs_src = {
2383 .ns_reg = 0x2968,
2384 .md_reg = 0x2964,
2385 .mn = {
2386 .mnctr_en_bit = 8,
2387 .mnctr_reset_bit = 7,
2388 .mnctr_mode_shift = 5,
2389 .n_val_shift = 16,
2390 .m_val_shift = 16,
2391 .width = 8,
2392 },
2393 .p = {
2394 .pre_div_shift = 3,
2395 .pre_div_width = 2,
2396 },
2397 .s = {
2398 .src_sel_shift = 0,
2399 .parent_map = gcc_pxo_pll8_map,
2400 },
2401 .freq_tbl = clk_tbl_usb,
2402 .clkr = {
2403 .enable_reg = 0x2968,
2404 .enable_mask = BIT(11),
2405 .hw.init = &(struct clk_init_data){
2406 .name = "usb_fs1_xcvr_fs_src",
2407 .parent_data = gcc_pxo_pll8,
2408 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
2409 .ops = &clk_rcg_ops,
2410 .flags = CLK_SET_RATE_GATE,
2411 },
2412 }
2413};
2414
2415static struct clk_branch usb_fs1_xcvr_fs_clk = {
2416 .halt_reg = 0x2fcc,
2417 .halt_bit = 15,
2418 .clkr = {
2419 .enable_reg = 0x2968,
2420 .enable_mask = BIT(9),
2421 .hw.init = &(struct clk_init_data){
2422 .name = "usb_fs1_xcvr_fs_clk",
2423 .parent_hws = (const struct clk_hw*[]){
2424 &usb_fs1_xcvr_fs_src.clkr.hw,
2425 },
2426 .num_parents = 1,
2427 .ops = &clk_branch_ops,
2428 .flags = CLK_SET_RATE_PARENT,
2429 },
2430 },
2431};
2432
2433static struct clk_branch usb_fs1_system_clk = {
2434 .halt_reg = 0x2fcc,
2435 .halt_bit = 16,
2436 .clkr = {
2437 .enable_reg = 0x296c,
2438 .enable_mask = BIT(4),
2439 .hw.init = &(struct clk_init_data){
2440 .parent_hws = (const struct clk_hw*[]){
2441 &usb_fs1_xcvr_fs_src.clkr.hw,
2442 },
2443 .num_parents = 1,
2444 .name = "usb_fs1_system_clk",
2445 .ops = &clk_branch_ops,
2446 .flags = CLK_SET_RATE_PARENT,
2447 },
2448 },
2449};
2450
2451static struct clk_rcg usb_fs2_xcvr_fs_src = {
2452 .ns_reg = 0x2988,
2453 .md_reg = 0x2984,
2454 .mn = {
2455 .mnctr_en_bit = 8,
2456 .mnctr_reset_bit = 7,
2457 .mnctr_mode_shift = 5,
2458 .n_val_shift = 16,
2459 .m_val_shift = 16,
2460 .width = 8,
2461 },
2462 .p = {
2463 .pre_div_shift = 3,
2464 .pre_div_width = 2,
2465 },
2466 .s = {
2467 .src_sel_shift = 0,
2468 .parent_map = gcc_pxo_pll8_map,
2469 },
2470 .freq_tbl = clk_tbl_usb,
2471 .clkr = {
2472 .enable_reg = 0x2988,
2473 .enable_mask = BIT(11),
2474 .hw.init = &(struct clk_init_data){
2475 .name = "usb_fs2_xcvr_fs_src",
2476 .parent_data = gcc_pxo_pll8,
2477 .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
2478 .ops = &clk_rcg_ops,
2479 .flags = CLK_SET_RATE_GATE,
2480 },
2481 }
2482};
2483
2484static struct clk_branch usb_fs2_xcvr_fs_clk = {
2485 .halt_reg = 0x2fcc,
2486 .halt_bit = 12,
2487 .clkr = {
2488 .enable_reg = 0x2988,
2489 .enable_mask = BIT(9),
2490 .hw.init = &(struct clk_init_data){
2491 .name = "usb_fs2_xcvr_fs_clk",
2492 .parent_hws = (const struct clk_hw*[]){
2493 &usb_fs2_xcvr_fs_src.clkr.hw,
2494 },
2495 .num_parents = 1,
2496 .ops = &clk_branch_ops,
2497 .flags = CLK_SET_RATE_PARENT,
2498 },
2499 },
2500};
2501
2502static struct clk_branch usb_fs2_system_clk = {
2503 .halt_reg = 0x2fcc,
2504 .halt_bit = 13,
2505 .clkr = {
2506 .enable_reg = 0x298c,
2507 .enable_mask = BIT(4),
2508 .hw.init = &(struct clk_init_data){
2509 .name = "usb_fs2_system_clk",
2510 .parent_hws = (const struct clk_hw*[]){
2511 &usb_fs2_xcvr_fs_src.clkr.hw,
2512 },
2513 .num_parents = 1,
2514 .ops = &clk_branch_ops,
2515 .flags = CLK_SET_RATE_PARENT,
2516 },
2517 },
2518};
2519
2520static struct clk_branch ce1_core_clk = {
2521 .hwcg_reg = 0x2724,
2522 .hwcg_bit = 6,
2523 .halt_reg = 0x2fd4,
2524 .halt_bit = 27,
2525 .clkr = {
2526 .enable_reg = 0x2724,
2527 .enable_mask = BIT(4),
2528 .hw.init = &(struct clk_init_data){
2529 .name = "ce1_core_clk",
2530 .ops = &clk_branch_ops,
2531 },
2532 },
2533};
2534
2535static struct clk_branch ce1_h_clk = {
2536 .halt_reg = 0x2fd4,
2537 .halt_bit = 1,
2538 .clkr = {
2539 .enable_reg = 0x2720,
2540 .enable_mask = BIT(4),
2541 .hw.init = &(struct clk_init_data){
2542 .name = "ce1_h_clk",
2543 .ops = &clk_branch_ops,
2544 },
2545 },
2546};
2547
2548static struct clk_branch dma_bam_h_clk = {
2549 .hwcg_reg = 0x25c0,
2550 .hwcg_bit = 6,
2551 .halt_reg = 0x2fc8,
2552 .halt_bit = 12,
2553 .clkr = {
2554 .enable_reg = 0x25c0,
2555 .enable_mask = BIT(4),
2556 .hw.init = &(struct clk_init_data){
2557 .name = "dma_bam_h_clk",
2558 .ops = &clk_branch_ops,
2559 },
2560 },
2561};
2562
2563static struct clk_branch gsbi1_h_clk = {
2564 .hwcg_reg = 0x29c0,
2565 .hwcg_bit = 6,
2566 .halt_reg = 0x2fcc,
2567 .halt_bit = 11,
2568 .clkr = {
2569 .enable_reg = 0x29c0,
2570 .enable_mask = BIT(4),
2571 .hw.init = &(struct clk_init_data){
2572 .name = "gsbi1_h_clk",
2573 .ops = &clk_branch_ops,
2574 },
2575 },
2576};
2577
2578static struct clk_branch gsbi2_h_clk = {
2579 .hwcg_reg = 0x29e0,
2580 .hwcg_bit = 6,
2581 .halt_reg = 0x2fcc,
2582 .halt_bit = 7,
2583 .clkr = {
2584 .enable_reg = 0x29e0,
2585 .enable_mask = BIT(4),
2586 .hw.init = &(struct clk_init_data){
2587 .name = "gsbi2_h_clk",
2588 .ops = &clk_branch_ops,
2589 },
2590 },
2591};
2592
2593static struct clk_branch gsbi3_h_clk = {
2594 .hwcg_reg = 0x2a00,
2595 .hwcg_bit = 6,
2596 .halt_reg = 0x2fcc,
2597 .halt_bit = 3,
2598 .clkr = {
2599 .enable_reg = 0x2a00,
2600 .enable_mask = BIT(4),
2601 .hw.init = &(struct clk_init_data){
2602 .name = "gsbi3_h_clk",
2603 .ops = &clk_branch_ops,
2604 },
2605 },
2606};
2607
2608static struct clk_branch gsbi4_h_clk = {
2609 .hwcg_reg = 0x2a20,
2610 .hwcg_bit = 6,
2611 .halt_reg = 0x2fd0,
2612 .halt_bit = 27,
2613 .clkr = {
2614 .enable_reg = 0x2a20,
2615 .enable_mask = BIT(4),
2616 .hw.init = &(struct clk_init_data){
2617 .name = "gsbi4_h_clk",
2618 .ops = &clk_branch_ops,
2619 },
2620 },
2621};
2622
2623static struct clk_branch gsbi5_h_clk = {
2624 .hwcg_reg = 0x2a40,
2625 .hwcg_bit = 6,
2626 .halt_reg = 0x2fd0,
2627 .halt_bit = 23,
2628 .clkr = {
2629 .enable_reg = 0x2a40,
2630 .enable_mask = BIT(4),
2631 .hw.init = &(struct clk_init_data){
2632 .name = "gsbi5_h_clk",
2633 .ops = &clk_branch_ops,
2634 },
2635 },
2636};
2637
2638static struct clk_branch gsbi6_h_clk = {
2639 .hwcg_reg = 0x2a60,
2640 .hwcg_bit = 6,
2641 .halt_reg = 0x2fd0,
2642 .halt_bit = 19,
2643 .clkr = {
2644 .enable_reg = 0x2a60,
2645 .enable_mask = BIT(4),
2646 .hw.init = &(struct clk_init_data){
2647 .name = "gsbi6_h_clk",
2648 .ops = &clk_branch_ops,
2649 },
2650 },
2651};
2652
2653static struct clk_branch gsbi7_h_clk = {
2654 .hwcg_reg = 0x2a80,
2655 .hwcg_bit = 6,
2656 .halt_reg = 0x2fd0,
2657 .halt_bit = 15,
2658 .clkr = {
2659 .enable_reg = 0x2a80,
2660 .enable_mask = BIT(4),
2661 .hw.init = &(struct clk_init_data){
2662 .name = "gsbi7_h_clk",
2663 .ops = &clk_branch_ops,
2664 },
2665 },
2666};
2667
2668static struct clk_branch gsbi8_h_clk = {
2669 .hwcg_reg = 0x2aa0,
2670 .hwcg_bit = 6,
2671 .halt_reg = 0x2fd0,
2672 .halt_bit = 11,
2673 .clkr = {
2674 .enable_reg = 0x2aa0,
2675 .enable_mask = BIT(4),
2676 .hw.init = &(struct clk_init_data){
2677 .name = "gsbi8_h_clk",
2678 .ops = &clk_branch_ops,
2679 },
2680 },
2681};
2682
2683static struct clk_branch gsbi9_h_clk = {
2684 .hwcg_reg = 0x2ac0,
2685 .hwcg_bit = 6,
2686 .halt_reg = 0x2fd0,
2687 .halt_bit = 7,
2688 .clkr = {
2689 .enable_reg = 0x2ac0,
2690 .enable_mask = BIT(4),
2691 .hw.init = &(struct clk_init_data){
2692 .name = "gsbi9_h_clk",
2693 .ops = &clk_branch_ops,
2694 },
2695 },
2696};
2697
2698static struct clk_branch gsbi10_h_clk = {
2699 .hwcg_reg = 0x2ae0,
2700 .hwcg_bit = 6,
2701 .halt_reg = 0x2fd0,
2702 .halt_bit = 3,
2703 .clkr = {
2704 .enable_reg = 0x2ae0,
2705 .enable_mask = BIT(4),
2706 .hw.init = &(struct clk_init_data){
2707 .name = "gsbi10_h_clk",
2708 .ops = &clk_branch_ops,
2709 },
2710 },
2711};
2712
2713static struct clk_branch gsbi11_h_clk = {
2714 .hwcg_reg = 0x2b00,
2715 .hwcg_bit = 6,
2716 .halt_reg = 0x2fd4,
2717 .halt_bit = 18,
2718 .clkr = {
2719 .enable_reg = 0x2b00,
2720 .enable_mask = BIT(4),
2721 .hw.init = &(struct clk_init_data){
2722 .name = "gsbi11_h_clk",
2723 .ops = &clk_branch_ops,
2724 },
2725 },
2726};
2727
2728static struct clk_branch gsbi12_h_clk = {
2729 .hwcg_reg = 0x2b20,
2730 .hwcg_bit = 6,
2731 .halt_reg = 0x2fd4,
2732 .halt_bit = 14,
2733 .clkr = {
2734 .enable_reg = 0x2b20,
2735 .enable_mask = BIT(4),
2736 .hw.init = &(struct clk_init_data){
2737 .name = "gsbi12_h_clk",
2738 .ops = &clk_branch_ops,
2739 },
2740 },
2741};
2742
2743static struct clk_branch tsif_h_clk = {
2744 .hwcg_reg = 0x2700,
2745 .hwcg_bit = 6,
2746 .halt_reg = 0x2fd4,
2747 .halt_bit = 7,
2748 .clkr = {
2749 .enable_reg = 0x2700,
2750 .enable_mask = BIT(4),
2751 .hw.init = &(struct clk_init_data){
2752 .name = "tsif_h_clk",
2753 .ops = &clk_branch_ops,
2754 },
2755 },
2756};
2757
2758static struct clk_branch usb_fs1_h_clk = {
2759 .halt_reg = 0x2fcc,
2760 .halt_bit = 17,
2761 .clkr = {
2762 .enable_reg = 0x2960,
2763 .enable_mask = BIT(4),
2764 .hw.init = &(struct clk_init_data){
2765 .name = "usb_fs1_h_clk",
2766 .ops = &clk_branch_ops,
2767 },
2768 },
2769};
2770
2771static struct clk_branch usb_fs2_h_clk = {
2772 .halt_reg = 0x2fcc,
2773 .halt_bit = 14,
2774 .clkr = {
2775 .enable_reg = 0x2980,
2776 .enable_mask = BIT(4),
2777 .hw.init = &(struct clk_init_data){
2778 .name = "usb_fs2_h_clk",
2779 .ops = &clk_branch_ops,
2780 },
2781 },
2782};
2783
2784static struct clk_branch usb_hs1_h_clk = {
2785 .hwcg_reg = 0x2900,
2786 .hwcg_bit = 6,
2787 .halt_reg = 0x2fc8,
2788 .halt_bit = 1,
2789 .clkr = {
2790 .enable_reg = 0x2900,
2791 .enable_mask = BIT(4),
2792 .hw.init = &(struct clk_init_data){
2793 .name = "usb_hs1_h_clk",
2794 .ops = &clk_branch_ops,
2795 },
2796 },
2797};
2798
2799static struct clk_branch usb_hs3_h_clk = {
2800 .halt_reg = 0x2fc8,
2801 .halt_bit = 31,
2802 .clkr = {
2803 .enable_reg = 0x3700,
2804 .enable_mask = BIT(4),
2805 .hw.init = &(struct clk_init_data){
2806 .name = "usb_hs3_h_clk",
2807 .ops = &clk_branch_ops,
2808 },
2809 },
2810};
2811
2812static struct clk_branch usb_hs4_h_clk = {
2813 .halt_reg = 0x2fc8,
2814 .halt_bit = 7,
2815 .clkr = {
2816 .enable_reg = 0x3720,
2817 .enable_mask = BIT(4),
2818 .hw.init = &(struct clk_init_data){
2819 .name = "usb_hs4_h_clk",
2820 .ops = &clk_branch_ops,
2821 },
2822 },
2823};
2824
2825static struct clk_branch usb_hsic_h_clk = {
2826 .halt_reg = 0x2fcc,
2827 .halt_bit = 28,
2828 .clkr = {
2829 .enable_reg = 0x2920,
2830 .enable_mask = BIT(4),
2831 .hw.init = &(struct clk_init_data){
2832 .name = "usb_hsic_h_clk",
2833 .ops = &clk_branch_ops,
2834 },
2835 },
2836};
2837
2838static struct clk_branch sdc1_h_clk = {
2839 .hwcg_reg = 0x2820,
2840 .hwcg_bit = 6,
2841 .halt_reg = 0x2fc8,
2842 .halt_bit = 11,
2843 .clkr = {
2844 .enable_reg = 0x2820,
2845 .enable_mask = BIT(4),
2846 .hw.init = &(struct clk_init_data){
2847 .name = "sdc1_h_clk",
2848 .ops = &clk_branch_ops,
2849 },
2850 },
2851};
2852
2853static struct clk_branch sdc2_h_clk = {
2854 .hwcg_reg = 0x2840,
2855 .hwcg_bit = 6,
2856 .halt_reg = 0x2fc8,
2857 .halt_bit = 10,
2858 .clkr = {
2859 .enable_reg = 0x2840,
2860 .enable_mask = BIT(4),
2861 .hw.init = &(struct clk_init_data){
2862 .name = "sdc2_h_clk",
2863 .ops = &clk_branch_ops,
2864 },
2865 },
2866};
2867
2868static struct clk_branch sdc3_h_clk = {
2869 .hwcg_reg = 0x2860,
2870 .hwcg_bit = 6,
2871 .halt_reg = 0x2fc8,
2872 .halt_bit = 9,
2873 .clkr = {
2874 .enable_reg = 0x2860,
2875 .enable_mask = BIT(4),
2876 .hw.init = &(struct clk_init_data){
2877 .name = "sdc3_h_clk",
2878 .ops = &clk_branch_ops,
2879 },
2880 },
2881};
2882
2883static struct clk_branch sdc4_h_clk = {
2884 .hwcg_reg = 0x2880,
2885 .hwcg_bit = 6,
2886 .halt_reg = 0x2fc8,
2887 .halt_bit = 8,
2888 .clkr = {
2889 .enable_reg = 0x2880,
2890 .enable_mask = BIT(4),
2891 .hw.init = &(struct clk_init_data){
2892 .name = "sdc4_h_clk",
2893 .ops = &clk_branch_ops,
2894 },
2895 },
2896};
2897
2898static struct clk_branch sdc5_h_clk = {
2899 .hwcg_reg = 0x28a0,
2900 .hwcg_bit = 6,
2901 .halt_reg = 0x2fc8,
2902 .halt_bit = 7,
2903 .clkr = {
2904 .enable_reg = 0x28a0,
2905 .enable_mask = BIT(4),
2906 .hw.init = &(struct clk_init_data){
2907 .name = "sdc5_h_clk",
2908 .ops = &clk_branch_ops,
2909 },
2910 },
2911};
2912
2913static struct clk_branch adm0_clk = {
2914 .halt_reg = 0x2fdc,
2915 .halt_check = BRANCH_HALT_VOTED,
2916 .halt_bit = 14,
2917 .clkr = {
2918 .enable_reg = 0x3080,
2919 .enable_mask = BIT(2),
2920 .hw.init = &(struct clk_init_data){
2921 .name = "adm0_clk",
2922 .ops = &clk_branch_ops,
2923 },
2924 },
2925};
2926
2927static struct clk_branch adm0_pbus_clk = {
2928 .hwcg_reg = 0x2208,
2929 .hwcg_bit = 6,
2930 .halt_reg = 0x2fdc,
2931 .halt_check = BRANCH_HALT_VOTED,
2932 .halt_bit = 13,
2933 .clkr = {
2934 .enable_reg = 0x3080,
2935 .enable_mask = BIT(3),
2936 .hw.init = &(struct clk_init_data){
2937 .name = "adm0_pbus_clk",
2938 .ops = &clk_branch_ops,
2939 },
2940 },
2941};
2942
2943static struct freq_tbl clk_tbl_ce3[] = {
2944 { 48000000, P_PLL8, 8 },
2945 { 100000000, P_PLL3, 12 },
2946 { 120000000, P_PLL3, 10 },
2947 { }
2948};
2949
2950static struct clk_rcg ce3_src = {
2951 .ns_reg = 0x36c0,
2952 .p = {
2953 .pre_div_shift = 3,
2954 .pre_div_width = 4,
2955 },
2956 .s = {
2957 .src_sel_shift = 0,
2958 .parent_map = gcc_pxo_pll8_pll3_map,
2959 },
2960 .freq_tbl = clk_tbl_ce3,
2961 .clkr = {
2962 .enable_reg = 0x36c0,
2963 .enable_mask = BIT(7),
2964 .hw.init = &(struct clk_init_data){
2965 .name = "ce3_src",
2966 .parent_data = gcc_pxo_pll8_pll3,
2967 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll3),
2968 .ops = &clk_rcg_ops,
2969 .flags = CLK_SET_RATE_GATE,
2970 },
2971 },
2972};
2973
2974static struct clk_branch ce3_core_clk = {
2975 .halt_reg = 0x2fdc,
2976 .halt_bit = 5,
2977 .clkr = {
2978 .enable_reg = 0x36cc,
2979 .enable_mask = BIT(4),
2980 .hw.init = &(struct clk_init_data){
2981 .name = "ce3_core_clk",
2982 .parent_hws = (const struct clk_hw*[]){
2983 &ce3_src.clkr.hw
2984 },
2985 .num_parents = 1,
2986 .ops = &clk_branch_ops,
2987 .flags = CLK_SET_RATE_PARENT,
2988 },
2989 },
2990};
2991
2992static struct clk_branch ce3_h_clk = {
2993 .halt_reg = 0x2fc4,
2994 .halt_bit = 16,
2995 .clkr = {
2996 .enable_reg = 0x36c4,
2997 .enable_mask = BIT(4),
2998 .hw.init = &(struct clk_init_data){
2999 .name = "ce3_h_clk",
3000 .parent_hws = (const struct clk_hw*[]){
3001 &ce3_src.clkr.hw
3002 },
3003 .num_parents = 1,
3004 .ops = &clk_branch_ops,
3005 .flags = CLK_SET_RATE_PARENT,
3006 },
3007 },
3008};
3009
3010static const struct freq_tbl clk_tbl_sata_ref[] = {
3011 { 48000000, P_PLL8, 8, 0, 0 },
3012 { 100000000, P_PLL3, 12, 0, 0 },
3013 { }
3014};
3015
3016static struct clk_rcg sata_clk_src = {
3017 .ns_reg = 0x2c08,
3018 .p = {
3019 .pre_div_shift = 3,
3020 .pre_div_width = 4,
3021 },
3022 .s = {
3023 .src_sel_shift = 0,
3024 .parent_map = gcc_pxo_pll8_pll3_map,
3025 },
3026 .freq_tbl = clk_tbl_sata_ref,
3027 .clkr = {
3028 .enable_reg = 0x2c08,
3029 .enable_mask = BIT(7),
3030 .hw.init = &(struct clk_init_data){
3031 .name = "sata_clk_src",
3032 .parent_data = gcc_pxo_pll8_pll3,
3033 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll3),
3034 .ops = &clk_rcg_ops,
3035 .flags = CLK_SET_RATE_GATE,
3036 },
3037 },
3038};
3039
3040static struct clk_branch sata_rxoob_clk = {
3041 .halt_reg = 0x2fdc,
3042 .halt_bit = 26,
3043 .clkr = {
3044 .enable_reg = 0x2c0c,
3045 .enable_mask = BIT(4),
3046 .hw.init = &(struct clk_init_data){
3047 .name = "sata_rxoob_clk",
3048 .parent_hws = (const struct clk_hw*[]){
3049 &sata_clk_src.clkr.hw,
3050 },
3051 .num_parents = 1,
3052 .ops = &clk_branch_ops,
3053 .flags = CLK_SET_RATE_PARENT,
3054 },
3055 },
3056};
3057
3058static struct clk_branch sata_pmalive_clk = {
3059 .halt_reg = 0x2fdc,
3060 .halt_bit = 25,
3061 .clkr = {
3062 .enable_reg = 0x2c10,
3063 .enable_mask = BIT(4),
3064 .hw.init = &(struct clk_init_data){
3065 .name = "sata_pmalive_clk",
3066 .parent_hws = (const struct clk_hw*[]){
3067 &sata_clk_src.clkr.hw,
3068 },
3069 .num_parents = 1,
3070 .ops = &clk_branch_ops,
3071 .flags = CLK_SET_RATE_PARENT,
3072 },
3073 },
3074};
3075
3076static struct clk_branch sata_phy_ref_clk = {
3077 .halt_reg = 0x2fdc,
3078 .halt_bit = 24,
3079 .clkr = {
3080 .enable_reg = 0x2c14,
3081 .enable_mask = BIT(4),
3082 .hw.init = &(struct clk_init_data){
3083 .name = "sata_phy_ref_clk",
3084 .parent_data = &(const struct clk_parent_data){
3085 .fw_name = "pxo", .name = "pxo_board",
3086 },
3087 .num_parents = 1,
3088 .ops = &clk_branch_ops,
3089 },
3090 },
3091};
3092
3093static struct clk_branch sata_a_clk = {
3094 .halt_reg = 0x2fc0,
3095 .halt_bit = 12,
3096 .clkr = {
3097 .enable_reg = 0x2c20,
3098 .enable_mask = BIT(4),
3099 .hw.init = &(struct clk_init_data){
3100 .name = "sata_a_clk",
3101 .ops = &clk_branch_ops,
3102 },
3103 },
3104};
3105
3106static struct clk_branch sata_h_clk = {
3107 .halt_reg = 0x2fdc,
3108 .halt_bit = 27,
3109 .clkr = {
3110 .enable_reg = 0x2c00,
3111 .enable_mask = BIT(4),
3112 .hw.init = &(struct clk_init_data){
3113 .name = "sata_h_clk",
3114 .ops = &clk_branch_ops,
3115 },
3116 },
3117};
3118
3119static struct clk_branch sfab_sata_s_h_clk = {
3120 .halt_reg = 0x2fc4,
3121 .halt_bit = 14,
3122 .clkr = {
3123 .enable_reg = 0x2480,
3124 .enable_mask = BIT(4),
3125 .hw.init = &(struct clk_init_data){
3126 .name = "sfab_sata_s_h_clk",
3127 .ops = &clk_branch_ops,
3128 },
3129 },
3130};
3131
3132static struct clk_branch sata_phy_cfg_clk = {
3133 .halt_reg = 0x2fcc,
3134 .halt_bit = 12,
3135 .clkr = {
3136 .enable_reg = 0x2c40,
3137 .enable_mask = BIT(4),
3138 .hw.init = &(struct clk_init_data){
3139 .name = "sata_phy_cfg_clk",
3140 .ops = &clk_branch_ops,
3141 },
3142 },
3143};
3144
3145static struct clk_branch pcie_phy_ref_clk = {
3146 .halt_reg = 0x2fdc,
3147 .halt_bit = 29,
3148 .clkr = {
3149 .enable_reg = 0x22d0,
3150 .enable_mask = BIT(4),
3151 .hw.init = &(struct clk_init_data){
3152 .name = "pcie_phy_ref_clk",
3153 .ops = &clk_branch_ops,
3154 },
3155 },
3156};
3157
3158static struct clk_branch pcie_h_clk = {
3159 .halt_reg = 0x2fd4,
3160 .halt_bit = 8,
3161 .clkr = {
3162 .enable_reg = 0x22cc,
3163 .enable_mask = BIT(4),
3164 .hw.init = &(struct clk_init_data){
3165 .name = "pcie_h_clk",
3166 .ops = &clk_branch_ops,
3167 },
3168 },
3169};
3170
3171static struct clk_branch pcie_a_clk = {
3172 .halt_reg = 0x2fc0,
3173 .halt_bit = 13,
3174 .clkr = {
3175 .enable_reg = 0x22c0,
3176 .enable_mask = BIT(4),
3177 .hw.init = &(struct clk_init_data){
3178 .name = "pcie_a_clk",
3179 .ops = &clk_branch_ops,
3180 },
3181 },
3182};
3183
3184static struct clk_branch pmic_arb0_h_clk = {
3185 .halt_reg = 0x2fd8,
3186 .halt_check = BRANCH_HALT_VOTED,
3187 .halt_bit = 22,
3188 .clkr = {
3189 .enable_reg = 0x3080,
3190 .enable_mask = BIT(8),
3191 .hw.init = &(struct clk_init_data){
3192 .name = "pmic_arb0_h_clk",
3193 .ops = &clk_branch_ops,
3194 },
3195 },
3196};
3197
3198static struct clk_branch pmic_arb1_h_clk = {
3199 .halt_reg = 0x2fd8,
3200 .halt_check = BRANCH_HALT_VOTED,
3201 .halt_bit = 21,
3202 .clkr = {
3203 .enable_reg = 0x3080,
3204 .enable_mask = BIT(9),
3205 .hw.init = &(struct clk_init_data){
3206 .name = "pmic_arb1_h_clk",
3207 .ops = &clk_branch_ops,
3208 },
3209 },
3210};
3211
3212static struct clk_branch pmic_ssbi2_clk = {
3213 .halt_reg = 0x2fd8,
3214 .halt_check = BRANCH_HALT_VOTED,
3215 .halt_bit = 23,
3216 .clkr = {
3217 .enable_reg = 0x3080,
3218 .enable_mask = BIT(7),
3219 .hw.init = &(struct clk_init_data){
3220 .name = "pmic_ssbi2_clk",
3221 .ops = &clk_branch_ops,
3222 },
3223 },
3224};
3225
3226static struct clk_branch rpm_msg_ram_h_clk = {
3227 .hwcg_reg = 0x27e0,
3228 .hwcg_bit = 6,
3229 .halt_reg = 0x2fd8,
3230 .halt_check = BRANCH_HALT_VOTED,
3231 .halt_bit = 12,
3232 .clkr = {
3233 .enable_reg = 0x3080,
3234 .enable_mask = BIT(6),
3235 .hw.init = &(struct clk_init_data){
3236 .name = "rpm_msg_ram_h_clk",
3237 .ops = &clk_branch_ops,
3238 },
3239 },
3240};
3241
3242static struct clk_regmap *gcc_msm8960_clks[] = {
3243 [PLL3] = &pll3.clkr,
3244 [PLL4_VOTE] = &pll4_vote,
3245 [PLL8] = &pll8.clkr,
3246 [PLL8_VOTE] = &pll8_vote,
3247 [PLL14] = &pll14.clkr,
3248 [PLL14_VOTE] = &pll14_vote,
3249 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
3250 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
3251 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
3252 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
3253 [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
3254 [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
3255 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
3256 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
3257 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
3258 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
3259 [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
3260 [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
3261 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
3262 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
3263 [GSBI8_UART_SRC] = &gsbi8_uart_src.clkr,
3264 [GSBI8_UART_CLK] = &gsbi8_uart_clk.clkr,
3265 [GSBI9_UART_SRC] = &gsbi9_uart_src.clkr,
3266 [GSBI9_UART_CLK] = &gsbi9_uart_clk.clkr,
3267 [GSBI10_UART_SRC] = &gsbi10_uart_src.clkr,
3268 [GSBI10_UART_CLK] = &gsbi10_uart_clk.clkr,
3269 [GSBI11_UART_SRC] = &gsbi11_uart_src.clkr,
3270 [GSBI11_UART_CLK] = &gsbi11_uart_clk.clkr,
3271 [GSBI12_UART_SRC] = &gsbi12_uart_src.clkr,
3272 [GSBI12_UART_CLK] = &gsbi12_uart_clk.clkr,
3273 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
3274 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
3275 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
3276 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
3277 [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
3278 [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
3279 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
3280 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
3281 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
3282 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
3283 [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
3284 [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
3285 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
3286 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
3287 [GSBI8_QUP_SRC] = &gsbi8_qup_src.clkr,
3288 [GSBI8_QUP_CLK] = &gsbi8_qup_clk.clkr,
3289 [GSBI9_QUP_SRC] = &gsbi9_qup_src.clkr,
3290 [GSBI9_QUP_CLK] = &gsbi9_qup_clk.clkr,
3291 [GSBI10_QUP_SRC] = &gsbi10_qup_src.clkr,
3292 [GSBI10_QUP_CLK] = &gsbi10_qup_clk.clkr,
3293 [GSBI11_QUP_SRC] = &gsbi11_qup_src.clkr,
3294 [GSBI11_QUP_CLK] = &gsbi11_qup_clk.clkr,
3295 [GSBI12_QUP_SRC] = &gsbi12_qup_src.clkr,
3296 [GSBI12_QUP_CLK] = &gsbi12_qup_clk.clkr,
3297 [GP0_SRC] = &gp0_src.clkr,
3298 [GP0_CLK] = &gp0_clk.clkr,
3299 [GP1_SRC] = &gp1_src.clkr,
3300 [GP1_CLK] = &gp1_clk.clkr,
3301 [GP2_SRC] = &gp2_src.clkr,
3302 [GP2_CLK] = &gp2_clk.clkr,
3303 [PMEM_A_CLK] = &pmem_clk.clkr,
3304 [PRNG_SRC] = &prng_src.clkr,
3305 [PRNG_CLK] = &prng_clk.clkr,
3306 [SDC1_SRC] = &sdc1_src.clkr,
3307 [SDC1_CLK] = &sdc1_clk.clkr,
3308 [SDC2_SRC] = &sdc2_src.clkr,
3309 [SDC2_CLK] = &sdc2_clk.clkr,
3310 [SDC3_SRC] = &sdc3_src.clkr,
3311 [SDC3_CLK] = &sdc3_clk.clkr,
3312 [SDC4_SRC] = &sdc4_src.clkr,
3313 [SDC4_CLK] = &sdc4_clk.clkr,
3314 [SDC5_SRC] = &sdc5_src.clkr,
3315 [SDC5_CLK] = &sdc5_clk.clkr,
3316 [TSIF_REF_SRC] = &tsif_ref_src.clkr,
3317 [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
3318 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
3319 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
3320 [USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,
3321 [USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,
3322 [USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,
3323 [USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,
3324 [USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,
3325 [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
3326 [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
3327 [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
3328 [USB_FS2_XCVR_FS_SRC] = &usb_fs2_xcvr_fs_src.clkr,
3329 [USB_FS2_XCVR_FS_CLK] = &usb_fs2_xcvr_fs_clk.clkr,
3330 [USB_FS2_SYSTEM_CLK] = &usb_fs2_system_clk.clkr,
3331 [CE1_CORE_CLK] = &ce1_core_clk.clkr,
3332 [CE1_H_CLK] = &ce1_h_clk.clkr,
3333 [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
3334 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
3335 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
3336 [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
3337 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
3338 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
3339 [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
3340 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
3341 [GSBI8_H_CLK] = &gsbi8_h_clk.clkr,
3342 [GSBI9_H_CLK] = &gsbi9_h_clk.clkr,
3343 [GSBI10_H_CLK] = &gsbi10_h_clk.clkr,
3344 [GSBI11_H_CLK] = &gsbi11_h_clk.clkr,
3345 [GSBI12_H_CLK] = &gsbi12_h_clk.clkr,
3346 [TSIF_H_CLK] = &tsif_h_clk.clkr,
3347 [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
3348 [USB_FS2_H_CLK] = &usb_fs2_h_clk.clkr,
3349 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
3350 [USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,
3351 [SDC1_H_CLK] = &sdc1_h_clk.clkr,
3352 [SDC2_H_CLK] = &sdc2_h_clk.clkr,
3353 [SDC3_H_CLK] = &sdc3_h_clk.clkr,
3354 [SDC4_H_CLK] = &sdc4_h_clk.clkr,
3355 [SDC5_H_CLK] = &sdc5_h_clk.clkr,
3356 [ADM0_CLK] = &adm0_clk.clkr,
3357 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
3358 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
3359 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
3360 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
3361 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
3362 [PLL9] = &hfpll0.clkr,
3363 [PLL10] = &hfpll1.clkr,
3364 [PLL12] = &hfpll_l2.clkr,
3365};
3366
3367static const struct qcom_reset_map gcc_msm8960_resets[] = {
3368 [SFAB_MSS_Q6_SW_RESET] = { 0x2040, 7 },
3369 [SFAB_MSS_Q6_FW_RESET] = { 0x2044, 7 },
3370 [QDSS_STM_RESET] = { 0x2060, 6 },
3371 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
3372 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
3373 [AFAB_SMPSS_M0_RESET] = { 0x20b8 },
3374 [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
3375 [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7},
3376 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
3377 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
3378 [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
3379 [ADM0_C2_RESET] = { 0x220c, 4},
3380 [ADM0_C1_RESET] = { 0x220c, 3},
3381 [ADM0_C0_RESET] = { 0x220c, 2},
3382 [ADM0_PBUS_RESET] = { 0x220c, 1 },
3383 [ADM0_RESET] = { 0x220c },
3384 [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
3385 [QDSS_POR_RESET] = { 0x2260, 4 },
3386 [QDSS_TSCTR_RESET] = { 0x2260, 3 },
3387 [QDSS_HRESET_RESET] = { 0x2260, 2 },
3388 [QDSS_AXI_RESET] = { 0x2260, 1 },
3389 [QDSS_DBG_RESET] = { 0x2260 },
3390 [PCIE_A_RESET] = { 0x22c0, 7 },
3391 [PCIE_AUX_RESET] = { 0x22c8, 7 },
3392 [PCIE_H_RESET] = { 0x22d0, 7 },
3393 [SFAB_PCIE_M_RESET] = { 0x22d4, 1 },
3394 [SFAB_PCIE_S_RESET] = { 0x22d4 },
3395 [SFAB_MSS_M_RESET] = { 0x2340, 7 },
3396 [SFAB_USB3_M_RESET] = { 0x2360, 7 },
3397 [SFAB_RIVA_M_RESET] = { 0x2380, 7 },
3398 [SFAB_LPASS_RESET] = { 0x23a0, 7 },
3399 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
3400 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
3401 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
3402 [SFAB_SATA_S_RESET] = { 0x2480, 7 },
3403 [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
3404 [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
3405 [DFAB_SWAY0_RESET] = { 0x2540, 7 },
3406 [DFAB_SWAY1_RESET] = { 0x2544, 7 },
3407 [DFAB_ARB0_RESET] = { 0x2560, 7 },
3408 [DFAB_ARB1_RESET] = { 0x2564, 7 },
3409 [PPSS_PROC_RESET] = { 0x2594, 1 },
3410 [PPSS_RESET] = { 0x2594},
3411 [DMA_BAM_RESET] = { 0x25c0, 7 },
3412 [SPS_TIC_H_RESET] = { 0x2600, 7 },
3413 [SLIMBUS_H_RESET] = { 0x2620, 7 },
3414 [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
3415 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
3416 [TSIF_H_RESET] = { 0x2700, 7 },
3417 [CE1_H_RESET] = { 0x2720, 7 },
3418 [CE1_CORE_RESET] = { 0x2724, 7 },
3419 [CE1_SLEEP_RESET] = { 0x2728, 7 },
3420 [CE2_H_RESET] = { 0x2740, 7 },
3421 [CE2_CORE_RESET] = { 0x2744, 7 },
3422 [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
3423 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
3424 [RPM_PROC_RESET] = { 0x27c0, 7 },
3425 [PMIC_SSBI2_RESET] = { 0x280c, 12 },
3426 [SDC1_RESET] = { 0x2830 },
3427 [SDC2_RESET] = { 0x2850 },
3428 [SDC3_RESET] = { 0x2870 },
3429 [SDC4_RESET] = { 0x2890 },
3430 [SDC5_RESET] = { 0x28b0 },
3431 [DFAB_A2_RESET] = { 0x28c0, 7 },
3432 [USB_HS1_RESET] = { 0x2910 },
3433 [USB_HSIC_RESET] = { 0x2934 },
3434 [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
3435 [USB_FS1_RESET] = { 0x2974 },
3436 [USB_FS2_XCVR_RESET] = { 0x2994, 1 },
3437 [USB_FS2_RESET] = { 0x2994 },
3438 [GSBI1_RESET] = { 0x29dc },
3439 [GSBI2_RESET] = { 0x29fc },
3440 [GSBI3_RESET] = { 0x2a1c },
3441 [GSBI4_RESET] = { 0x2a3c },
3442 [GSBI5_RESET] = { 0x2a5c },
3443 [GSBI6_RESET] = { 0x2a7c },
3444 [GSBI7_RESET] = { 0x2a9c },
3445 [GSBI8_RESET] = { 0x2abc },
3446 [GSBI9_RESET] = { 0x2adc },
3447 [GSBI10_RESET] = { 0x2afc },
3448 [GSBI11_RESET] = { 0x2b1c },
3449 [GSBI12_RESET] = { 0x2b3c },
3450 [SPDM_RESET] = { 0x2b6c },
3451 [TLMM_H_RESET] = { 0x2ba0, 7 },
3452 [SFAB_MSS_S_RESET] = { 0x2c00, 7 },
3453 [MSS_SLP_RESET] = { 0x2c60, 7 },
3454 [MSS_Q6SW_JTAG_RESET] = { 0x2c68, 7 },
3455 [MSS_Q6FW_JTAG_RESET] = { 0x2c6c, 7 },
3456 [MSS_RESET] = { 0x2c64 },
3457 [SATA_H_RESET] = { 0x2c80, 7 },
3458 [SATA_RXOOB_RESE] = { 0x2c8c, 7 },
3459 [SATA_PMALIVE_RESET] = { 0x2c90, 7 },
3460 [SATA_SFAB_M_RESET] = { 0x2c98, 7 },
3461 [TSSC_RESET] = { 0x2ca0, 7 },
3462 [PDM_RESET] = { 0x2cc0, 12 },
3463 [MPM_H_RESET] = { 0x2da0, 7 },
3464 [MPM_RESET] = { 0x2da4 },
3465 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
3466 [PRNG_RESET] = { 0x2e80, 12 },
3467 [RIVA_RESET] = { 0x35e0 },
3468};
3469
3470static struct clk_regmap *gcc_apq8064_clks[] = {
3471 [PLL3] = &pll3.clkr,
3472 [PLL4_VOTE] = &pll4_vote,
3473 [PLL8] = &pll8.clkr,
3474 [PLL8_VOTE] = &pll8_vote,
3475 [PLL14] = &pll14.clkr,
3476 [PLL14_VOTE] = &pll14_vote,
3477 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
3478 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
3479 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
3480 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
3481 [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
3482 [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
3483 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
3484 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
3485 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
3486 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
3487 [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
3488 [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
3489 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
3490 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
3491 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
3492 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
3493 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
3494 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
3495 [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
3496 [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
3497 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
3498 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
3499 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
3500 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
3501 [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
3502 [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
3503 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
3504 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
3505 [GP0_SRC] = &gp0_src.clkr,
3506 [GP0_CLK] = &gp0_clk.clkr,
3507 [GP1_SRC] = &gp1_src.clkr,
3508 [GP1_CLK] = &gp1_clk.clkr,
3509 [GP2_SRC] = &gp2_src.clkr,
3510 [GP2_CLK] = &gp2_clk.clkr,
3511 [PMEM_A_CLK] = &pmem_clk.clkr,
3512 [PRNG_SRC] = &prng_src.clkr,
3513 [PRNG_CLK] = &prng_clk.clkr,
3514 [SDC1_SRC] = &sdc1_src.clkr,
3515 [SDC1_CLK] = &sdc1_clk.clkr,
3516 [SDC2_SRC] = &sdc2_src.clkr,
3517 [SDC2_CLK] = &sdc2_clk.clkr,
3518 [SDC3_SRC] = &sdc3_src.clkr,
3519 [SDC3_CLK] = &sdc3_clk.clkr,
3520 [SDC4_SRC] = &sdc4_src.clkr,
3521 [SDC4_CLK] = &sdc4_clk.clkr,
3522 [TSIF_REF_SRC] = &tsif_ref_src.clkr,
3523 [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
3524 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
3525 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
3526 [USB_HS3_XCVR_SRC] = &usb_hs3_xcvr_src.clkr,
3527 [USB_HS3_XCVR_CLK] = &usb_hs3_xcvr_clk.clkr,
3528 [USB_HS4_XCVR_SRC] = &usb_hs4_xcvr_src.clkr,
3529 [USB_HS4_XCVR_CLK] = &usb_hs4_xcvr_clk.clkr,
3530 [USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,
3531 [USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,
3532 [USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,
3533 [USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,
3534 [USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,
3535 [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
3536 [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
3537 [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
3538 [SATA_H_CLK] = &sata_h_clk.clkr,
3539 [SATA_CLK_SRC] = &sata_clk_src.clkr,
3540 [SATA_RXOOB_CLK] = &sata_rxoob_clk.clkr,
3541 [SATA_PMALIVE_CLK] = &sata_pmalive_clk.clkr,
3542 [SATA_PHY_REF_CLK] = &sata_phy_ref_clk.clkr,
3543 [SATA_PHY_CFG_CLK] = &sata_phy_cfg_clk.clkr,
3544 [SATA_A_CLK] = &sata_a_clk.clkr,
3545 [SFAB_SATA_S_H_CLK] = &sfab_sata_s_h_clk.clkr,
3546 [CE3_SRC] = &ce3_src.clkr,
3547 [CE3_CORE_CLK] = &ce3_core_clk.clkr,
3548 [CE3_H_CLK] = &ce3_h_clk.clkr,
3549 [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
3550 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
3551 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
3552 [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
3553 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
3554 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
3555 [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
3556 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
3557 [TSIF_H_CLK] = &tsif_h_clk.clkr,
3558 [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
3559 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
3560 [USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,
3561 [USB_HS3_H_CLK] = &usb_hs3_h_clk.clkr,
3562 [USB_HS4_H_CLK] = &usb_hs4_h_clk.clkr,
3563 [SDC1_H_CLK] = &sdc1_h_clk.clkr,
3564 [SDC2_H_CLK] = &sdc2_h_clk.clkr,
3565 [SDC3_H_CLK] = &sdc3_h_clk.clkr,
3566 [SDC4_H_CLK] = &sdc4_h_clk.clkr,
3567 [ADM0_CLK] = &adm0_clk.clkr,
3568 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
3569 [PCIE_A_CLK] = &pcie_a_clk.clkr,
3570 [PCIE_PHY_REF_CLK] = &pcie_phy_ref_clk.clkr,
3571 [PCIE_H_CLK] = &pcie_h_clk.clkr,
3572 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
3573 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
3574 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
3575 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
3576 [PLL9] = &hfpll0.clkr,
3577 [PLL10] = &hfpll1.clkr,
3578 [PLL12] = &hfpll_l2.clkr,
3579 [PLL16] = &hfpll2.clkr,
3580 [PLL17] = &hfpll3.clkr,
3581};
3582
3583static const struct qcom_reset_map gcc_apq8064_resets[] = {
3584 [QDSS_STM_RESET] = { 0x2060, 6 },
3585 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
3586 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
3587 [AFAB_SMPSS_M0_RESET] = { 0x20b8 },
3588 [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
3589 [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7},
3590 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
3591 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
3592 [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
3593 [ADM0_C2_RESET] = { 0x220c, 4},
3594 [ADM0_C1_RESET] = { 0x220c, 3},
3595 [ADM0_C0_RESET] = { 0x220c, 2},
3596 [ADM0_PBUS_RESET] = { 0x220c, 1 },
3597 [ADM0_RESET] = { 0x220c },
3598 [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
3599 [QDSS_POR_RESET] = { 0x2260, 4 },
3600 [QDSS_TSCTR_RESET] = { 0x2260, 3 },
3601 [QDSS_HRESET_RESET] = { 0x2260, 2 },
3602 [QDSS_AXI_RESET] = { 0x2260, 1 },
3603 [QDSS_DBG_RESET] = { 0x2260 },
3604 [SFAB_PCIE_M_RESET] = { 0x22d8, 1 },
3605 [SFAB_PCIE_S_RESET] = { 0x22d8 },
3606 [PCIE_EXT_PCI_RESET] = { 0x22dc, 6 },
3607 [PCIE_PHY_RESET] = { 0x22dc, 5 },
3608 [PCIE_PCI_RESET] = { 0x22dc, 4 },
3609 [PCIE_POR_RESET] = { 0x22dc, 3 },
3610 [PCIE_HCLK_RESET] = { 0x22dc, 2 },
3611 [PCIE_ACLK_RESET] = { 0x22dc },
3612 [SFAB_USB3_M_RESET] = { 0x2360, 7 },
3613 [SFAB_RIVA_M_RESET] = { 0x2380, 7 },
3614 [SFAB_LPASS_RESET] = { 0x23a0, 7 },
3615 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
3616 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
3617 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
3618 [SFAB_SATA_S_RESET] = { 0x2480, 7 },
3619 [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
3620 [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
3621 [DFAB_SWAY0_RESET] = { 0x2540, 7 },
3622 [DFAB_SWAY1_RESET] = { 0x2544, 7 },
3623 [DFAB_ARB0_RESET] = { 0x2560, 7 },
3624 [DFAB_ARB1_RESET] = { 0x2564, 7 },
3625 [PPSS_PROC_RESET] = { 0x2594, 1 },
3626 [PPSS_RESET] = { 0x2594},
3627 [DMA_BAM_RESET] = { 0x25c0, 7 },
3628 [SPS_TIC_H_RESET] = { 0x2600, 7 },
3629 [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
3630 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
3631 [TSIF_H_RESET] = { 0x2700, 7 },
3632 [CE1_H_RESET] = { 0x2720, 7 },
3633 [CE1_CORE_RESET] = { 0x2724, 7 },
3634 [CE1_SLEEP_RESET] = { 0x2728, 7 },
3635 [CE2_H_RESET] = { 0x2740, 7 },
3636 [CE2_CORE_RESET] = { 0x2744, 7 },
3637 [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
3638 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
3639 [RPM_PROC_RESET] = { 0x27c0, 7 },
3640 [PMIC_SSBI2_RESET] = { 0x280c, 12 },
3641 [SDC1_RESET] = { 0x2830 },
3642 [SDC2_RESET] = { 0x2850 },
3643 [SDC3_RESET] = { 0x2870 },
3644 [SDC4_RESET] = { 0x2890 },
3645 [USB_HS1_RESET] = { 0x2910 },
3646 [USB_HSIC_RESET] = { 0x2934 },
3647 [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
3648 [USB_FS1_RESET] = { 0x2974 },
3649 [GSBI1_RESET] = { 0x29dc },
3650 [GSBI2_RESET] = { 0x29fc },
3651 [GSBI3_RESET] = { 0x2a1c },
3652 [GSBI4_RESET] = { 0x2a3c },
3653 [GSBI5_RESET] = { 0x2a5c },
3654 [GSBI6_RESET] = { 0x2a7c },
3655 [GSBI7_RESET] = { 0x2a9c },
3656 [SPDM_RESET] = { 0x2b6c },
3657 [TLMM_H_RESET] = { 0x2ba0, 7 },
3658 [SATA_SFAB_M_RESET] = { 0x2c18 },
3659 [SATA_RESET] = { 0x2c1c },
3660 [GSS_SLP_RESET] = { 0x2c60, 7 },
3661 [GSS_RESET] = { 0x2c64 },
3662 [TSSC_RESET] = { 0x2ca0, 7 },
3663 [PDM_RESET] = { 0x2cc0, 12 },
3664 [MPM_H_RESET] = { 0x2da0, 7 },
3665 [MPM_RESET] = { 0x2da4 },
3666 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
3667 [PRNG_RESET] = { 0x2e80, 12 },
3668 [RIVA_RESET] = { 0x35e0 },
3669 [CE3_H_RESET] = { 0x36c4, 7 },
3670 [SFAB_CE3_M_RESET] = { 0x36c8, 1 },
3671 [SFAB_CE3_S_RESET] = { 0x36c8 },
3672 [CE3_RESET] = { 0x36cc, 7 },
3673 [CE3_SLEEP_RESET] = { 0x36d0, 7 },
3674 [USB_HS3_RESET] = { 0x3710 },
3675 [USB_HS4_RESET] = { 0x3730 },
3676};
3677
3678static const struct regmap_config gcc_msm8960_regmap_config = {
3679 .reg_bits = 32,
3680 .reg_stride = 4,
3681 .val_bits = 32,
3682 .max_register = 0x3660,
3683 .fast_io = true,
3684};
3685
3686static const struct regmap_config gcc_apq8064_regmap_config = {
3687 .reg_bits = 32,
3688 .reg_stride = 4,
3689 .val_bits = 32,
3690 .max_register = 0x3880,
3691 .fast_io = true,
3692};
3693
3694static const struct qcom_cc_desc gcc_msm8960_desc = {
3695 .config = &gcc_msm8960_regmap_config,
3696 .clks = gcc_msm8960_clks,
3697 .num_clks = ARRAY_SIZE(gcc_msm8960_clks),
3698 .resets = gcc_msm8960_resets,
3699 .num_resets = ARRAY_SIZE(gcc_msm8960_resets),
3700};
3701
3702static const struct qcom_cc_desc gcc_apq8064_desc = {
3703 .config = &gcc_apq8064_regmap_config,
3704 .clks = gcc_apq8064_clks,
3705 .num_clks = ARRAY_SIZE(gcc_apq8064_clks),
3706 .resets = gcc_apq8064_resets,
3707 .num_resets = ARRAY_SIZE(gcc_apq8064_resets),
3708};
3709
3710static const struct of_device_id gcc_msm8960_match_table[] = {
3711 { .compatible = "qcom,gcc-msm8960", .data = &gcc_msm8960_desc },
3712 { .compatible = "qcom,gcc-apq8064", .data = &gcc_apq8064_desc },
3713 { }
3714};
3715MODULE_DEVICE_TABLE(of, gcc_msm8960_match_table);
3716
3717static int gcc_msm8960_probe(struct platform_device *pdev)
3718{
3719 struct device *dev = &pdev->dev;
3720 struct platform_device *tsens;
3721 const struct qcom_cc_desc *desc = device_get_match_data(dev);
3722 int ret;
3723
3724 ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 19200000);
3725 if (ret)
3726 return ret;
3727
3728 ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 27000000);
3729 if (ret)
3730 return ret;
3731
3732 ret = qcom_cc_probe(pdev, desc);
3733 if (ret)
3734 return ret;
3735
3736 if (desc == &gcc_apq8064_desc) {
3737 hfpll1.d = &hfpll1_8064_data;
3738 hfpll_l2.d = &hfpll_l2_8064_data;
3739 }
3740
3741 if (of_get_available_child_count(pdev->dev.of_node) != 0)
3742 return devm_of_platform_populate(&pdev->dev);
3743
3744 tsens = platform_device_register_data(&pdev->dev, "qcom-tsens", -1,
3745 NULL, 0);
3746 if (IS_ERR(tsens))
3747 return PTR_ERR(tsens);
3748
3749 platform_set_drvdata(pdev, tsens);
3750
3751 return 0;
3752}
3753
3754static void gcc_msm8960_remove(struct platform_device *pdev)
3755{
3756 struct platform_device *tsens = platform_get_drvdata(pdev);
3757
3758 if (tsens)
3759 platform_device_unregister(tsens);
3760}
3761
3762static struct platform_driver gcc_msm8960_driver = {
3763 .probe = gcc_msm8960_probe,
3764 .remove_new = gcc_msm8960_remove,
3765 .driver = {
3766 .name = "gcc-msm8960",
3767 .of_match_table = gcc_msm8960_match_table,
3768 },
3769};
3770
3771static int __init gcc_msm8960_init(void)
3772{
3773 return platform_driver_register(&gcc_msm8960_driver);
3774}
3775core_initcall(gcc_msm8960_init);
3776
3777static void __exit gcc_msm8960_exit(void)
3778{
3779 platform_driver_unregister(&gcc_msm8960_driver);
3780}
3781module_exit(gcc_msm8960_exit);
3782
3783MODULE_DESCRIPTION("QCOM GCC MSM8960 Driver");
3784MODULE_LICENSE("GPL v2");
3785MODULE_ALIAS("platform:gcc-msm8960");