1// SPDX-License-Identifier: GPL-2.0-only
   2// Copyright (c) 2021, The Linux Foundation. All rights reserved.
   3
   4#include <linux/kernel.h>
   5#include <linux/bitops.h>
   6#include <linux/err.h>
   7#include <linux/module.h>
   8#include <linux/platform_device.h>
   9#include <linux/of.h>
  10#include <linux/clk-provider.h>
  11#include <linux/regmap.h>
  12#include <linux/reset-controller.h>
  13
  14#include <dt-bindings/clock/qcom,gcc-msm8953.h>
  15
  16#include "clk-alpha-pll.h"
  17#include "clk-branch.h"
  18#include "clk-rcg.h"
  19#include "common.h"
  20#include "gdsc.h"
  21#include "reset.h"
  22
  23enum {
  24	P_XO,
  25	P_SLEEP_CLK,
  26	P_GPLL0,
  27	P_GPLL0_DIV2,
  28	P_GPLL2,
  29	P_GPLL3,
  30	P_GPLL4,
  31	P_GPLL6,
  32	P_GPLL6_DIV2,
  33	P_DSI0PLL,
  34	P_DSI0PLL_BYTE,
  35	P_DSI1PLL,
  36	P_DSI1PLL_BYTE,
  37};
  38
  39static struct clk_alpha_pll gpll0_early = {
  40	.offset = 0x21000,
  41	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  42	.clkr = {
  43		.enable_reg = 0x45000,
  44		.enable_mask = BIT(0),
  45		.hw.init = &(struct clk_init_data) {
  46			.name = "gpll0_early",
  47			.parent_data = &(const struct clk_parent_data) {
  48				.fw_name = "xo",
  49			},
  50			.num_parents = 1,
  51			.ops = &clk_alpha_pll_fixed_ops,
  52		},
  53	},
  54};
  55
  56static struct clk_fixed_factor gpll0_early_div = {
  57	.mult = 1,
  58	.div = 2,
  59	.hw.init = &(struct clk_init_data){
  60		.name = "gpll0_early_div",
  61		.parent_hws = (const struct clk_hw*[]){
  62			&gpll0_early.clkr.hw,
  63		},
  64		.num_parents = 1,
  65		.ops = &clk_fixed_factor_ops,
  66	},
  67};
  68
  69static struct clk_alpha_pll_postdiv gpll0 = {
  70	.offset = 0x21000,
  71	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  72	.clkr.hw.init = &(struct clk_init_data){
  73		.name = "gpll0",
  74		.parent_hws = (const struct clk_hw*[]){
  75			&gpll0_early.clkr.hw,
  76		},
  77		.num_parents = 1,
  78		.ops = &clk_alpha_pll_postdiv_ro_ops,
  79	},
  80};
  81
  82static struct clk_alpha_pll gpll2_early = {
  83	.offset = 0x4a000,
  84	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  85	.clkr = {
  86		.enable_reg = 0x45000,
  87		.enable_mask = BIT(2),
  88		.hw.init = &(struct clk_init_data){
  89			.name = "gpll2_early",
  90			.parent_data = &(const struct clk_parent_data) {
  91				.fw_name = "xo",
  92			},
  93			.num_parents = 1,
  94			.ops = &clk_alpha_pll_fixed_ops,
  95		},
  96	},
  97};
  98
  99static struct clk_alpha_pll_postdiv gpll2 = {
 100	.offset = 0x4a000,
 101	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 102	.clkr.hw.init = &(struct clk_init_data){
 103		.name = "gpll2",
 104		.parent_hws = (const struct clk_hw*[]){
 105			&gpll2_early.clkr.hw,
 106		},
 107		.num_parents = 1,
 108		.ops = &clk_alpha_pll_postdiv_ro_ops,
 109	},
 110};
 111
 112static const struct pll_vco gpll3_p_vco[] = {
 113	{ 1000000000, 2000000000, 0 },
 114};
 115
 116static const struct alpha_pll_config gpll3_early_config = {
 117	.l = 63,
 118	.config_ctl_val = 0x4001055b,
 119	.early_output_mask = 0,
 120	.post_div_mask = GENMASK(11, 8),
 121	.post_div_val = BIT(8),
 122};
 123
 124static struct clk_alpha_pll gpll3_early = {
 125	.offset = 0x22000,
 126	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 127	.vco_table = gpll3_p_vco,
 128	.num_vco = ARRAY_SIZE(gpll3_p_vco),
 129	.flags = SUPPORTS_DYNAMIC_UPDATE,
 130	.clkr = {
 131		.hw.init = &(struct clk_init_data){
 132			.name = "gpll3_early",
 133			.parent_data = &(const struct clk_parent_data) {
 134				.fw_name = "xo",
 135			},
 136			.num_parents = 1,
 137			.ops = &clk_alpha_pll_ops,
 138		},
 139	},
 140};
 141
 142static struct clk_alpha_pll_postdiv gpll3 = {
 143	.offset = 0x22000,
 144	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 145	.clkr.hw.init = &(struct clk_init_data){
 146		.name = "gpll3",
 147		.parent_hws = (const struct clk_hw*[]){
 148			&gpll3_early.clkr.hw,
 149		},
 150		.num_parents = 1,
 151		.ops = &clk_alpha_pll_postdiv_ops,
 152		.flags = CLK_SET_RATE_PARENT,
 153	},
 154};
 155
 156static struct clk_alpha_pll gpll4_early = {
 157	.offset = 0x24000,
 158	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 159	.clkr = {
 160		.enable_reg = 0x45000,
 161		.enable_mask = BIT(5),
 162		.hw.init = &(struct clk_init_data){
 163			.name = "gpll4_early",
 164			.parent_data = &(const struct clk_parent_data) {
 165				.fw_name = "xo",
 166			},
 167			.num_parents = 1,
 168			.ops = &clk_alpha_pll_fixed_ops,
 169		},
 170	},
 171};
 172
 173static struct clk_alpha_pll_postdiv gpll4 = {
 174	.offset = 0x24000,
 175	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 176	.clkr.hw.init = &(struct clk_init_data){
 177		.name = "gpll4",
 178		.parent_hws = (const struct clk_hw*[]){
 179			&gpll4_early.clkr.hw,
 180		},
 181		.num_parents = 1,
 182		.ops = &clk_alpha_pll_postdiv_ro_ops,
 183	},
 184};
 185
 186static struct clk_alpha_pll gpll6_early = {
 187	.offset = 0x37000,
 188	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 189	.clkr = {
 190		.enable_reg = 0x45000,
 191		.enable_mask = BIT(7),
 192		.hw.init = &(struct clk_init_data){
 193			.name = "gpll6_early",
 194			.parent_data = &(const struct clk_parent_data) {
 195				.fw_name = "xo",
 196			},
 197			.num_parents = 1,
 198			.ops = &clk_alpha_pll_fixed_ops,
 199		},
 200	},
 201};
 202
 203static struct clk_fixed_factor gpll6_early_div = {
 204	.mult = 1,
 205	.div = 2,
 206	.hw.init = &(struct clk_init_data){
 207		.name = "gpll6_early_div",
 208		.parent_hws = (const struct clk_hw*[]){
 209			&gpll6_early.clkr.hw,
 210		},
 211		.num_parents = 1,
 212		.ops = &clk_fixed_factor_ops,
 213	},
 214};
 215
 216static struct clk_alpha_pll_postdiv gpll6 = {
 217	.offset = 0x37000,
 218	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 219	.clkr.hw.init = &(struct clk_init_data){
 220		.name = "gpll6",
 221		.parent_hws = (const struct clk_hw*[]){
 222			&gpll6_early.clkr.hw,
 223		},
 224		.num_parents = 1,
 225		.ops = &clk_alpha_pll_postdiv_ro_ops,
 226	},
 227};
 228
 229static const struct parent_map gcc_xo_gpll0_gpll0div2_2_map[] = {
 230	{ P_XO, 0 },
 231	{ P_GPLL0, 1 },
 232	{ P_GPLL0_DIV2, 2 },
 233};
 234
 235static const struct parent_map gcc_xo_gpll0_gpll0div2_4_map[] = {
 236	{ P_XO, 0 },
 237	{ P_GPLL0, 1 },
 238	{ P_GPLL0_DIV2, 4 },
 239};
 240
 241static const struct clk_parent_data gcc_xo_gpll0_gpll0div2_data[] = {
 242	{ .fw_name = "xo" },
 243	{ .hw = &gpll0.clkr.hw },
 244	{ .hw = &gpll0_early_div.hw },
 245};
 246
 247static const struct parent_map gcc_apc_droop_detector_map[] = {
 248	{ P_XO, 0 },
 249	{ P_GPLL0, 1 },
 250	{ P_GPLL4, 2 },
 251};
 252
 253static const struct clk_parent_data gcc_apc_droop_detector_data[] = {
 254	{ .fw_name = "xo" },
 255	{ .hw = &gpll0.clkr.hw },
 256	{ .hw = &gpll4.clkr.hw },
 257};
 258
 259static const struct freq_tbl ftbl_apc_droop_detector_clk_src[] = {
 260	F(19200000, P_XO, 1, 0, 0),
 261	F(400000000, P_GPLL0, 2, 0, 0),
 262	F(576000000, P_GPLL4, 2, 0, 0),
 263	{ }
 264};
 265
 266static struct clk_rcg2 apc0_droop_detector_clk_src = {
 267	.cmd_rcgr = 0x78008,
 268	.hid_width = 5,
 269	.freq_tbl = ftbl_apc_droop_detector_clk_src,
 270	.parent_map = gcc_apc_droop_detector_map,
 271	.clkr.hw.init = &(struct clk_init_data) {
 272		.name = "apc0_droop_detector_clk_src",
 273		.parent_data = gcc_apc_droop_detector_data,
 274		.num_parents = ARRAY_SIZE(gcc_apc_droop_detector_data),
 275		.ops = &clk_rcg2_ops,
 276	}
 277};
 278static struct clk_rcg2 apc1_droop_detector_clk_src = {
 279	.cmd_rcgr = 0x79008,
 280	.hid_width = 5,
 281	.freq_tbl = ftbl_apc_droop_detector_clk_src,
 282	.parent_map = gcc_apc_droop_detector_map,
 283	.clkr.hw.init = &(struct clk_init_data) {
 284		.name = "apc1_droop_detector_clk_src",
 285		.parent_data = gcc_apc_droop_detector_data,
 286		.num_parents = ARRAY_SIZE(gcc_apc_droop_detector_data),
 287		.ops = &clk_rcg2_ops,
 288	}
 289};
 290
 291static const struct freq_tbl ftbl_apss_ahb_clk_src[] = {
 292	F(19200000, P_XO, 1, 0, 0),
 293	F(25000000, P_GPLL0_DIV2, 16, 0, 0),
 294	F(50000000, P_GPLL0, 16, 0, 0),
 295	F(100000000, P_GPLL0, 8, 0, 0),
 296	F(133330000, P_GPLL0, 6, 0, 0),
 297	{ }
 298};
 299
 300static struct clk_rcg2 apss_ahb_clk_src = {
 301	.cmd_rcgr = 0x46000,
 302	.hid_width = 5,
 303	.freq_tbl = ftbl_apss_ahb_clk_src,
 304	.parent_map = gcc_xo_gpll0_gpll0div2_4_map,
 305	.clkr.hw.init = &(struct clk_init_data) {
 306		.name = "apss_ahb_clk_src",
 307		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 308		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 309		.ops = &clk_rcg2_ops,
 310	}
 311};
 312
 313static const struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = {
 314	F(19200000, P_XO, 1, 0, 0),
 315	F(25000000, P_GPLL0_DIV2, 16, 0, 0),
 316	F(50000000, P_GPLL0, 16, 0, 0),
 317	{ }
 318};
 319
 320static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 321	.cmd_rcgr = 0x0200c,
 322	.hid_width = 5,
 323	.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 324	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
 325	.clkr.hw.init = &(struct clk_init_data) {
 326		.name = "blsp1_qup1_i2c_apps_clk_src",
 327		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 328		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 329		.ops = &clk_rcg2_ops,
 330	}
 331};
 332
 333static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 334	.cmd_rcgr = 0x03000,
 335	.hid_width = 5,
 336	.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 337	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
 338	.clkr.hw.init = &(struct clk_init_data) {
 339		.name = "blsp1_qup2_i2c_apps_clk_src",
 340		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 341		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 342		.ops = &clk_rcg2_ops,
 343	}
 344};
 345
 346static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 347	.cmd_rcgr = 0x04000,
 348	.hid_width = 5,
 349	.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 350	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
 351	.clkr.hw.init = &(struct clk_init_data) {
 352		.name = "blsp1_qup3_i2c_apps_clk_src",
 353		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 354		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 355		.ops = &clk_rcg2_ops,
 356	}
 357};
 358
 359static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 360	.cmd_rcgr = 0x05000,
 361	.hid_width = 5,
 362	.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 363	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
 364	.clkr.hw.init = &(struct clk_init_data) {
 365		.name = "blsp1_qup4_i2c_apps_clk_src",
 366		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 367		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 368		.ops = &clk_rcg2_ops,
 369	}
 370};
 371
 372static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
 373	.cmd_rcgr = 0x0c00c,
 374	.hid_width = 5,
 375	.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 376	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
 377	.clkr.hw.init = &(struct clk_init_data) {
 378		.name = "blsp2_qup1_i2c_apps_clk_src",
 379		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 380		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 381		.ops = &clk_rcg2_ops,
 382	}
 383};
 384
 385static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
 386	.cmd_rcgr = 0x0d000,
 387	.hid_width = 5,
 388	.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 389	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
 390	.clkr.hw.init = &(struct clk_init_data) {
 391		.name = "blsp2_qup2_i2c_apps_clk_src",
 392		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 393		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 394		.ops = &clk_rcg2_ops,
 395	}
 396};
 397
 398static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
 399	.cmd_rcgr = 0x0f000,
 400	.hid_width = 5,
 401	.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 402	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
 403	.clkr.hw.init = &(struct clk_init_data) {
 404		.name = "blsp2_qup3_i2c_apps_clk_src",
 405		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 406		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 407		.ops = &clk_rcg2_ops,
 408	}
 409};
 410
 411static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
 412	.cmd_rcgr = 0x18000,
 413	.hid_width = 5,
 414	.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 415	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
 416	.clkr.hw.init = &(struct clk_init_data) {
 417		.name = "blsp2_qup4_i2c_apps_clk_src",
 418		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 419		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 420		.ops = &clk_rcg2_ops,
 421	}
 422};
 423
 424static const struct freq_tbl ftbl_blsp_spi_apps_clk_src[] = {
 425	F(960000, P_XO, 10, 1, 2),
 426	F(4800000, P_XO, 4, 0, 0),
 427	F(9600000, P_XO, 2, 0, 0),
 428	F(12500000, P_GPLL0_DIV2, 16, 1, 2),
 429	F(16000000, P_GPLL0, 10, 1, 5),
 430	F(19200000, P_XO, 1, 0, 0),
 431	F(25000000, P_GPLL0, 16, 1, 2),
 432	F(50000000, P_GPLL0, 16, 0, 0),
 433	{ }
 434};
 435
 436static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 437	.cmd_rcgr = 0x02024,
 438	.hid_width = 5,
 439	.mnd_width = 8,
 440	.freq_tbl = ftbl_blsp_spi_apps_clk_src,
 441	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
 442	.clkr.hw.init = &(struct clk_init_data) {
 443		.name = "blsp1_qup1_spi_apps_clk_src",
 444		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 445		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 446		.ops = &clk_rcg2_ops,
 447	}
 448};
 449
 450static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 451	.cmd_rcgr = 0x03014,
 452	.hid_width = 5,
 453	.mnd_width = 8,
 454	.freq_tbl = ftbl_blsp_spi_apps_clk_src,
 455	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
 456	.clkr.hw.init = &(struct clk_init_data) {
 457		.name = "blsp1_qup2_spi_apps_clk_src",
 458		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 459		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 460		.ops = &clk_rcg2_ops,
 461	}
 462};
 463
 464static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 465	.cmd_rcgr = 0x04024,
 466	.hid_width = 5,
 467	.mnd_width = 8,
 468	.freq_tbl = ftbl_blsp_spi_apps_clk_src,
 469	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
 470	.clkr.hw.init = &(struct clk_init_data) {
 471		.name = "blsp1_qup3_spi_apps_clk_src",
 472		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 473		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 474		.ops = &clk_rcg2_ops,
 475	}
 476};
 477
 478static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 479	.cmd_rcgr = 0x05024,
 480	.hid_width = 5,
 481	.mnd_width = 8,
 482	.freq_tbl = ftbl_blsp_spi_apps_clk_src,
 483	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
 484	.clkr.hw.init = &(struct clk_init_data) {
 485		.name = "blsp1_qup4_spi_apps_clk_src",
 486		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 487		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 488		.ops = &clk_rcg2_ops,
 489	}
 490};
 491
 492static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
 493	.cmd_rcgr = 0x0c024,
 494	.hid_width = 5,
 495	.mnd_width = 8,
 496	.freq_tbl = ftbl_blsp_spi_apps_clk_src,
 497	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
 498	.clkr.hw.init = &(struct clk_init_data) {
 499		.name = "blsp2_qup1_spi_apps_clk_src",
 500		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 501		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 502		.ops = &clk_rcg2_ops,
 503	}
 504};
 505
 506static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
 507	.cmd_rcgr = 0x0d014,
 508	.hid_width = 5,
 509	.mnd_width = 8,
 510	.freq_tbl = ftbl_blsp_spi_apps_clk_src,
 511	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
 512	.clkr.hw.init = &(struct clk_init_data) {
 513		.name = "blsp2_qup2_spi_apps_clk_src",
 514		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 515		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 516		.ops = &clk_rcg2_ops,
 517	}
 518};
 519
 520static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
 521	.cmd_rcgr = 0x0f024,
 522	.hid_width = 5,
 523	.mnd_width = 8,
 524	.freq_tbl = ftbl_blsp_spi_apps_clk_src,
 525	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
 526	.clkr.hw.init = &(struct clk_init_data) {
 527		.name = "blsp2_qup3_spi_apps_clk_src",
 528		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 529		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 530		.ops = &clk_rcg2_ops,
 531	}
 532};
 533
 534static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
 535	.cmd_rcgr = 0x18024,
 536	.hid_width = 5,
 537	.mnd_width = 8,
 538	.freq_tbl = ftbl_blsp_spi_apps_clk_src,
 539	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
 540	.clkr.hw.init = &(struct clk_init_data) {
 541		.name = "blsp2_qup4_spi_apps_clk_src",
 542		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 543		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 544		.ops = &clk_rcg2_ops,
 545	}
 546};
 547
 548static const struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = {
 549	F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
 550	F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
 551	F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
 552	F(16000000, P_GPLL0_DIV2, 5, 1, 5),
 553	F(19200000, P_XO, 1, 0, 0),
 554	F(24000000, P_GPLL0, 1, 3, 100),
 555	F(25000000, P_GPLL0, 16, 1, 2),
 556	F(32000000, P_GPLL0, 1, 1, 25),
 557	F(40000000, P_GPLL0, 1, 1, 20),
 558	F(46400000, P_GPLL0, 1, 29, 500),
 559	F(48000000, P_GPLL0, 1, 3, 50),
 560	F(51200000, P_GPLL0, 1, 8, 125),
 561	F(56000000, P_GPLL0, 1, 7, 100),
 562	F(58982400, P_GPLL0, 1, 1152, 15625),
 563	F(60000000, P_GPLL0, 1, 3, 40),
 564	F(64000000, P_GPLL0, 1, 2, 25),
 565	{ }
 566};
 567
 568static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 569	.cmd_rcgr = 0x02044,
 570	.hid_width = 5,
 571	.mnd_width = 16,
 572	.freq_tbl = ftbl_blsp_uart_apps_clk_src,
 573	.parent_map = gcc_xo_gpll0_gpll0div2_4_map,
 574	.clkr.hw.init = &(struct clk_init_data) {
 575		.name = "blsp1_uart1_apps_clk_src",
 576		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 577		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 578		.ops = &clk_rcg2_ops,
 579	}
 580};
 581
 582static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 583	.cmd_rcgr = 0x03034,
 584	.hid_width = 5,
 585	.mnd_width = 16,
 586	.freq_tbl = ftbl_blsp_uart_apps_clk_src,
 587	.parent_map = gcc_xo_gpll0_gpll0div2_4_map,
 588	.clkr.hw.init = &(struct clk_init_data) {
 589		.name = "blsp1_uart2_apps_clk_src",
 590		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 591		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 592		.ops = &clk_rcg2_ops,
 593	}
 594};
 595
 596static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
 597	.cmd_rcgr = 0x0c044,
 598	.hid_width = 5,
 599	.mnd_width = 16,
 600	.freq_tbl = ftbl_blsp_uart_apps_clk_src,
 601	.parent_map = gcc_xo_gpll0_gpll0div2_4_map,
 602	.clkr.hw.init = &(struct clk_init_data) {
 603		.name = "blsp2_uart1_apps_clk_src",
 604		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 605		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 606		.ops = &clk_rcg2_ops,
 607	}
 608};
 609
 610static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
 611	.cmd_rcgr = 0x0d034,
 612	.hid_width = 5,
 613	.mnd_width = 16,
 614	.freq_tbl = ftbl_blsp_uart_apps_clk_src,
 615	.parent_map = gcc_xo_gpll0_gpll0div2_4_map,
 616	.clkr.hw.init = &(struct clk_init_data) {
 617		.name = "blsp2_uart2_apps_clk_src",
 618		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 619		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 620		.ops = &clk_rcg2_ops,
 621	}
 622};
 623
 624static const struct parent_map gcc_byte0_map[] = {
 625	{ P_XO, 0 },
 626	{ P_DSI0PLL_BYTE, 1 },
 627	{ P_DSI1PLL_BYTE, 3 },
 628};
 629
 630static const struct parent_map gcc_byte1_map[] = {
 631	{ P_XO, 0 },
 632	{ P_DSI0PLL_BYTE, 3 },
 633	{ P_DSI1PLL_BYTE, 1 },
 634};
 635
 636static const struct clk_parent_data gcc_byte_data[] = {
 637	{ .fw_name = "xo" },
 638	{ .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
 639	{ .fw_name = "dsi1pllbyte", .name = "dsi1pllbyte" },
 640};
 641
 642static struct clk_rcg2 byte0_clk_src = {
 643	.cmd_rcgr = 0x4d044,
 644	.hid_width = 5,
 645	.parent_map = gcc_byte0_map,
 646	.clkr.hw.init = &(struct clk_init_data) {
 647		.name = "byte0_clk_src",
 648		.parent_data = gcc_byte_data,
 649		.num_parents = ARRAY_SIZE(gcc_byte_data),
 650		.ops = &clk_byte2_ops,
 651		.flags = CLK_SET_RATE_PARENT,
 652	}
 653};
 654
 655static struct clk_rcg2 byte1_clk_src = {
 656	.cmd_rcgr = 0x4d0b0,
 657	.hid_width = 5,
 658	.parent_map = gcc_byte1_map,
 659	.clkr.hw.init = &(struct clk_init_data) {
 660		.name = "byte1_clk_src",
 661		.parent_data = gcc_byte_data,
 662		.num_parents = ARRAY_SIZE(gcc_byte_data),
 663		.ops = &clk_byte2_ops,
 664		.flags = CLK_SET_RATE_PARENT,
 665	}
 666};
 667
 668static const struct parent_map gcc_gp_map[] = {
 669	{ P_XO, 0 },
 670	{ P_GPLL0, 1 },
 671	{ P_GPLL6, 2 },
 672	{ P_GPLL0_DIV2, 4 },
 673	{ P_SLEEP_CLK, 6 },
 674};
 675
 676static const struct clk_parent_data gcc_gp_data[] = {
 677	{ .fw_name = "xo" },
 678	{ .hw = &gpll0.clkr.hw },
 679	{ .hw = &gpll6.clkr.hw },
 680	{ .hw = &gpll0_early_div.hw },
 681	{ .fw_name = "sleep", .name = "sleep" },
 682};
 683
 684static const struct freq_tbl ftbl_camss_gp_clk_src[] = {
 685	F(50000000, P_GPLL0_DIV2, 8, 0, 0),
 686	F(100000000, P_GPLL0, 8, 0, 0),
 687	F(200000000, P_GPLL0, 4, 0, 0),
 688	F(266670000, P_GPLL0, 3, 0, 0),
 689	{ }
 690};
 691
 692static struct clk_rcg2 camss_gp0_clk_src = {
 693	.cmd_rcgr = 0x54000,
 694	.hid_width = 5,
 695	.mnd_width = 8,
 696	.freq_tbl = ftbl_camss_gp_clk_src,
 697	.parent_map = gcc_gp_map,
 698	.clkr.hw.init = &(struct clk_init_data) {
 699		.name = "camss_gp0_clk_src",
 700		.parent_data = gcc_gp_data,
 701		.num_parents = ARRAY_SIZE(gcc_gp_data),
 702		.ops = &clk_rcg2_ops,
 703	}
 704};
 705
 706static struct clk_rcg2 camss_gp1_clk_src = {
 707	.cmd_rcgr = 0x55000,
 708	.hid_width = 5,
 709	.mnd_width = 8,
 710	.freq_tbl = ftbl_camss_gp_clk_src,
 711	.parent_map = gcc_gp_map,
 712	.clkr.hw.init = &(struct clk_init_data) {
 713		.name = "camss_gp1_clk_src",
 714		.parent_data = gcc_gp_data,
 715		.num_parents = ARRAY_SIZE(gcc_gp_data),
 716		.ops = &clk_rcg2_ops,
 717	}
 718};
 719
 720static const struct freq_tbl ftbl_camss_top_ahb_clk_src[] = {
 721	F(40000000, P_GPLL0_DIV2, 10, 0, 0),
 722	F(80000000, P_GPLL0, 10, 0, 0),
 723	{ }
 724};
 725
 726static struct clk_rcg2 camss_top_ahb_clk_src = {
 727	.cmd_rcgr = 0x5a000,
 728	.hid_width = 5,
 729	.freq_tbl = ftbl_camss_top_ahb_clk_src,
 730	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
 731	.clkr.hw.init = &(struct clk_init_data) {
 732		.name = "camss_top_ahb_clk_src",
 733		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 734		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 735		.ops = &clk_rcg2_ops,
 736	}
 737};
 738
 739static const struct parent_map gcc_cci_map[] = {
 740	{ P_XO, 0 },
 741	{ P_GPLL0, 2 },
 742	{ P_GPLL0_DIV2, 3 },
 743	{ P_SLEEP_CLK, 6 },
 744};
 745
 746static const struct clk_parent_data gcc_cci_data[] = {
 747	{ .fw_name = "xo" },
 748	{ .hw = &gpll0.clkr.hw },
 749	{ .hw = &gpll0_early_div.hw },
 750	{ .fw_name = "sleep", .name = "sleep" },
 751};
 752
 753static const struct freq_tbl ftbl_cci_clk_src[] = {
 754	F(19200000, P_XO, 1, 0, 0),
 755	F(37500000, P_GPLL0_DIV2, 1, 3, 32),
 756	{ }
 757};
 758
 759static struct clk_rcg2 cci_clk_src = {
 760	.cmd_rcgr = 0x51000,
 761	.hid_width = 5,
 762	.mnd_width = 8,
 763	.freq_tbl = ftbl_cci_clk_src,
 764	.parent_map = gcc_cci_map,
 765	.clkr.hw.init = &(struct clk_init_data) {
 766		.name = "cci_clk_src",
 767		.parent_data = gcc_cci_data,
 768		.num_parents = ARRAY_SIZE(gcc_cci_data),
 769		.ops = &clk_rcg2_ops,
 770	}
 771};
 772
 773static const struct parent_map gcc_cpp_map[] = {
 774	{ P_XO, 0 },
 775	{ P_GPLL0, 1 },
 776	{ P_GPLL6, 3 },
 777	{ P_GPLL2, 4 },
 778	{ P_GPLL0_DIV2, 5 },
 779};
 780
 781static const struct clk_parent_data gcc_cpp_data[] = {
 782	{ .fw_name = "xo" },
 783	{ .hw = &gpll0.clkr.hw },
 784	{ .hw = &gpll6.clkr.hw },
 785	{ .hw = &gpll2.clkr.hw },
 786	{ .hw = &gpll0_early_div.hw },
 787};
 788
 789static const struct freq_tbl ftbl_cpp_clk_src[] = {
 790	F(100000000, P_GPLL0_DIV2, 4, 0, 0),
 791	F(200000000, P_GPLL0, 4, 0, 0),
 792	F(266670000, P_GPLL0, 3, 0, 0),
 793	F(320000000, P_GPLL0, 2.5, 0, 0),
 794	F(400000000, P_GPLL0, 2, 0, 0),
 795	F(465000000, P_GPLL2, 2, 0, 0),
 796	{ }
 797};
 798
 799static struct clk_rcg2 cpp_clk_src = {
 800	.cmd_rcgr = 0x58018,
 801	.hid_width = 5,
 802	.freq_tbl = ftbl_cpp_clk_src,
 803	.parent_map = gcc_cpp_map,
 804	.clkr.hw.init = &(struct clk_init_data) {
 805		.name = "cpp_clk_src",
 806		.parent_data = gcc_cpp_data,
 807		.num_parents = ARRAY_SIZE(gcc_cpp_data),
 808		.ops = &clk_rcg2_ops,
 809	}
 810};
 811
 812static const struct freq_tbl ftbl_crypto_clk_src[] = {
 813	F(40000000, P_GPLL0_DIV2, 10, 0, 0),
 814	F(80000000, P_GPLL0, 10, 0, 0),
 815	F(100000000, P_GPLL0, 8, 0, 0),
 816	F(160000000, P_GPLL0, 5, 0, 0),
 817	{ }
 818};
 819
 820static struct clk_rcg2 crypto_clk_src = {
 821	.cmd_rcgr = 0x16004,
 822	.hid_width = 5,
 823	.freq_tbl = ftbl_crypto_clk_src,
 824	.parent_map = gcc_xo_gpll0_gpll0div2_4_map,
 825	.clkr.hw.init = &(struct clk_init_data) {
 826		.name = "crypto_clk_src",
 827		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 828		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 829		.ops = &clk_rcg2_ops,
 830	}
 831};
 832
 833static const struct parent_map gcc_csi0_map[] = {
 834	{ P_XO, 0 },
 835	{ P_GPLL0, 1 },
 836	{ P_GPLL2, 4 },
 837	{ P_GPLL0_DIV2, 5 },
 838};
 839
 840static const struct parent_map gcc_csi12_map[] = {
 841	{ P_XO, 0 },
 842	{ P_GPLL0, 1 },
 843	{ P_GPLL2, 5 },
 844	{ P_GPLL0_DIV2, 4 },
 845};
 846
 847static const struct clk_parent_data gcc_csi_data[] = {
 848	{ .fw_name = "xo" },
 849	{ .hw = &gpll0.clkr.hw },
 850	{ .hw = &gpll2.clkr.hw },
 851	{ .hw = &gpll0_early_div.hw },
 852};
 853
 854static const struct freq_tbl ftbl_csi_clk_src[] = {
 855	F(100000000, P_GPLL0_DIV2, 4, 0, 0),
 856	F(200000000, P_GPLL0, 4, 0, 0),
 857	F(310000000, P_GPLL2, 3, 0, 0),
 858	F(400000000, P_GPLL0, 2, 0, 0),
 859	F(465000000, P_GPLL2, 2, 0, 0),
 860	{ }
 861};
 862
 863static struct clk_rcg2 csi0_clk_src = {
 864	.cmd_rcgr = 0x4e020,
 865	.hid_width = 5,
 866	.freq_tbl = ftbl_csi_clk_src,
 867	.parent_map = gcc_csi0_map,
 868	.clkr.hw.init = &(struct clk_init_data) {
 869		.name = "csi0_clk_src",
 870		.parent_data = gcc_csi_data,
 871		.num_parents = ARRAY_SIZE(gcc_csi_data),
 872		.ops = &clk_rcg2_ops,
 873	}
 874};
 875
 876static struct clk_rcg2 csi1_clk_src = {
 877	.cmd_rcgr = 0x4f020,
 878	.hid_width = 5,
 879	.freq_tbl = ftbl_csi_clk_src,
 880	.parent_map = gcc_csi12_map,
 881	.clkr.hw.init = &(struct clk_init_data) {
 882		.name = "csi1_clk_src",
 883		.parent_data = gcc_csi_data,
 884		.num_parents = ARRAY_SIZE(gcc_csi_data),
 885		.ops = &clk_rcg2_ops,
 886	}
 887};
 888
 889static struct clk_rcg2 csi2_clk_src = {
 890	.cmd_rcgr = 0x3c020,
 891	.hid_width = 5,
 892	.freq_tbl = ftbl_csi_clk_src,
 893	.parent_map = gcc_csi12_map,
 894	.clkr.hw.init = &(struct clk_init_data) {
 895		.name = "csi2_clk_src",
 896		.parent_data = gcc_csi_data,
 897		.num_parents = ARRAY_SIZE(gcc_csi_data),
 898		.ops = &clk_rcg2_ops,
 899	}
 900};
 901
 902static const struct parent_map gcc_csip_map[] = {
 903	{ P_XO, 0 },
 904	{ P_GPLL0, 1 },
 905	{ P_GPLL4, 3 },
 906	{ P_GPLL2, 4 },
 907	{ P_GPLL0_DIV2, 5 },
 908};
 909
 910static const struct clk_parent_data gcc_csip_data[] = {
 911	{ .fw_name = "xo" },
 912	{ .hw = &gpll0.clkr.hw },
 913	{ .hw = &gpll4.clkr.hw },
 914	{ .hw = &gpll2.clkr.hw },
 915	{ .hw = &gpll0_early_div.hw },
 916};
 917
 918static const struct freq_tbl ftbl_csi_p_clk_src[] = {
 919	F(66670000, P_GPLL0_DIV2, 6, 0, 0),
 920	F(133330000, P_GPLL0, 6, 0, 0),
 921	F(200000000, P_GPLL0, 4, 0, 0),
 922	F(266670000, P_GPLL0, 3, 0, 0),
 923	F(310000000, P_GPLL2, 3, 0, 0),
 924	{ }
 925};
 926
 927static struct clk_rcg2 csi0p_clk_src = {
 928	.cmd_rcgr = 0x58084,
 929	.hid_width = 5,
 930	.freq_tbl = ftbl_csi_p_clk_src,
 931	.parent_map = gcc_csip_map,
 932	.clkr.hw.init = &(struct clk_init_data) {
 933		.name = "csi0p_clk_src",
 934		.parent_data = gcc_csip_data,
 935		.num_parents = ARRAY_SIZE(gcc_csip_data),
 936		.ops = &clk_rcg2_ops,
 937	}
 938};
 939
 940static struct clk_rcg2 csi1p_clk_src = {
 941	.cmd_rcgr = 0x58094,
 942	.hid_width = 5,
 943	.freq_tbl = ftbl_csi_p_clk_src,
 944	.parent_map = gcc_csip_map,
 945	.clkr.hw.init = &(struct clk_init_data) {
 946		.name = "csi1p_clk_src",
 947		.parent_data = gcc_csip_data,
 948		.num_parents = ARRAY_SIZE(gcc_csip_data),
 949		.ops = &clk_rcg2_ops,
 950	}
 951};
 952
 953static struct clk_rcg2 csi2p_clk_src = {
 954	.cmd_rcgr = 0x580a4,
 955	.hid_width = 5,
 956	.freq_tbl = ftbl_csi_p_clk_src,
 957	.parent_map = gcc_csip_map,
 958	.clkr.hw.init = &(struct clk_init_data) {
 959		.name = "csi2p_clk_src",
 960		.parent_data = gcc_csip_data,
 961		.num_parents = ARRAY_SIZE(gcc_csip_data),
 962		.ops = &clk_rcg2_ops,
 963	}
 964};
 965
 966static const struct freq_tbl ftbl_csi_phytimer_clk_src[] = {
 967	F(100000000, P_GPLL0_DIV2, 4, 0, 0),
 968	F(200000000, P_GPLL0, 4, 0, 0),
 969	F(266670000, P_GPLL0, 3, 0, 0),
 970	{ }
 971};
 972
 973static struct clk_rcg2 csi0phytimer_clk_src = {
 974	.cmd_rcgr = 0x4e000,
 975	.hid_width = 5,
 976	.freq_tbl = ftbl_csi_phytimer_clk_src,
 977	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
 978	.clkr.hw.init = &(struct clk_init_data) {
 979		.name = "csi0phytimer_clk_src",
 980		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 981		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 982		.ops = &clk_rcg2_ops,
 983	}
 984};
 985
 986static struct clk_rcg2 csi1phytimer_clk_src = {
 987	.cmd_rcgr = 0x4f000,
 988	.hid_width = 5,
 989	.freq_tbl = ftbl_csi_phytimer_clk_src,
 990	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
 991	.clkr.hw.init = &(struct clk_init_data) {
 992		.name = "csi1phytimer_clk_src",
 993		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 994		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 995		.ops = &clk_rcg2_ops,
 996	}
 997};
 998
 999static struct clk_rcg2 csi2phytimer_clk_src = {
1000	.cmd_rcgr = 0x4f05c,
1001	.hid_width = 5,
1002	.freq_tbl = ftbl_csi_phytimer_clk_src,
1003	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
1004	.clkr.hw.init = &(struct clk_init_data) {
1005		.name = "csi2phytimer_clk_src",
1006		.parent_data = gcc_xo_gpll0_gpll0div2_data,
1007		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
1008		.ops = &clk_rcg2_ops,
1009	}
1010};
1011
1012static const struct parent_map gcc_esc_map[] = {
1013	{ P_XO, 0 },
1014	{ P_GPLL0, 3 },
1015};
1016
1017static const struct clk_parent_data gcc_esc_vsync_data[] = {
1018	{ .fw_name = "xo" },
1019	{ .hw = &gpll0.clkr.hw },
1020};
1021
1022static const struct freq_tbl ftbl_esc0_1_clk_src[] = {
1023	F(19200000, P_XO, 1, 0, 0),
1024	{ }
1025};
1026
1027static struct clk_rcg2 esc0_clk_src = {
1028	.cmd_rcgr = 0x4d05c,
1029	.hid_width = 5,
1030	.freq_tbl = ftbl_esc0_1_clk_src,
1031	.parent_map = gcc_esc_map,
1032	.clkr.hw.init = &(struct clk_init_data) {
1033		.name = "esc0_clk_src",
1034		.parent_data = gcc_esc_vsync_data,
1035		.num_parents = ARRAY_SIZE(gcc_esc_vsync_data),
1036		.ops = &clk_rcg2_ops,
1037	}
1038};
1039
1040static struct clk_rcg2 esc1_clk_src = {
1041	.cmd_rcgr = 0x4d0a8,
1042	.hid_width = 5,
1043	.freq_tbl = ftbl_esc0_1_clk_src,
1044	.parent_map = gcc_esc_map,
1045	.clkr.hw.init = &(struct clk_init_data) {
1046		.name = "esc1_clk_src",
1047		.parent_data = gcc_esc_vsync_data,
1048		.num_parents = ARRAY_SIZE(gcc_esc_vsync_data),
1049		.ops = &clk_rcg2_ops,
1050	}
1051};
1052
1053static const struct parent_map gcc_gfx3d_map[] = {
1054	{ P_XO, 0 },
1055	{ P_GPLL0, 1 },
1056	{ P_GPLL3, 2 },
1057	{ P_GPLL6, 3 },
1058	{ P_GPLL4, 4 },
1059	{ P_GPLL0_DIV2, 5 },
1060	{ P_GPLL6_DIV2, 6 },
1061};
1062
1063static const struct clk_parent_data gcc_gfx3d_data[] = {
1064	{ .fw_name = "xo" },
1065	{ .hw = &gpll0.clkr.hw },
1066	{ .hw = &gpll3.clkr.hw },
1067	{ .hw = &gpll6.clkr.hw },
1068	{ .hw = &gpll4.clkr.hw },
1069	{ .hw = &gpll0_early_div.hw },
1070	{ .hw = &gpll6_early_div.hw },
1071};
1072
1073static const struct freq_tbl ftbl_gfx3d_clk_src[] = {
1074	F(19200000, P_XO, 1, 0, 0),
1075	F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1076	F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1077	F(100000000, P_GPLL0_DIV2, 4, 0, 0),
1078	F(133330000, P_GPLL0_DIV2, 3, 0, 0),
1079	F(160000000, P_GPLL0_DIV2, 2.5, 0, 0),
1080	F(200000000, P_GPLL0_DIV2, 2, 0, 0),
1081	F(266670000, P_GPLL0, 3.0, 0, 0),
1082	F(320000000, P_GPLL0, 2.5, 0, 0),
1083	F(400000000, P_GPLL0, 2, 0, 0),
1084	F(460800000, P_GPLL4, 2.5, 0, 0),
1085	F(510000000, P_GPLL3, 2, 0, 0),
1086	F(560000000, P_GPLL3, 2, 0, 0),
1087	F(600000000, P_GPLL3, 2, 0, 0),
1088	F(650000000, P_GPLL3, 2, 0, 0),
1089	F(685000000, P_GPLL3, 2, 0, 0),
1090	F(725000000, P_GPLL3, 2, 0, 0),
1091	{ }
1092};
1093
1094static struct clk_rcg2 gfx3d_clk_src = {
1095	.cmd_rcgr = 0x59000,
1096	.hid_width = 5,
1097	.freq_tbl = ftbl_gfx3d_clk_src,
1098	.parent_map = gcc_gfx3d_map,
1099	.clkr.hw.init = &(struct clk_init_data) {
1100		.name = "gfx3d_clk_src",
1101		.parent_data = gcc_gfx3d_data,
1102		.num_parents = ARRAY_SIZE(gcc_gfx3d_data),
1103		.ops = &clk_rcg2_floor_ops,
1104		.flags = CLK_SET_RATE_PARENT,
1105	}
1106};
1107
1108static const struct freq_tbl ftbl_gp_clk_src[] = {
1109	F(19200000, P_XO, 1, 0, 0),
1110	{ }
1111};
1112
1113static struct clk_rcg2 gp1_clk_src = {
1114	.cmd_rcgr = 0x08004,
1115	.hid_width = 5,
1116	.mnd_width = 8,
1117	.freq_tbl = ftbl_gp_clk_src,
1118	.parent_map = gcc_gp_map,
1119	.clkr.hw.init = &(struct clk_init_data) {
1120		.name = "gp1_clk_src",
1121		.parent_data = gcc_gp_data,
1122		.num_parents = ARRAY_SIZE(gcc_gp_data),
1123		.ops = &clk_rcg2_ops,
1124	}
1125};
1126
1127static struct clk_rcg2 gp2_clk_src = {
1128	.cmd_rcgr = 0x09004,
1129	.hid_width = 5,
1130	.mnd_width = 8,
1131	.freq_tbl = ftbl_gp_clk_src,
1132	.parent_map = gcc_gp_map,
1133	.clkr.hw.init = &(struct clk_init_data) {
1134		.name = "gp2_clk_src",
1135		.parent_data = gcc_gp_data,
1136		.num_parents = ARRAY_SIZE(gcc_gp_data),
1137		.ops = &clk_rcg2_ops,
1138	}
1139};
1140
1141static struct clk_rcg2 gp3_clk_src = {
1142	.cmd_rcgr = 0x0a004,
1143	.hid_width = 5,
1144	.mnd_width = 8,
1145	.freq_tbl = ftbl_gp_clk_src,
1146	.parent_map = gcc_gp_map,
1147	.clkr.hw.init = &(struct clk_init_data) {
1148		.name = "gp3_clk_src",
1149		.parent_data = gcc_gp_data,
1150		.num_parents = ARRAY_SIZE(gcc_gp_data),
1151		.ops = &clk_rcg2_ops,
1152	}
1153};
1154
1155static const struct parent_map gcc_jpeg0_map[] = {
1156	{ P_XO, 0 },
1157	{ P_GPLL0, 1 },
1158	{ P_GPLL6, 2 },
1159	{ P_GPLL0_DIV2, 4 },
1160	{ P_GPLL2, 5 },
1161};
1162
1163static const struct clk_parent_data gcc_jpeg0_data[] = {
1164	{ .fw_name = "xo" },
1165	{ .hw = &gpll0.clkr.hw },
1166	{ .hw = &gpll6.clkr.hw },
1167	{ .hw = &gpll0_early_div.hw },
1168	{ .hw = &gpll2.clkr.hw },
1169};
1170
1171static const struct freq_tbl ftbl_jpeg0_clk_src[] = {
1172	F(66670000, P_GPLL0_DIV2, 6, 0, 0),
1173	F(133330000, P_GPLL0, 6, 0, 0),
1174	F(200000000, P_GPLL0, 4, 0, 0),
1175	F(266670000, P_GPLL0, 3, 0, 0),
1176	F(310000000, P_GPLL2, 3, 0, 0),
1177	F(320000000, P_GPLL0, 2.5, 0, 0),
1178	{ }
1179};
1180
1181static struct clk_rcg2 jpeg0_clk_src = {
1182	.cmd_rcgr = 0x57000,
1183	.hid_width = 5,
1184	.freq_tbl = ftbl_jpeg0_clk_src,
1185	.parent_map = gcc_jpeg0_map,
1186	.clkr.hw.init = &(struct clk_init_data) {
1187		.name = "jpeg0_clk_src",
1188		.parent_data = gcc_jpeg0_data,
1189		.num_parents = ARRAY_SIZE(gcc_jpeg0_data),
1190		.ops = &clk_rcg2_ops,
1191	}
1192};
1193
1194static const struct parent_map gcc_mclk_map[] = {
1195	{ P_XO, 0 },
1196	{ P_GPLL0, 1 },
1197	{ P_GPLL6, 2 },
1198	{ P_GPLL0_DIV2, 4 },
1199	{ P_GPLL6_DIV2, 5 },
1200	{ P_SLEEP_CLK, 6 },
1201};
1202
1203static const struct clk_parent_data gcc_mclk_data[] = {
1204	{ .fw_name = "xo" },
1205	{ .hw = &gpll0.clkr.hw },
1206	{ .hw = &gpll6.clkr.hw },
1207	{ .hw = &gpll0_early_div.hw },
1208	{ .hw = &gpll6_early_div.hw },
1209	{ .fw_name = "sleep", .name = "sleep" },
1210};
1211
1212static const struct freq_tbl ftbl_mclk_clk_src[] = {
1213	F(19200000, P_GPLL6, 5, 4, 45),
1214	F(24000000, P_GPLL6_DIV2, 1, 2, 45),
1215	F(26000000, P_GPLL0, 1, 4, 123),
1216	F(33330000, P_GPLL0_DIV2, 12, 0, 0),
1217	F(36610000, P_GPLL6, 1, 2, 59),
1218	F(66667000, P_GPLL0, 12, 0, 0),
1219	{ }
1220};
1221
1222static struct clk_rcg2 mclk0_clk_src = {
1223	.cmd_rcgr = 0x52000,
1224	.hid_width = 5,
1225	.mnd_width = 8,
1226	.freq_tbl = ftbl_mclk_clk_src,
1227	.parent_map = gcc_mclk_map,
1228	.clkr.hw.init = &(struct clk_init_data) {
1229		.name = "mclk0_clk_src",
1230		.parent_data = gcc_mclk_data,
1231		.num_parents = ARRAY_SIZE(gcc_mclk_data),
1232		.ops = &clk_rcg2_ops,
1233	}
1234};
1235
1236static struct clk_rcg2 mclk1_clk_src = {
1237	.cmd_rcgr = 0x53000,
1238	.hid_width = 5,
1239	.mnd_width = 8,
1240	.freq_tbl = ftbl_mclk_clk_src,
1241	.parent_map = gcc_mclk_map,
1242	.clkr.hw.init = &(struct clk_init_data) {
1243		.name = "mclk1_clk_src",
1244		.parent_data = gcc_mclk_data,
1245		.num_parents = ARRAY_SIZE(gcc_mclk_data),
1246		.ops = &clk_rcg2_ops,
1247	}
1248};
1249
1250static struct clk_rcg2 mclk2_clk_src = {
1251	.cmd_rcgr = 0x5c000,
1252	.hid_width = 5,
1253	.mnd_width = 8,
1254	.freq_tbl = ftbl_mclk_clk_src,
1255	.parent_map = gcc_mclk_map,
1256	.clkr.hw.init = &(struct clk_init_data) {
1257		.name = "mclk2_clk_src",
1258		.parent_data = gcc_mclk_data,
1259		.num_parents = ARRAY_SIZE(gcc_mclk_data),
1260		.ops = &clk_rcg2_ops,
1261	}
1262};
1263
1264static struct clk_rcg2 mclk3_clk_src = {
1265	.cmd_rcgr = 0x5e000,
1266	.hid_width = 5,
1267	.mnd_width = 8,
1268	.freq_tbl = ftbl_mclk_clk_src,
1269	.parent_map = gcc_mclk_map,
1270	.clkr.hw.init = &(struct clk_init_data) {
1271		.name = "mclk3_clk_src",
1272		.parent_data = gcc_mclk_data,
1273		.num_parents = ARRAY_SIZE(gcc_mclk_data),
1274		.ops = &clk_rcg2_ops,
1275	}
1276};
1277
1278static const struct parent_map gcc_mdp_map[] = {
1279	{ P_XO, 0 },
1280	{ P_GPLL0, 1 },
1281	{ P_GPLL6, 3 },
1282	{ P_GPLL0_DIV2, 4 },
1283};
1284
1285static const struct clk_parent_data gcc_mdp_data[] = {
1286	{ .fw_name = "xo" },
1287	{ .hw = &gpll0.clkr.hw },
1288	{ .hw = &gpll6.clkr.hw },
1289	{ .hw = &gpll0_early_div.hw },
1290};
1291
1292static const struct freq_tbl ftbl_mdp_clk_src[] = {
1293	F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1294	F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1295	F(160000000, P_GPLL0_DIV2, 2.5, 0, 0),
1296	F(200000000, P_GPLL0, 4, 0, 0),
1297	F(266670000, P_GPLL0, 3, 0, 0),
1298	F(320000000, P_GPLL0, 2.5, 0, 0),
1299	F(400000000, P_GPLL0, 2, 0, 0),
1300	{ }
1301};
1302
1303static struct clk_rcg2 mdp_clk_src = {
1304	.cmd_rcgr = 0x4d014,
1305	.hid_width = 5,
1306	.freq_tbl = ftbl_mdp_clk_src,
1307	.parent_map = gcc_mdp_map,
1308	.clkr.hw.init = &(struct clk_init_data) {
1309		.name = "mdp_clk_src",
1310		.parent_data = gcc_mdp_data,
1311		.num_parents = ARRAY_SIZE(gcc_mdp_data),
1312		.ops = &clk_rcg2_ops,
1313	}
1314};
1315
1316static const struct parent_map gcc_pclk0_map[] = {
1317	{ P_XO, 0 },
1318	{ P_DSI0PLL, 1 },
1319	{ P_DSI1PLL, 3 },
1320};
1321
1322static const struct parent_map gcc_pclk1_map[] = {
1323	{ P_XO, 0 },
1324	{ P_DSI0PLL, 3 },
1325	{ P_DSI1PLL, 1 },
1326};
1327
1328static const struct clk_parent_data gcc_pclk_data[] = {
1329	{ .fw_name = "xo" },
1330	{ .fw_name = "dsi0pll", .name = "dsi0pll" },
1331	{ .fw_name = "dsi1pll", .name = "dsi1pll" },
1332};
1333
1334static struct clk_rcg2 pclk0_clk_src = {
1335	.cmd_rcgr = 0x4d000,
1336	.hid_width = 5,
1337	.mnd_width = 8,
1338	.parent_map = gcc_pclk0_map,
1339	.clkr.hw.init = &(struct clk_init_data) {
1340		.name = "pclk0_clk_src",
1341		.parent_data = gcc_pclk_data,
1342		.num_parents = ARRAY_SIZE(gcc_pclk_data),
1343		.ops = &clk_pixel_ops,
1344		.flags = CLK_SET_RATE_PARENT,
1345	}
1346};
1347
1348static struct clk_rcg2 pclk1_clk_src = {
1349	.cmd_rcgr = 0x4d0b8,
1350	.hid_width = 5,
1351	.mnd_width = 8,
1352	.parent_map = gcc_pclk1_map,
1353	.clkr.hw.init = &(struct clk_init_data) {
1354		.name = "pclk1_clk_src",
1355		.parent_data = gcc_pclk_data,
1356		.num_parents = ARRAY_SIZE(gcc_pclk_data),
1357		.ops = &clk_pixel_ops,
1358		.flags = CLK_SET_RATE_PARENT,
1359	}
1360};
1361
1362static const struct freq_tbl ftbl_pdm2_clk_src[] = {
1363	F(32000000, P_GPLL0_DIV2, 12.5, 0, 0),
1364	F(64000000, P_GPLL0, 12.5, 0, 0),
1365	{ }
1366};
1367
1368static struct clk_rcg2 pdm2_clk_src = {
1369	.cmd_rcgr = 0x44010,
1370	.hid_width = 5,
1371	.freq_tbl = ftbl_pdm2_clk_src,
1372	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
1373	.clkr.hw.init = &(struct clk_init_data) {
1374		.name = "pdm2_clk_src",
1375		.parent_data = gcc_xo_gpll0_gpll0div2_data,
1376		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
1377		.ops = &clk_rcg2_ops,
1378	}
1379};
1380
1381static const struct freq_tbl ftbl_rbcpr_gfx_clk_src[] = {
1382	F(19200000, P_XO, 1, 0, 0),
1383	F(50000000, P_GPLL0, 16, 0, 0),
1384	{ }
1385};
1386
1387static struct clk_rcg2 rbcpr_gfx_clk_src = {
1388	.cmd_rcgr = 0x3a00c,
1389	.hid_width = 5,
1390	.freq_tbl = ftbl_rbcpr_gfx_clk_src,
1391	.parent_map = gcc_xo_gpll0_gpll0div2_4_map,
1392	.clkr.hw.init = &(struct clk_init_data) {
1393		.name = "rbcpr_gfx_clk_src",
1394		.parent_data = gcc_xo_gpll0_gpll0div2_data,
1395		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
1396		.ops = &clk_rcg2_ops,
1397	}
1398};
1399
1400static const struct parent_map gcc_sdcc1_ice_core_map[] = {
1401	{ P_XO, 0 },
1402	{ P_GPLL0, 1 },
1403	{ P_GPLL6, 2 },
1404	{ P_GPLL0_DIV2, 4 },
1405};
1406
1407static const struct clk_parent_data gcc_sdcc1_ice_core_data[] = {
1408	{ .fw_name = "xo" },
1409	{ .hw = &gpll0.clkr.hw },
1410	{ .hw = &gpll6.clkr.hw },
1411	{ .hw = &gpll0_early_div.hw },
1412};
1413
1414static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
1415	F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1416	F(160000000, P_GPLL0, 5, 0, 0),
1417	F(270000000, P_GPLL6, 4, 0, 0),
1418	{ }
1419};
1420
1421static struct clk_rcg2 sdcc1_ice_core_clk_src = {
1422	.cmd_rcgr = 0x5d000,
1423	.hid_width = 5,
1424	.freq_tbl = ftbl_sdcc1_ice_core_clk_src,
1425	.parent_map = gcc_sdcc1_ice_core_map,
1426	.clkr.hw.init = &(struct clk_init_data) {
1427		.name = "sdcc1_ice_core_clk_src",
1428		.parent_data = gcc_sdcc1_ice_core_data,
1429		.num_parents = ARRAY_SIZE(gcc_sdcc1_ice_core_data),
1430		.ops = &clk_rcg2_ops,
1431	}
1432};
1433
1434static const struct parent_map gcc_sdcc_apps_map[] = {
1435	{ P_XO, 0 },
1436	{ P_GPLL0, 1 },
1437	{ P_GPLL4, 2 },
1438	{ P_GPLL0_DIV2, 4 },
1439};
1440
1441static const struct clk_parent_data gcc_sdcc_apss_data[] = {
1442	{ .fw_name = "xo" },
1443	{ .hw = &gpll0.clkr.hw },
1444	{ .hw = &gpll4.clkr.hw },
1445	{ .hw = &gpll0_early_div.hw },
1446};
1447
1448static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
1449	F(144000, P_XO, 16, 3, 25),
1450	F(400000, P_XO, 12, 1, 4),
1451	F(20000000, P_GPLL0_DIV2, 5, 1, 4),
1452	F(25000000, P_GPLL0_DIV2, 16, 0, 0),
1453	F(50000000, P_GPLL0, 16, 0, 0),
1454	F(100000000, P_GPLL0, 8, 0, 0),
1455	F(177770000, P_GPLL0, 4.5, 0, 0),
1456	F(192000000, P_GPLL4, 6, 0, 0),
1457	F(384000000, P_GPLL4, 3, 0, 0),
1458	{ }
1459};
1460
1461static struct clk_rcg2 sdcc1_apps_clk_src = {
1462	.cmd_rcgr = 0x42004,
1463	.hid_width = 5,
1464	.mnd_width = 8,
1465	.freq_tbl = ftbl_sdcc1_apps_clk_src,
1466	.parent_map = gcc_sdcc_apps_map,
1467	.clkr.hw.init = &(struct clk_init_data) {
1468		.name = "sdcc1_apps_clk_src",
1469		.parent_data = gcc_sdcc_apss_data,
1470		.num_parents = ARRAY_SIZE(gcc_sdcc_apss_data),
1471		.ops = &clk_rcg2_floor_ops,
1472	}
1473};
1474
1475static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
1476	F(144000, P_XO, 16, 3, 25),
1477	F(400000, P_XO, 12, 1, 4),
1478	F(20000000, P_GPLL0_DIV2, 5, 1, 4),
1479	F(25000000, P_GPLL0_DIV2, 16, 0, 0),
1480	F(50000000, P_GPLL0, 16, 0, 0),
1481	F(100000000, P_GPLL0, 8, 0, 0),
1482	F(177770000, P_GPLL0, 4.5, 0, 0),
1483	F(192000000, P_GPLL4, 6, 0, 0),
1484	F(200000000, P_GPLL0, 4, 0, 0),
1485	{ }
1486};
1487
1488static struct clk_rcg2 sdcc2_apps_clk_src = {
1489	.cmd_rcgr = 0x43004,
1490	.hid_width = 5,
1491	.mnd_width = 8,
1492	.freq_tbl = ftbl_sdcc2_apps_clk_src,
1493	.parent_map = gcc_sdcc_apps_map,
1494	.clkr.hw.init = &(struct clk_init_data) {
1495		.name = "sdcc2_apps_clk_src",
1496		.parent_data = gcc_sdcc_apss_data,
1497		.num_parents = ARRAY_SIZE(gcc_sdcc_apss_data),
1498		.ops = &clk_rcg2_floor_ops,
1499	}
1500};
1501
1502static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
1503	F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1504	F(100000000, P_GPLL0, 8, 0, 0),
1505	F(133330000, P_GPLL0, 6, 0, 0),
1506	{ }
1507};
1508
1509static struct clk_rcg2 usb30_master_clk_src = {
1510	.cmd_rcgr = 0x3f00c,
1511	.hid_width = 5,
1512	.freq_tbl = ftbl_usb30_master_clk_src,
1513	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
1514	.clkr.hw.init = &(struct clk_init_data) {
1515		.name = "usb30_master_clk_src",
1516		.parent_data = gcc_xo_gpll0_gpll0div2_data,
1517		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
1518		.ops = &clk_rcg2_ops,
1519	}
1520};
1521
1522static const struct parent_map gcc_usb30_mock_utmi_map[] = {
1523	{ P_XO, 0 },
1524	{ P_GPLL6, 1 },
1525	{ P_GPLL6_DIV2, 2 },
1526	{ P_GPLL0, 3 },
1527	{ P_GPLL0_DIV2, 4 },
1528};
1529
1530static const struct clk_parent_data gcc_usb30_mock_utmi_data[] = {
1531	{ .fw_name = "xo" },
1532	{ .hw = &gpll6.clkr.hw },
1533	{ .hw = &gpll6_early_div.hw },
1534	{ .hw = &gpll0.clkr.hw },
1535	{ .hw = &gpll0_early_div.hw },
1536};
1537
1538static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
1539	F(19200000, P_XO, 1, 0, 0),
1540	F(60000000, P_GPLL6_DIV2, 9, 1, 1),
1541	{ }
1542};
1543
1544static struct clk_rcg2 usb30_mock_utmi_clk_src = {
1545	.cmd_rcgr = 0x3f020,
1546	.hid_width = 5,
1547	.mnd_width = 8,
1548	.freq_tbl = ftbl_usb30_mock_utmi_clk_src,
1549	.parent_map = gcc_usb30_mock_utmi_map,
1550	.clkr.hw.init = &(struct clk_init_data) {
1551		.name = "usb30_mock_utmi_clk_src",
1552		.parent_data = gcc_usb30_mock_utmi_data,
1553		.num_parents = ARRAY_SIZE(gcc_usb30_mock_utmi_data),
1554		.ops = &clk_rcg2_ops,
1555	}
1556};
1557
1558static const struct parent_map gcc_usb3_aux_map[] = {
1559	{ P_XO, 0 },
1560	{ P_SLEEP_CLK, 6 },
1561};
1562
1563static const struct clk_parent_data gcc_usb3_aux_data[] = {
1564	{ .fw_name = "xo" },
1565	{ .fw_name = "sleep", .name = "sleep" },
1566};
1567
1568static const struct freq_tbl ftbl_usb3_aux_clk_src[] = {
1569	F(19200000, P_XO, 1, 0, 0),
1570	{ }
1571};
1572
1573static struct clk_rcg2 usb3_aux_clk_src = {
1574	.cmd_rcgr = 0x3f05c,
1575	.hid_width = 5,
1576	.mnd_width = 8,
1577	.freq_tbl = ftbl_usb3_aux_clk_src,
1578	.parent_map = gcc_usb3_aux_map,
1579	.clkr.hw.init = &(struct clk_init_data) {
1580		.name = "usb3_aux_clk_src",
1581		.parent_data = gcc_usb3_aux_data,
1582		.num_parents = ARRAY_SIZE(gcc_usb3_aux_data),
1583		.ops = &clk_rcg2_ops,
1584	}
1585};
1586
1587static const struct parent_map gcc_vcodec0_map[] = {
1588	{ P_XO, 0 },
1589	{ P_GPLL0, 1 },
1590	{ P_GPLL6, 2 },
1591	{ P_GPLL2, 3 },
1592	{ P_GPLL0_DIV2, 4 },
1593};
1594
1595static const struct clk_parent_data gcc_vcodec0_data[] = {
1596	{ .fw_name = "xo" },
1597	{ .hw = &gpll0.clkr.hw },
1598	{ .hw = &gpll6.clkr.hw },
1599	{ .hw = &gpll2.clkr.hw },
1600	{ .hw = &gpll0_early_div.hw },
1601};
1602
1603static const struct freq_tbl ftbl_vcodec0_clk_src[] = {
1604	F(114290000, P_GPLL0_DIV2, 3.5, 0, 0),
1605	F(228570000, P_GPLL0, 3.5, 0, 0),
1606	F(310000000, P_GPLL2, 3, 0, 0),
1607	F(360000000, P_GPLL6, 3, 0, 0),
1608	F(400000000, P_GPLL0, 2, 0, 0),
1609	F(465000000, P_GPLL2, 2, 0, 0),
1610	F(540000000, P_GPLL6, 2, 0, 0),
1611	{ }
1612};
1613
1614static struct clk_rcg2 vcodec0_clk_src = {
1615	.cmd_rcgr = 0x4c000,
1616	.hid_width = 5,
1617	.freq_tbl = ftbl_vcodec0_clk_src,
1618	.parent_map = gcc_vcodec0_map,
1619	.clkr.hw.init = &(struct clk_init_data) {
1620		.name = "vcodec0_clk_src",
1621		.parent_data = gcc_vcodec0_data,
1622		.num_parents = ARRAY_SIZE(gcc_vcodec0_data),
1623		.ops = &clk_rcg2_ops,
1624	}
1625};
1626
1627static const struct parent_map gcc_vfe_map[] = {
1628	{ P_XO, 0 },
1629	{ P_GPLL0, 1 },
1630	{ P_GPLL6, 2 },
1631	{ P_GPLL4, 3 },
1632	{ P_GPLL2, 4 },
1633	{ P_GPLL0_DIV2, 5 },
1634};
1635
1636static const struct clk_parent_data gcc_vfe_data[] = {
1637	{ .fw_name = "xo" },
1638	{ .hw = &gpll0.clkr.hw },
1639	{ .hw = &gpll6.clkr.hw },
1640	{ .hw = &gpll4.clkr.hw },
1641	{ .hw = &gpll2.clkr.hw },
1642	{ .hw = &gpll0_early_div.hw },
1643};
1644
1645static const struct freq_tbl ftbl_vfe_clk_src[] = {
1646	F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1647	F(100000000, P_GPLL0_DIV2, 4, 0, 0),
1648	F(133330000, P_GPLL0, 6, 0, 0),
1649	F(160000000, P_GPLL0, 5, 0, 0),
1650	F(200000000, P_GPLL0, 4, 0, 0),
1651	F(266670000, P_GPLL0, 3, 0, 0),
1652	F(310000000, P_GPLL2, 3, 0, 0),
1653	F(400000000, P_GPLL0, 2, 0, 0),
1654	F(465000000, P_GPLL2, 2, 0, 0),
1655	{ }
1656};
1657
1658static struct clk_rcg2 vfe0_clk_src = {
1659	.cmd_rcgr = 0x58000,
1660	.hid_width = 5,
1661	.freq_tbl = ftbl_vfe_clk_src,
1662	.parent_map = gcc_vfe_map,
1663	.clkr.hw.init = &(struct clk_init_data) {
1664		.name = "vfe0_clk_src",
1665		.parent_data = gcc_vfe_data,
1666		.num_parents = ARRAY_SIZE(gcc_vfe_data),
1667		.ops = &clk_rcg2_ops,
1668	}
1669};
1670
1671static struct clk_rcg2 vfe1_clk_src = {
1672	.cmd_rcgr = 0x58054,
1673	.hid_width = 5,
1674	.freq_tbl = ftbl_vfe_clk_src,
1675	.parent_map = gcc_vfe_map,
1676	.clkr.hw.init = &(struct clk_init_data) {
1677		.name = "vfe1_clk_src",
1678		.parent_data = gcc_vfe_data,
1679		.num_parents = ARRAY_SIZE(gcc_vfe_data),
1680		.ops = &clk_rcg2_ops,
1681	}
1682};
1683
1684static const struct parent_map gcc_vsync_map[] = {
1685	{ P_XO, 0 },
1686	{ P_GPLL0, 2 },
1687};
1688
1689static const struct freq_tbl ftbl_vsync_clk_src[] = {
1690	F(19200000, P_XO, 1, 0, 0),
1691	{ }
1692};
1693
1694static struct clk_rcg2 vsync_clk_src = {
1695	.cmd_rcgr = 0x4d02c,
1696	.hid_width = 5,
1697	.freq_tbl = ftbl_vsync_clk_src,
1698	.parent_map = gcc_vsync_map,
1699	.clkr.hw.init = &(struct clk_init_data) {
1700		.name = "vsync_clk_src",
1701		.parent_data = gcc_esc_vsync_data,
1702		.num_parents = ARRAY_SIZE(gcc_esc_vsync_data),
1703		.ops = &clk_rcg2_ops,
1704	}
1705};
1706
1707static struct clk_branch gcc_apc0_droop_detector_gpll0_clk = {
1708	.halt_reg = 0x78004,
1709	.halt_check = BRANCH_HALT,
1710	.clkr = {
1711		.enable_reg = 0x78004,
1712		.enable_mask = BIT(0),
1713		.hw.init = &(struct clk_init_data) {
1714			.name = "gcc_apc0_droop_detector_gpll0_clk",
1715			.parent_hws = (const struct clk_hw*[]){
1716				&apc0_droop_detector_clk_src.clkr.hw,
1717			},
1718			.num_parents = 1,
1719			.ops = &clk_branch2_ops,
1720			.flags = CLK_SET_RATE_PARENT,
1721		}
1722	}
1723};
1724
1725static struct clk_branch gcc_apc1_droop_detector_gpll0_clk = {
1726	.halt_reg = 0x79004,
1727	.halt_check = BRANCH_HALT,
1728	.clkr = {
1729		.enable_reg = 0x79004,
1730		.enable_mask = BIT(0),
1731		.hw.init = &(struct clk_init_data) {
1732			.name = "gcc_apc1_droop_detector_gpll0_clk",
1733			.parent_hws = (const struct clk_hw*[]){
1734				&apc1_droop_detector_clk_src.clkr.hw,
1735			},
1736			.num_parents = 1,
1737			.ops = &clk_branch2_ops,
1738			.flags = CLK_SET_RATE_PARENT,
1739		}
1740	}
1741};
1742
1743static struct clk_branch gcc_apss_ahb_clk = {
1744	.halt_reg = 0x4601c,
1745	.halt_check = BRANCH_HALT_VOTED,
1746	.clkr = {
1747		.enable_reg = 0x45004,
1748		.enable_mask = BIT(14),
1749		.hw.init = &(struct clk_init_data) {
1750			.name = "gcc_apss_ahb_clk",
1751			.parent_hws = (const struct clk_hw*[]){
1752				&apss_ahb_clk_src.clkr.hw,
1753			},
1754			.num_parents = 1,
1755			.ops = &clk_branch2_ops,
1756			.flags = CLK_SET_RATE_PARENT,
1757		}
1758	}
1759};
1760
1761static struct clk_branch gcc_apss_axi_clk = {
1762	.halt_reg = 0x46020,
1763	.halt_check = BRANCH_HALT_VOTED,
1764	.clkr = {
1765		.enable_reg = 0x45004,
1766		.enable_mask = BIT(13),
1767		.hw.init = &(struct clk_init_data) {
1768			.name = "gcc_apss_axi_clk",
1769			.ops = &clk_branch2_ops,
1770		}
1771	}
1772};
1773
1774static struct clk_branch gcc_apss_tcu_async_clk = {
1775	.halt_reg = 0x12018,
1776	.halt_check = BRANCH_HALT_VOTED,
1777	.clkr = {
1778		.enable_reg = 0x4500c,
1779		.enable_mask = BIT(1),
1780		.hw.init = &(struct clk_init_data) {
1781			.name = "gcc_apss_tcu_async_clk",
1782			.ops = &clk_branch2_ops,
1783		}
1784	}
1785};
1786
1787static struct clk_branch gcc_bimc_gfx_clk = {
1788	.halt_reg = 0x59034,
1789	.halt_check = BRANCH_HALT,
1790	.clkr = {
1791		.enable_reg = 0x59034,
1792		.enable_mask = BIT(0),
1793		.hw.init = &(struct clk_init_data) {
1794			.name = "gcc_bimc_gfx_clk",
1795			.ops = &clk_branch2_ops,
1796		}
1797	}
1798};
1799
1800static struct clk_branch gcc_bimc_gpu_clk = {
1801	.halt_reg = 0x59030,
1802	.halt_check = BRANCH_HALT,
1803	.clkr = {
1804		.enable_reg = 0x59030,
1805		.enable_mask = BIT(0),
1806		.hw.init = &(struct clk_init_data) {
1807			.name = "gcc_bimc_gpu_clk",
1808			.ops = &clk_branch2_ops,
1809		}
1810	}
1811};
1812
1813static struct clk_branch gcc_blsp1_ahb_clk = {
1814	.halt_reg = 0x01008,
1815	.halt_check = BRANCH_HALT_VOTED,
1816	.clkr = {
1817		.enable_reg = 0x45004,
1818		.enable_mask = BIT(10),
1819		.hw.init = &(struct clk_init_data) {
1820			.name = "gcc_blsp1_ahb_clk",
1821			.ops = &clk_branch2_ops,
1822		}
1823	}
1824};
1825
1826static struct clk_branch gcc_blsp2_ahb_clk = {
1827	.halt_reg = 0x0b008,
1828	.halt_check = BRANCH_HALT_VOTED,
1829	.clkr = {
1830		.enable_reg = 0x45004,
1831		.enable_mask = BIT(20),
1832		.hw.init = &(struct clk_init_data) {
1833			.name = "gcc_blsp2_ahb_clk",
1834			.ops = &clk_branch2_ops,
1835		}
1836	}
1837};
1838
1839static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1840	.halt_reg = 0x02008,
1841	.halt_check = BRANCH_HALT,
1842	.clkr = {
1843		.enable_reg = 0x02008,
1844		.enable_mask = BIT(0),
1845		.hw.init = &(struct clk_init_data) {
1846			.name = "gcc_blsp1_qup1_i2c_apps_clk",
1847			.parent_hws = (const struct clk_hw*[]){
1848				&blsp1_qup1_i2c_apps_clk_src.clkr.hw,
1849			},
1850			.num_parents = 1,
1851			.ops = &clk_branch2_ops,
1852			.flags = CLK_SET_RATE_PARENT,
1853		}
1854	}
1855};
1856
1857static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1858	.halt_reg = 0x03010,
1859	.halt_check = BRANCH_HALT,
1860	.clkr = {
1861		.enable_reg = 0x03010,
1862		.enable_mask = BIT(0),
1863		.hw.init = &(struct clk_init_data) {
1864			.name = "gcc_blsp1_qup2_i2c_apps_clk",
1865			.parent_hws = (const struct clk_hw*[]){
1866				&blsp1_qup2_i2c_apps_clk_src.clkr.hw,
1867			},
1868			.num_parents = 1,
1869			.ops = &clk_branch2_ops,
1870			.flags = CLK_SET_RATE_PARENT,
1871		}
1872	}
1873};
1874
1875static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1876	.halt_reg = 0x04020,
1877	.halt_check = BRANCH_HALT,
1878	.clkr = {
1879		.enable_reg = 0x04020,
1880		.enable_mask = BIT(0),
1881		.hw.init = &(struct clk_init_data) {
1882			.name = "gcc_blsp1_qup3_i2c_apps_clk",
1883			.parent_hws = (const struct clk_hw*[]){
1884				&blsp1_qup3_i2c_apps_clk_src.clkr.hw,
1885			},
1886			.num_parents = 1,
1887			.ops = &clk_branch2_ops,
1888			.flags = CLK_SET_RATE_PARENT,
1889		}
1890	}
1891};
1892
1893static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1894	.halt_reg = 0x05020,
1895	.halt_check = BRANCH_HALT,
1896	.clkr = {
1897		.enable_reg = 0x05020,
1898		.enable_mask = BIT(0),
1899		.hw.init = &(struct clk_init_data) {
1900			.name = "gcc_blsp1_qup4_i2c_apps_clk",
1901			.parent_hws = (const struct clk_hw*[]){
1902				&blsp1_qup4_i2c_apps_clk_src.clkr.hw,
1903			},
1904			.num_parents = 1,
1905			.ops = &clk_branch2_ops,
1906			.flags = CLK_SET_RATE_PARENT,
1907		}
1908	}
1909};
1910
1911static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1912	.halt_reg = 0x0c008,
1913	.halt_check = BRANCH_HALT,
1914	.clkr = {
1915		.enable_reg = 0x0c008,
1916		.enable_mask = BIT(0),
1917		.hw.init = &(struct clk_init_data) {
1918			.name = "gcc_blsp2_qup1_i2c_apps_clk",
1919			.parent_hws = (const struct clk_hw*[]){
1920				&blsp2_qup1_i2c_apps_clk_src.clkr.hw,
1921			},
1922			.num_parents = 1,
1923			.ops = &clk_branch2_ops,
1924			.flags = CLK_SET_RATE_PARENT,
1925		}
1926	}
1927};
1928
1929static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1930	.halt_reg = 0x0d010,
1931	.halt_check = BRANCH_HALT,
1932	.clkr = {
1933		.enable_reg = 0x0d010,
1934		.enable_mask = BIT(0),
1935		.hw.init = &(struct clk_init_data) {
1936			.name = "gcc_blsp2_qup2_i2c_apps_clk",
1937			.parent_hws = (const struct clk_hw*[]){
1938				&blsp2_qup2_i2c_apps_clk_src.clkr.hw,
1939			},
1940			.num_parents = 1,
1941			.ops = &clk_branch2_ops,
1942			.flags = CLK_SET_RATE_PARENT,
1943		}
1944	}
1945};
1946
1947static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1948	.halt_reg = 0x0f020,
1949	.halt_check = BRANCH_HALT,
1950	.clkr = {
1951		.enable_reg = 0x0f020,
1952		.enable_mask = BIT(0),
1953		.hw.init = &(struct clk_init_data) {
1954			.name = "gcc_blsp2_qup3_i2c_apps_clk",
1955			.parent_hws = (const struct clk_hw*[]){
1956				&blsp2_qup3_i2c_apps_clk_src.clkr.hw,
1957			},
1958			.num_parents = 1,
1959			.ops = &clk_branch2_ops,
1960			.flags = CLK_SET_RATE_PARENT,
1961		}
1962	}
1963};
1964
1965static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1966	.halt_reg = 0x18020,
1967	.halt_check = BRANCH_HALT,
1968	.clkr = {
1969		.enable_reg = 0x18020,
1970		.enable_mask = BIT(0),
1971		.hw.init = &(struct clk_init_data) {
1972			.name = "gcc_blsp2_qup4_i2c_apps_clk",
1973			.parent_hws = (const struct clk_hw*[]){
1974				&blsp2_qup4_i2c_apps_clk_src.clkr.hw,
1975			},
1976			.num_parents = 1,
1977			.ops = &clk_branch2_ops,
1978			.flags = CLK_SET_RATE_PARENT,
1979		}
1980	}
1981};
1982
1983static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1984	.halt_reg = 0x02004,
1985	.halt_check = BRANCH_HALT,
1986	.clkr = {
1987		.enable_reg = 0x02004,
1988		.enable_mask = BIT(0),
1989		.hw.init = &(struct clk_init_data) {
1990			.name = "gcc_blsp1_qup1_spi_apps_clk",
1991			.parent_hws = (const struct clk_hw*[]){
1992				&blsp1_qup1_spi_apps_clk_src.clkr.hw,
1993			},
1994			.num_parents = 1,
1995			.ops = &clk_branch2_ops,
1996			.flags = CLK_SET_RATE_PARENT,
1997		}
1998	}
1999};
2000
2001static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
2002	.halt_reg = 0x0300c,
2003	.halt_check = BRANCH_HALT,
2004	.clkr = {
2005		.enable_reg = 0x0300c,
2006		.enable_mask = BIT(0),
2007		.hw.init = &(struct clk_init_data) {
2008			.name = "gcc_blsp1_qup2_spi_apps_clk",
2009			.parent_hws = (const struct clk_hw*[]){
2010				&blsp1_qup2_spi_apps_clk_src.clkr.hw,
2011			},
2012			.num_parents = 1,
2013			.ops = &clk_branch2_ops,
2014			.flags = CLK_SET_RATE_PARENT,
2015		}
2016	}
2017};
2018
2019static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
2020	.halt_reg = 0x0401c,
2021	.halt_check = BRANCH_HALT,
2022	.clkr = {
2023		.enable_reg = 0x0401c,
2024		.enable_mask = BIT(0),
2025		.hw.init = &(struct clk_init_data) {
2026			.name = "gcc_blsp1_qup3_spi_apps_clk",
2027			.parent_hws = (const struct clk_hw*[]){
2028				&blsp1_qup3_spi_apps_clk_src.clkr.hw,
2029			},
2030			.num_parents = 1,
2031			.ops = &clk_branch2_ops,
2032			.flags = CLK_SET_RATE_PARENT,
2033		}
2034	}
2035};
2036
2037static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
2038	.halt_reg = 0x0501c,
2039	.halt_check = BRANCH_HALT,
2040	.clkr = {
2041		.enable_reg = 0x0501c,
2042		.enable_mask = BIT(0),
2043		.hw.init = &(struct clk_init_data) {
2044			.name = "gcc_blsp1_qup4_spi_apps_clk",
2045			.parent_hws = (const struct clk_hw*[]){
2046				&blsp1_qup4_spi_apps_clk_src.clkr.hw,
2047			},
2048			.num_parents = 1,
2049			.ops = &clk_branch2_ops,
2050			.flags = CLK_SET_RATE_PARENT,
2051		}
2052	}
2053};
2054
2055static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
2056	.halt_reg = 0x0c004,
2057	.halt_check = BRANCH_HALT,
2058	.clkr = {
2059		.enable_reg = 0x0c004,
2060		.enable_mask = BIT(0),
2061		.hw.init = &(struct clk_init_data) {
2062			.name = "gcc_blsp2_qup1_spi_apps_clk",
2063			.parent_hws = (const struct clk_hw*[]){
2064				&blsp2_qup1_spi_apps_clk_src.clkr.hw,
2065			},
2066			.num_parents = 1,
2067			.ops = &clk_branch2_ops,
2068			.flags = CLK_SET_RATE_PARENT,
2069		}
2070	}
2071};
2072
2073static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
2074	.halt_reg = 0x0d00c,
2075	.halt_check = BRANCH_HALT,
2076	.clkr = {
2077		.enable_reg = 0x0d00c,
2078		.enable_mask = BIT(0),
2079		.hw.init = &(struct clk_init_data) {
2080			.name = "gcc_blsp2_qup2_spi_apps_clk",
2081			.parent_hws = (const struct clk_hw*[]){
2082				&blsp2_qup2_spi_apps_clk_src.clkr.hw,
2083			},
2084			.num_parents = 1,
2085			.ops = &clk_branch2_ops,
2086			.flags = CLK_SET_RATE_PARENT,
2087		}
2088	}
2089};
2090
2091static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
2092	.halt_reg = 0x0f01c,
2093	.halt_check = BRANCH_HALT,
2094	.clkr = {
2095		.enable_reg = 0x0f01c,
2096		.enable_mask = BIT(0),
2097		.hw.init = &(struct clk_init_data) {
2098			.name = "gcc_blsp2_qup3_spi_apps_clk",
2099			.parent_hws = (const struct clk_hw*[]){
2100				&blsp2_qup3_spi_apps_clk_src.clkr.hw,
2101			},
2102			.num_parents = 1,
2103			.ops = &clk_branch2_ops,
2104			.flags = CLK_SET_RATE_PARENT,
2105		}
2106	}
2107};
2108
2109static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
2110	.halt_reg = 0x1801c,
2111	.halt_check = BRANCH_HALT,
2112	.clkr = {
2113		.enable_reg = 0x1801c,
2114		.enable_mask = BIT(0),
2115		.hw.init = &(struct clk_init_data) {
2116			.name = "gcc_blsp2_qup4_spi_apps_clk",
2117			.parent_hws = (const struct clk_hw*[]){
2118				&blsp2_qup4_spi_apps_clk_src.clkr.hw,
2119			},
2120			.num_parents = 1,
2121			.ops = &clk_branch2_ops,
2122			.flags = CLK_SET_RATE_PARENT,
2123		}
2124	}
2125};
2126
2127static struct clk_branch gcc_blsp1_uart1_apps_clk = {
2128	.halt_reg = 0x0203c,
2129	.halt_check = BRANCH_HALT,
2130	.clkr = {
2131		.enable_reg = 0x0203c,
2132		.enable_mask = BIT(0),
2133		.hw.init = &(struct clk_init_data) {
2134			.name = "gcc_blsp1_uart1_apps_clk",
2135			.parent_hws = (const struct clk_hw*[]){
2136				&blsp1_uart1_apps_clk_src.clkr.hw,
2137			},
2138			.num_parents = 1,
2139			.ops = &clk_branch2_ops,
2140			.flags = CLK_SET_RATE_PARENT,
2141		}
2142	}
2143};
2144
2145static struct clk_branch gcc_blsp1_uart2_apps_clk = {
2146	.halt_reg = 0x0302c,
2147	.halt_check = BRANCH_HALT,
2148	.clkr = {
2149		.enable_reg = 0x0302c,
2150		.enable_mask = BIT(0),
2151		.hw.init = &(struct clk_init_data) {
2152			.name = "gcc_blsp1_uart2_apps_clk",
2153			.parent_hws = (const struct clk_hw*[]){
2154				&blsp1_uart2_apps_clk_src.clkr.hw,
2155			},
2156			.num_parents = 1,
2157			.ops = &clk_branch2_ops,
2158			.flags = CLK_SET_RATE_PARENT,
2159		}
2160	}
2161};
2162
2163static struct clk_branch gcc_blsp2_uart1_apps_clk = {
2164	.halt_reg = 0x0c03c,
2165	.halt_check = BRANCH_HALT,
2166	.clkr = {
2167		.enable_reg = 0x0c03c,
2168		.enable_mask = BIT(0),
2169		.hw.init = &(struct clk_init_data) {
2170			.name = "gcc_blsp2_uart1_apps_clk",
2171			.parent_hws = (const struct clk_hw*[]){
2172				&blsp2_uart1_apps_clk_src.clkr.hw,
2173			},
2174			.num_parents = 1,
2175			.ops = &clk_branch2_ops,
2176			.flags = CLK_SET_RATE_PARENT,
2177		}
2178	}
2179};
2180
2181static struct clk_branch gcc_blsp2_uart2_apps_clk = {
2182	.halt_reg = 0x0d02c,
2183	.halt_check = BRANCH_HALT,
2184	.clkr = {
2185		.enable_reg = 0x0d02c,
2186		.enable_mask = BIT(0),
2187		.hw.init = &(struct clk_init_data) {
2188			.name = "gcc_blsp2_uart2_apps_clk",
2189			.parent_hws = (const struct clk_hw*[]){
2190				&blsp2_uart2_apps_clk_src.clkr.hw,
2191			},
2192			.num_parents = 1,
2193			.ops = &clk_branch2_ops,
2194			.flags = CLK_SET_RATE_PARENT,
2195		}
2196	}
2197};
2198
2199static struct clk_branch gcc_boot_rom_ahb_clk = {
2200	.halt_reg = 0x1300c,
2201	.halt_check = BRANCH_HALT_VOTED,
2202	.clkr = {
2203		.enable_reg = 0x45004,
2204		.enable_mask = BIT(7),
2205		.hw.init = &(struct clk_init_data) {
2206			.name = "gcc_boot_rom_ahb_clk",
2207			.ops = &clk_branch2_ops,
2208		}
2209	}
2210};
2211
2212static struct clk_branch gcc_camss_ahb_clk = {
2213	.halt_reg = 0x56004,
2214	.halt_check = BRANCH_HALT,
2215	.clkr = {
2216		.enable_reg = 0x56004,
2217		.enable_mask = BIT(0),
2218		.hw.init = &(struct clk_init_data) {
2219			.name = "gcc_camss_ahb_clk",
2220			.ops = &clk_branch2_ops,
2221		}
2222	}
2223};
2224
2225static struct clk_branch gcc_camss_cci_ahb_clk = {
2226	.halt_reg = 0x5101c,
2227	.halt_check = BRANCH_HALT,
2228	.clkr = {
2229		.enable_reg = 0x5101c,
2230		.enable_mask = BIT(0),
2231		.hw.init = &(struct clk_init_data) {
2232			.name = "gcc_camss_cci_ahb_clk",
2233			.parent_hws = (const struct clk_hw*[]){
2234				&camss_top_ahb_clk_src.clkr.hw,
2235			},
2236			.num_parents = 1,
2237			.ops = &clk_branch2_ops,
2238			.flags = CLK_SET_RATE_PARENT,
2239		}
2240	}
2241};
2242
2243static struct clk_branch gcc_camss_cci_clk = {
2244	.halt_reg = 0x51018,
2245	.halt_check = BRANCH_HALT,
2246	.clkr = {
2247		.enable_reg = 0x51018,
2248		.enable_mask = BIT(0),
2249		.hw.init = &(struct clk_init_data) {
2250			.name = "gcc_camss_cci_clk",
2251			.parent_hws = (const struct clk_hw*[]){
2252				&cci_clk_src.clkr.hw,
2253			},
2254			.num_parents = 1,
2255			.ops = &clk_branch2_ops,
2256			.flags = CLK_SET_RATE_PARENT,
2257		}
2258	}
2259};
2260
2261static struct clk_branch gcc_camss_cpp_ahb_clk = {
2262	.halt_reg = 0x58040,
2263	.halt_check = BRANCH_HALT,
2264	.clkr = {
2265		.enable_reg = 0x58040,
2266		.enable_mask = BIT(0),
2267		.hw.init = &(struct clk_init_data) {
2268			.name = "gcc_camss_cpp_ahb_clk",
2269			.parent_hws = (const struct clk_hw*[]){
2270				&camss_top_ahb_clk_src.clkr.hw,
2271			},
2272			.num_parents = 1,
2273			.ops = &clk_branch2_ops,
2274			.flags = CLK_SET_RATE_PARENT,
2275		}
2276	}
2277};
2278
2279static struct clk_branch gcc_camss_cpp_axi_clk = {
2280	.halt_reg = 0x58064,
2281	.halt_check = BRANCH_HALT,
2282	.clkr = {
2283		.enable_reg = 0x58064,
2284		.enable_mask = BIT(0),
2285		.hw.init = &(struct clk_init_data) {
2286			.name = "gcc_camss_cpp_axi_clk",
2287			.ops = &clk_branch2_ops,
2288		}
2289	}
2290};
2291
2292static struct clk_branch gcc_camss_cpp_clk = {
2293	.halt_reg = 0x5803c,
2294	.halt_check = BRANCH_HALT,
2295	.clkr = {
2296		.enable_reg = 0x5803c,
2297		.enable_mask = BIT(0),
2298		.hw.init = &(struct clk_init_data) {
2299			.name = "gcc_camss_cpp_clk",
2300			.parent_hws = (const struct clk_hw*[]){
2301				&cpp_clk_src.clkr.hw,
2302			},
2303			.num_parents = 1,
2304			.ops = &clk_branch2_ops,
2305			.flags = CLK_SET_RATE_PARENT,
2306		}
2307	}
2308};
2309
2310static struct clk_branch gcc_camss_csi0_ahb_clk = {
2311	.halt_reg = 0x4e040,
2312	.halt_check = BRANCH_HALT,
2313	.clkr = {
2314		.enable_reg = 0x4e040,
2315		.enable_mask = BIT(0),
2316		.hw.init = &(struct clk_init_data) {
2317			.name = "gcc_camss_csi0_ahb_clk",
2318			.parent_hws = (const struct clk_hw*[]){
2319				&camss_top_ahb_clk_src.clkr.hw,
2320			},
2321			.num_parents = 1,
2322			.ops = &clk_branch2_ops,
2323			.flags = CLK_SET_RATE_PARENT,
2324		}
2325	}
2326};
2327
2328static struct clk_branch gcc_camss_csi1_ahb_clk = {
2329	.halt_reg = 0x4f040,
2330	.halt_check = BRANCH_HALT,
2331	.clkr = {
2332		.enable_reg = 0x4f040,
2333		.enable_mask = BIT(0),
2334		.hw.init = &(struct clk_init_data) {
2335			.name = "gcc_camss_csi1_ahb_clk",
2336			.parent_hws = (const struct clk_hw*[]){
2337				&camss_top_ahb_clk_src.clkr.hw,
2338			},
2339			.num_parents = 1,
2340			.ops = &clk_branch2_ops,
2341			.flags = CLK_SET_RATE_PARENT,
2342		}
2343	}
2344};
2345
2346static struct clk_branch gcc_camss_csi2_ahb_clk = {
2347	.halt_reg = 0x3c040,
2348	.halt_check = BRANCH_HALT,
2349	.clkr = {
2350		.enable_reg = 0x3c040,
2351		.enable_mask = BIT(0),
2352		.hw.init = &(struct clk_init_data) {
2353			.name = "gcc_camss_csi2_ahb_clk",
2354			.parent_hws = (const struct clk_hw*[]){
2355				&camss_top_ahb_clk_src.clkr.hw,
2356			},
2357			.num_parents = 1,
2358			.ops = &clk_branch2_ops,
2359			.flags = CLK_SET_RATE_PARENT,
2360		}
2361	}
2362};
2363
2364static struct clk_branch gcc_camss_csi0_clk = {
2365	.halt_reg = 0x4e03c,
2366	.halt_check = BRANCH_HALT,
2367	.clkr = {
2368		.enable_reg = 0x4e03c,
2369		.enable_mask = BIT(0),
2370		.hw.init = &(struct clk_init_data) {
2371			.name = "gcc_camss_csi0_clk",
2372			.parent_hws = (const struct clk_hw*[]){
2373				&csi0_clk_src.clkr.hw,
2374			},
2375			.num_parents = 1,
2376			.ops = &clk_branch2_ops,
2377			.flags = CLK_SET_RATE_PARENT,
2378		}
2379	}
2380};
2381
2382static struct clk_branch gcc_camss_csi1_clk = {
2383	.halt_reg = 0x4f03c,
2384	.halt_check = BRANCH_HALT,
2385	.clkr = {
2386		.enable_reg = 0x4f03c,
2387		.enable_mask = BIT(0),
2388		.hw.init = &(struct clk_init_data) {
2389			.name = "gcc_camss_csi1_clk",
2390			.parent_hws = (const struct clk_hw*[]){
2391				&csi1_clk_src.clkr.hw,
2392			},
2393			.num_parents = 1,
2394			.ops = &clk_branch2_ops,
2395			.flags = CLK_SET_RATE_PARENT,
2396		}
2397	}
2398};
2399
2400static struct clk_branch gcc_camss_csi2_clk = {
2401	.halt_reg = 0x3c03c,
2402	.halt_check = BRANCH_HALT,
2403	.clkr = {
2404		.enable_reg = 0x3c03c,
2405		.enable_mask = BIT(0),
2406		.hw.init = &(struct clk_init_data) {
2407			.name = "gcc_camss_csi2_clk",
2408			.parent_hws = (const struct clk_hw*[]){
2409				&csi2_clk_src.clkr.hw,
2410			},
2411			.num_parents = 1,
2412			.ops = &clk_branch2_ops,
2413			.flags = CLK_SET_RATE_PARENT,
2414		}
2415	}
2416};
2417
2418static struct clk_branch gcc_camss_csi0_csiphy_3p_clk = {
2419	.halt_reg = 0x58090,
2420	.halt_check = BRANCH_HALT,
2421	.clkr = {
2422		.enable_reg = 0x58090,
2423		.enable_mask = BIT(0),
2424		.hw.init = &(struct clk_init_data) {
2425			.name = "gcc_camss_csi0_csiphy_3p_clk",
2426			.parent_hws = (const struct clk_hw*[]){
2427				&csi0p_clk_src.clkr.hw,
2428			},
2429			.num_parents = 1,
2430			.ops = &clk_branch2_ops,
2431			.flags = CLK_SET_RATE_PARENT,
2432		}
2433	}
2434};
2435
2436static struct clk_branch gcc_camss_csi1_csiphy_3p_clk = {
2437	.halt_reg = 0x580a0,
2438	.halt_check = BRANCH_HALT,
2439	.clkr = {
2440		.enable_reg = 0x580a0,
2441		.enable_mask = BIT(0),
2442		.hw.init = &(struct clk_init_data) {
2443			.name = "gcc_camss_csi1_csiphy_3p_clk",
2444			.parent_hws = (const struct clk_hw*[]){
2445				&csi1p_clk_src.clkr.hw,
2446			},
2447			.num_parents = 1,
2448			.ops = &clk_branch2_ops,
2449			.flags = CLK_SET_RATE_PARENT,
2450		}
2451	}
2452};
2453
2454static struct clk_branch gcc_camss_csi2_csiphy_3p_clk = {
2455	.halt_reg = 0x580b0,
2456	.halt_check = BRANCH_HALT,
2457	.clkr = {
2458		.enable_reg = 0x580b0,
2459		.enable_mask = BIT(0),
2460		.hw.init = &(struct clk_init_data) {
2461			.name = "gcc_camss_csi2_csiphy_3p_clk",
2462			.parent_hws = (const struct clk_hw*[]){
2463				&csi2p_clk_src.clkr.hw,
2464			},
2465			.num_parents = 1,
2466			.ops = &clk_branch2_ops,
2467			.flags = CLK_SET_RATE_PARENT,
2468		}
2469	}
2470};
2471
2472static struct clk_branch gcc_camss_csi0phy_clk = {
2473	.halt_reg = 0x4e048,
2474	.halt_check = BRANCH_HALT,
2475	.clkr = {
2476		.enable_reg = 0x4e048,
2477		.enable_mask = BIT(0),
2478		.hw.init = &(struct clk_init_data) {
2479			.name = "gcc_camss_csi0phy_clk",
2480			.parent_hws = (const struct clk_hw*[]){
2481				&csi0_clk_src.clkr.hw,
2482			},
2483			.num_parents = 1,
2484			.ops = &clk_branch2_ops,
2485			.flags = CLK_SET_RATE_PARENT,
2486		}
2487	}
2488};
2489
2490static struct clk_branch gcc_camss_csi1phy_clk = {
2491	.halt_reg = 0x4f048,
2492	.halt_check = BRANCH_HALT,
2493	.clkr = {
2494		.enable_reg = 0x4f048,
2495		.enable_mask = BIT(0),
2496		.hw.init = &(struct clk_init_data) {
2497			.name = "gcc_camss_csi1phy_clk",
2498			.parent_hws = (const struct clk_hw*[]){
2499				&csi1_clk_src.clkr.hw,
2500			},
2501			.num_parents = 1,
2502			.ops = &clk_branch2_ops,
2503			.flags = CLK_SET_RATE_PARENT,
2504		}
2505	}
2506};
2507
2508static struct clk_branch gcc_camss_csi2phy_clk = {
2509	.halt_reg = 0x3c048,
2510	.halt_check = BRANCH_HALT,
2511	.clkr = {
2512		.enable_reg = 0x3c048,
2513		.enable_mask = BIT(0),
2514		.hw.init = &(struct clk_init_data) {
2515			.name = "gcc_camss_csi2phy_clk",
2516			.parent_hws = (const struct clk_hw*[]){
2517				&csi2_clk_src.clkr.hw,
2518			},
2519			.num_parents = 1,
2520			.ops = &clk_branch2_ops,
2521			.flags = CLK_SET_RATE_PARENT,
2522		}
2523	}
2524};
2525
2526static struct clk_branch gcc_camss_csi0phytimer_clk = {
2527	.halt_reg = 0x4e01c,
2528	.halt_check = BRANCH_HALT,
2529	.clkr = {
2530		.enable_reg = 0x4e01c,
2531		.enable_mask = BIT(0),
2532		.hw.init = &(struct clk_init_data) {
2533			.name = "gcc_camss_csi0phytimer_clk",
2534			.parent_hws = (const struct clk_hw*[]){
2535				&csi0phytimer_clk_src.clkr.hw,
2536			},
2537			.num_parents = 1,
2538			.ops = &clk_branch2_ops,
2539			.flags = CLK_SET_RATE_PARENT,
2540		}
2541	}
2542};
2543
2544static struct clk_branch gcc_camss_csi1phytimer_clk = {
2545	.halt_reg = 0x4f01c,
2546	.halt_check = BRANCH_HALT,
2547	.clkr = {
2548		.enable_reg = 0x4f01c,
2549		.enable_mask = BIT(0),
2550		.hw.init = &(struct clk_init_data) {
2551			.name = "gcc_camss_csi1phytimer_clk",
2552			.parent_hws = (const struct clk_hw*[]){
2553				&csi1phytimer_clk_src.clkr.hw,
2554			},
2555			.num_parents = 1,
2556			.ops = &clk_branch2_ops,
2557			.flags = CLK_SET_RATE_PARENT,
2558		}
2559	}
2560};
2561
2562static struct clk_branch gcc_camss_csi2phytimer_clk = {
2563	.halt_reg = 0x4f068,
2564	.halt_check = BRANCH_HALT,
2565	.clkr = {
2566		.enable_reg = 0x4f068,
2567		.enable_mask = BIT(0),
2568		.hw.init = &(struct clk_init_data) {
2569			.name = "gcc_camss_csi2phytimer_clk",
2570			.parent_hws = (const struct clk_hw*[]){
2571				&csi2phytimer_clk_src.clkr.hw,
2572			},
2573			.num_parents = 1,
2574			.ops = &clk_branch2_ops,
2575			.flags = CLK_SET_RATE_PARENT,
2576		}
2577	}
2578};
2579
2580static struct clk_branch gcc_camss_csi0pix_clk = {
2581	.halt_reg = 0x4e058,
2582	.halt_check = BRANCH_HALT,
2583	.clkr = {
2584		.enable_reg = 0x4e058,
2585		.enable_mask = BIT(0),
2586		.hw.init = &(struct clk_init_data) {
2587			.name = "gcc_camss_csi0pix_clk",
2588			.parent_hws = (const struct clk_hw*[]){
2589				&csi0_clk_src.clkr.hw,
2590			},
2591			.num_parents = 1,
2592			.ops = &clk_branch2_ops,
2593			.flags = CLK_SET_RATE_PARENT,
2594		}
2595	}
2596};
2597
2598static struct clk_branch gcc_camss_csi1pix_clk = {
2599	.halt_reg = 0x4f058,
2600	.halt_check = BRANCH_HALT,
2601	.clkr = {
2602		.enable_reg = 0x4f058,
2603		.enable_mask = BIT(0),
2604		.hw.init = &(struct clk_init_data) {
2605			.name = "gcc_camss_csi1pix_clk",
2606			.parent_hws = (const struct clk_hw*[]){
2607				&csi1_clk_src.clkr.hw,
2608			},
2609			.num_parents = 1,
2610			.ops = &clk_branch2_ops,
2611			.flags = CLK_SET_RATE_PARENT,
2612		}
2613	}
2614};
2615
2616static struct clk_branch gcc_camss_csi2pix_clk = {
2617	.halt_reg = 0x3c058,
2618	.halt_check = BRANCH_HALT,
2619	.clkr = {
2620		.enable_reg = 0x3c058,
2621		.enable_mask = BIT(0),
2622		.hw.init = &(struct clk_init_data) {
2623			.name = "gcc_camss_csi2pix_clk",
2624			.parent_hws = (const struct clk_hw*[]){
2625				&csi2_clk_src.clkr.hw,
2626			},
2627			.num_parents = 1,
2628			.ops = &clk_branch2_ops,
2629			.flags = CLK_SET_RATE_PARENT,
2630		}
2631	}
2632};
2633
2634static struct clk_branch gcc_camss_csi0rdi_clk = {
2635	.halt_reg = 0x4e050,
2636	.halt_check = BRANCH_HALT,
2637	.clkr = {
2638		.enable_reg = 0x4e050,
2639		.enable_mask = BIT(0),
2640		.hw.init = &(struct clk_init_data) {
2641			.name = "gcc_camss_csi0rdi_clk",
2642			.parent_hws = (const struct clk_hw*[]){
2643				&csi0_clk_src.clkr.hw,
2644			},
2645			.num_parents = 1,
2646			.ops = &clk_branch2_ops,
2647			.flags = CLK_SET_RATE_PARENT,
2648		}
2649	}
2650};
2651
2652static struct clk_branch gcc_camss_csi1rdi_clk = {
2653	.halt_reg = 0x4f050,
2654	.halt_check = BRANCH_HALT,
2655	.clkr = {
2656		.enable_reg = 0x4f050,
2657		.enable_mask = BIT(0),
2658		.hw.init = &(struct clk_init_data) {
2659			.name = "gcc_camss_csi1rdi_clk",
2660			.parent_hws = (const struct clk_hw*[]){
2661				&csi1_clk_src.clkr.hw,
2662			},
2663			.num_parents = 1,
2664			.ops = &clk_branch2_ops,
2665			.flags = CLK_SET_RATE_PARENT,
2666		}
2667	}
2668};
2669
2670static struct clk_branch gcc_camss_csi2rdi_clk = {
2671	.halt_reg = 0x3c050,
2672	.halt_check = BRANCH_HALT,
2673	.clkr = {
2674		.enable_reg = 0x3c050,
2675		.enable_mask = BIT(0),
2676		.hw.init = &(struct clk_init_data) {
2677			.name = "gcc_camss_csi2rdi_clk",
2678			.parent_hws = (const struct clk_hw*[]){
2679				&csi2_clk_src.clkr.hw,
2680			},
2681			.num_parents = 1,
2682			.ops = &clk_branch2_ops,
2683			.flags = CLK_SET_RATE_PARENT,
2684		}
2685	}
2686};
2687
2688static struct clk_branch gcc_camss_csi_vfe0_clk = {
2689	.halt_reg = 0x58050,
2690	.halt_check = BRANCH_HALT,
2691	.clkr = {
2692		.enable_reg = 0x58050,
2693		.enable_mask = BIT(0),
2694		.hw.init = &(struct clk_init_data) {
2695			.name = "gcc_camss_csi_vfe0_clk",
2696			.parent_hws = (const struct clk_hw*[]){
2697				&vfe0_clk_src.clkr.hw,
2698			},
2699			.num_parents = 1,
2700			.ops = &clk_branch2_ops,
2701			.flags = CLK_SET_RATE_PARENT,
2702		}
2703	}
2704};
2705
2706static struct clk_branch gcc_camss_csi_vfe1_clk = {
2707	.halt_reg = 0x58074,
2708	.halt_check = BRANCH_HALT,
2709	.clkr = {
2710		.enable_reg = 0x58074,
2711		.enable_mask = BIT(0),
2712		.hw.init = &(struct clk_init_data) {
2713			.name = "gcc_camss_csi_vfe1_clk",
2714			.parent_hws = (const struct clk_hw*[]){
2715				&vfe1_clk_src.clkr.hw,
2716			},
2717			.num_parents = 1,
2718			.ops = &clk_branch2_ops,
2719			.flags = CLK_SET_RATE_PARENT,
2720		}
2721	}
2722};
2723
2724static struct clk_branch gcc_camss_gp0_clk = {
2725	.halt_reg = 0x54018,
2726	.halt_check = BRANCH_HALT,
2727	.clkr = {
2728		.enable_reg = 0x54018,
2729		.enable_mask = BIT(0),
2730		.hw.init = &(struct clk_init_data) {
2731			.name = "gcc_camss_gp0_clk",
2732			.parent_hws = (const struct clk_hw*[]){
2733				&camss_gp0_clk_src.clkr.hw,
2734			},
2735			.num_parents = 1,
2736			.ops = &clk_branch2_ops,
2737			.flags = CLK_SET_RATE_PARENT,
2738		}
2739	}
2740};
2741
2742static struct clk_branch gcc_camss_gp1_clk = {
2743	.halt_reg = 0x55018,
2744	.halt_check = BRANCH_HALT,
2745	.clkr = {
2746		.enable_reg = 0x55018,
2747		.enable_mask = BIT(0),
2748		.hw.init = &(struct clk_init_data) {
2749			.name = "gcc_camss_gp1_clk",
2750			.parent_hws = (const struct clk_hw*[]){
2751				&camss_gp1_clk_src.clkr.hw,
2752			},
2753			.num_parents = 1,
2754			.ops = &clk_branch2_ops,
2755			.flags = CLK_SET_RATE_PARENT,
2756		}
2757	}
2758};
2759
2760static struct clk_branch gcc_camss_ispif_ahb_clk = {
2761	.halt_reg = 0x50004,
2762	.halt_check = BRANCH_HALT,
2763	.clkr = {
2764		.enable_reg = 0x50004,
2765		.enable_mask = BIT(0),
2766		.hw.init = &(struct clk_init_data) {
2767			.name = "gcc_camss_ispif_ahb_clk",
2768			.parent_hws = (const struct clk_hw*[]){
2769				&camss_top_ahb_clk_src.clkr.hw,
2770			},
2771			.num_parents = 1,
2772			.ops = &clk_branch2_ops,
2773			.flags = CLK_SET_RATE_PARENT,
2774		}
2775	}
2776};
2777
2778static struct clk_branch gcc_camss_jpeg0_clk = {
2779	.halt_reg = 0x57020,
2780	.halt_check = BRANCH_HALT,
2781	.clkr = {
2782		.enable_reg = 0x57020,
2783		.enable_mask = BIT(0),
2784		.hw.init = &(struct clk_init_data) {
2785			.name = "gcc_camss_jpeg0_clk",
2786			.parent_hws = (const struct clk_hw*[]){
2787				&jpeg0_clk_src.clkr.hw,
2788			},
2789			.num_parents = 1,
2790			.ops = &clk_branch2_ops,
2791			.flags = CLK_SET_RATE_PARENT,
2792		}
2793	}
2794};
2795
2796static struct clk_branch gcc_camss_jpeg_ahb_clk = {
2797	.halt_reg = 0x57024,
2798	.halt_check = BRANCH_HALT,
2799	.clkr = {
2800		.enable_reg = 0x57024,
2801		.enable_mask = BIT(0),
2802		.hw.init = &(struct clk_init_data) {
2803			.name = "gcc_camss_jpeg_ahb_clk",
2804			.parent_hws = (const struct clk_hw*[]){
2805				&camss_top_ahb_clk_src.clkr.hw,
2806			},
2807			.num_parents = 1,
2808			.ops = &clk_branch2_ops,
2809			.flags = CLK_SET_RATE_PARENT,
2810		}
2811	}
2812};
2813
2814static struct clk_branch gcc_camss_jpeg_axi_clk = {
2815	.halt_reg = 0x57028,
2816	.halt_check = BRANCH_HALT,
2817	.clkr = {
2818		.enable_reg = 0x57028,
2819		.enable_mask = BIT(0),
2820		.hw.init = &(struct clk_init_data) {
2821			.name = "gcc_camss_jpeg_axi_clk",
2822			.ops = &clk_branch2_ops,
2823		}
2824	}
2825};
2826
2827static struct clk_branch gcc_camss_mclk0_clk = {
2828	.halt_reg = 0x52018,
2829	.halt_check = BRANCH_HALT,
2830	.clkr = {
2831		.enable_reg = 0x52018,
2832		.enable_mask = BIT(0),
2833		.hw.init = &(struct clk_init_data) {
2834			.name = "gcc_camss_mclk0_clk",
2835			.parent_hws = (const struct clk_hw*[]){
2836				&mclk0_clk_src.clkr.hw,
2837			},
2838			.num_parents = 1,
2839			.ops = &clk_branch2_ops,
2840			.flags = CLK_SET_RATE_PARENT,
2841		}
2842	}
2843};
2844
2845static struct clk_branch gcc_camss_mclk1_clk = {
2846	.halt_reg = 0x53018,
2847	.halt_check = BRANCH_HALT,
2848	.clkr = {
2849		.enable_reg = 0x53018,
2850		.enable_mask = BIT(0),
2851		.hw.init = &(struct clk_init_data) {
2852			.name = "gcc_camss_mclk1_clk",
2853			.parent_hws = (const struct clk_hw*[]){
2854				&mclk1_clk_src.clkr.hw,
2855			},
2856			.num_parents = 1,
2857			.ops = &clk_branch2_ops,
2858			.flags = CLK_SET_RATE_PARENT,
2859		}
2860	}
2861};
2862
2863static struct clk_branch gcc_camss_mclk2_clk = {
2864	.halt_reg = 0x5c018,
2865	.halt_check = BRANCH_HALT,
2866	.clkr = {
2867		.enable_reg = 0x5c018,
2868		.enable_mask = BIT(0),
2869		.hw.init = &(struct clk_init_data) {
2870			.name = "gcc_camss_mclk2_clk",
2871			.parent_hws = (const struct clk_hw*[]){
2872				&mclk2_clk_src.clkr.hw,
2873			},
2874			.num_parents = 1,
2875			.ops = &clk_branch2_ops,
2876			.flags = CLK_SET_RATE_PARENT,
2877		}
2878	}
2879};
2880
2881static struct clk_branch gcc_camss_mclk3_clk = {
2882	.halt_reg = 0x5e018,
2883	.halt_check = BRANCH_HALT,
2884	.clkr = {
2885		.enable_reg = 0x5e018,
2886		.enable_mask = BIT(0),
2887		.hw.init = &(struct clk_init_data) {
2888			.name = "gcc_camss_mclk3_clk",
2889			.parent_hws = (const struct clk_hw*[]){
2890				&mclk3_clk_src.clkr.hw,
2891			},
2892			.num_parents = 1,
2893			.ops = &clk_branch2_ops,
2894			.flags = CLK_SET_RATE_PARENT,
2895		}
2896	}
2897};
2898
2899static struct clk_branch gcc_camss_micro_ahb_clk = {
2900	.halt_reg = 0x5600c,
2901	.halt_check = BRANCH_HALT,
2902	.clkr = {
2903		.enable_reg = 0x5600c,
2904		.enable_mask = BIT(0),
2905		.hw.init = &(struct clk_init_data) {
2906			.name = "gcc_camss_micro_ahb_clk",
2907			.parent_hws = (const struct clk_hw*[]){
2908				&camss_top_ahb_clk_src.clkr.hw,
2909			},
2910			.num_parents = 1,
2911			.ops = &clk_branch2_ops,
2912			.flags = CLK_SET_RATE_PARENT,
2913		}
2914	}
2915};
2916
2917static struct clk_branch gcc_camss_top_ahb_clk = {
2918	.halt_reg = 0x5a014,
2919	.halt_check = BRANCH_HALT,
2920	.clkr = {
2921		.enable_reg = 0x5a014,
2922		.enable_mask = BIT(0),
2923		.hw.init = &(struct clk_init_data) {
2924			.name = "gcc_camss_top_ahb_clk",
2925			.parent_hws = (const struct clk_hw*[]){
2926				&camss_top_ahb_clk_src.clkr.hw,
2927			},
2928			.num_parents = 1,
2929			.ops = &clk_branch2_ops,
2930			.flags = CLK_SET_RATE_PARENT,
2931		}
2932	}
2933};
2934
2935static struct clk_branch gcc_camss_vfe0_ahb_clk = {
2936	.halt_reg = 0x58044,
2937	.halt_check = BRANCH_HALT,
2938	.clkr = {
2939		.enable_reg = 0x58044,
2940		.enable_mask = BIT(0),
2941		.hw.init = &(struct clk_init_data) {
2942			.name = "gcc_camss_vfe0_ahb_clk",
2943			.parent_hws = (const struct clk_hw*[]){
2944				&camss_top_ahb_clk_src.clkr.hw,
2945			},
2946			.num_parents = 1,
2947			.ops = &clk_branch2_ops,
2948			.flags = CLK_SET_RATE_PARENT,
2949		}
2950	}
2951};
2952
2953static struct clk_branch gcc_camss_vfe0_axi_clk = {
2954	.halt_reg = 0x58048,
2955	.halt_check = BRANCH_HALT,
2956	.clkr = {
2957		.enable_reg = 0x58048,
2958		.enable_mask = BIT(0),
2959		.hw.init = &(struct clk_init_data) {
2960			.name = "gcc_camss_vfe0_axi_clk",
2961			.ops = &clk_branch2_ops,
2962		}
2963	}
2964};
2965
2966static struct clk_branch gcc_camss_vfe0_clk = {
2967	.halt_reg = 0x58038,
2968	.halt_check = BRANCH_HALT,
2969	.clkr = {
2970		.enable_reg = 0x58038,
2971		.enable_mask = BIT(0),
2972		.hw.init = &(struct clk_init_data) {
2973			.name = "gcc_camss_vfe0_clk",
2974			.parent_hws = (const struct clk_hw*[]){
2975				&vfe0_clk_src.clkr.hw,
2976			},
2977			.num_parents = 1,
2978			.ops = &clk_branch2_ops,
2979			.flags = CLK_SET_RATE_PARENT,
2980		}
2981	}
2982};
2983
2984static struct clk_branch gcc_camss_vfe1_ahb_clk = {
2985	.halt_reg = 0x58060,
2986	.halt_check = BRANCH_HALT,
2987	.clkr = {
2988		.enable_reg = 0x58060,
2989		.enable_mask = BIT(0),
2990		.hw.init = &(struct clk_init_data) {
2991			.name = "gcc_camss_vfe1_ahb_clk",
2992			.parent_hws = (const struct clk_hw*[]){
2993				&camss_top_ahb_clk_src.clkr.hw,
2994			},
2995			.num_parents = 1,
2996			.ops = &clk_branch2_ops,
2997			.flags = CLK_SET_RATE_PARENT,
2998		}
2999	}
3000};
3001
3002static struct clk_branch gcc_camss_vfe1_axi_clk = {
3003	.halt_reg = 0x58068,
3004	.halt_check = BRANCH_HALT,
3005	.clkr = {
3006		.enable_reg = 0x58068,
3007		.enable_mask = BIT(0),
3008		.hw.init = &(struct clk_init_data) {
3009			.name = "gcc_camss_vfe1_axi_clk",
3010			.ops = &clk_branch2_ops,
3011		}
3012	}
3013};
3014
3015static struct clk_branch gcc_camss_vfe1_clk = {
3016	.halt_reg = 0x5805c,
3017	.halt_check = BRANCH_HALT,
3018	.clkr = {
3019		.enable_reg = 0x5805c,
3020		.enable_mask = BIT(0),
3021		.hw.init = &(struct clk_init_data) {
3022			.name = "gcc_camss_vfe1_clk",
3023			.parent_hws = (const struct clk_hw*[]){
3024				&vfe1_clk_src.clkr.hw,
3025			},
3026			.num_parents = 1,
3027			.ops = &clk_branch2_ops,
3028			.flags = CLK_SET_RATE_PARENT,
3029		}
3030	}
3031};
3032
3033static struct clk_branch gcc_cpp_tbu_clk = {
3034	.halt_reg = 0x12040,
3035	.halt_check = BRANCH_HALT_VOTED,
3036	.clkr = {
3037		.enable_reg = 0x4500c,
3038		.enable_mask = BIT(14),
3039		.hw.init = &(struct clk_init_data) {
3040			.name = "gcc_cpp_tbu_clk",
3041			.ops = &clk_branch2_ops,
3042		}
3043	}
3044};
3045
3046static struct clk_branch gcc_crypto_ahb_clk = {
3047	.halt_reg = 0x16024,
3048	.halt_check = BRANCH_HALT_VOTED,
3049	.clkr = {
3050		.enable_reg = 0x45004,
3051		.enable_mask = BIT(0),
3052		.hw.init = &(struct clk_init_data) {
3053			.name = "gcc_crypto_ahb_clk",
3054			.ops = &clk_branch2_ops,
3055		}
3056	}
3057};
3058
3059static struct clk_branch gcc_crypto_axi_clk = {
3060	.halt_reg = 0x16020,
3061	.halt_check = BRANCH_HALT_VOTED,
3062	.clkr = {
3063		.enable_reg = 0x45004,
3064		.enable_mask = BIT(1),
3065		.hw.init = &(struct clk_init_data) {
3066			.name = "gcc_crypto_axi_clk",
3067			.ops = &clk_branch2_ops,
3068		}
3069	}
3070};
3071
3072static struct clk_branch gcc_crypto_clk = {
3073	.halt_reg = 0x1601c,
3074	.halt_check = BRANCH_HALT_VOTED,
3075	.clkr = {
3076		.enable_reg = 0x45004,
3077		.enable_mask = BIT(2),
3078		.hw.init = &(struct clk_init_data) {
3079			.name = "gcc_crypto_clk",
3080			.parent_hws = (const struct clk_hw*[]){
3081				&crypto_clk_src.clkr.hw,
3082			},
3083			.num_parents = 1,
3084			.ops = &clk_branch2_ops,
3085			.flags = CLK_SET_RATE_PARENT,
3086		}
3087	}
3088};
3089
3090static struct clk_branch gcc_dcc_clk = {
3091	.halt_reg = 0x77004,
3092	.halt_check = BRANCH_HALT,
3093	.clkr = {
3094		.enable_reg = 0x77004,
3095		.enable_mask = BIT(0),
3096		.hw.init = &(struct clk_init_data) {
3097			.name = "gcc_dcc_clk",
3098			.ops = &clk_branch2_ops,
3099		}
3100	}
3101};
3102
3103static struct clk_branch gcc_gp1_clk = {
3104	.halt_reg = 0x08000,
3105	.halt_check = BRANCH_HALT,
3106	.clkr = {
3107		.enable_reg = 0x08000,
3108		.enable_mask = BIT(0),
3109		.hw.init = &(struct clk_init_data) {
3110			.name = "gcc_gp1_clk",
3111			.parent_hws = (const struct clk_hw*[]){
3112				&gp1_clk_src.clkr.hw,
3113			},
3114			.num_parents = 1,
3115			.ops = &clk_branch2_ops,
3116			.flags = CLK_SET_RATE_PARENT,
3117		}
3118	}
3119};
3120
3121static struct clk_branch gcc_gp2_clk = {
3122	.halt_reg = 0x09000,
3123	.halt_check = BRANCH_HALT,
3124	.clkr = {
3125		.enable_reg = 0x09000,
3126		.enable_mask = BIT(0),
3127		.hw.init = &(struct clk_init_data) {
3128			.name = "gcc_gp2_clk",
3129			.parent_hws = (const struct clk_hw*[]){
3130				&gp2_clk_src.clkr.hw,
3131			},
3132			.num_parents = 1,
3133			.ops = &clk_branch2_ops,
3134			.flags = CLK_SET_RATE_PARENT,
3135		}
3136	}
3137};
3138
3139static struct clk_branch gcc_gp3_clk = {
3140	.halt_reg = 0x0a000,
3141	.halt_check = BRANCH_HALT,
3142	.clkr = {
3143		.enable_reg = 0x0a000,
3144		.enable_mask = BIT(0),
3145		.hw.init = &(struct clk_init_data) {
3146			.name = "gcc_gp3_clk",
3147			.parent_hws = (const struct clk_hw*[]){
3148				&gp3_clk_src.clkr.hw,
3149			},
3150			.num_parents = 1,
3151			.ops = &clk_branch2_ops,
3152			.flags = CLK_SET_RATE_PARENT,
3153		}
3154	}
3155};
3156
3157static struct clk_branch gcc_jpeg_tbu_clk = {
3158	.halt_reg = 0x12034,
3159	.halt_check = BRANCH_HALT_VOTED,
3160	.clkr = {
3161		.enable_reg = 0x4500c,
3162		.enable_mask = BIT(10),
3163		.hw.init = &(struct clk_init_data) {
3164			.name = "gcc_jpeg_tbu_clk",
3165			.ops = &clk_branch2_ops,
3166		}
3167	}
3168};
3169
3170static struct clk_branch gcc_mdp_tbu_clk = {
3171	.halt_reg = 0x1201c,
3172	.halt_check = BRANCH_HALT_VOTED,
3173	.clkr = {
3174		.enable_reg = 0x4500c,
3175		.enable_mask = BIT(4),
3176		.hw.init = &(struct clk_init_data) {
3177			.name = "gcc_mdp_tbu_clk",
3178			.ops = &clk_branch2_ops,
3179		}
3180	}
3181};
3182
3183static struct clk_branch gcc_mdss_ahb_clk = {
3184	.halt_reg = 0x4d07c,
3185	.halt_check = BRANCH_HALT,
3186	.clkr = {
3187		.enable_reg = 0x4d07c,
3188		.enable_mask = BIT(0),
3189		.hw.init = &(struct clk_init_data) {
3190			.name = "gcc_mdss_ahb_clk",
3191			.ops = &clk_branch2_ops,
3192		}
3193	}
3194};
3195
3196static struct clk_branch gcc_mdss_axi_clk = {
3197	.halt_reg = 0x4d080,
3198	.halt_check = BRANCH_HALT,
3199	.clkr = {
3200		.enable_reg = 0x4d080,
3201		.enable_mask = BIT(0),
3202		.hw.init = &(struct clk_init_data) {
3203			.name = "gcc_mdss_axi_clk",
3204			.ops = &clk_branch2_ops,
3205		}
3206	}
3207};
3208
3209static struct clk_branch gcc_mdss_byte0_clk = {
3210	.halt_reg = 0x4d094,
3211	.halt_check = BRANCH_HALT,
3212	.clkr = {
3213		.enable_reg = 0x4d094,
3214		.enable_mask = BIT(0),
3215		.hw.init = &(struct clk_init_data) {
3216			.name = "gcc_mdss_byte0_clk",
3217			.parent_hws = (const struct clk_hw*[]){
3218				&byte0_clk_src.clkr.hw,
3219			},
3220			.num_parents = 1,
3221			.ops = &clk_branch2_ops,
3222			.flags = CLK_SET_RATE_PARENT,
3223		}
3224	}
3225};
3226
3227static struct clk_branch gcc_mdss_byte1_clk = {
3228	.halt_reg = 0x4d0a0,
3229	.halt_check = BRANCH_HALT,
3230	.clkr = {
3231		.enable_reg = 0x4d0a0,
3232		.enable_mask = BIT(0),
3233		.hw.init = &(struct clk_init_data) {
3234			.name = "gcc_mdss_byte1_clk",
3235			.parent_hws = (const struct clk_hw*[]){
3236				&byte1_clk_src.clkr.hw,
3237			},
3238			.num_parents = 1,
3239			.ops = &clk_branch2_ops,
3240			.flags = CLK_SET_RATE_PARENT,
3241		}
3242	}
3243};
3244
3245static struct clk_branch gcc_mdss_esc0_clk = {
3246	.halt_reg = 0x4d098,
3247	.halt_check = BRANCH_HALT,
3248	.clkr = {
3249		.enable_reg = 0x4d098,
3250		.enable_mask = BIT(0),
3251		.hw.init = &(struct clk_init_data) {
3252			.name = "gcc_mdss_esc0_clk",
3253			.parent_hws = (const struct clk_hw*[]){
3254				&esc0_clk_src.clkr.hw,
3255			},
3256			.num_parents = 1,
3257			.ops = &clk_branch2_ops,
3258			.flags = CLK_SET_RATE_PARENT,
3259		}
3260	}
3261};
3262
3263static struct clk_branch gcc_mdss_esc1_clk = {
3264	.halt_reg = 0x4d09c,
3265	.halt_check = BRANCH_HALT,
3266	.clkr = {
3267		.enable_reg = 0x4d09c,
3268		.enable_mask = BIT(0),
3269		.hw.init = &(struct clk_init_data) {
3270			.name = "gcc_mdss_esc1_clk",
3271			.parent_hws = (const struct clk_hw*[]){
3272				&esc1_clk_src.clkr.hw,
3273			},
3274			.num_parents = 1,
3275			.ops = &clk_branch2_ops,
3276			.flags = CLK_SET_RATE_PARENT,
3277		}
3278	}
3279};
3280
3281static struct clk_branch gcc_mdss_mdp_clk = {
3282	.halt_reg = 0x4d088,
3283	.halt_check = BRANCH_HALT,
3284	.clkr = {
3285		.enable_reg = 0x4d088,
3286		.enable_mask = BIT(0),
3287		.hw.init = &(struct clk_init_data) {
3288			.name = "gcc_mdss_mdp_clk",
3289			.parent_hws = (const struct clk_hw*[]){
3290				&mdp_clk_src.clkr.hw,
3291			},
3292			.num_parents = 1,
3293			.ops = &clk_branch2_ops,
3294			.flags = CLK_SET_RATE_PARENT,
3295		}
3296	}
3297};
3298
3299static struct clk_branch gcc_mdss_pclk0_clk = {
3300	.halt_reg = 0x4d084,
3301	.halt_check = BRANCH_HALT,
3302	.clkr = {
3303		.enable_reg = 0x4d084,
3304		.enable_mask = BIT(0),
3305		.hw.init = &(struct clk_init_data) {
3306			.name = "gcc_mdss_pclk0_clk",
3307			.parent_hws = (const struct clk_hw*[]){
3308				&pclk0_clk_src.clkr.hw,
3309			},
3310			.num_parents = 1,
3311			.ops = &clk_branch2_ops,
3312			.flags = CLK_SET_RATE_PARENT,
3313		}
3314	}
3315};
3316
3317static struct clk_branch gcc_mdss_pclk1_clk = {
3318	.halt_reg = 0x4d0a4,
3319	.halt_check = BRANCH_HALT,
3320	.clkr = {
3321		.enable_reg = 0x4d0a4,
3322		.enable_mask = BIT(0),
3323		.hw.init = &(struct clk_init_data) {
3324			.name = "gcc_mdss_pclk1_clk",
3325			.parent_hws = (const struct clk_hw*[]){
3326				&pclk1_clk_src.clkr.hw,
3327			},
3328			.num_parents = 1,
3329			.ops = &clk_branch2_ops,
3330			.flags = CLK_SET_RATE_PARENT,
3331		}
3332	}
3333};
3334
3335static struct clk_branch gcc_mdss_vsync_clk = {
3336	.halt_reg = 0x4d090,
3337	.halt_check = BRANCH_HALT,
3338	.clkr = {
3339		.enable_reg = 0x4d090,
3340		.enable_mask = BIT(0),
3341		.hw.init = &(struct clk_init_data) {
3342			.name = "gcc_mdss_vsync_clk",
3343			.parent_hws = (const struct clk_hw*[]){
3344				&vsync_clk_src.clkr.hw,
3345			},
3346			.num_parents = 1,
3347			.ops = &clk_branch2_ops,
3348			.flags = CLK_SET_RATE_PARENT,
3349		}
3350	}
3351};
3352
3353static struct clk_branch gcc_mss_cfg_ahb_clk = {
3354	.halt_reg = 0x49000,
3355	.halt_check = BRANCH_HALT,
3356	.clkr = {
3357		.enable_reg = 0x49000,
3358		.enable_mask = BIT(0),
3359		.hw.init = &(struct clk_init_data) {
3360			.name = "gcc_mss_cfg_ahb_clk",
3361			.ops = &clk_branch2_ops,
3362		}
3363	}
3364};
3365
3366static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
3367	.halt_reg = 0x49004,
3368	.halt_check = BRANCH_HALT,
3369	.clkr = {
3370		.enable_reg = 0x49004,
3371		.enable_mask = BIT(0),
3372		.hw.init = &(struct clk_init_data) {
3373			.name = "gcc_mss_q6_bimc_axi_clk",
3374			.ops = &clk_branch2_ops,
3375		}
3376	}
3377};
3378
3379static struct clk_branch gcc_oxili_ahb_clk = {
3380	.halt_reg = 0x59028,
3381	.halt_check = BRANCH_HALT,
3382	.clkr = {
3383		.enable_reg = 0x59028,
3384		.enable_mask = BIT(0),
3385		.hw.init = &(struct clk_init_data) {
3386			.name = "gcc_oxili_ahb_clk",
3387			.ops = &clk_branch2_ops,
3388		}
3389	}
3390};
3391
3392static struct clk_branch gcc_oxili_aon_clk = {
3393	.halt_reg = 0x59044,
3394	.halt_check = BRANCH_HALT,
3395	.clkr = {
3396		.enable_reg = 0x59044,
3397		.enable_mask = BIT(0),
3398		.hw.init = &(struct clk_init_data) {
3399			.name = "gcc_oxili_aon_clk",
3400			.parent_hws = (const struct clk_hw*[]){
3401				&gfx3d_clk_src.clkr.hw,
3402			},
3403			.num_parents = 1,
3404			.ops = &clk_branch2_ops,
3405		}
3406	}
3407};
3408
3409static struct clk_branch gcc_oxili_gfx3d_clk = {
3410	.halt_reg = 0x59020,
3411	.halt_check = BRANCH_HALT,
3412	.clkr = {
3413		.enable_reg = 0x59020,
3414		.enable_mask = BIT(0),
3415		.hw.init = &(struct clk_init_data) {
3416			.name = "gcc_oxili_gfx3d_clk",
3417			.parent_hws = (const struct clk_hw*[]){
3418				&gfx3d_clk_src.clkr.hw,
3419			},
3420			.num_parents = 1,
3421			.ops = &clk_branch2_ops,
3422			.flags = CLK_SET_RATE_PARENT,
3423		}
3424	}
3425};
3426
3427static struct clk_branch gcc_oxili_timer_clk = {
3428	.halt_reg = 0x59040,
3429	.halt_check = BRANCH_HALT,
3430	.clkr = {
3431		.enable_reg = 0x59040,
3432		.enable_mask = BIT(0),
3433		.hw.init = &(struct clk_init_data) {
3434			.name = "gcc_oxili_timer_clk",
3435			.ops = &clk_branch2_ops,
3436		}
3437	}
3438};
3439
3440static struct clk_branch gcc_pcnoc_usb3_axi_clk = {
3441	.halt_reg = 0x3f038,
3442	.halt_check = BRANCH_HALT,
3443	.clkr = {
3444		.enable_reg = 0x3f038,
3445		.enable_mask = BIT(0),
3446		.hw.init = &(struct clk_init_data) {
3447			.name = "gcc_pcnoc_usb3_axi_clk",
3448			.parent_hws = (const struct clk_hw*[]){
3449				&usb30_master_clk_src.clkr.hw,
3450			},
3451			.num_parents = 1,
3452			.ops = &clk_branch2_ops,
3453			.flags = CLK_SET_RATE_PARENT,
3454		}
3455	}
3456};
3457
3458static struct clk_branch gcc_pdm2_clk = {
3459	.halt_reg = 0x4400c,
3460	.halt_check = BRANCH_HALT,
3461	.clkr = {
3462		.enable_reg = 0x4400c,
3463		.enable_mask = BIT(0),
3464		.hw.init = &(struct clk_init_data) {
3465			.name = "gcc_pdm2_clk",
3466			.parent_hws = (const struct clk_hw*[]){
3467				&pdm2_clk_src.clkr.hw,
3468			},
3469			.num_parents = 1,
3470			.ops = &clk_branch2_ops,
3471			.flags = CLK_SET_RATE_PARENT,
3472		}
3473	}
3474};
3475
3476static struct clk_branch gcc_pdm_ahb_clk = {
3477	.halt_reg = 0x44004,
3478	.halt_check = BRANCH_HALT,
3479	.clkr = {
3480		.enable_reg = 0x44004,
3481		.enable_mask = BIT(0),
3482		.hw.init = &(struct clk_init_data) {
3483			.name = "gcc_pdm_ahb_clk",
3484			.ops = &clk_branch2_ops,
3485		}
3486	}
3487};
3488
3489static struct clk_branch gcc_prng_ahb_clk = {
3490	.halt_reg = 0x13004,
3491	.halt_check = BRANCH_HALT_VOTED,
3492	.clkr = {
3493		.enable_reg = 0x45004,
3494		.enable_mask = BIT(8),
3495		.hw.init = &(struct clk_init_data) {
3496			.name = "gcc_prng_ahb_clk",
3497			.ops = &clk_branch2_ops,
3498		}
3499	}
3500};
3501
3502static struct clk_branch gcc_qdss_dap_clk = {
3503	.halt_reg = 0x29084,
3504	.halt_check = BRANCH_HALT_VOTED,
3505	.clkr = {
3506		.enable_reg = 0x45004,
3507		.enable_mask = BIT(11),
3508		.hw.init = &(struct clk_init_data) {
3509			.name = "gcc_qdss_dap_clk",
3510			.ops = &clk_branch2_ops,
3511		}
3512	}
3513};
3514
3515static struct clk_branch gcc_qusb_ref_clk = {
3516	.halt_reg = 0,
3517	.halt_check = BRANCH_HALT_SKIP,
3518	.clkr = {
3519		.enable_reg = 0x41030,
3520		.enable_mask = BIT(0),
3521		.hw.init = &(struct clk_init_data) {
3522			.name = "gcc_qusb_ref_clk",
3523			.ops = &clk_branch2_ops,
3524		}
3525	}
3526};
3527
3528static struct clk_branch gcc_rbcpr_gfx_clk = {
3529	.halt_reg = 0x3a004,
3530	.halt_check = BRANCH_HALT,
3531	.clkr = {
3532		.enable_reg = 0x3a004,
3533		.enable_mask = BIT(0),
3534		.hw.init = &(struct clk_init_data) {
3535			.name = "gcc_rbcpr_gfx_clk",
3536			.parent_hws = (const struct clk_hw*[]){
3537				&rbcpr_gfx_clk_src.clkr.hw,
3538			},
3539			.num_parents = 1,
3540			.ops = &clk_branch2_ops,
3541			.flags = CLK_SET_RATE_PARENT,
3542		}
3543	}
3544};
3545
3546static struct clk_branch gcc_sdcc1_ice_core_clk = {
3547	.halt_reg = 0x5d014,
3548	.halt_check = BRANCH_HALT,
3549	.clkr = {
3550		.enable_reg = 0x5d014,
3551		.enable_mask = BIT(0),
3552		.hw.init = &(struct clk_init_data) {
3553			.name = "gcc_sdcc1_ice_core_clk",
3554			.parent_hws = (const struct clk_hw*[]){
3555				&sdcc1_ice_core_clk_src.clkr.hw,
3556			},
3557			.num_parents = 1,
3558			.ops = &clk_branch2_ops,
3559			.flags = CLK_SET_RATE_PARENT,
3560		}
3561	}
3562};
3563
3564static struct clk_branch gcc_sdcc1_ahb_clk = {
3565	.halt_reg = 0x4201c,
3566	.halt_check = BRANCH_HALT,
3567	.clkr = {
3568		.enable_reg = 0x4201c,
3569		.enable_mask = BIT(0),
3570		.hw.init = &(struct clk_init_data) {
3571			.name = "gcc_sdcc1_ahb_clk",
3572			.ops = &clk_branch2_ops,
3573		}
3574	}
3575};
3576
3577static struct clk_branch gcc_sdcc2_ahb_clk = {
3578	.halt_reg = 0x4301c,
3579	.halt_check = BRANCH_HALT,
3580	.clkr = {
3581		.enable_reg = 0x4301c,
3582		.enable_mask = BIT(0),
3583		.hw.init = &(struct clk_init_data) {
3584			.name = "gcc_sdcc2_ahb_clk",
3585			.ops = &clk_branch2_ops,
3586		}
3587	}
3588};
3589
3590static struct clk_branch gcc_sdcc1_apps_clk = {
3591	.halt_reg = 0x42018,
3592	.halt_check = BRANCH_HALT,
3593	.clkr = {
3594		.enable_reg = 0x42018,
3595		.enable_mask = BIT(0),
3596		.hw.init = &(struct clk_init_data) {
3597			.name = "gcc_sdcc1_apps_clk",
3598			.parent_hws = (const struct clk_hw*[]){
3599				&sdcc1_apps_clk_src.clkr.hw,
3600			},
3601			.num_parents = 1,
3602			.ops = &clk_branch2_ops,
3603			.flags = CLK_SET_RATE_PARENT,
3604		}
3605	}
3606};
3607
3608static struct clk_branch gcc_sdcc2_apps_clk = {
3609	.halt_reg = 0x43018,
3610	.halt_check = BRANCH_HALT,
3611	.clkr = {
3612		.enable_reg = 0x43018,
3613		.enable_mask = BIT(0),
3614		.hw.init = &(struct clk_init_data) {
3615			.name = "gcc_sdcc2_apps_clk",
3616			.parent_hws = (const struct clk_hw*[]){
3617				&sdcc2_apps_clk_src.clkr.hw,
3618			},
3619			.num_parents = 1,
3620			.ops = &clk_branch2_ops,
3621			.flags = CLK_SET_RATE_PARENT,
3622		}
3623	}
3624};
3625
3626static struct clk_branch gcc_smmu_cfg_clk = {
3627	.halt_reg = 0x12038,
3628	.halt_check = BRANCH_HALT_VOTED,
3629	.clkr = {
3630		.enable_reg = 0x4500c,
3631		.enable_mask = BIT(12),
3632		.hw.init = &(struct clk_init_data) {
3633			.name = "gcc_smmu_cfg_clk",
3634			.ops = &clk_branch2_ops,
3635		}
3636	}
3637};
3638
3639static struct clk_branch gcc_usb30_master_clk = {
3640	.halt_reg = 0x3f000,
3641	.halt_check = BRANCH_HALT,
3642	.clkr = {
3643		.enable_reg = 0x3f000,
3644		.enable_mask = BIT(0),
3645		.hw.init = &(struct clk_init_data) {
3646			.name = "gcc_usb30_master_clk",
3647			.parent_hws = (const struct clk_hw*[]){
3648				&usb30_master_clk_src.clkr.hw,
3649			},
3650			.num_parents = 1,
3651			.ops = &clk_branch2_ops,
3652			.flags = CLK_SET_RATE_PARENT,
3653		}
3654	}
3655};
3656
3657static struct clk_branch gcc_usb30_mock_utmi_clk = {
3658	.halt_reg = 0x3f008,
3659	.halt_check = BRANCH_HALT,
3660	.clkr = {
3661		.enable_reg = 0x3f008,
3662		.enable_mask = BIT(0),
3663		.hw.init = &(struct clk_init_data) {
3664			.name = "gcc_usb30_mock_utmi_clk",
3665			.parent_hws = (const struct clk_hw*[]){
3666				&usb30_mock_utmi_clk_src.clkr.hw,
3667			},
3668			.num_parents = 1,
3669			.ops = &clk_branch2_ops,
3670			.flags = CLK_SET_RATE_PARENT,
3671		}
3672	}
3673};
3674
3675static struct clk_branch gcc_usb30_sleep_clk = {
3676	.halt_reg = 0x3f004,
3677	.halt_check = BRANCH_HALT,
3678	.clkr = {
3679		.enable_reg = 0x3f004,
3680		.enable_mask = BIT(0),
3681		.hw.init = &(struct clk_init_data) {
3682			.name = "gcc_usb30_sleep_clk",
3683			.ops = &clk_branch2_ops,
3684		}
3685	}
3686};
3687
3688static struct clk_branch gcc_usb3_aux_clk = {
3689	.halt_reg = 0x3f044,
3690	.halt_check = BRANCH_HALT,
3691	.clkr = {
3692		.enable_reg = 0x3f044,
3693		.enable_mask = BIT(0),
3694		.hw.init = &(struct clk_init_data) {
3695			.name = "gcc_usb3_aux_clk",
3696			.parent_hws = (const struct clk_hw*[]){
3697				&usb3_aux_clk_src.clkr.hw,
3698			},
3699			.num_parents = 1,
3700			.ops = &clk_branch2_ops,
3701			.flags = CLK_SET_RATE_PARENT,
3702		}
3703	}
3704};
3705
3706static struct clk_branch gcc_usb3_pipe_clk = {
3707	.halt_reg = 0,
3708	.halt_check = BRANCH_HALT_DELAY,
3709	.clkr = {
3710		.enable_reg = 0x3f040,
3711		.enable_mask = BIT(0),
3712		.hw.init = &(struct clk_init_data) {
3713			.name = "gcc_usb3_pipe_clk",
3714			.ops = &clk_branch2_ops,
3715		}
3716	}
3717};
3718
3719static struct clk_branch gcc_usb_phy_cfg_ahb_clk = {
3720	.halt_reg = 0x3f080,
3721	.halt_check = BRANCH_VOTED,
3722	.clkr = {
3723		.enable_reg = 0x3f080,
3724		.enable_mask = BIT(0),
3725		.hw.init = &(struct clk_init_data) {
3726			.name = "gcc_usb_phy_cfg_ahb_clk",
3727			.ops = &clk_branch2_ops,
3728		}
3729	}
3730};
3731
3732static struct clk_branch gcc_usb_ss_ref_clk = {
3733	.halt_reg = 0,
3734	.halt_check = BRANCH_HALT_SKIP,
3735	.clkr = {
3736		.enable_reg = 0x3f07c,
3737		.enable_mask = BIT(0),
3738		.hw.init = &(struct clk_init_data) {
3739			.name = "gcc_usb_ss_ref_clk",
3740			.ops = &clk_branch2_ops,
3741		}
3742	}
3743};
3744
3745static struct clk_branch gcc_venus0_ahb_clk = {
3746	.halt_reg = 0x4c020,
3747	.halt_check = BRANCH_HALT,
3748	.clkr = {
3749		.enable_reg = 0x4c020,
3750		.enable_mask = BIT(0),
3751		.hw.init = &(struct clk_init_data) {
3752			.name = "gcc_venus0_ahb_clk",
3753			.ops = &clk_branch2_ops,
3754		}
3755	}
3756};
3757
3758static struct clk_branch gcc_venus0_axi_clk = {
3759	.halt_reg = 0x4c024,
3760	.halt_check = BRANCH_HALT,
3761	.clkr = {
3762		.enable_reg = 0x4c024,
3763		.enable_mask = BIT(0),
3764		.hw.init = &(struct clk_init_data) {
3765			.name = "gcc_venus0_axi_clk",
3766			.ops = &clk_branch2_ops,
3767		}
3768	}
3769};
3770
3771static struct clk_branch gcc_venus0_core0_vcodec0_clk = {
3772	.halt_reg = 0x4c02c,
3773	.halt_check = BRANCH_HALT,
3774	.clkr = {
3775		.enable_reg = 0x4c02c,
3776		.enable_mask = BIT(0),
3777		.hw.init = &(struct clk_init_data) {
3778			.name = "gcc_venus0_core0_vcodec0_clk",
3779			.parent_hws = (const struct clk_hw*[]){
3780				&vcodec0_clk_src.clkr.hw,
3781			},
3782			.num_parents = 1,
3783			.ops = &clk_branch2_ops,
3784			.flags = CLK_SET_RATE_PARENT,
3785		}
3786	}
3787};
3788
3789static struct clk_branch gcc_venus0_vcodec0_clk = {
3790	.halt_reg = 0x4c01c,
3791	.halt_check = BRANCH_HALT,
3792	.clkr = {
3793		.enable_reg = 0x4c01c,
3794		.enable_mask = BIT(0),
3795		.hw.init = &(struct clk_init_data) {
3796			.name = "gcc_venus0_vcodec0_clk",
3797			.parent_hws = (const struct clk_hw*[]){
3798				&vcodec0_clk_src.clkr.hw,
3799			},
3800			.num_parents = 1,
3801			.ops = &clk_branch2_ops,
3802			.flags = CLK_SET_RATE_PARENT,
3803		}
3804	}
3805};
3806
3807static struct clk_branch gcc_venus_tbu_clk = {
3808	.halt_reg = 0x12014,
3809	.halt_check = BRANCH_HALT_VOTED,
3810	.clkr = {
3811		.enable_reg = 0x4500c,
3812		.enable_mask = BIT(5),
3813		.hw.init = &(struct clk_init_data) {
3814			.name = "gcc_venus_tbu_clk",
3815			.ops = &clk_branch2_ops,
3816		}
3817	}
3818};
3819
3820static struct clk_branch gcc_vfe1_tbu_clk = {
3821	.halt_reg = 0x12090,
3822	.halt_check = BRANCH_HALT_VOTED,
3823	.clkr = {
3824		.enable_reg = 0x4500c,
3825		.enable_mask = BIT(17),
3826		.hw.init = &(struct clk_init_data) {
3827			.name = "gcc_vfe1_tbu_clk",
3828			.ops = &clk_branch2_ops,
3829		}
3830	}
3831};
3832
3833static struct clk_branch gcc_vfe_tbu_clk = {
3834	.halt_reg = 0x1203c,
3835	.halt_check = BRANCH_HALT_VOTED,
3836	.clkr = {
3837		.enable_reg = 0x4500c,
3838		.enable_mask = BIT(9),
3839		.hw.init = &(struct clk_init_data) {
3840			.name = "gcc_vfe_tbu_clk",
3841			.ops = &clk_branch2_ops,
3842		}
3843	}
3844};
3845
3846static struct gdsc usb30_gdsc = {
3847	.gdscr = 0x3f078,
3848	.pd = {
3849		.name = "usb30_gdsc",
3850	},
3851	.pwrsts = PWRSTS_OFF_ON,
3852	/*
3853	 * FIXME: dwc3 usb gadget cannot resume after GDSC power off
3854	 * dwc3 7000000.dwc3: failed to enable ep0out
3855	 */
3856	.flags = ALWAYS_ON,
3857};
3858
3859static struct gdsc venus_gdsc = {
3860	.gdscr = 0x4c018,
3861	.cxcs = (unsigned int []){ 0x4c024, 0x4c01c },
3862	.cxc_count = 2,
3863	.pd = {
3864		.name = "venus_gdsc",
3865	},
3866	.pwrsts = PWRSTS_OFF_ON,
3867};
3868
3869static struct gdsc venus_core0_gdsc = {
3870	.gdscr = 0x4c028,
3871	.cxcs = (unsigned int []){ 0x4c02c },
3872	.cxc_count = 1,
3873	.pd = {
3874		.name = "venus_core0",
3875	},
3876	.flags = HW_CTRL,
3877	.pwrsts = PWRSTS_OFF_ON,
3878};
3879
3880static struct gdsc mdss_gdsc = {
3881	.gdscr = 0x4d078,
3882	.cxcs = (unsigned int []){ 0x4d080, 0x4d088 },
3883	.cxc_count = 2,
3884	.pd = {
3885		.name = "mdss_gdsc",
3886	},
3887	.pwrsts = PWRSTS_OFF_ON,
3888};
3889
3890static struct gdsc jpeg_gdsc = {
3891	.gdscr = 0x5701c,
3892	.cxcs = (unsigned int []){ 0x57020, 0x57028 },
3893	.cxc_count = 2,
3894	.pd = {
3895		.name = "jpeg_gdsc",
3896	},
3897	.pwrsts = PWRSTS_OFF_ON,
3898};
3899
3900static struct gdsc vfe0_gdsc = {
3901	.gdscr = 0x58034,
3902	.cxcs = (unsigned int []){ 0x58038, 0x58048, 0x5600c, 0x58050 },
3903	.cxc_count = 4,
3904	.pd = {
3905		.name = "vfe0_gdsc",
3906	},
3907	.pwrsts = PWRSTS_OFF_ON,
3908};
3909
3910static struct gdsc vfe1_gdsc = {
3911	.gdscr = 0x5806c,
3912	.cxcs = (unsigned int []){ 0x5805c, 0x58068, 0x5600c, 0x58074 },
3913	.cxc_count = 4,
3914	.pd = {
3915		.name = "vfe1_gdsc",
3916	},
3917	.pwrsts = PWRSTS_OFF_ON,
3918};
3919
3920static struct gdsc oxili_gx_gdsc = {
3921	.gdscr = 0x5901c,
3922	.clamp_io_ctrl = 0x5b00c,
3923	.cxcs = (unsigned int []){ 0x59000, 0x59024 },
3924	.cxc_count = 2,
3925	.pd = {
3926		.name = "oxili_gx_gdsc",
3927	},
3928	.pwrsts = PWRSTS_OFF_ON,
3929	.flags = CLAMP_IO,
3930};
3931
3932static struct gdsc oxili_cx_gdsc = {
3933	.gdscr = 0x5904c,
3934	.cxcs = (unsigned int []){ 0x59020 },
3935	.cxc_count = 1,
3936	.pd = {
3937		.name = "oxili_cx_gdsc",
3938	},
3939	.pwrsts = PWRSTS_OFF_ON,
3940};
3941
3942static struct gdsc cpp_gdsc = {
3943	.gdscr = 0x58078,
3944	.cxcs = (unsigned int []){ 0x5803c, 0x58064 },
3945	.cxc_count = 2,
3946	.pd = {
3947		.name = "cpp_gdsc",
3948	},
3949	.flags = ALWAYS_ON,
3950	.pwrsts = PWRSTS_OFF_ON,
3951};
3952
3953static struct clk_hw *gcc_msm8953_hws[] = {
3954	&gpll0_early_div.hw,
3955	&gpll6_early_div.hw,
3956};
3957
3958static struct clk_regmap *gcc_msm8953_clocks[] = {
3959	[GPLL0] = &gpll0.clkr,
3960	[GPLL0_EARLY] = &gpll0_early.clkr,
3961	[GPLL2] = &gpll2.clkr,
3962	[GPLL2_EARLY] = &gpll2_early.clkr,
3963	[GPLL3] = &gpll3.clkr,
3964	[GPLL3_EARLY] = &gpll3_early.clkr,
3965	[GPLL4] = &gpll4.clkr,
3966	[GPLL4_EARLY] = &gpll4_early.clkr,
3967	[GPLL6] = &gpll6.clkr,
3968	[GPLL6_EARLY] = &gpll6_early.clkr,
3969	[GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,
3970	[GCC_APSS_AXI_CLK] = &gcc_apss_axi_clk.clkr,
3971	[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3972	[GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
3973	[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3974	[GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
3975	[GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
3976	[GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
3977	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3978	[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
3979	[GCC_APSS_TCU_ASYNC_CLK] = &gcc_apss_tcu_async_clk.clkr,
3980	[GCC_CPP_TBU_CLK] = &gcc_cpp_tbu_clk.clkr,
3981	[GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr,
3982	[GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
3983	[GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
3984	[GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr,
3985	[GCC_VFE1_TBU_CLK] = &gcc_vfe1_tbu_clk.clkr,
3986	[GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
3987	[CAMSS_TOP_AHB_CLK_SRC] = &camss_top_ahb_clk_src.clkr,
3988	[CSI0_CLK_SRC] = &csi0_clk_src.clkr,
3989	[APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
3990	[CSI1_CLK_SRC] = &csi1_clk_src.clkr,
3991	[CSI2_CLK_SRC] = &csi2_clk_src.clkr,
3992	[VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
3993	[VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
3994	[CPP_CLK_SRC] = &cpp_clk_src.clkr,
3995	[JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
3996	[USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
3997	[VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
3998	[APC0_DROOP_DETECTOR_CLK_SRC] = &apc0_droop_detector_clk_src.clkr,
3999	[APC1_DROOP_DETECTOR_CLK_SRC] = &apc1_droop_detector_clk_src.clkr,
4000	[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
4001	[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
4002	[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
4003	[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
4004	[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
4005	[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
4006	[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
4007	[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
4008	[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
4009	[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
4010	[BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
4011	[BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
4012	[BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
4013	[BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
4014	[BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
4015	[BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
4016	[BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
4017	[BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
4018	[BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
4019	[BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
4020	[CCI_CLK_SRC] = &cci_clk_src.clkr,
4021	[CSI0P_CLK_SRC] = &csi0p_clk_src.clkr,
4022	[CSI1P_CLK_SRC] = &csi1p_clk_src.clkr,
4023	[CSI2P_CLK_SRC] = &csi2p_clk_src.clkr,
4024	[CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
4025	[CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
4026	[MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
4027	[MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
4028	[MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
4029	[MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
4030	[CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
4031	[CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
4032	[CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
4033	[CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
4034	[GP1_CLK_SRC] = &gp1_clk_src.clkr,
4035	[GP2_CLK_SRC] = &gp2_clk_src.clkr,
4036	[GP3_CLK_SRC] = &gp3_clk_src.clkr,
4037	[PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
4038	[RBCPR_GFX_CLK_SRC] = &rbcpr_gfx_clk_src.clkr,
4039	[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
4040	[SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
4041	[SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
4042	[USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
4043	[USB3_AUX_CLK_SRC] = &usb3_aux_clk_src.clkr,
4044	[GCC_APC0_DROOP_DETECTOR_GPLL0_CLK] = &gcc_apc0_droop_detector_gpll0_clk.clkr,
4045	[GCC_APC1_DROOP_DETECTOR_GPLL0_CLK] = &gcc_apc1_droop_detector_gpll0_clk.clkr,
4046	[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
4047	[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
4048	[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
4049	[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
4050	[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
4051	[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
4052	[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
4053	[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
4054	[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
4055	[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
4056	[GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
4057	[GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
4058	[GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
4059	[GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
4060	[GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
4061	[GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
4062	[GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
4063	[GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
4064	[GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
4065	[GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
4066	[GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr,
4067	[GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr,
4068	[GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr,
4069	[GCC_CAMSS_CPP_AXI_CLK] = &gcc_camss_cpp_axi_clk.clkr,
4070	[GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr,
4071	[GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,
4072	[GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,
4073	[GCC_CAMSS_CSI0_CSIPHY_3P_CLK] = &gcc_camss_csi0_csiphy_3p_clk.clkr,
4074	[GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr,
4075	[GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,
4076	[GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,
4077	[GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,
4078	[GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,
4079	[GCC_CAMSS_CSI1_CSIPHY_3P_CLK] = &gcc_camss_csi1_csiphy_3p_clk.clkr,
4080	[GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,
4081	[GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
4082	[GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
4083	[GCC_CAMSS_CSI2_AHB_CLK] = &gcc_camss_csi2_ahb_clk.clkr,
4084	[GCC_CAMSS_CSI2_CLK] = &gcc_camss_csi2_clk.clkr,
4085	[GCC_CAMSS_CSI2_CSIPHY_3P_CLK] = &gcc_camss_csi2_csiphy_3p_clk.clkr,
4086	[GCC_CAMSS_CSI2PHY_CLK] = &gcc_camss_csi2phy_clk.clkr,
4087	[GCC_CAMSS_CSI2PIX_CLK] = &gcc_camss_csi2pix_clk.clkr,
4088	[GCC_CAMSS_CSI2RDI_CLK] = &gcc_camss_csi2rdi_clk.clkr,
4089	[GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
4090	[GCC_CAMSS_CSI_VFE1_CLK] = &gcc_camss_csi_vfe1_clk.clkr,
4091	[GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
4092	[GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,
4093	[GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,
4094	[GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr,
4095	[GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr,
4096	[GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr,
4097	[GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
4098	[GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
4099	[GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr,
4100	[GCC_CAMSS_MCLK3_CLK] = &gcc_camss_mclk3_clk.clkr,
4101	[GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr,
4102	[GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
4103	[GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
4104	[GCC_CAMSS_CSI2PHYTIMER_CLK] = &gcc_camss_csi2phytimer_clk.clkr,
4105	[GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr,
4106	[GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
4107	[GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,
4108	[GCC_CAMSS_VFE0_AHB_CLK] = &gcc_camss_vfe0_ahb_clk.clkr,
4109	[GCC_CAMSS_VFE0_AXI_CLK] = &gcc_camss_vfe0_axi_clk.clkr,
4110	[GCC_CAMSS_VFE1_AHB_CLK] = &gcc_camss_vfe1_ahb_clk.clkr,
4111	[GCC_CAMSS_VFE1_AXI_CLK] = &gcc_camss_vfe1_axi_clk.clkr,
4112	[GCC_CAMSS_VFE1_CLK] = &gcc_camss_vfe1_clk.clkr,
4113	[GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
4114	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
4115	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
4116	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
4117	[GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
4118	[GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
4119	[GCC_PCNOC_USB3_AXI_CLK] = &gcc_pcnoc_usb3_axi_clk.clkr,
4120	[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
4121	[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
4122	[GCC_RBCPR_GFX_CLK] = &gcc_rbcpr_gfx_clk.clkr,
4123	[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
4124	[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
4125	[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
4126	[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
4127	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
4128	[GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
4129	[GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
4130	[GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
4131	[GCC_USB3_AUX_CLK] = &gcc_usb3_aux_clk.clkr,
4132	[GCC_USB_PHY_CFG_AHB_CLK] = &gcc_usb_phy_cfg_ahb_clk.clkr,
4133	[GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr,
4134	[GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr,
4135	[GCC_VENUS0_CORE0_VCODEC0_CLK] = &gcc_venus0_core0_vcodec0_clk.clkr,
4136	[GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
4137	[GCC_QUSB_REF_CLK] = &gcc_qusb_ref_clk.clkr,
4138	[GCC_USB_SS_REF_CLK] = &gcc_usb_ss_ref_clk.clkr,
4139	[GCC_USB3_PIPE_CLK] = &gcc_usb3_pipe_clk.clkr,
4140	[MDP_CLK_SRC] = &mdp_clk_src.clkr,
4141	[PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
4142	[BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
4143	[ESC0_CLK_SRC] = &esc0_clk_src.clkr,
4144	[PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
4145	[BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
4146	[ESC1_CLK_SRC] = &esc1_clk_src.clkr,
4147	[VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
4148	[GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
4149	[GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
4150	[GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
4151	[GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
4152	[GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
4153	[GCC_MDSS_PCLK1_CLK] = &gcc_mdss_pclk1_clk.clkr,
4154	[GCC_MDSS_BYTE1_CLK] = &gcc_mdss_byte1_clk.clkr,
4155	[GCC_MDSS_ESC1_CLK] = &gcc_mdss_esc1_clk.clkr,
4156	[GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
4157	[GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
4158	[GCC_OXILI_TIMER_CLK] = &gcc_oxili_timer_clk.clkr,
4159	[GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
4160	[GCC_OXILI_AON_CLK] = &gcc_oxili_aon_clk.clkr,
4161	[GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
4162	[GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
4163	[GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
4164	[GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
4165};
4166
4167static const struct qcom_reset_map gcc_msm8953_resets[] = {
4168	[GCC_CAMSS_MICRO_BCR]	= { 0x56008 },
4169	[GCC_MSS_BCR]		= { 0x71000 },
4170	[GCC_QUSB2_PHY_BCR]	= { 0x4103c },
4171	[GCC_USB3PHY_PHY_BCR]	= { 0x3f03c },
4172	[GCC_USB3_PHY_BCR]	= { 0x3f034 },
4173	[GCC_USB_30_BCR]	= { 0x3f070 },
4174};
4175
4176static const struct regmap_config gcc_msm8953_regmap_config = {
4177	.reg_bits	= 32,
4178	.reg_stride	= 4,
4179	.val_bits	= 32,
4180	.max_register	= 0x80000,
4181	.fast_io	= true,
4182};
4183
4184static struct gdsc *gcc_msm8953_gdscs[] = {
4185	[CPP_GDSC] = &cpp_gdsc,
4186	[JPEG_GDSC] = &jpeg_gdsc,
4187	[MDSS_GDSC] = &mdss_gdsc,
4188	[OXILI_CX_GDSC] = &oxili_cx_gdsc,
4189	[OXILI_GX_GDSC] = &oxili_gx_gdsc,
4190	[USB30_GDSC] = &usb30_gdsc,
4191	[VENUS_CORE0_GDSC] = &venus_core0_gdsc,
4192	[VENUS_GDSC] = &venus_gdsc,
4193	[VFE0_GDSC] = &vfe0_gdsc,
4194	[VFE1_GDSC] = &vfe1_gdsc,
4195};
4196
4197static const struct qcom_cc_desc gcc_msm8953_desc = {
4198	.config = &gcc_msm8953_regmap_config,
4199	.clks = gcc_msm8953_clocks,
4200	.num_clks = ARRAY_SIZE(gcc_msm8953_clocks),
4201	.resets = gcc_msm8953_resets,
4202	.num_resets = ARRAY_SIZE(gcc_msm8953_resets),
4203	.gdscs = gcc_msm8953_gdscs,
4204	.num_gdscs = ARRAY_SIZE(gcc_msm8953_gdscs),
4205	.clk_hws = gcc_msm8953_hws,
4206	.num_clk_hws = ARRAY_SIZE(gcc_msm8953_hws),
4207};
4208
4209static int gcc_msm8953_probe(struct platform_device *pdev)
4210{
4211	struct regmap *regmap;
4212
4213	regmap  = qcom_cc_map(pdev, &gcc_msm8953_desc);
4214	if (IS_ERR(regmap))
4215		return PTR_ERR(regmap);
4216
4217	clk_alpha_pll_configure(&gpll3_early, regmap, &gpll3_early_config);
4218
4219	return qcom_cc_really_probe(pdev, &gcc_msm8953_desc, regmap);
4220}
4221
4222static const struct of_device_id gcc_msm8953_match_table[] = {
4223	{ .compatible = "qcom,gcc-msm8953" },
4224	{},
4225};
4226
4227static struct platform_driver gcc_msm8953_driver = {
4228	.probe = gcc_msm8953_probe,
4229	.driver = {
4230		.name = "gcc-msm8953",
4231		.of_match_table = gcc_msm8953_match_table,
4232	},
4233};
4234
4235static int __init gcc_msm8953_init(void)
4236{
4237	return platform_driver_register(&gcc_msm8953_driver);
4238}
4239core_initcall(gcc_msm8953_init);
4240
4241static void __exit gcc_msm8953_exit(void)
4242{
4243	platform_driver_unregister(&gcc_msm8953_driver);
4244}
4245module_exit(gcc_msm8953_exit);
4246
4247MODULE_DESCRIPTION("Qualcomm GCC MSM8953 Driver");
4248MODULE_LICENSE("GPL v2");