1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2/*
   3 * Copyright (c) 2023 The Linux Foundation. All rights reserved.
   4 */
   5
   6#include <linux/clk-provider.h>
   7#include <linux/kernel.h>
   8#include <linux/module.h>
   9#include <linux/of.h>
  10#include <linux/platform_device.h>
  11#include <linux/regmap.h>
  12
  13#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
  14#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
  15
  16#include "clk-alpha-pll.h"
  17#include "clk-branch.h"
  18#include "clk-rcg.h"
  19#include "clk-regmap.h"
  20#include "clk-regmap-divider.h"
  21#include "clk-regmap-mux.h"
  22#include "clk-regmap-phy-mux.h"
  23#include "common.h"
  24#include "reset.h"
  25
  26/* Need to match the order of clocks in DT binding */
  27enum {
  28	DT_XO,
  29	DT_SLEEP_CLK,
  30	DT_BIAS_PLL_UBI_NC_CLK,
  31	DT_PCIE30_PHY0_PIPE_CLK,
  32	DT_PCIE30_PHY1_PIPE_CLK,
  33	DT_PCIE30_PHY2_PIPE_CLK,
  34	DT_PCIE30_PHY3_PIPE_CLK,
  35	DT_USB3PHY_0_CC_PIPE_CLK,
  36};
  37
  38enum {
  39	P_XO,
  40	P_PCIE30_PHY0_PIPE,
  41	P_PCIE30_PHY1_PIPE,
  42	P_PCIE30_PHY2_PIPE,
  43	P_PCIE30_PHY3_PIPE,
  44	P_USB3PHY_0_PIPE,
  45	P_GPLL0,
  46	P_GPLL0_DIV2,
  47	P_GPLL0_OUT_AUX,
  48	P_GPLL2,
  49	P_GPLL4,
  50	P_PI_SLEEP,
  51	P_BIAS_PLL_UBI_NC_CLK,
  52};
  53
  54static const struct parent_map gcc_xo_map[] = {
  55	{ P_XO, 0 },
  56};
  57
  58static const struct clk_parent_data gcc_xo_data[] = {
  59	{ .index = DT_XO },
  60};
  61
  62static const struct clk_parent_data gcc_sleep_clk_data[] = {
  63	{ .index = DT_SLEEP_CLK },
  64};
  65
  66static struct clk_alpha_pll gpll0_main = {
  67	.offset = 0x20000,
  68	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  69	.clkr = {
  70		.enable_reg = 0x0b000,
  71		.enable_mask = BIT(0),
  72		.hw.init = &(const struct clk_init_data) {
  73			.name = "gpll0_main",
  74			.parent_data = gcc_xo_data,
  75			.num_parents = ARRAY_SIZE(gcc_xo_data),
  76			.ops = &clk_alpha_pll_ops,
  77		},
  78	},
  79};
  80
  81static struct clk_fixed_factor gpll0_out_main_div2 = {
  82	.mult = 1,
  83	.div = 2,
  84	.hw.init = &(const struct clk_init_data) {
  85		.name = "gpll0_out_main_div2",
  86		.parent_hws = (const struct clk_hw *[]) {
  87			&gpll0_main.clkr.hw
  88		},
  89		.num_parents = 1,
  90		.ops = &clk_fixed_factor_ops,
  91	},
  92};
  93
  94static struct clk_alpha_pll_postdiv gpll0 = {
  95	.offset = 0x20000,
  96	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  97	.width = 4,
  98	.clkr.hw.init = &(const struct clk_init_data) {
  99		.name = "gpll0",
 100		.parent_hws = (const struct clk_hw *[]) {
 101			&gpll0_main.clkr.hw
 102		},
 103		.num_parents = 1,
 104		.ops = &clk_alpha_pll_postdiv_ro_ops,
 105	},
 106};
 107
 108static struct clk_alpha_pll gpll4_main = {
 109	.offset = 0x22000,
 110	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 111	.clkr = {
 112		.enable_reg = 0x0b000,
 113		.enable_mask = BIT(2),
 114		.hw.init = &(const struct clk_init_data) {
 115			.name = "gpll4_main",
 116			.parent_data = gcc_xo_data,
 117			.num_parents = ARRAY_SIZE(gcc_xo_data),
 118			.ops = &clk_alpha_pll_ops,
 119		},
 120	},
 121};
 122
 123static struct clk_alpha_pll_postdiv gpll4 = {
 124	.offset = 0x22000,
 125	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 126	.width = 4,
 127	.clkr.hw.init = &(const struct clk_init_data) {
 128		.name = "gpll4",
 129		.parent_hws = (const struct clk_hw *[]) {
 130			&gpll4_main.clkr.hw
 131		},
 132		.num_parents = 1,
 133		.ops = &clk_alpha_pll_postdiv_ro_ops,
 134	},
 135};
 136
 137static struct clk_alpha_pll gpll2_main = {
 138	.offset = 0x21000,
 139	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 140	.clkr = {
 141		.enable_reg = 0x0b000,
 142		.enable_mask = BIT(1),
 143		.hw.init = &(const struct clk_init_data) {
 144			.name = "gpll2_main",
 145			.parent_data = gcc_xo_data,
 146			.num_parents = ARRAY_SIZE(gcc_xo_data),
 147			.ops = &clk_alpha_pll_ops,
 148		},
 149	},
 150};
 151
 152static struct clk_alpha_pll_postdiv gpll2 = {
 153	.offset = 0x21000,
 154	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 155	.width = 4,
 156	.clkr.hw.init = &(const struct clk_init_data) {
 157		.name = "gpll2",
 158		.parent_hws = (const struct clk_hw *[]) {
 159			&gpll2_main.clkr.hw
 160		},
 161		.num_parents = 1,
 162		.ops = &clk_alpha_pll_postdiv_ro_ops,
 163	},
 164};
 165
 166static struct clk_branch gcc_sleep_clk_src = {
 167	.halt_reg = 0x3400c,
 168	.clkr = {
 169		.enable_reg = 0x3400c,
 170		.enable_mask = BIT(1),
 171		.hw.init = &(const struct clk_init_data) {
 172			.name = "gcc_sleep_clk_src",
 173			.parent_data = gcc_sleep_clk_data,
 174			.num_parents = ARRAY_SIZE(gcc_sleep_clk_data),
 175			.flags = CLK_IS_CRITICAL,
 176			.ops = &clk_branch2_ops,
 177		},
 178	},
 179};
 180
 181static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = {
 182	{ .index = DT_XO },
 183	{ .hw = &gpll0.clkr.hw },
 184	{ .hw = &gpll0_out_main_div2.hw },
 185};
 186
 187static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
 188	{ P_XO, 0 },
 189	{ P_GPLL0, 1 },
 190	{ P_GPLL0_DIV2, 4 },
 191};
 192
 193static const struct clk_parent_data gcc_xo_gpll0[] = {
 194	{ .index = DT_XO },
 195	{ .hw = &gpll0.clkr.hw },
 196};
 197
 198static const struct parent_map gcc_xo_gpll0_map[] = {
 199	{ P_XO, 0 },
 200	{ P_GPLL0, 1 },
 201};
 202
 203static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
 204	{ .index = DT_XO },
 205	{ .hw = &gpll0.clkr.hw },
 206	{ .hw = &gpll4.clkr.hw },
 207};
 208
 209static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
 210	{ P_XO, 0 },
 211	{ P_GPLL0, 1 },
 212	{ P_GPLL4, 2 },
 213};
 214
 215static const struct clk_parent_data gcc_xo_gpll0_gpll0_div2_gpll0[] = {
 216	{ .index = DT_XO },
 217	{ .hw = &gpll0.clkr.hw },
 218	{ .hw = &gpll0_out_main_div2.hw },
 219	{ .hw = &gpll0.clkr.hw },
 220};
 221
 222static const struct parent_map gcc_xo_gpll0_gpll0_div2_gpll0_map[] = {
 223	{ P_XO, 0 },
 224	{ P_GPLL0, 1 },
 225	{ P_GPLL0_DIV2, 4 },
 226	{ P_GPLL0, 5 },
 227};
 228
 229static const struct clk_parent_data gcc_xo_gpll0_gpll0_sleep_clk[] = {
 230	{ .index = DT_XO },
 231	{ .hw = &gpll0.clkr.hw },
 232	{ .hw = &gpll0_out_main_div2.hw },
 233	{ .index = DT_SLEEP_CLK },
 234};
 235
 236static const struct parent_map gcc_xo_gpll0_gpll0_sleep_clk_map[] = {
 237	{ P_XO, 0 },
 238	{ P_GPLL0, 1 },
 239	{ P_GPLL0_DIV2, 4 },
 240	{ P_PI_SLEEP, 6 },
 241};
 242
 243static const struct clk_parent_data gcc_xo_gpll0_core_pi_sleep_clk[] = {
 244	{ .index = DT_XO },
 245	{ .hw = &gpll0.clkr.hw },
 246	{ .index = DT_SLEEP_CLK },
 247};
 248
 249static const struct parent_map gcc_xo_gpll0_core_pi_sleep_clk_map[] = {
 250	{ P_XO, 0 },
 251	{ P_GPLL0, 2 },
 252	{ P_PI_SLEEP, 6 },
 253};
 254
 255static const struct clk_parent_data gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk[] = {
 256	{ .index = DT_XO },
 257	{ .hw = &gpll0.clkr.hw },
 258	{ .hw = &gpll4.clkr.hw },
 259	{ .index = DT_BIAS_PLL_UBI_NC_CLK },
 260};
 261
 262static const struct parent_map gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk_map[] = {
 263	{ P_XO, 0 },
 264	{ P_GPLL0, 1 },
 265	{ P_GPLL4, 2 },
 266	{ P_BIAS_PLL_UBI_NC_CLK, 3 },
 267};
 268
 269static const struct clk_parent_data
 270			gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk[] = {
 271	{ .index = DT_XO },
 272	{ .hw = &gpll0.clkr.hw },
 273	{ .hw = &gpll0.clkr.hw },
 274	{ .index = DT_SLEEP_CLK },
 275};
 276
 277static const struct parent_map
 278			gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk_map[] = {
 279	{ P_XO, 0 },
 280	{ P_GPLL0, 1 },
 281	{ P_GPLL0_OUT_AUX, 2 },
 282	{ P_PI_SLEEP, 6 },
 283};
 284
 285static const struct clk_parent_data gcc_xo_gpll0_out_main_div2_gpll0[] = {
 286	{ .index = DT_XO },
 287	{ .hw = &gpll0.clkr.hw },
 288	{ .hw = &gpll0_out_main_div2.hw },
 289};
 290
 291static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
 292	{ P_XO, 0 },
 293	{ P_GPLL0, 1 },
 294	{ P_GPLL0_DIV2, 4 },
 295};
 296
 297static const struct clk_parent_data
 298			gcc_xo_gpll4_gpll0_gpll0_out_main_div2[] = {
 299	{ .index = DT_XO },
 300	{ .hw = &gpll4.clkr.hw },
 301	{ .hw = &gpll0.clkr.hw },
 302	{ .hw = &gpll0_out_main_div2.hw },
 303};
 304
 305static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map[] = {
 306	{ P_XO, 0 },
 307	{ P_GPLL4, 1 },
 308	{ P_GPLL0, 3 },
 309	{ P_GPLL0_DIV2, 4 },
 310};
 311
 312static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
 313	{ .index = DT_USB3PHY_0_CC_PIPE_CLK },
 314	{ .index = DT_XO },
 315};
 316
 317static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
 318	{ P_USB3PHY_0_PIPE, 0 },
 319	{ P_XO, 2 },
 320};
 321
 322static const struct clk_parent_data
 323			gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
 324	{ .index = DT_XO },
 325	{ .hw = &gpll0.clkr.hw },
 326	{ .hw = &gpll2.clkr.hw },
 327	{ .hw = &gpll0_out_main_div2.hw },
 328};
 329
 330static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
 331	{ P_XO, 0 },
 332	{ P_GPLL0, 1 },
 333	{ P_GPLL2, 2 },
 334	{ P_GPLL0_DIV2, 4 },
 335};
 336
 337static const struct clk_parent_data gcc_xo_gpll0_gpll4_gpll0_div2[] = {
 338	{ .index = DT_XO},
 339	{ .hw = &gpll0.clkr.hw },
 340	{ .hw = &gpll4.clkr.hw },
 341	{ .hw = &gpll0_out_main_div2.hw },
 342};
 343
 344static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_div2_map[] = {
 345	{ P_XO, 0 },
 346	{ P_GPLL0, 1 },
 347	{ P_GPLL4, 2 },
 348	{ P_GPLL0_DIV2, 4 },
 349};
 350
 351static const struct clk_parent_data gcc_xo_gpll4_gpll0_gpll0_div2[] = {
 352	{ .index = DT_XO },
 353	{ .hw = &gpll4.clkr.hw },
 354	{ .hw = &gpll0.clkr.hw },
 355	{ .hw = &gpll0_out_main_div2.hw },
 356};
 357
 358static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_div2_map[] = {
 359	{ P_XO, 0 },
 360	{ P_GPLL4, 1 },
 361	{ P_GPLL0, 2 },
 362	{ P_GPLL0_DIV2, 4 },
 363};
 364
 365static const struct clk_parent_data gcc_xo_gpll0_gpll2[] = {
 366	{ .index = DT_XO },
 367	{ .hw = &gpll0.clkr.hw },
 368	{ .hw = &gpll2.clkr.hw },
 369};
 370
 371static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
 372	{ P_XO, 0 },
 373	{ P_GPLL0, 1 },
 374	{ P_GPLL2, 2 },
 375};
 376
 377static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll4_pi_sleep[] = {
 378	{ .index = DT_XO },
 379	{ .hw = &gpll0.clkr.hw },
 380	{ .hw = &gpll2.clkr.hw },
 381	{ .hw = &gpll4.clkr.hw },
 382	{ .index = DT_SLEEP_CLK },
 383};
 384
 385static const struct parent_map gcc_xo_gpll0_gpll2_gpll4_pi_sleep_map[] = {
 386	{ P_XO, 0 },
 387	{ P_GPLL0, 1 },
 388	{ P_GPLL2, 2 },
 389	{ P_GPLL4, 3 },
 390	{ P_PI_SLEEP, 6 },
 391};
 392
 393static const struct clk_parent_data gcc_xo_gpll0_gpll0_aux_gpll2[] = {
 394	{ .index = DT_XO },
 395	{ .hw = &gpll0.clkr.hw },
 396	{ .hw = &gpll0.clkr.hw },
 397	{ .hw = &gpll2.clkr.hw },
 398};
 399
 400static const struct parent_map gcc_xo_gpll0_gpll0_aux_gpll2_map[] = {
 401	{ P_XO, 0 },
 402	{ P_GPLL0, 1 },
 403	{ P_GPLL0_OUT_AUX, 2 },
 404	{ P_GPLL2, 3 },
 405};
 406
 407static const struct freq_tbl ftbl_apss_ahb_clk_src[] = {
 408	F(24000000, P_XO, 1, 0, 0),
 409	F(50000000, P_GPLL0, 16, 0, 0),
 410	F(100000000, P_GPLL0, 8, 0, 0),
 411	{ }
 412};
 413
 414static struct clk_rcg2 apss_ahb_clk_src = {
 415	.cmd_rcgr = 0x2400c,
 416	.freq_tbl = ftbl_apss_ahb_clk_src,
 417	.hid_width = 5,
 418	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 419	.clkr.hw.init = &(const struct clk_init_data) {
 420		.name = "apss_ahb_clk_src",
 421		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 422		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 423		.ops = &clk_rcg2_ops,
 424	},
 425};
 426
 427static const struct freq_tbl ftbl_apss_axi_clk_src[] = {
 428	F(533000000, P_GPLL0, 1.5, 0, 0),
 429	{ }
 430};
 431
 432static struct clk_rcg2 apss_axi_clk_src = {
 433	.cmd_rcgr = 0x24004,
 434	.freq_tbl = ftbl_apss_axi_clk_src,
 435	.hid_width = 5,
 436	.parent_map = gcc_xo_gpll0_gpll0_div2_gpll0_map,
 437	.clkr.hw.init = &(const struct clk_init_data) {
 438		.name = "apss_axi_clk_src",
 439		.parent_data = gcc_xo_gpll0_gpll0_div2_gpll0,
 440		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_div2_gpll0),
 441		.ops = &clk_rcg2_ops,
 442	},
 443};
 444
 445static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = {
 446	F(9600000, P_XO, 2.5, 0, 0),
 447	F(24000000, P_XO, 1, 0, 0),
 448	F(50000000, P_GPLL0, 16, 0, 0),
 449	{ }
 450};
 451
 452static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 453	.cmd_rcgr = 0x02018,
 454	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 455	.hid_width = 5,
 456	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 457	.clkr.hw.init = &(const struct clk_init_data) {
 458		.name = "blsp1_qup1_i2c_apps_clk_src",
 459		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 460		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 461		.ops = &clk_rcg2_ops,
 462	},
 463};
 464
 465static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = {
 466	F(960000, P_XO, 10, 2, 5),
 467	F(4800000, P_XO, 5, 0, 0),
 468	F(9600000, P_XO, 2, 4, 5),
 469	F(16000000, P_GPLL0, 10, 1, 5),
 470	F(24000000, P_XO, 1, 0, 0),
 471	F(25000000, P_GPLL0, 16, 1, 2),
 472	F(50000000, P_GPLL0, 16, 0, 0),
 473	{ }
 474};
 475
 476static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 477	.cmd_rcgr = 0x02004,
 478	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 479	.mnd_width = 8,
 480	.hid_width = 5,
 481	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 482	.clkr.hw.init = &(const struct clk_init_data) {
 483		.name = "blsp1_qup1_spi_apps_clk_src",
 484		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 485		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 486		.ops = &clk_rcg2_ops,
 487	},
 488};
 489
 490static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 491	.cmd_rcgr = 0x03018,
 492	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 493	.hid_width = 5,
 494	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 495	.clkr.hw.init = &(const struct clk_init_data) {
 496		.name = "blsp1_qup2_i2c_apps_clk_src",
 497		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 498		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 499		.ops = &clk_rcg2_ops,
 500	},
 501};
 502
 503static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 504	.cmd_rcgr = 0x03004,
 505	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 506	.mnd_width = 8,
 507	.hid_width = 5,
 508	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 509	.clkr.hw.init = &(const struct clk_init_data) {
 510		.name = "blsp1_qup2_spi_apps_clk_src",
 511		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 512		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 513		.ops = &clk_rcg2_ops,
 514	},
 515};
 516
 517static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 518	.cmd_rcgr = 0x04018,
 519	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 520	.hid_width = 5,
 521	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 522	.clkr.hw.init = &(const struct clk_init_data) {
 523		.name = "blsp1_qup3_i2c_apps_clk_src",
 524		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 525		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 526		.ops = &clk_rcg2_ops,
 527	},
 528};
 529
 530static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 531	.cmd_rcgr = 0x04004,
 532	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 533	.mnd_width = 8,
 534	.hid_width = 5,
 535	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 536	.clkr.hw.init = &(const struct clk_init_data) {
 537		.name = "blsp1_qup3_spi_apps_clk_src",
 538		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 539		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 540		.ops = &clk_rcg2_ops,
 541	},
 542};
 543
 544static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 545	.cmd_rcgr = 0x05018,
 546	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 547	.hid_width = 5,
 548	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 549	.clkr.hw.init = &(const struct clk_init_data) {
 550		.name = "blsp1_qup4_i2c_apps_clk_src",
 551		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 552		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 553		.ops = &clk_rcg2_ops,
 554	},
 555};
 556
 557static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 558	.cmd_rcgr = 0x05004,
 559	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 560	.mnd_width = 8,
 561	.hid_width = 5,
 562	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 563	.clkr.hw.init = &(const struct clk_init_data) {
 564		.name = "blsp1_qup4_spi_apps_clk_src",
 565		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 566		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 567		.ops = &clk_rcg2_ops,
 568	},
 569};
 570
 571static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 572	.cmd_rcgr = 0x06018,
 573	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 574	.hid_width = 5,
 575	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 576	.clkr.hw.init = &(const struct clk_init_data) {
 577		.name = "blsp1_qup5_i2c_apps_clk_src",
 578		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 579		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 580		.ops = &clk_rcg2_ops,
 581	},
 582};
 583
 584static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 585	.cmd_rcgr = 0x06004,
 586	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 587	.mnd_width = 8,
 588	.hid_width = 5,
 589	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 590	.clkr.hw.init = &(const struct clk_init_data) {
 591		.name = "blsp1_qup5_spi_apps_clk_src",
 592		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 593		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 594		.ops = &clk_rcg2_ops,
 595	},
 596};
 597
 598static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 599	.cmd_rcgr = 0x07018,
 600	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 601	.hid_width = 5,
 602	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 603	.clkr.hw.init = &(const struct clk_init_data) {
 604		.name = "blsp1_qup6_i2c_apps_clk_src",
 605		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 606		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 607		.ops = &clk_rcg2_ops,
 608	},
 609};
 610
 611static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 612	.cmd_rcgr = 0x07004,
 613	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 614	.mnd_width = 8,
 615	.hid_width = 5,
 616	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 617	.clkr.hw.init = &(const struct clk_init_data) {
 618		.name = "blsp1_qup6_spi_apps_clk_src",
 619		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 620		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 621		.ops = &clk_rcg2_ops,
 622	},
 623};
 624
 625static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = {
 626	F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
 627	F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
 628	F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
 629	F(24000000, P_XO, 1, 0, 0),
 630	F(25000000, P_GPLL0, 16, 1, 2),
 631	F(32000000, P_GPLL0, 1, 1, 25),
 632	F(40000000, P_GPLL0, 1, 1, 20),
 633	F(46400000, P_GPLL0, 1, 29, 500),
 634	F(48000000, P_GPLL0, 1, 3, 50),
 635	F(51200000, P_GPLL0, 1, 8, 125),
 636	F(56000000, P_GPLL0, 1, 7, 100),
 637	F(58982400, P_GPLL0, 1, 1152, 15625),
 638	F(60000000, P_GPLL0, 1, 3, 40),
 639	F(64000000, P_GPLL0, 12.5, 0, 0),
 640	{ }
 641};
 642
 643static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 644	.cmd_rcgr = 0x0202c,
 645	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 646	.mnd_width = 16,
 647	.hid_width = 5,
 648	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 649	.clkr.hw.init = &(const struct clk_init_data) {
 650		.name = "blsp1_uart1_apps_clk_src",
 651		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 652		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 653		.ops = &clk_rcg2_ops,
 654	},
 655};
 656
 657static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 658	.cmd_rcgr = 0x0302c,
 659	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 660	.mnd_width = 16,
 661	.hid_width = 5,
 662	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 663	.clkr.hw.init = &(const struct clk_init_data) {
 664		.name = "blsp1_uart2_apps_clk_src",
 665		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 666		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 667		.ops = &clk_rcg2_ops,
 668	},
 669};
 670
 671static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 672	.cmd_rcgr = 0x0402c,
 673	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 674	.mnd_width = 16,
 675	.hid_width = 5,
 676	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 677	.clkr.hw.init = &(const struct clk_init_data) {
 678		.name = "blsp1_uart3_apps_clk_src",
 679		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 680		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 681		.ops = &clk_rcg2_ops,
 682	},
 683};
 684
 685static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
 686	.cmd_rcgr = 0x0502c,
 687	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 688	.mnd_width = 16,
 689	.hid_width = 5,
 690	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 691	.clkr.hw.init = &(const struct clk_init_data) {
 692		.name = "blsp1_uart4_apps_clk_src",
 693		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 694		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 695		.ops = &clk_rcg2_ops,
 696	},
 697};
 698
 699static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
 700	.cmd_rcgr = 0x0602c,
 701	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 702	.mnd_width = 16,
 703	.hid_width = 5,
 704	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 705	.clkr.hw.init = &(const struct clk_init_data) {
 706		.name = "blsp1_uart5_apps_clk_src",
 707		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 708		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 709		.ops = &clk_rcg2_ops,
 710	},
 711};
 712
 713static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
 714	.cmd_rcgr = 0x0702c,
 715	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 716	.mnd_width = 16,
 717	.hid_width = 5,
 718	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 719	.clkr.hw.init = &(const struct clk_init_data) {
 720		.name = "blsp1_uart6_apps_clk_src",
 721		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 722		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 723		.ops = &clk_rcg2_ops,
 724	},
 725};
 726
 727static const struct freq_tbl ftbl_gcc_crypto_clk_src[] = {
 728	F(160000000, P_GPLL0, 5, 0, 0),
 729	{ }
 730};
 731
 732static struct clk_rcg2 gcc_crypto_clk_src = {
 733	.cmd_rcgr = 0x16004,
 734	.freq_tbl = ftbl_gcc_crypto_clk_src,
 735	.hid_width = 5,
 736	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 737	.clkr.hw.init = &(const struct clk_init_data) {
 738		.name = "gcc_crypto_clk_src",
 739		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 740		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 741		.ops = &clk_rcg2_ops,
 742	},
 743};
 744
 745static struct clk_branch gcc_crypto_clk = {
 746	.halt_reg = 0x1600c,
 747	.halt_check = BRANCH_HALT_VOTED,
 748	.clkr = {
 749		.enable_reg = 0x0b004,
 750		.enable_mask = BIT(14),
 751		.hw.init = &(const struct clk_init_data) {
 752			.name = "gcc_crypto_clk",
 753			.parent_hws = (const struct clk_hw *[]) {
 754				&gcc_crypto_clk_src.clkr.hw },
 755			.num_parents = 1,
 756			.flags = CLK_SET_RATE_PARENT,
 757			.ops = &clk_branch2_ops,
 758		},
 759	},
 760};
 761
 762static struct clk_branch gcc_apss_ahb_clk = {
 763	.halt_reg = 0x24018,
 764	.halt_check = BRANCH_HALT_VOTED,
 765	.clkr = {
 766		.enable_reg = 0x0b004,
 767		.enable_mask = BIT(0),
 768		.hw.init = &(const struct clk_init_data) {
 769			.name = "gcc_apss_ahb_clk",
 770			.parent_hws = (const struct clk_hw *[]) {
 771				&apss_ahb_clk_src.clkr.hw
 772			},
 773			.num_parents = 1,
 774			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
 775			.ops = &clk_branch2_ops,
 776		},
 777	},
 778};
 779
 780static struct clk_branch gcc_apss_axi_clk = {
 781	.halt_reg = 0x2401c,
 782	.halt_check = BRANCH_HALT_VOTED,
 783	.clkr = {
 784		.enable_reg = 0x0b004,
 785		.enable_mask = BIT(1),
 786		.hw.init = &(const struct clk_init_data) {
 787			.name = "gcc_apss_axi_clk",
 788			.parent_hws = (const struct clk_hw *[]) {
 789				&apss_axi_clk_src.clkr.hw
 790			},
 791			.num_parents = 1,
 792			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
 793			.ops = &clk_branch2_ops,
 794		},
 795	},
 796};
 797
 798static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
 799	.halt_reg = 0x2024,
 800	.clkr = {
 801		.enable_reg = 0x2024,
 802		.enable_mask = BIT(0),
 803		.hw.init = &(const struct clk_init_data) {
 804			.name = "gcc_blsp1_qup1_i2c_apps_clk",
 805			.parent_hws = (const struct clk_hw *[]) {
 806				&blsp1_qup1_i2c_apps_clk_src.clkr.hw
 807			},
 808			.num_parents = 1,
 809			.flags = CLK_SET_RATE_PARENT,
 810			.ops = &clk_branch2_ops,
 811		},
 812	},
 813};
 814
 815static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
 816	.halt_reg = 0x02020,
 817	.clkr = {
 818		.enable_reg = 0x02020,
 819		.enable_mask = BIT(0),
 820		.hw.init = &(const struct clk_init_data) {
 821			.name = "gcc_blsp1_qup1_spi_apps_clk",
 822			.parent_hws = (const struct clk_hw *[]) {
 823				&blsp1_qup1_spi_apps_clk_src.clkr.hw
 824			},
 825			.num_parents = 1,
 826			.flags = CLK_SET_RATE_PARENT,
 827			.ops = &clk_branch2_ops,
 828		},
 829	},
 830};
 831
 832static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
 833	.halt_reg = 0x03024,
 834	.clkr = {
 835		.enable_reg = 0x03024,
 836		.enable_mask = BIT(0),
 837		.hw.init = &(const struct clk_init_data) {
 838			.name = "gcc_blsp1_qup2_i2c_apps_clk",
 839			.parent_hws = (const struct clk_hw *[]) {
 840				&blsp1_qup2_i2c_apps_clk_src.clkr.hw
 841			},
 842			.num_parents = 1,
 843			.flags = CLK_SET_RATE_PARENT,
 844			.ops = &clk_branch2_ops,
 845		},
 846	},
 847};
 848
 849static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
 850	.halt_reg = 0x03020,
 851	.clkr = {
 852		.enable_reg = 0x03020,
 853		.enable_mask = BIT(0),
 854		.hw.init = &(const struct clk_init_data) {
 855			.name = "gcc_blsp1_qup2_spi_apps_clk",
 856			.parent_hws = (const struct clk_hw *[]) {
 857				&blsp1_qup2_spi_apps_clk_src.clkr.hw
 858			},
 859			.num_parents = 1,
 860			.flags = CLK_SET_RATE_PARENT,
 861			.ops = &clk_branch2_ops,
 862		},
 863	},
 864};
 865
 866static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
 867	.halt_reg = 0x04024,
 868	.clkr = {
 869		.enable_reg = 0x04024,
 870		.enable_mask = BIT(0),
 871		.hw.init = &(const struct clk_init_data) {
 872			.name = "gcc_blsp1_qup3_i2c_apps_clk",
 873			.parent_hws = (const struct clk_hw *[]) {
 874				&blsp1_qup3_i2c_apps_clk_src.clkr.hw
 875			},
 876			.num_parents = 1,
 877			.flags = CLK_SET_RATE_PARENT,
 878			.ops = &clk_branch2_ops,
 879		},
 880	},
 881};
 882
 883static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
 884	.halt_reg = 0x04020,
 885	.clkr = {
 886		.enable_reg = 0x04020,
 887		.enable_mask = BIT(0),
 888		.hw.init = &(const struct clk_init_data) {
 889			.name = "gcc_blsp1_qup3_spi_apps_clk",
 890			.parent_hws = (const struct clk_hw *[]) {
 891				&blsp1_qup3_spi_apps_clk_src.clkr.hw
 892			},
 893			.num_parents = 1,
 894			.flags = CLK_SET_RATE_PARENT,
 895			.ops = &clk_branch2_ops,
 896		},
 897	},
 898};
 899
 900static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
 901	.halt_reg = 0x05024,
 902	.clkr = {
 903		.enable_reg = 0x05024,
 904		.enable_mask = BIT(0),
 905		.hw.init = &(const struct clk_init_data) {
 906			.name = "gcc_blsp1_qup4_i2c_apps_clk",
 907			.parent_hws = (const struct clk_hw *[]) {
 908				&blsp1_qup4_i2c_apps_clk_src.clkr.hw
 909			},
 910			.num_parents = 1,
 911			.flags = CLK_SET_RATE_PARENT,
 912			.ops = &clk_branch2_ops,
 913		},
 914	},
 915};
 916
 917static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
 918	.halt_reg = 0x05020,
 919	.clkr = {
 920		.enable_reg = 0x05020,
 921		.enable_mask = BIT(0),
 922		.hw.init = &(const struct clk_init_data) {
 923			.name = "gcc_blsp1_qup4_spi_apps_clk",
 924			.parent_hws = (const struct clk_hw *[]) {
 925				&blsp1_qup4_spi_apps_clk_src.clkr.hw
 926			},
 927			.num_parents = 1,
 928			.flags = CLK_SET_RATE_PARENT,
 929			.ops = &clk_branch2_ops,
 930		},
 931	},
 932};
 933
 934static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
 935	.halt_reg = 0x06024,
 936	.clkr = {
 937		.enable_reg = 0x06024,
 938		.enable_mask = BIT(0),
 939		.hw.init = &(const struct clk_init_data) {
 940			.name = "gcc_blsp1_qup5_i2c_apps_clk",
 941			.parent_hws = (const struct clk_hw *[]) {
 942				&blsp1_qup5_i2c_apps_clk_src.clkr.hw
 943			},
 944			.num_parents = 1,
 945			.flags = CLK_SET_RATE_PARENT,
 946			.ops = &clk_branch2_ops,
 947		},
 948	},
 949};
 950
 951static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
 952	.halt_reg = 0x06020,
 953	.clkr = {
 954		.enable_reg = 0x06020,
 955		.enable_mask = BIT(0),
 956		.hw.init = &(const struct clk_init_data) {
 957			.name = "gcc_blsp1_qup5_spi_apps_clk",
 958			.parent_hws = (const struct clk_hw *[]) {
 959				&blsp1_qup5_spi_apps_clk_src.clkr.hw
 960			},
 961			.num_parents = 1,
 962			.flags = CLK_SET_RATE_PARENT,
 963			.ops = &clk_branch2_ops,
 964		},
 965	},
 966};
 967
 968static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
 969	.halt_reg = 0x07024,
 970	.clkr = {
 971		.enable_reg = 0x07024,
 972		.enable_mask = BIT(0),
 973		.hw.init = &(const struct clk_init_data) {
 974			.name = "gcc_blsp1_qup6_i2c_apps_clk",
 975			.parent_hws = (const struct clk_hw *[]) {
 976				&blsp1_qup6_i2c_apps_clk_src.clkr.hw
 977			},
 978			.num_parents = 1,
 979			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
 980			.ops = &clk_branch2_ops,
 981		},
 982	},
 983};
 984
 985static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
 986	.halt_reg = 0x07020,
 987	.clkr = {
 988		.enable_reg = 0x07020,
 989		.enable_mask = BIT(0),
 990		.hw.init = &(const struct clk_init_data) {
 991			.name = "gcc_blsp1_qup6_spi_apps_clk",
 992			.parent_hws = (const struct clk_hw *[]) {
 993				&blsp1_qup6_spi_apps_clk_src.clkr.hw
 994			},
 995			.num_parents = 1,
 996			.flags = CLK_SET_RATE_PARENT,
 997			.ops = &clk_branch2_ops,
 998		},
 999	},
1000};
1001
1002static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1003	.halt_reg = 0x02040,
1004	.clkr = {
1005		.enable_reg = 0x02040,
1006		.enable_mask = BIT(0),
1007		.hw.init = &(const struct clk_init_data) {
1008			.name = "gcc_blsp1_uart1_apps_clk",
1009			.parent_hws = (const struct clk_hw *[]) {
1010				&blsp1_uart1_apps_clk_src.clkr.hw
1011			},
1012			.num_parents = 1,
1013			.flags = CLK_SET_RATE_PARENT,
1014			.ops = &clk_branch2_ops,
1015		},
1016	},
1017};
1018
1019static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1020	.halt_reg = 0x03040,
1021	.clkr = {
1022		.enable_reg = 0x03040,
1023		.enable_mask = BIT(0),
1024		.hw.init = &(const struct clk_init_data) {
1025			.name = "gcc_blsp1_uart2_apps_clk",
1026			.parent_hws = (const struct clk_hw *[]) {
1027				&blsp1_uart2_apps_clk_src.clkr.hw
1028			},
1029			.num_parents = 1,
1030			.flags = CLK_SET_RATE_PARENT,
1031			.ops = &clk_branch2_ops,
1032		},
1033	},
1034};
1035
1036static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1037	.halt_reg = 0x04054,
1038	.clkr = {
1039		.enable_reg = 0x04054,
1040		.enable_mask = BIT(0),
1041		.hw.init = &(const struct clk_init_data) {
1042			.name = "gcc_blsp1_uart3_apps_clk",
1043			.parent_hws = (const struct clk_hw *[]) {
1044				&blsp1_uart3_apps_clk_src.clkr.hw
1045			},
1046			.num_parents = 1,
1047			.flags = CLK_SET_RATE_PARENT,
1048			.ops = &clk_branch2_ops,
1049		},
1050	},
1051};
1052
1053static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1054	.halt_reg = 0x05040,
1055	.clkr = {
1056		.enable_reg = 0x05040,
1057		.enable_mask = BIT(0),
1058		.hw.init = &(const struct clk_init_data) {
1059			.name = "gcc_blsp1_uart4_apps_clk",
1060			.parent_hws = (const struct clk_hw *[]) {
1061				&blsp1_uart4_apps_clk_src.clkr.hw
1062			},
1063			.num_parents = 1,
1064			.flags = CLK_SET_RATE_PARENT,
1065			.ops = &clk_branch2_ops,
1066		},
1067	},
1068};
1069
1070static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1071	.halt_reg = 0x06040,
1072	.clkr = {
1073		.enable_reg = 0x06040,
1074		.enable_mask = BIT(0),
1075		.hw.init = &(const struct clk_init_data) {
1076			.name = "gcc_blsp1_uart5_apps_clk",
1077			.parent_hws = (const struct clk_hw *[]) {
1078				&blsp1_uart5_apps_clk_src.clkr.hw
1079			},
1080			.num_parents = 1,
1081			.flags = CLK_SET_RATE_PARENT,
1082			.ops = &clk_branch2_ops,
1083		},
1084	},
1085};
1086
1087static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1088	.halt_reg = 0x07040,
1089	.clkr = {
1090		.enable_reg = 0x07040,
1091		.enable_mask = BIT(0),
1092		.hw.init = &(const struct clk_init_data) {
1093			.name = "gcc_blsp1_uart6_apps_clk",
1094			.parent_hws = (const struct clk_hw *[]) {
1095				&blsp1_uart6_apps_clk_src.clkr.hw
1096			},
1097			.num_parents = 1,
1098			.flags = CLK_SET_RATE_PARENT,
1099			.ops = &clk_branch2_ops,
1100		},
1101	},
1102};
1103
1104static const struct freq_tbl ftbl_pcie0_axi_m_clk_src[] = {
1105	F(240000000, P_GPLL4, 5, 0, 0),
1106	{ }
1107};
1108
1109static struct clk_rcg2 pcie0_axi_m_clk_src = {
1110	.cmd_rcgr = 0x28018,
1111	.freq_tbl = ftbl_pcie0_axi_m_clk_src,
1112	.hid_width = 5,
1113	.parent_map = gcc_xo_gpll0_gpll4_map,
1114	.clkr.hw.init = &(const struct clk_init_data) {
1115		.name = "pcie0_axi_m_clk_src",
1116		.parent_data = gcc_xo_gpll0_gpll4,
1117		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
1118		.ops = &clk_rcg2_ops,
1119	},
1120};
1121
1122static struct clk_branch gcc_pcie0_axi_m_clk = {
1123	.halt_reg = 0x28038,
1124	.clkr = {
1125		.enable_reg = 0x28038,
1126		.enable_mask = BIT(0),
1127		.hw.init = &(const struct clk_init_data) {
1128			.name = "gcc_pcie0_axi_m_clk",
1129			.parent_hws = (const struct clk_hw *[]) {
1130				&pcie0_axi_m_clk_src.clkr.hw
1131			},
1132			.num_parents = 1,
1133			.flags = CLK_SET_RATE_PARENT,
1134			.ops = &clk_branch2_ops,
1135		},
1136	},
1137};
1138
1139static struct clk_branch gcc_anoc_pcie0_1lane_m_clk = {
1140	.halt_reg = 0x2e07c,
1141	.clkr = {
1142		.enable_reg = 0x2e07c,
1143		.enable_mask = BIT(0),
1144		.hw.init = &(const struct clk_init_data) {
1145			.name = "gcc_anoc_pcie0_1lane_m_clk",
1146			.parent_hws = (const struct clk_hw *[]) {
1147				&pcie0_axi_m_clk_src.clkr.hw
1148			},
1149			.num_parents = 1,
1150			.flags = CLK_SET_RATE_PARENT,
1151			.ops = &clk_branch2_ops,
1152		},
1153	},
1154};
1155
1156static struct clk_rcg2 pcie1_axi_m_clk_src = {
1157	.cmd_rcgr = 0x29018,
1158	.freq_tbl = ftbl_pcie0_axi_m_clk_src,
1159	.hid_width = 5,
1160	.parent_map = gcc_xo_gpll0_gpll4_map,
1161	.clkr.hw.init = &(const struct clk_init_data) {
1162		.name = "pcie1_axi_m_clk_src",
1163		.parent_data = gcc_xo_gpll0_gpll4,
1164		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
1165		.ops = &clk_rcg2_ops,
1166	},
1167};
1168
1169static struct clk_branch gcc_pcie1_axi_m_clk = {
1170	.halt_reg = 0x29038,
1171	.clkr = {
1172		.enable_reg = 0x29038,
1173		.enable_mask = BIT(0),
1174		.hw.init = &(const struct clk_init_data) {
1175			.name = "gcc_pcie1_axi_m_clk",
1176			.parent_hws = (const struct clk_hw *[]) {
1177				&pcie1_axi_m_clk_src.clkr.hw
1178			},
1179			.num_parents = 1,
1180			.flags = CLK_SET_RATE_PARENT,
1181			.ops = &clk_branch2_ops,
1182		},
1183	},
1184};
1185
1186static struct clk_branch gcc_anoc_pcie1_1lane_m_clk = {
1187	.halt_reg = 0x2e08c,
1188	.clkr = {
1189		.enable_reg = 0x2e08c,
1190		.enable_mask = BIT(0),
1191		.hw.init = &(const struct clk_init_data) {
1192			.name = "gcc_anoc_pcie1_1lane_m_clk",
1193			.parent_hws = (const struct clk_hw *[]) {
1194				&pcie1_axi_m_clk_src.clkr.hw
1195			},
1196			.num_parents = 1,
1197			.flags = CLK_SET_RATE_PARENT,
1198			.ops = &clk_branch2_ops,
1199		},
1200	},
1201};
1202
1203static const struct freq_tbl ftbl_pcie2_axi_m_clk_src[] = {
1204	F(342857143, P_GPLL4, 3.5, 0, 0),
1205	{ }
1206};
1207
1208static struct clk_rcg2 pcie2_axi_m_clk_src = {
1209	.cmd_rcgr = 0x2a018,
1210	.freq_tbl = ftbl_pcie2_axi_m_clk_src,
1211	.hid_width = 5,
1212	.parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk_map,
1213	.clkr.hw.init = &(const struct clk_init_data) {
1214		.name = "pcie2_axi_m_clk_src",
1215		.parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk,
1216		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk),
1217		.ops = &clk_rcg2_ops,
1218	},
1219};
1220
1221static struct clk_branch gcc_pcie2_axi_m_clk = {
1222	.halt_reg = 0x2a038,
1223	.clkr = {
1224		.enable_reg = 0x2a038,
1225		.enable_mask = BIT(0),
1226		.hw.init = &(const struct clk_init_data) {
1227			.name = "gcc_pcie2_axi_m_clk",
1228			.parent_hws = (const struct clk_hw *[]) {
1229				&pcie2_axi_m_clk_src.clkr.hw
1230			},
1231			.num_parents = 1,
1232			.flags = CLK_SET_RATE_PARENT,
1233			.ops = &clk_branch2_ops,
1234		},
1235	},
1236};
1237
1238static struct clk_branch gcc_anoc_pcie2_2lane_m_clk = {
1239	.halt_reg = 0x2e080,
1240	.clkr = {
1241		.enable_reg = 0x2e080,
1242		.enable_mask = BIT(0),
1243		.hw.init = &(const struct clk_init_data) {
1244			.name = "gcc_anoc_pcie2_2lane_m_clk",
1245			.parent_hws = (const struct clk_hw *[]) {
1246				&pcie2_axi_m_clk_src.clkr.hw
1247			},
1248			.num_parents = 1,
1249			.flags = CLK_SET_RATE_PARENT,
1250			.ops = &clk_branch2_ops,
1251		},
1252	},
1253};
1254
1255static struct clk_rcg2 pcie3_axi_m_clk_src = {
1256	.cmd_rcgr = 0x2b018,
1257	.freq_tbl = ftbl_pcie2_axi_m_clk_src,
1258	.hid_width = 5,
1259	.parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk_map,
1260	.clkr.hw.init = &(const struct clk_init_data) {
1261		.name = "pcie3_axi_m_clk_src",
1262		.parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk,
1263		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk),
1264		.ops = &clk_rcg2_ops,
1265	},
1266};
1267
1268static struct clk_branch gcc_pcie3_axi_m_clk = {
1269	.halt_reg = 0x2b038,
1270	.clkr = {
1271		.enable_reg = 0x2b038,
1272		.enable_mask = BIT(0),
1273		.hw.init = &(const struct clk_init_data) {
1274			.name = "gcc_pcie3_axi_m_clk",
1275			.parent_hws = (const struct clk_hw *[]) {
1276				&pcie3_axi_m_clk_src.clkr.hw
1277			},
1278			.num_parents = 1,
1279			.flags = CLK_SET_RATE_PARENT,
1280			.ops = &clk_branch2_ops,
1281		},
1282	},
1283};
1284
1285static struct clk_branch gcc_anoc_pcie3_2lane_m_clk = {
1286	.halt_reg = 0x2e090,
1287	.clkr = {
1288		.enable_reg = 0x2e090,
1289		.enable_mask = BIT(0),
1290		.hw.init = &(const struct clk_init_data) {
1291			.name = "gcc_anoc_pcie3_2lane_m_clk",
1292			.parent_hws = (const struct clk_hw *[]) {
1293				&pcie3_axi_m_clk_src.clkr.hw
1294			},
1295			.num_parents = 1,
1296			.flags = CLK_SET_RATE_PARENT,
1297			.ops = &clk_branch2_ops,
1298		},
1299	},
1300};
1301
1302static struct clk_rcg2 pcie0_axi_s_clk_src = {
1303	.cmd_rcgr = 0x28020,
1304	.freq_tbl = ftbl_pcie0_axi_m_clk_src,
1305	.hid_width = 5,
1306	.parent_map = gcc_xo_gpll0_gpll4_map,
1307	.clkr.hw.init = &(const struct clk_init_data) {
1308		.name = "pcie0_axi_s_clk_src",
1309		.parent_data = gcc_xo_gpll0_gpll4,
1310		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
1311		.ops = &clk_rcg2_ops,
1312	},
1313};
1314
1315static struct clk_branch gcc_pcie0_axi_s_clk = {
1316	.halt_reg = 0x2803c,
1317	.clkr = {
1318		.enable_reg = 0x2803c,
1319		.enable_mask = BIT(0),
1320		.hw.init = &(const struct clk_init_data) {
1321			.name = "gcc_pcie0_axi_s_clk",
1322			.parent_hws = (const struct clk_hw *[]) {
1323				&pcie0_axi_s_clk_src.clkr.hw
1324			},
1325			.num_parents = 1,
1326			.flags = CLK_SET_RATE_PARENT,
1327			.ops = &clk_branch2_ops,
1328		},
1329	},
1330};
1331
1332static struct clk_branch gcc_pcie0_axi_s_bridge_clk = {
1333	.halt_reg = 0x28040,
1334	.clkr = {
1335		.enable_reg = 0x28040,
1336		.enable_mask = BIT(0),
1337		.hw.init = &(const struct clk_init_data) {
1338			.name = "gcc_pcie0_axi_s_bridge_clk",
1339			.parent_hws = (const struct clk_hw *[]) {
1340				&pcie0_axi_s_clk_src.clkr.hw
1341			},
1342			.num_parents = 1,
1343			.flags = CLK_SET_RATE_PARENT,
1344			.ops = &clk_branch2_ops,
1345		},
1346	},
1347};
1348
1349static struct clk_branch gcc_snoc_pcie0_1lane_s_clk = {
1350	.halt_reg = 0x2e048,
1351	.clkr = {
1352		.enable_reg = 0x2e048,
1353		.enable_mask = BIT(0),
1354		.hw.init = &(const struct clk_init_data) {
1355			.name = "gcc_snoc_pcie0_1lane_s_clk",
1356			.parent_hws = (const struct clk_hw *[]) {
1357				&pcie0_axi_s_clk_src.clkr.hw
1358			},
1359			.num_parents = 1,
1360			.flags = CLK_SET_RATE_PARENT,
1361			.ops = &clk_branch2_ops,
1362		},
1363	},
1364};
1365
1366static struct clk_rcg2 pcie1_axi_s_clk_src = {
1367	.cmd_rcgr = 0x29020,
1368	.freq_tbl = ftbl_pcie0_axi_m_clk_src,
1369	.hid_width = 5,
1370	.parent_map = gcc_xo_gpll0_gpll4_map,
1371	.clkr.hw.init = &(const struct clk_init_data) {
1372		.name = "pcie1_axi_s_clk_src",
1373		.parent_data = gcc_xo_gpll0_gpll4,
1374		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
1375		.ops = &clk_rcg2_ops,
1376	},
1377};
1378
1379static struct clk_branch gcc_pcie1_axi_s_clk = {
1380	.halt_reg = 0x2903c,
1381	.clkr = {
1382		.enable_reg = 0x2903c,
1383		.enable_mask = BIT(0),
1384		.hw.init = &(const struct clk_init_data) {
1385			.name = "gcc_pcie1_axi_s_clk",
1386			.parent_hws = (const struct clk_hw *[]) {
1387				&pcie1_axi_s_clk_src.clkr.hw
1388			},
1389			.num_parents = 1,
1390			.flags = CLK_SET_RATE_PARENT,
1391			.ops = &clk_branch2_ops,
1392		},
1393	},
1394};
1395
1396static struct clk_branch gcc_pcie1_axi_s_bridge_clk = {
1397	.halt_reg = 0x29040,
1398	.clkr = {
1399		.enable_reg = 0x29040,
1400		.enable_mask = BIT(0),
1401		.hw.init = &(const struct clk_init_data) {
1402			.name = "gcc_pcie1_axi_s_bridge_clk",
1403			.parent_hws = (const struct clk_hw *[]) {
1404				&pcie1_axi_s_clk_src.clkr.hw
1405			},
1406			.num_parents = 1,
1407			.flags = CLK_SET_RATE_PARENT,
1408			.ops = &clk_branch2_ops,
1409		},
1410	},
1411};
1412
1413static struct clk_branch gcc_snoc_pcie1_1lane_s_clk = {
1414	.halt_reg = 0x2e04c,
1415	.clkr = {
1416		.enable_reg = 0x2e04c,
1417		.enable_mask = BIT(0),
1418		.hw.init = &(const struct clk_init_data) {
1419			.name = "gcc_snoc_pcie1_1lane_s_clk",
1420			.parent_hws = (const struct clk_hw *[]) {
1421				&pcie1_axi_s_clk_src.clkr.hw
1422			},
1423			.num_parents = 1,
1424			.flags = CLK_SET_RATE_PARENT,
1425			.ops = &clk_branch2_ops,
1426		},
1427	},
1428};
1429
1430static struct clk_rcg2 pcie2_axi_s_clk_src = {
1431	.cmd_rcgr = 0x2a020,
1432	.freq_tbl = ftbl_pcie0_axi_m_clk_src,
1433	.hid_width = 5,
1434	.parent_map = gcc_xo_gpll0_gpll4_map,
1435	.clkr.hw.init = &(const struct clk_init_data) {
1436		.name = "pcie2_axi_s_clk_src",
1437		.parent_data = gcc_xo_gpll0_gpll4,
1438		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
1439		.ops = &clk_rcg2_ops,
1440	},
1441};
1442
1443static struct clk_branch gcc_pcie2_axi_s_clk = {
1444	.halt_reg = 0x2a03c,
1445	.clkr = {
1446		.enable_reg = 0x2a03c,
1447		.enable_mask = BIT(0),
1448		.hw.init = &(const struct clk_init_data) {
1449			.name = "gcc_pcie2_axi_s_clk",
1450			.parent_hws = (const struct clk_hw *[]) {
1451				&pcie2_axi_s_clk_src.clkr.hw
1452			},
1453			.num_parents = 1,
1454			.flags = CLK_SET_RATE_PARENT,
1455			.ops = &clk_branch2_ops,
1456		},
1457	},
1458};
1459
1460static struct clk_branch gcc_pcie2_axi_s_bridge_clk = {
1461	.halt_reg = 0x2a040,
1462	.clkr = {
1463		.enable_reg = 0x2a040,
1464		.enable_mask = BIT(0),
1465		.hw.init = &(const struct clk_init_data) {
1466			.name = "gcc_pcie2_axi_s_bridge_clk",
1467			.parent_hws = (const struct clk_hw *[]) {
1468				&pcie2_axi_s_clk_src.clkr.hw
1469			},
1470			.num_parents = 1,
1471			.flags = CLK_SET_RATE_PARENT,
1472			.ops = &clk_branch2_ops,
1473		},
1474	},
1475};
1476
1477static struct clk_branch gcc_snoc_pcie2_2lane_s_clk = {
1478	.halt_reg = 0x2e050,
1479	.clkr = {
1480		.enable_reg = 0x2e050,
1481		.enable_mask = BIT(0),
1482		.hw.init = &(const struct clk_init_data) {
1483			.name = "gcc_snoc_pcie2_2lane_s_clk",
1484			.parent_hws = (const struct clk_hw *[]) {
1485				&pcie2_axi_s_clk_src.clkr.hw
1486			},
1487			.num_parents = 1,
1488			.flags = CLK_SET_RATE_PARENT,
1489			.ops = &clk_branch2_ops,
1490		},
1491	},
1492};
1493
1494static struct clk_rcg2 pcie3_axi_s_clk_src = {
1495	.cmd_rcgr = 0x2b020,
1496	.freq_tbl = ftbl_pcie0_axi_m_clk_src,
1497	.hid_width = 5,
1498	.parent_map = gcc_xo_gpll0_gpll4_map,
1499	.clkr.hw.init = &(const struct clk_init_data) {
1500		.name = "pcie3_axi_s_clk_src",
1501		.parent_data = gcc_xo_gpll0_gpll4,
1502		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
1503		.ops = &clk_rcg2_ops,
1504	},
1505};
1506
1507static struct clk_branch gcc_pcie3_axi_s_clk = {
1508	.halt_reg = 0x2b03c,
1509	.clkr = {
1510		.enable_reg = 0x2b03c,
1511		.enable_mask = BIT(0),
1512		.hw.init = &(const struct clk_init_data) {
1513			.name = "gcc_pcie3_axi_s_clk",
1514			.parent_hws = (const struct clk_hw *[]) {
1515				&pcie3_axi_s_clk_src.clkr.hw
1516			},
1517			.num_parents = 1,
1518			.flags = CLK_SET_RATE_PARENT,
1519			.ops = &clk_branch2_ops,
1520		},
1521	},
1522};
1523
1524static struct clk_branch gcc_pcie3_axi_s_bridge_clk = {
1525	.halt_reg = 0x2b040,
1526	.clkr = {
1527		.enable_reg = 0x2b040,
1528		.enable_mask = BIT(0),
1529		.hw.init = &(const struct clk_init_data) {
1530			.name = "gcc_pcie3_axi_s_bridge_clk",
1531			.parent_hws = (const struct clk_hw *[]) {
1532				&pcie3_axi_s_clk_src.clkr.hw
1533			},
1534			.num_parents = 1,
1535			.flags = CLK_SET_RATE_PARENT,
1536			.ops = &clk_branch2_ops,
1537		},
1538	},
1539};
1540
1541static struct clk_branch gcc_snoc_pcie3_2lane_s_clk = {
1542	.halt_reg = 0x2e054,
1543	.clkr = {
1544		.enable_reg = 0x2e054,
1545		.enable_mask = BIT(0),
1546		.hw.init = &(const struct clk_init_data) {
1547			.name = "gcc_snoc_pcie3_2lane_s_clk",
1548			.parent_hws = (const struct clk_hw *[]) {
1549				&pcie3_axi_s_clk_src.clkr.hw
1550			},
1551			.num_parents = 1,
1552			.flags = CLK_SET_RATE_PARENT,
1553			.ops = &clk_branch2_ops,
1554		},
1555	},
1556};
1557
1558static struct clk_regmap_phy_mux pcie0_pipe_clk_src = {
1559	.reg = 0x28064,
1560	.clkr = {
1561		.hw.init = &(const struct clk_init_data) {
1562			.name = "pcie0_pipe_clk_src",
1563			.parent_data = &(const struct clk_parent_data) {
1564				.index = DT_PCIE30_PHY0_PIPE_CLK,
1565			},
1566			.num_parents = 1,
1567			.ops = &clk_regmap_phy_mux_ops,
1568		},
1569	},
1570};
1571
1572static struct clk_regmap_phy_mux pcie1_pipe_clk_src = {
1573	.reg = 0x29064,
1574	.clkr = {
1575		.hw.init = &(const struct clk_init_data) {
1576			.name = "pcie1_pipe_clk_src",
1577			.parent_data = &(const struct clk_parent_data) {
1578				.index = DT_PCIE30_PHY1_PIPE_CLK,
1579			},
1580			.num_parents = 1,
1581			.ops = &clk_regmap_phy_mux_ops,
1582		},
1583	},
1584};
1585
1586static struct clk_regmap_phy_mux pcie2_pipe_clk_src = {
1587	.reg = 0x2a064,
1588	.clkr = {
1589		.hw.init = &(const struct clk_init_data) {
1590			.name = "pcie2_pipe_clk_src",
1591			.parent_data = &(const struct clk_parent_data) {
1592				.index = DT_PCIE30_PHY2_PIPE_CLK,
1593			},
1594			.num_parents = 1,
1595			.ops = &clk_regmap_phy_mux_ops,
1596		},
1597	},
1598};
1599
1600static struct clk_regmap_phy_mux pcie3_pipe_clk_src = {
1601	.reg = 0x2b064,
1602	.clkr = {
1603		.hw.init = &(const struct clk_init_data) {
1604			.name = "pcie3_pipe_clk_src",
1605			.parent_data = &(const struct clk_parent_data) {
1606				.index = DT_PCIE30_PHY3_PIPE_CLK,
1607			},
1608			.num_parents = 1,
1609			.ops = &clk_regmap_phy_mux_ops,
1610		},
1611	},
1612};
1613
1614static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = {
1615	F(24000000, P_XO, 1, 0, 0),
1616	F(100000000, P_GPLL0, 8, 0, 0),
1617	{ }
1618};
1619
1620static struct clk_rcg2 pcie0_rchng_clk_src = {
1621	.cmd_rcgr = 0x28028,
1622	.freq_tbl = ftbl_pcie_rchng_clk_src,
1623	.hid_width = 5,
1624	.parent_map = gcc_xo_gpll0_map,
1625	.clkr.hw.init = &(const struct clk_init_data) {
1626		.name = "pcie0_rchng_clk_src",
1627		.parent_data = gcc_xo_gpll0,
1628		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1629		.ops = &clk_rcg2_ops,
1630	},
1631};
1632
1633static struct clk_branch gcc_pcie0_rchng_clk = {
1634	.halt_reg = 0x28028,
1635	.clkr = {
1636		.enable_reg = 0x28028,
1637		.enable_mask = BIT(1),
1638		.hw.init = &(const struct clk_init_data) {
1639			.name = "gcc_pcie0_rchng_clk",
1640			.parent_hws = (const struct clk_hw *[]) {
1641				&pcie0_rchng_clk_src.clkr.hw
1642
1643			},
1644			.num_parents = 1,
1645			.flags = CLK_SET_RATE_PARENT,
1646			.ops = &clk_branch2_ops,
1647		},
1648	},
1649};
1650
1651static struct clk_rcg2 pcie1_rchng_clk_src = {
1652	.cmd_rcgr = 0x29028,
1653	.freq_tbl = ftbl_pcie_rchng_clk_src,
1654	.hid_width = 5,
1655	.parent_map = gcc_xo_gpll0_map,
1656	.clkr.hw.init = &(const struct clk_init_data) {
1657		.name = "pcie1_rchng_clk_src",
1658		.parent_data = gcc_xo_gpll0,
1659		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1660		.ops = &clk_rcg2_ops,
1661	},
1662};
1663
1664static struct clk_branch gcc_pcie1_rchng_clk = {
1665	.halt_reg = 0x29028,
1666	.clkr = {
1667		.enable_reg = 0x29028,
1668		.enable_mask = BIT(1),
1669		.hw.init = &(const struct clk_init_data) {
1670			.name = "gcc_pcie1_rchng_clk",
1671			.parent_hws = (const struct clk_hw *[]) {
1672				&pcie1_rchng_clk_src.clkr.hw
1673			},
1674			.num_parents = 1,
1675			.flags = CLK_SET_RATE_PARENT,
1676			.ops = &clk_branch2_ops,
1677		},
1678	},
1679};
1680
1681static struct clk_rcg2 pcie2_rchng_clk_src = {
1682	.cmd_rcgr = 0x2a028,
1683	.freq_tbl = ftbl_pcie_rchng_clk_src,
1684	.hid_width = 5,
1685	.parent_map = gcc_xo_gpll0_map,
1686	.clkr.hw.init = &(const struct clk_init_data) {
1687		.name = "pcie2_rchng_clk_src",
1688		.parent_data = gcc_xo_gpll0,
1689		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1690		.ops = &clk_rcg2_ops,
1691	},
1692};
1693
1694static struct clk_branch gcc_pcie2_rchng_clk = {
1695	.halt_reg = 0x2a028,
1696	.clkr = {
1697		.enable_reg = 0x2a028,
1698		.enable_mask = BIT(1),
1699		.hw.init = &(const struct clk_init_data) {
1700			.name = "gcc_pcie2_rchng_clk",
1701			.parent_hws = (const struct clk_hw *[]) {
1702				&pcie2_rchng_clk_src.clkr.hw
1703			},
1704			.num_parents = 1,
1705			.flags = CLK_SET_RATE_PARENT,
1706			.ops = &clk_branch2_ops,
1707		},
1708	},
1709};
1710
1711static struct clk_rcg2 pcie3_rchng_clk_src = {
1712	.cmd_rcgr = 0x2b028,
1713	.freq_tbl = ftbl_pcie_rchng_clk_src,
1714	.hid_width = 5,
1715	.parent_map = gcc_xo_gpll0_map,
1716	.clkr.hw.init = &(const struct clk_init_data) {
1717		.name = "pcie3_rchng_clk_src",
1718		.parent_data = gcc_xo_gpll0,
1719		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1720		.ops = &clk_rcg2_ops,
1721	},
1722};
1723
1724static struct clk_branch gcc_pcie3_rchng_clk = {
1725	.halt_reg = 0x2b028,
1726	.clkr = {
1727		.enable_reg = 0x2b028,
1728		.enable_mask = BIT(1),
1729		.hw.init = &(const struct clk_init_data) {
1730			.name = "gcc_pcie3_rchng_clk",
1731			.parent_hws = (const struct clk_hw *[]) {
1732				&pcie3_rchng_clk_src.clkr.hw
1733			},
1734			.num_parents = 1,
1735			.flags = CLK_SET_RATE_PARENT,
1736			.ops = &clk_branch2_ops,
1737		},
1738	},
1739};
1740
1741static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
1742	F(20000000, P_GPLL0, 10, 1, 4),
1743	{ }
1744};
1745
1746static struct clk_rcg2 pcie_aux_clk_src = {
1747	.cmd_rcgr = 0x28004,
1748	.freq_tbl = ftbl_pcie_aux_clk_src,
1749	.mnd_width = 16,
1750	.hid_width = 5,
1751	.parent_map = gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk_map,
1752	.clkr.hw.init = &(const struct clk_init_data) {
1753		.name = "pcie_aux_clk_src",
1754		.parent_data = gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk,
1755		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk),
1756		.ops = &clk_rcg2_ops,
1757	},
1758};
1759
1760static struct clk_branch gcc_pcie0_aux_clk = {
1761	.halt_reg = 0x28034,
1762	.clkr = {
1763		.enable_reg = 0x28034,
1764		.enable_mask = BIT(0),
1765		.hw.init = &(const struct clk_init_data) {
1766			.name = "gcc_pcie0_aux_clk",
1767			.parent_hws = (const struct clk_hw *[]) {
1768				&pcie_aux_clk_src.clkr.hw
1769			},
1770			.num_parents = 1,
1771			.flags = CLK_SET_RATE_PARENT,
1772			.ops = &clk_branch2_ops,
1773		},
1774	},
1775};
1776
1777static struct clk_branch gcc_pcie1_aux_clk = {
1778	.halt_reg = 0x29034,
1779	.clkr = {
1780		.enable_reg = 0x29034,
1781		.enable_mask = BIT(0),
1782		.hw.init = &(const struct clk_init_data) {
1783			.name = "gcc_pcie1_aux_clk",
1784			.parent_hws = (const struct clk_hw *[]) {
1785				&pcie_aux_clk_src.clkr.hw
1786			},
1787			.num_parents = 1,
1788			.flags = CLK_SET_RATE_PARENT,
1789			.ops = &clk_branch2_ops,
1790		},
1791	},
1792};
1793
1794static struct clk_branch gcc_pcie2_aux_clk = {
1795	.halt_reg = 0x2a034,
1796	.clkr = {
1797		.enable_reg = 0x2a034,
1798		.enable_mask = BIT(0),
1799		.hw.init = &(const struct clk_init_data) {
1800			.name = "gcc_pcie2_aux_clk",
1801			.parent_hws = (const struct clk_hw *[]) {
1802				&pcie_aux_clk_src.clkr.hw
1803			},
1804			.num_parents = 1,
1805			.flags = CLK_SET_RATE_PARENT,
1806			.ops = &clk_branch2_ops,
1807		},
1808	},
1809};
1810
1811static struct clk_branch gcc_pcie3_aux_clk = {
1812	.halt_reg = 0x2b034,
1813	.clkr = {
1814		.enable_reg = 0x2b034,
1815		.enable_mask = BIT(0),
1816		.hw.init = &(const struct clk_init_data) {
1817			.name = "gcc_pcie3_aux_clk",
1818			.parent_hws = (const struct clk_hw *[]) {
1819				&pcie_aux_clk_src.clkr.hw
1820			},
1821			.num_parents = 1,
1822			.flags = CLK_SET_RATE_PARENT,
1823			.ops = &clk_branch2_ops,
1824		},
1825	},
1826};
1827
1828static const struct freq_tbl ftbl_usb_aux_clk_src[] = {
1829	F(24000000, P_XO, 1, 0, 0),
1830	{ }
1831};
1832
1833static struct clk_rcg2 usb0_aux_clk_src = {
1834	.cmd_rcgr = 0x2c018,
1835	.freq_tbl = ftbl_usb_aux_clk_src,
1836	.mnd_width = 16,
1837	.hid_width = 5,
1838	.parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
1839	.clkr.hw.init = &(const struct clk_init_data) {
1840		.name = "usb0_aux_clk_src",
1841		.parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
1842		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk),
1843		.ops = &clk_rcg2_ops,
1844	},
1845};
1846
1847static struct clk_branch gcc_usb0_aux_clk = {
1848	.halt_reg = 0x2c048,
1849	.clkr = {
1850		.enable_reg = 0x2c048,
1851		.enable_mask = BIT(0),
1852		.hw.init = &(const struct clk_init_data) {
1853			.name = "gcc_usb0_aux_clk",
1854			.parent_hws = (const struct clk_hw *[]) {
1855				&usb0_aux_clk_src.clkr.hw
1856			},
1857			.num_parents = 1,
1858			.flags = CLK_SET_RATE_PARENT,
1859			.ops = &clk_branch2_ops,
1860		},
1861	},
1862};
1863
1864static const struct freq_tbl ftbl_usb0_master_clk_src[] = {
1865	F(100000000, P_GPLL0, 8, 0, 0),
1866	F(200000000, P_GPLL0, 4, 0, 0),
1867	{ }
1868};
1869
1870static struct clk_rcg2 usb0_master_clk_src = {
1871	.cmd_rcgr = 0x2c004,
1872	.freq_tbl = ftbl_usb0_master_clk_src,
1873	.mnd_width = 8,
1874	.hid_width = 5,
1875	.parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
1876	.clkr.hw.init = &(const struct clk_init_data) {
1877		.name = "usb0_master_clk_src",
1878		.parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
1879		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0),
1880		.ops = &clk_rcg2_ops,
1881	},
1882};
1883
1884static struct clk_branch gcc_usb0_master_clk = {
1885	.halt_reg = 0x2c044,
1886	.clkr = {
1887		.enable_reg = 0x2c044,
1888		.enable_mask = BIT(0),
1889		.hw.init = &(const struct clk_init_data) {
1890			.name = "gcc_usb0_master_clk",
1891			.parent_hws = (const struct clk_hw *[]) {
1892				&usb0_master_clk_src.clkr.hw
1893			},
1894			.num_parents = 1,
1895			.flags = CLK_SET_RATE_PARENT,
1896			.ops = &clk_branch2_ops,
1897		},
1898	},
1899};
1900
1901static struct clk_branch gcc_snoc_usb_clk = {
1902	.halt_reg = 0x2e058,
1903	.clkr = {
1904		.enable_reg = 0x2e058,
1905		.enable_mask = BIT(0),
1906		.hw.init = &(const struct clk_init_data) {
1907			.name = "gcc_snoc_usb_clk",
1908			.parent_hws = (const struct clk_hw *[]) {
1909				&usb0_master_clk_src.clkr.hw
1910			},
1911			.num_parents = 1,
1912			.flags = CLK_SET_RATE_PARENT,
1913			.ops = &clk_branch2_ops,
1914		},
1915	},
1916};
1917
1918static struct clk_branch gcc_anoc_usb_axi_clk = {
1919	.halt_reg = 0x2e084,
1920	.clkr = {
1921		.enable_reg = 0x2e084,
1922		.enable_mask = BIT(0),
1923		.hw.init = &(const struct clk_init_data) {
1924			.name = "gcc_anoc_usb_axi_clk",
1925			.parent_hws = (const struct clk_hw *[]) {
1926				&usb0_master_clk_src.clkr.hw
1927			},
1928			.num_parents = 1,
1929			.flags = CLK_SET_RATE_PARENT,
1930			.ops = &clk_branch2_ops,
1931		},
1932	},
1933};
1934
1935static const struct freq_tbl ftbl_usb0_mock_utmi_clk_src[] = {
1936	F(24000000, P_XO, 1, 0, 0),
1937	F(60000000, P_GPLL4, 10, 1, 2),
1938	{ }
1939};
1940
1941static struct clk_rcg2 usb0_mock_utmi_clk_src = {
1942	.cmd_rcgr = 0x2c02c,
1943	.freq_tbl = ftbl_usb0_mock_utmi_clk_src,
1944	.mnd_width = 8,
1945	.hid_width = 5,
1946	.parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map,
1947	.clkr.hw.init = &(const struct clk_init_data) {
1948		.name = "usb0_mock_utmi_clk_src",
1949		.parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,
1950		.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),
1951		.ops = &clk_rcg2_ops,
1952	},
1953};
1954
1955static struct clk_regmap_div usb0_mock_utmi_div_clk_src = {
1956	.reg = 0x2c040,
1957	.shift = 0,
1958	.width = 2,
1959	.clkr.hw.init = &(const struct clk_init_data) {
1960		.name = "usb0_mock_utmi_div_clk_src",
1961		.parent_data = &(const struct clk_parent_data) {
1962			.hw = &usb0_mock_utmi_clk_src.clkr.hw,
1963		},
1964		.num_parents = 1,
1965		.flags = CLK_SET_RATE_PARENT,
1966		.ops = &clk_regmap_div_ro_ops,
1967	},
1968};
1969
1970static struct clk_branch gcc_usb0_mock_utmi_clk = {
1971	.halt_reg = 0x2c04c,
1972	.clkr = {
1973		.enable_reg = 0x2c04c,
1974		.enable_mask = BIT(0),
1975		.hw.init = &(const struct clk_init_data) {
1976			.name = "gcc_usb0_mock_utmi_clk",
1977			.parent_hws = (const struct clk_hw *[]) {
1978				&usb0_mock_utmi_div_clk_src.clkr.hw
1979			},
1980			.num_parents = 1,
1981			.flags = CLK_SET_RATE_PARENT,
1982			.ops = &clk_branch2_ops,
1983		},
1984	},
1985};
1986
1987static struct clk_regmap_mux usb0_pipe_clk_src = {
1988	.reg = 0x2C074,
1989	.shift = 8,
1990	.width = 2,
1991	.parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map,
1992	.clkr = {
1993		.hw.init = &(const struct clk_init_data) {
1994			.name = "usb0_pipe_clk_src",
1995			.parent_data = gcc_usb3phy_0_cc_pipe_clk_xo,
1996			.num_parents = ARRAY_SIZE(gcc_usb3phy_0_cc_pipe_clk_xo),
1997			.flags = CLK_SET_RATE_PARENT,
1998			.ops = &clk_regmap_mux_closest_ops,
1999		},
2000	},
2001};
2002
2003static struct clk_branch gcc_usb0_pipe_clk = {
2004	.halt_reg = 0x2c054,
2005	.halt_check = BRANCH_HALT_DELAY,
2006	.clkr = {
2007		.enable_reg = 0x2c054,
2008		.enable_mask = BIT(0),
2009		.hw.init = &(const struct clk_init_data){
2010			.name = "gcc_usb0_pipe_clk",
2011			.parent_hws = (const struct clk_hw *[]) {
2012				&usb0_pipe_clk_src.clkr.hw
2013			},
2014			.num_parents = 1,
2015			.flags = CLK_SET_RATE_PARENT,
2016			.ops = &clk_branch2_ops,
2017		},
2018	},
2019};
2020
2021static struct clk_branch gcc_usb0_sleep_clk = {
2022	.halt_reg = 0x2c058,
2023	.clkr = {
2024		.enable_reg = 0x2c058,
2025		.enable_mask = BIT(0),
2026		.hw.init = &(const struct clk_init_data){
2027			.name = "gcc_usb0_sleep_clk",
2028			.parent_hws = (const struct clk_hw *[]) {
2029				&gcc_sleep_clk_src.clkr.hw
2030			},
2031			.num_parents = 1,
2032			.flags = CLK_SET_RATE_PARENT,
2033			.ops = &clk_branch2_ops,
2034		},
2035	},
2036};
2037
2038static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
2039	F(144000, P_XO, 16, 12, 125),
2040	F(400000, P_XO, 12, 1, 5),
2041	F(24000000, P_GPLL2, 12, 1, 4),
2042	F(48000000, P_GPLL2, 12, 1, 2),
2043	F(96000000, P_GPLL2, 12, 0, 0),
2044	F(177777778, P_GPLL0, 4.5, 0, 0),
2045	F(192000000, P_GPLL2, 6, 0, 0),
2046	F(384000000, P_GPLL2, 3, 0, 0),
2047	F(400000000, P_GPLL0, 2, 0, 0),
2048	{ }
2049};
2050
2051static struct clk_rcg2 sdcc1_apps_clk_src = {
2052	.cmd_rcgr = 0x33004,
2053	.freq_tbl = ftbl_sdcc_apps_clk_src,
2054	.mnd_width = 8,
2055	.hid_width = 5,
2056	.parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
2057	.clkr.hw.init = &(const struct clk_init_data) {
2058		.name = "sdcc1_apps_clk_src",
2059		.parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
2060		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
2061		.ops = &clk_rcg2_floor_ops,
2062	},
2063};
2064
2065static struct clk_branch gcc_sdcc1_apps_clk = {
2066	.halt_reg = 0x3302c,
2067	.clkr = {
2068		.enable_reg = 0x3302c,
2069		.enable_mask = BIT(0),
2070		.hw.init = &(const struct clk_init_data) {
2071			.name = "gcc_sdcc1_apps_clk",
2072			.parent_hws = (const struct clk_hw *[]) {
2073				&sdcc1_apps_clk_src.clkr.hw
2074			},
2075			.num_parents = 1,
2076			.flags = CLK_SET_RATE_PARENT,
2077			.ops = &clk_branch2_ops,
2078		},
2079	},
2080};
2081
2082static const struct freq_tbl ftbl_sdcc_ice_core_clk_src[] = {
2083	F(150000000, P_GPLL4, 8, 0, 0),
2084	F(300000000, P_GPLL4, 4, 0, 0),
2085};
2086
2087static struct clk_rcg2 sdcc1_ice_core_clk_src = {
2088	.cmd_rcgr = 0x33018,
2089	.freq_tbl = ftbl_sdcc_ice_core_clk_src,
2090	.mnd_width = 8,
2091	.hid_width = 5,
2092	.parent_map = gcc_xo_gpll0_gpll4_gpll0_div2_map,
2093	.clkr.hw.init = &(const struct clk_init_data) {
2094		.name = "sdcc1_ice_core_clk_src",
2095		.parent_data = gcc_xo_gpll0_gpll4_gpll0_div2,
2096		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_div2),
2097		.ops = &clk_rcg2_ops,
2098	},
2099};
2100
2101static struct clk_branch gcc_sdcc1_ice_core_clk = {
2102	.halt_reg = 0x33030,
2103	.clkr = {
2104		.enable_reg = 0x33030,
2105		.enable_mask = BIT(0),
2106		.hw.init = &(const struct clk_init_data) {
2107			.name = "gcc_sdcc1_ice_core_clk",
2108			.parent_hws = (const struct clk_hw *[]) {
2109				&sdcc1_ice_core_clk_src.clkr.hw
2110			},
2111			.num_parents = 1,
2112			.flags = CLK_SET_RATE_PARENT,
2113			.ops = &clk_branch2_ops,
2114		},
2115	},
2116};
2117
2118static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {
2119	F(24000000, P_XO, 1, 0, 0),
2120	F(50000000, P_GPLL0, 16, 0, 0),
2121	F(80000000, P_GPLL0, 10, 0, 0),
2122	F(100000000, P_GPLL0, 8, 0, 0),
2123	{ }
2124};
2125
2126static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
2127	.cmd_rcgr = 0x31004,
2128	.freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
2129	.hid_width = 5,
2130	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
2131	.clkr.hw.init = &(const struct clk_init_data) {
2132		.name = "pcnoc_bfdcd_clk_src",
2133		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
2134		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
2135		.flags = CLK_IS_CRITICAL,
2136		.ops = &clk_rcg2_ops,
2137	},
2138};
2139
2140static struct clk_branch gcc_crypto_axi_clk = {
2141	.halt_reg = 0x16010,
2142	.clkr = {
2143		.enable_reg = 0x16010,
2144		.enable_mask = BIT(0),
2145		.hw.init = &(const struct clk_init_data) {
2146			.name = "gcc_crypto_axi_clk",
2147			.parent_hws = (const struct clk_hw *[]) {
2148				&pcnoc_bfdcd_clk_src.clkr.hw },
2149			.num_parents = 1,
2150			.flags = CLK_SET_RATE_PARENT,
2151			.ops = &clk_branch2_ops,
2152		},
2153	},
2154};
2155
2156static struct clk_branch gcc_crypto_ahb_clk = {
2157	.halt_reg = 0x16014,
2158	.clkr = {
2159		.enable_reg = 0x16014,
2160		.enable_mask = BIT(0),
2161		.hw.init = &(const struct clk_init_data) {
2162			.name = "gcc_crypto_ahb_clk",
2163			.parent_hws = (const struct clk_hw *[]) {
2164				&pcnoc_bfdcd_clk_src.clkr.hw },
2165			.num_parents = 1,
2166			.flags = CLK_SET_RATE_PARENT,
2167			.ops = &clk_branch2_ops,
2168		},
2169	},
2170};
2171
2172static struct clk_branch gcc_nsscfg_clk = {
2173	.halt_reg = 0x1702c,
2174	.clkr = {
2175		.enable_reg = 0x1702c,
2176		.enable_mask = BIT(0),
2177		.hw.init = &(const struct clk_init_data) {
2178			.name = "gcc_nsscfg_clk",
2179			.parent_hws = (const struct clk_hw *[]) {
2180				&pcnoc_bfdcd_clk_src.clkr.hw
2181			},
2182			.num_parents = 1,
2183			.flags = CLK_SET_RATE_PARENT,
2184			.ops = &clk_branch2_ops,
2185		},
2186	},
2187};
2188
2189static struct clk_branch gcc_nssnoc_nsscc_clk = {
2190	.halt_reg = 0x17030,
2191	.clkr = {
2192		.enable_reg = 0x17030,
2193		.enable_mask = BIT(0),
2194		.hw.init = &(const struct clk_init_data) {
2195			.name = "gcc_nssnoc_nsscc_clk",
2196			.parent_hws = (const struct clk_hw *[]) {
2197				&pcnoc_bfdcd_clk_src.clkr.hw
2198			},
2199			.num_parents = 1,
2200			.flags = CLK_SET_RATE_PARENT,
2201			.ops = &clk_branch2_ops,
2202		},
2203	},
2204};
2205
2206static struct clk_branch gcc_nsscc_clk = {
2207	.halt_reg = 0x17034,
2208	.clkr = {
2209		.enable_reg = 0x17034,
2210		.enable_mask = BIT(0),
2211		.hw.init = &(const struct clk_init_data) {
2212			.name = "gcc_nsscc_clk",
2213			.parent_hws = (const struct clk_hw *[]) {
2214				&pcnoc_bfdcd_clk_src.clkr.hw
2215			},
2216			.num_parents = 1,
2217			.flags = CLK_SET_RATE_PARENT,
2218			.ops = &clk_branch2_ops,
2219		},
2220	},
2221};
2222
2223static struct clk_branch gcc_nssnoc_pcnoc_1_clk = {
2224	.halt_reg = 0x17080,
2225	.clkr = {
2226		.enable_reg = 0x17080,
2227		.enable_mask = BIT(0),
2228		.hw.init = &(const struct clk_init_data) {
2229			.name = "gcc_nssnoc_pcnoc_1_clk",
2230			.parent_hws = (const struct clk_hw *[]) {
2231				&pcnoc_bfdcd_clk_src.clkr.hw
2232			},
2233			.num_parents = 1,
2234			.flags = CLK_SET_RATE_PARENT,
2235			.ops = &clk_branch2_ops,
2236		},
2237	},
2238};
2239
2240static struct clk_branch gcc_qdss_dap_ahb_clk = {
2241	.halt_reg = 0x2d064,
2242	.clkr = {
2243		.enable_reg = 0x2d064,
2244		.enable_mask = BIT(0),
2245		.hw.init = &(const struct clk_init_data) {
2246			.name = "gcc_qdss_dap_ahb_clk",
2247			.parent_hws = (const struct clk_hw *[]) {
2248				&pcnoc_bfdcd_clk_src.clkr.hw
2249			},
2250			.num_parents = 1,
2251			.flags = CLK_SET_RATE_PARENT,
2252			.ops = &clk_branch2_ops,
2253		},
2254	},
2255};
2256
2257static struct clk_branch gcc_qdss_cfg_ahb_clk = {
2258	.halt_reg = 0x2d068,
2259	.clkr = {
2260		.enable_reg = 0x2d068,
2261		.enable_mask = BIT(0),
2262		.hw.init = &(const struct clk_init_data) {
2263			.name = "gcc_qdss_cfg_ahb_clk",
2264			.parent_hws = (const struct clk_hw *[]) {
2265				&pcnoc_bfdcd_clk_src.clkr.hw
2266			},
2267			.num_parents = 1,
2268			.flags = CLK_SET_RATE_PARENT,
2269			.ops = &clk_branch2_ops,
2270		},
2271	},
2272};
2273
2274static struct clk_branch gcc_qpic_ahb_clk = {
2275	.halt_reg = 0x32010,
2276	.clkr = {
2277		.enable_reg = 0x32010,
2278		.enable_mask = BIT(0),
2279		.hw.init = &(const struct clk_init_data) {
2280			.name = "gcc_qpic_ahb_clk",
2281			.parent_hws = (const struct clk_hw *[]) {
2282				&pcnoc_bfdcd_clk_src.clkr.hw
2283			},
2284			.num_parents = 1,
2285			.flags = CLK_SET_RATE_PARENT,
2286			.ops = &clk_branch2_ops,
2287		},
2288	},
2289};
2290
2291static struct clk_branch gcc_qpic_clk = {
2292	.halt_reg = 0x32014,
2293	.clkr = {
2294		.enable_reg = 0x32014,
2295		.enable_mask = BIT(0),
2296		.hw.init = &(const struct clk_init_data) {
2297			.name = "gcc_qpic_clk",
2298			.parent_hws = (const struct clk_hw *[]) {
2299				&pcnoc_bfdcd_clk_src.clkr.hw
2300			},
2301			.num_parents = 1,
2302			.flags = CLK_SET_RATE_PARENT,
2303			.ops = &clk_branch2_ops,
2304		},
2305	},
2306};
2307
2308static struct clk_branch gcc_blsp1_ahb_clk = {
2309	.halt_reg = 0x01004,
2310	.halt_check = BRANCH_HALT_VOTED,
2311	.clkr = {
2312		.enable_reg = 0x0b004,
2313		.enable_mask = BIT(4),
2314		.hw.init = &(const struct clk_init_data) {
2315			.name = "gcc_blsp1_ahb_clk",
2316			.parent_hws = (const struct clk_hw *[]) {
2317				&pcnoc_bfdcd_clk_src.clkr.hw
2318			},
2319			.num_parents = 1,
2320			.flags = CLK_SET_RATE_PARENT,
2321			.ops = &clk_branch2_ops,
2322		},
2323	},
2324};
2325
2326static struct clk_branch gcc_mdio_ahb_clk = {
2327	.halt_reg = 0x17040,
2328	.clkr = {
2329		.enable_reg = 0x17040,
2330		.enable_mask = BIT(0),
2331		.hw.init = &(const struct clk_init_data) {
2332			.name = "gcc_mdio_ahb_clk",
2333			.parent_hws = (const struct clk_hw *[]) {
2334				&pcnoc_bfdcd_clk_src.clkr.hw
2335			},
2336			.num_parents = 1,
2337			.flags = CLK_SET_RATE_PARENT,
2338			.ops = &clk_branch2_ops,
2339		},
2340	},
2341};
2342
2343static struct clk_branch gcc_prng_ahb_clk = {
2344	.halt_reg = 0x13024,
2345	.halt_check = BRANCH_HALT_VOTED,
2346	.clkr = {
2347		.enable_reg = 0x0b004,
2348		.enable_mask = BIT(10),
2349		.hw.init = &(const struct clk_init_data) {
2350			.name = "gcc_prng_ahb_clk",
2351			.parent_hws = (const struct clk_hw *[]) {
2352				&pcnoc_bfdcd_clk_src.clkr.hw
2353			},
2354			.num_parents = 1,
2355			.flags = CLK_SET_RATE_PARENT,
2356			.ops = &clk_branch2_ops,
2357		},
2358	},
2359};
2360
2361static struct clk_branch gcc_uniphy0_ahb_clk = {
2362	.halt_reg = 0x1704c,
2363	.clkr = {
2364		.enable_reg = 0x1704c,
2365		.enable_mask = BIT(0),
2366		.hw.init = &(const struct clk_init_data) {
2367			.name = "gcc_uniphy0_ahb_clk",
2368			.parent_hws = (const struct clk_hw *[]) {
2369				&pcnoc_bfdcd_clk_src.clkr.hw
2370			},
2371			.num_parents = 1,
2372			.flags = CLK_SET_RATE_PARENT,
2373			.ops = &clk_branch2_ops,
2374		},
2375	},
2376};
2377
2378static struct clk_branch gcc_uniphy1_ahb_clk = {
2379	.halt_reg = 0x1705c,
2380	.clkr = {
2381		.enable_reg = 0x1705c,
2382		.enable_mask = BIT(0),
2383		.hw.init = &(const struct clk_init_data) {
2384			.name = "gcc_uniphy1_ahb_clk",
2385			.parent_hws = (const struct clk_hw *[]) {
2386				&pcnoc_bfdcd_clk_src.clkr.hw
2387			},
2388			.num_parents = 1,
2389			.flags = CLK_SET_RATE_PARENT,
2390			.ops = &clk_branch2_ops,
2391		},
2392	},
2393};
2394
2395static struct clk_branch gcc_uniphy2_ahb_clk = {
2396	.halt_reg = 0x1706c,
2397	.clkr = {
2398		.enable_reg = 0x1706c,
2399		.enable_mask = BIT(0),
2400		.hw.init = &(const struct clk_init_data) {
2401			.name = "gcc_uniphy2_ahb_clk",
2402			.parent_hws = (const struct clk_hw *[]) {
2403				&pcnoc_bfdcd_clk_src.clkr.hw
2404			},
2405			.num_parents = 1,
2406			.flags = CLK_SET_RATE_PARENT,
2407			.ops = &clk_branch2_ops,
2408		},
2409	},
2410};
2411
2412static struct clk_branch gcc_cmn_12gpll_ahb_clk = {
2413	.halt_reg = 0x3a004,
2414	.clkr = {
2415		.enable_reg = 0x3a004,
2416		.enable_mask = BIT(0),
2417		.hw.init = &(const struct clk_init_data) {
2418			.name = "gcc_cmn_12gpll_ahb_clk",
2419			.parent_hws = (const struct clk_hw *[]) {
2420				&pcnoc_bfdcd_clk_src.clkr.hw
2421			},
2422			.num_parents = 1,
2423			.flags = CLK_SET_RATE_PARENT,
2424			.ops = &clk_branch2_ops,
2425		},
2426	},
2427};
2428
2429static struct clk_branch gcc_cmn_12gpll_apu_clk = {
2430	.halt_reg = 0x3a00c,
2431	.clkr = {
2432		.enable_reg = 0x3a00c,
2433		.enable_mask = BIT(0),
2434		.hw.init = &(const struct clk_init_data) {
2435			.name = "gcc_cmn_12gpll_apu_clk",
2436			.parent_hws = (const struct clk_hw *[]) {
2437				&pcnoc_bfdcd_clk_src.clkr.hw
2438			},
2439			.num_parents = 1,
2440			.flags = CLK_SET_RATE_PARENT,
2441			.ops = &clk_branch2_ops,
2442		},
2443	},
2444};
2445
2446static struct clk_branch gcc_pcie0_ahb_clk = {
2447	.halt_reg = 0x28030,
2448	.clkr = {
2449		.enable_reg = 0x28030,
2450		.enable_mask = BIT(0),
2451		.hw.init = &(const struct clk_init_data) {
2452			.name = "gcc_pcie0_ahb_clk",
2453			.parent_hws = (const struct clk_hw *[]) {
2454				&pcnoc_bfdcd_clk_src.clkr.hw
2455			},
2456			.num_parents = 1,
2457			.flags = CLK_SET_RATE_PARENT,
2458			.ops = &clk_branch2_ops,
2459		},
2460	},
2461};
2462
2463static struct clk_branch gcc_pcie1_ahb_clk = {
2464	.halt_reg = 0x29030,
2465	.clkr = {
2466		.enable_reg = 0x29030,
2467		.enable_mask = BIT(0),
2468		.hw.init = &(const struct clk_init_data) {
2469			.name = "gcc_pcie1_ahb_clk",
2470			.parent_hws = (const struct clk_hw *[]) {
2471				&pcnoc_bfdcd_clk_src.clkr.hw
2472			},
2473			.num_parents = 1,
2474			.flags = CLK_SET_RATE_PARENT,
2475			.ops = &clk_branch2_ops,
2476		},
2477	},
2478};
2479
2480static struct clk_branch gcc_pcie2_ahb_clk = {
2481	.halt_reg = 0x2a030,
2482	.clkr = {
2483		.enable_reg = 0x2a030,
2484		.enable_mask = BIT(0),
2485		.hw.init = &(const struct clk_init_data) {
2486			.name = "gcc_pcie2_ahb_clk",
2487			.parent_hws = (const struct clk_hw *[]) {
2488				&pcnoc_bfdcd_clk_src.clkr.hw
2489			},
2490			.num_parents = 1,
2491			.flags = CLK_SET_RATE_PARENT,
2492			.ops = &clk_branch2_ops,
2493		},
2494	},
2495};
2496
2497static struct clk_branch gcc_pcie3_ahb_clk = {
2498	.halt_reg = 0x2b030,
2499	.clkr = {
2500		.enable_reg = 0x2b030,
2501		.enable_mask = BIT(0),
2502		.hw.init = &(const struct clk_init_data) {
2503			.name = "gcc_pcie3_ahb_clk",
2504			.parent_hws = (const struct clk_hw *[]) {
2505				&pcnoc_bfdcd_clk_src.clkr.hw
2506			},
2507			.num_parents = 1,
2508			.flags = CLK_SET_RATE_PARENT,
2509			.ops = &clk_branch2_ops,
2510		},
2511	},
2512};
2513
2514static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
2515	.halt_reg = 0x2c05c,
2516	.clkr = {
2517		.enable_reg = 0x2c05c,
2518		.enable_mask = BIT(0),
2519		.hw.init = &(const struct clk_init_data) {
2520			.name = "gcc_usb0_phy_cfg_ahb_clk",
2521			.parent_hws = (const struct clk_hw *[]) {
2522				&pcnoc_bfdcd_clk_src.clkr.hw
2523			},
2524			.num_parents = 1,
2525			.flags = CLK_SET_RATE_PARENT,
2526			.ops = &clk_branch2_ops,
2527		},
2528	},
2529};
2530
2531static struct clk_branch gcc_sdcc1_ahb_clk = {
2532	.halt_reg = 0x33034,
2533	.clkr = {
2534		.enable_reg = 0x33034,
2535		.enable_mask = BIT(0),
2536		.hw.init = &(const struct clk_init_data) {
2537			.name = "gcc_sdcc1_ahb_clk",
2538			.parent_hws = (const struct clk_hw *[]) {
2539				&pcnoc_bfdcd_clk_src.clkr.hw
2540			},
2541			.num_parents = 1,
2542			.flags = CLK_SET_RATE_PARENT,
2543			.ops = &clk_branch2_ops,
2544		},
2545	},
2546};
2547
2548static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = {
2549	F(24000000, P_XO, 1, 0, 0),
2550	F(133333333, P_GPLL0, 6, 0, 0),
2551	F(200000000, P_GPLL0, 4, 0, 0),
2552	F(342850000, P_GPLL4, 3.5, 0, 0),
2553	{ }
2554};
2555
2556static struct clk_rcg2 system_noc_bfdcd_clk_src = {
2557	.cmd_rcgr = 0x2e004,
2558	.freq_tbl = ftbl_system_noc_bfdcd_clk_src,
2559	.hid_width = 5,
2560	.parent_map = gcc_xo_gpll0_gpll4_map,
2561	.clkr.hw.init = &(const struct clk_init_data) {
2562		.name = "system_noc_bfdcd_clk_src",
2563		.parent_data = gcc_xo_gpll0_gpll4,
2564		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
2565		.flags = CLK_IS_CRITICAL,
2566		.ops = &clk_rcg2_ops,
2567	},
2568};
2569
2570static struct clk_branch gcc_q6ss_boot_clk = {
2571	.halt_reg = 0x25080,
2572	.halt_check = BRANCH_HALT_SKIP,
2573	.clkr = {
2574		.enable_reg = 0x25080,
2575		.enable_mask = BIT(0),
2576		.hw.init = &(const struct clk_init_data) {
2577			.name = "gcc_q6ss_boot_clk",
2578			.parent_hws = (const struct clk_hw *[]) {
2579				&system_noc_bfdcd_clk_src.clkr.hw
2580			},
2581			.num_parents = 1,
2582			.flags = CLK_SET_RATE_PARENT,
2583			.ops = &clk_branch2_ops,
2584		},
2585	},
2586};
2587
2588static struct clk_branch gcc_nssnoc_snoc_clk = {
2589	.halt_reg = 0x17028,
2590	.clkr = {
2591		.enable_reg = 0x17028,
2592		.enable_mask = BIT(0),
2593		.hw.init = &(const struct clk_init_data) {
2594			.name = "gcc_nssnoc_snoc_clk",
2595			.parent_hws = (const struct clk_hw *[]) {
2596				&system_noc_bfdcd_clk_src.clkr.hw
2597			},
2598			.num_parents = 1,
2599			.flags = CLK_SET_RATE_PARENT,
2600			.ops = &clk_branch2_ops,
2601		},
2602	},
2603};
2604
2605static struct clk_branch gcc_nssnoc_snoc_1_clk = {
2606	.halt_reg = 0x1707c,
2607	.clkr = {
2608		.enable_reg = 0x1707c,
2609		.enable_mask = BIT(0),
2610		.hw.init = &(const struct clk_init_data) {
2611			.name = "gcc_nssnoc_snoc_1_clk",
2612			.parent_hws = (const struct clk_hw *[]) {
2613				&system_noc_bfdcd_clk_src.clkr.hw
2614			},
2615			.num_parents = 1,
2616			.flags = CLK_SET_RATE_PARENT,
2617			.ops = &clk_branch2_ops,
2618		},
2619	},
2620};
2621
2622static struct clk_branch gcc_qdss_etr_usb_clk = {
2623	.halt_reg = 0x2d060,
2624	.clkr = {
2625		.enable_reg = 0x2d060,
2626		.enable_mask = BIT(0),
2627		.hw.init = &(const struct clk_init_data) {
2628			.name = "gcc_qdss_etr_usb_clk",
2629			.parent_hws = (const struct clk_hw *[]) {
2630				&system_noc_bfdcd_clk_src.clkr.hw
2631			},
2632			.num_parents = 1,
2633			.flags = CLK_SET_RATE_PARENT,
2634			.ops = &clk_branch2_ops,
2635		},
2636	},
2637};
2638
2639static const struct freq_tbl ftbl_wcss_ahb_clk_src[] = {
2640	F(24000000, P_XO, 1, 0, 0),
2641	F(133333333, P_GPLL0, 6, 0, 0),
2642	{ }
2643};
2644
2645static struct clk_rcg2 wcss_ahb_clk_src = {
2646	.cmd_rcgr = 0x25030,
2647	.freq_tbl = ftbl_wcss_ahb_clk_src,
2648	.hid_width = 5,
2649	.parent_map = gcc_xo_gpll0_map,
2650	.clkr.hw.init = &(const struct clk_init_data) {
2651		.name = "wcss_ahb_clk_src",
2652		.parent_data = gcc_xo_gpll0,
2653		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
2654		.ops = &clk_rcg2_ops,
2655	},
2656};
2657
2658static struct clk_branch gcc_q6_ahb_clk = {
2659	.halt_reg = 0x25014,
2660	.clkr = {
2661		.enable_reg = 0x25014,
2662		.enable_mask = BIT(0),
2663		.hw.init = &(const struct clk_init_data) {
2664			.name = "gcc_q6_ahb_clk",
2665			.parent_hws = (const struct clk_hw *[]) {
2666				&wcss_ahb_clk_src.clkr.hw
2667			},
2668			.num_parents = 1,
2669			.flags = CLK_SET_RATE_PARENT,
2670			.ops = &clk_branch2_ops,
2671		},
2672	},
2673};
2674
2675static struct clk_branch gcc_q6_ahb_s_clk = {
2676	.halt_reg = 0x25018,
2677	.clkr = {
2678		.enable_reg = 0x25018,
2679		.enable_mask = BIT(0),
2680		.hw.init = &(const struct clk_init_data) {
2681			.name = "gcc_q6_ahb_s_clk",
2682			.parent_hws = (const struct clk_hw *[]) {
2683				&wcss_ahb_clk_src.clkr.hw
2684			},
2685			.num_parents = 1,
2686			.flags = CLK_SET_RATE_PARENT,
2687			.ops = &clk_branch2_ops,
2688		},
2689	},
2690};
2691
2692static struct clk_branch gcc_wcss_ecahb_clk = {
2693	.halt_reg = 0x25058,
2694	.clkr = {
2695		.enable_reg = 0x25058,
2696		.enable_mask = BIT(0),
2697		.hw.init = &(const struct clk_init_data) {
2698			.name = "gcc_wcss_ecahb_clk",
2699			.parent_hws = (const struct clk_hw *[]) {
2700				&wcss_ahb_clk_src.clkr.hw
2701			},
2702			.num_parents = 1,
2703			.flags = CLK_SET_RATE_PARENT,
2704			.ops = &clk_branch2_ops,
2705		},
2706	},
2707};
2708
2709static struct clk_branch gcc_wcss_acmt_clk = {
2710	.halt_reg = 0x2505c,
2711	.clkr = {
2712		.enable_reg = 0x2505c,
2713		.enable_mask = BIT(0),
2714		.hw.init = &(const struct clk_init_data) {
2715			.name = "gcc_wcss_acmt_clk",
2716			.parent_hws = (const struct clk_hw *[]) {
2717				&wcss_ahb_clk_src.clkr.hw
2718			},
2719			.num_parents = 1,
2720			.flags = CLK_SET_RATE_PARENT,
2721			.ops = &clk_branch2_ops,
2722		},
2723	},
2724};
2725
2726static struct clk_branch gcc_sys_noc_wcss_ahb_clk = {
2727	.halt_reg = 0x2e030,
2728	.clkr = {
2729		.enable_reg = 0x2e030,
2730		.enable_mask = BIT(0),
2731		.hw.init = &(const struct clk_init_data) {
2732			.name = "gcc_sys_noc_wcss_ahb_clk",
2733			.parent_hws = (const struct clk_hw *[]) {
2734				&wcss_ahb_clk_src.clkr.hw
2735			},
2736			.num_parents = 1,
2737			.flags = CLK_SET_RATE_PARENT,
2738			.ops = &clk_branch2_ops,
2739		},
2740	},
2741};
2742
2743static const struct freq_tbl ftbl_wcss_axi_m_clk_src[] = {
2744	F(24000000, P_XO, 1, 0, 0),
2745	F(133333333, P_GPLL0, 6, 0, 0),
2746	F(266666667, P_GPLL0, 3, 0, 0),
2747	{ }
2748};
2749
2750static struct clk_rcg2 wcss_axi_m_clk_src = {
2751	.cmd_rcgr = 0x25078,
2752	.freq_tbl = ftbl_wcss_axi_m_clk_src,
2753	.hid_width = 5,
2754	.parent_map = gcc_xo_gpll0_map,
2755	.clkr.hw.init = &(const struct clk_init_data) {
2756		.name = "wcss_axi_m_clk_src",
2757		.parent_data = gcc_xo_gpll0,
2758		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
2759		.ops = &clk_rcg2_ops,
2760	},
2761};
2762
2763static struct clk_branch gcc_anoc_wcss_axi_m_clk = {
2764	.halt_reg = 0x2e0a8,
2765	.clkr = {
2766		.enable_reg = 0x2e0a8,
2767		.enable_mask = BIT(0),
2768		.hw.init = &(const struct clk_init_data) {
2769			.name = "gcc_anoc_wcss_axi_m_clk",
2770			.parent_hws = (const struct clk_hw *[]) {
2771				&wcss_axi_m_clk_src.clkr.hw
2772			},
2773			.num_parents = 1,
2774			.flags = CLK_SET_RATE_PARENT,
2775			.ops = &clk_branch2_ops,
2776		},
2777	},
2778};
2779
2780static const struct freq_tbl ftbl_qdss_at_clk_src[] = {
2781	F(240000000, P_GPLL4, 5, 0, 0),
2782	{ }
2783};
2784
2785static struct clk_rcg2 qdss_at_clk_src = {
2786	.cmd_rcgr = 0x2d004,
2787	.freq_tbl = ftbl_qdss_at_clk_src,
2788	.hid_width = 5,
2789	.parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
2790	.clkr.hw.init = &(const struct clk_init_data) {
2791		.name = "qdss_at_clk_src",
2792		.parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
2793		.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2),
2794		.ops = &clk_rcg2_ops,
2795	},
2796};
2797
2798static struct clk_branch gcc_q6ss_atbm_clk = {
2799	.halt_reg = 0x2501c,
2800	.clkr = {
2801		.enable_reg = 0x2501c,
2802		.enable_mask = BIT(0),
2803		.hw.init = &(const struct clk_init_data) {
2804			.name = "gcc_q6ss_atbm_clk",
2805			.parent_hws = (const struct clk_hw *[]) {
2806				&qdss_at_clk_src.clkr.hw
2807			},
2808			.num_parents = 1,
2809			.flags = CLK_SET_RATE_PARENT,
2810			.ops = &clk_branch2_ops,
2811		},
2812	},
2813};
2814
2815static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = {
2816	.halt_reg = 0x2503c,
2817	.clkr = {
2818		.enable_reg = 0x2503c,
2819		.enable_mask = BIT(0),
2820		.hw.init = &(const struct clk_init_data) {
2821			.name = "gcc_wcss_dbg_ifc_atb_clk",
2822			.parent_hws = (const struct clk_hw *[]) {
2823				&qdss_at_clk_src.clkr.hw
2824			},
2825			.num_parents = 1,
2826			.flags = CLK_SET_RATE_PARENT,
2827			.ops = &clk_branch2_ops,
2828		},
2829	},
2830};
2831
2832static struct clk_branch gcc_nssnoc_atb_clk = {
2833	.halt_reg = 0x17014,
2834	.clkr = {
2835		.enable_reg = 0x17014,
2836		.enable_mask = BIT(0),
2837		.hw.init = &(const struct clk_init_data) {
2838			.name = "gcc_nssnoc_atb_clk",
2839			.parent_hws = (const struct clk_hw *[]) {
2840				&qdss_at_clk_src.clkr.hw
2841			},
2842			.num_parents = 1,
2843			.flags = CLK_SET_RATE_PARENT,
2844			.ops = &clk_branch2_ops,
2845		},
2846	},
2847};
2848
2849static struct clk_branch gcc_qdss_at_clk = {
2850	.halt_reg = 0x2d038,
2851	.clkr = {
2852		.enable_reg = 0x2d038,
2853		.enable_mask = BIT(0),
2854		.hw.init = &(const struct clk_init_data) {
2855			.name = "gcc_qdss_at_clk",
2856			.parent_hws = (const struct clk_hw *[]) {
2857				&qdss_at_clk_src.clkr.hw
2858			},
2859			.num_parents = 1,
2860			.flags = CLK_SET_RATE_PARENT,
2861			.ops = &clk_branch2_ops,
2862		},
2863	},
2864};
2865
2866static struct clk_branch gcc_sys_noc_at_clk = {
2867	.halt_reg = 0x2e038,
2868	.clkr = {
2869		.enable_reg = 0x2e038,
2870		.enable_mask = BIT(0),
2871		.hw.init = &(const struct clk_init_data) {
2872			.name = "gcc_sys_noc_at_clk",
2873			.parent_hws = (const struct clk_hw *[]) {
2874				&qdss_at_clk_src.clkr.hw
2875			},
2876			.num_parents = 1,
2877			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2878			.ops = &clk_branch2_ops,
2879		},
2880	},
2881};
2882
2883static struct clk_branch gcc_pcnoc_at_clk = {
2884	.halt_reg = 0x31024,
2885	.clkr = {
2886		.enable_reg = 0x31024,
2887		.enable_mask = BIT(0),
2888		.hw.init = &(const struct clk_init_data) {
2889			.name = "gcc_pcnoc_at_clk",
2890			.parent_hws = (const struct clk_hw *[]) {
2891				&qdss_at_clk_src.clkr.hw
2892			},
2893			.num_parents = 1,
2894			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2895			.ops = &clk_branch2_ops,
2896		},
2897	},
2898};
2899
2900static struct clk_fixed_factor gcc_eud_at_div_clk_src = {
2901	.mult = 1,
2902	.div = 6,
2903	.hw.init = &(const struct clk_init_data) {
2904		.name = "gcc_eud_at_div_clk_src",
2905		.parent_hws = (const struct clk_hw *[]) {
2906			&qdss_at_clk_src.clkr.hw
2907		},
2908		.num_parents = 1,
2909		.flags = CLK_SET_RATE_PARENT,
2910		.ops = &clk_fixed_factor_ops,
2911	},
2912};
2913
2914static struct clk_branch gcc_usb0_eud_at_clk = {
2915	.halt_reg = 0x30004,
2916	.clkr = {
2917		.enable_reg = 0x30004,
2918		.enable_mask = BIT(0),
2919		.hw.init = &(const struct clk_init_data) {
2920			.name = "gcc_usb0_eud_at_clk",
2921			.parent_hws = (const struct clk_hw *[]) {
2922				&gcc_eud_at_div_clk_src.hw
2923			},
2924			.num_parents = 1,
2925			.flags = CLK_SET_RATE_PARENT,
2926			.ops = &clk_branch2_ops,
2927		},
2928	},
2929};
2930
2931static struct clk_branch gcc_qdss_eud_at_clk = {
2932	.halt_reg = 0x2d06c,
2933	.clkr = {
2934		.enable_reg = 0x2d06c,
2935		.enable_mask = BIT(0),
2936		.hw.init = &(const struct clk_init_data) {
2937			.name = "gcc_qdss_eud_at_clk",
2938			.parent_hws = (const struct clk_hw *[]) {
2939				&gcc_eud_at_div_clk_src.hw
2940			},
2941			.num_parents = 1,
2942			.flags = CLK_SET_RATE_PARENT,
2943			.ops = &clk_branch2_ops,
2944		},
2945	},
2946};
2947
2948static const struct freq_tbl ftbl_qdss_stm_clk_src[] = {
2949	F(24000000, P_XO, 1, 0, 0),
2950	F(200000000, P_GPLL0, 4, 0, 0),
2951	{ }
2952};
2953
2954static struct clk_rcg2 qdss_stm_clk_src = {
2955	.cmd_rcgr = 0x2d00c,
2956	.freq_tbl = ftbl_qdss_stm_clk_src,
2957	.hid_width = 5,
2958	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
2959	.clkr.hw.init = &(const struct clk_init_data) {
2960		.name = "qdss_stm_clk_src",
2961		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
2962		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
2963		.ops = &clk_rcg2_ops,
2964	},
2965};
2966
2967static struct clk_branch gcc_qdss_stm_clk = {
2968	.halt_reg = 0x2d03c,
2969	.clkr = {
2970		.enable_reg = 0x2d03c,
2971		.enable_mask = BIT(0),
2972		.hw.init = &(const struct clk_init_data) {
2973			.name = "gcc_qdss_stm_clk",
2974			.parent_hws = (const struct clk_hw *[]) {
2975				&qdss_stm_clk_src.clkr.hw
2976			},
2977			.num_parents = 1,
2978			.flags = CLK_SET_RATE_PARENT,
2979			.ops = &clk_branch2_ops,
2980		},
2981	},
2982};
2983
2984static struct clk_branch gcc_sys_noc_qdss_stm_axi_clk = {
2985	.halt_reg = 0x2e034,
2986	.clkr = {
2987		.enable_reg = 0x2e034,
2988		.enable_mask = BIT(0),
2989		.hw.init = &(const struct clk_init_data) {
2990			.name = "gcc_sys_noc_qdss_stm_axi_clk",
2991			.parent_hws = (const struct clk_hw *[]) {
2992				&qdss_stm_clk_src.clkr.hw
2993			},
2994			.num_parents = 1,
2995			.flags = CLK_SET_RATE_PARENT,
2996			.ops = &clk_branch2_ops,
2997		},
2998	},
2999};
3000
3001static const struct freq_tbl ftbl_qdss_traceclkin_clk_src[] = {
3002	F(300000000, P_GPLL4, 4, 0, 0),
3003	{ }
3004};
3005
3006static struct clk_rcg2 qdss_traceclkin_clk_src = {
3007	.cmd_rcgr = 0x2d014,
3008	.freq_tbl = ftbl_qdss_traceclkin_clk_src,
3009	.hid_width = 5,
3010	.parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
3011	.clkr.hw.init = &(const struct clk_init_data) {
3012		.name = "qdss_traceclkin_clk_src",
3013		.parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
3014		.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2),
3015		.ops = &clk_rcg2_ops,
3016	},
3017};
3018
3019static struct clk_branch gcc_qdss_traceclkin_clk = {
3020	.halt_reg = 0x2d040,
3021	.clkr = {
3022		.enable_reg = 0x2d040,
3023		.enable_mask = BIT(0),
3024		.hw.init = &(const struct clk_init_data) {
3025			.name = "gcc_qdss_traceclkin_clk",
3026			.parent_hws = (const struct clk_hw *[]) {
3027				&qdss_traceclkin_clk_src.clkr.hw
3028			},
3029			.num_parents = 1,
3030			.flags = CLK_SET_RATE_PARENT,
3031			.ops = &clk_branch2_ops,
3032		},
3033	},
3034};
3035
3036static const struct freq_tbl ftbl_qdss_tsctr_clk_src[] = {
3037	F(600000000, P_GPLL4, 2, 0, 0),
3038	{ }
3039};
3040
3041static struct clk_rcg2 qdss_tsctr_clk_src = {
3042	.cmd_rcgr = 0x2d01c,
3043	.freq_tbl = ftbl_qdss_tsctr_clk_src,
3044	.hid_width = 5,
3045	.parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
3046	.clkr.hw.init = &(const struct clk_init_data) {
3047		.name = "qdss_tsctr_clk_src",
3048		.parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
3049		.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2),
3050		.ops = &clk_rcg2_ops,
3051	},
3052};
3053
3054static struct clk_fixed_factor qdss_tsctr_div2_clk_src = {
3055	.mult = 1,
3056	.div = 2,
3057	.hw.init = &(const struct clk_init_data) {
3058		.name = "qdss_tsctr_div2_clk_src",
3059		.parent_hws = (const struct clk_hw *[]) {
3060			&qdss_tsctr_clk_src.clkr.hw
3061		},
3062		.num_parents = 1,
3063		.flags = CLK_SET_RATE_PARENT,
3064		.ops = &clk_fixed_factor_ops,
3065	},
3066};
3067
3068static struct clk_branch gcc_q6_tsctr_1to2_clk = {
3069	.halt_reg = 0x25020,
3070	.clkr = {
3071		.enable_reg = 0x25020,
3072		.enable_mask = BIT(0),
3073		.hw.init = &(const struct clk_init_data) {
3074			.name = "gcc_q6_tsctr_1to2_clk",
3075			.parent_hws = (const struct clk_hw *[]) {
3076				&qdss_tsctr_div2_clk_src.hw
3077			},
3078			.num_parents = 1,
3079			.flags = CLK_SET_RATE_PARENT,
3080			.ops = &clk_branch2_ops,
3081		},
3082	},
3083};
3084
3085static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = {
3086	.halt_reg = 0x25040,
3087	.clkr = {
3088		.enable_reg = 0x25040,
3089		.enable_mask = BIT(0),
3090		.hw.init = &(const struct clk_init_data) {
3091			.name = "gcc_wcss_dbg_ifc_nts_clk",
3092			.parent_hws = (const struct clk_hw *[]) {
3093				&qdss_tsctr_div2_clk_src.hw
3094			},
3095			.num_parents = 1,
3096			.flags = CLK_SET_RATE_PARENT,
3097			.ops = &clk_branch2_ops,
3098		},
3099	},
3100};
3101
3102static struct clk_branch gcc_qdss_tsctr_div2_clk = {
3103	.halt_reg = 0x2d044,
3104	.clkr = {
3105		.enable_reg = 0x2d044,
3106		.enable_mask = BIT(0),
3107		.hw.init = &(const struct clk_init_data) {
3108			.name = "gcc_qdss_tsctr_div2_clk",
3109			.parent_hws = (const struct clk_hw *[]) {
3110				&qdss_tsctr_div2_clk_src.hw
3111			},
3112			.num_parents = 1,
3113			.flags = CLK_SET_RATE_PARENT,
3114			.ops = &clk_branch2_ops,
3115		},
3116	},
3117};
3118
3119static const struct freq_tbl ftbl_uniphy_sys_clk_src[] = {
3120	F(24000000, P_XO, 1, 0, 0),
3121	{ }
3122};
3123
3124static struct clk_rcg2 uniphy_sys_clk_src = {
3125	.cmd_rcgr = 0x17090,
3126	.freq_tbl = ftbl_uniphy_sys_clk_src,
3127	.mnd_width = 8,
3128	.hid_width = 5,
3129	.parent_map = gcc_xo_map,
3130	.clkr.hw.init = &(const struct clk_init_data) {
3131		.name = "uniphy_sys_clk_src",
3132		.parent_data = gcc_xo_data,
3133		.num_parents = ARRAY_SIZE(gcc_xo_data),
3134		.ops = &clk_rcg2_ops,
3135	},
3136};
3137
3138static struct clk_rcg2 nss_ts_clk_src = {
3139	.cmd_rcgr = 0x17088,
3140	.freq_tbl = ftbl_uniphy_sys_clk_src,
3141	.mnd_width = 8,
3142	.hid_width = 5,
3143	.parent_map = gcc_xo_map,
3144	.clkr.hw.init = &(const struct clk_init_data) {
3145		.name = "nss_ts_clk_src",
3146		.parent_data = gcc_xo_data,
3147		.num_parents = ARRAY_SIZE(gcc_xo_data),
3148		.ops = &clk_rcg2_ops,
3149	},
3150};
3151
3152static struct clk_branch gcc_qdss_ts_clk = {
3153	.halt_reg = 0x2d078,
3154	.clkr = {
3155		.enable_reg = 0x2d078,
3156		.enable_mask = BIT(0),
3157		.hw.init = &(const struct clk_init_data) {
3158			.name = "gcc_qdss_ts_clk",
3159			.parent_hws = (const struct clk_hw *[]) {
3160				&nss_ts_clk_src.clkr.hw
3161			},
3162			.num_parents = 1,
3163			.flags = CLK_SET_RATE_PARENT,
3164			.ops = &clk_branch2_ops,
3165		},
3166	},
3167};
3168
3169static struct clk_fixed_factor qdss_dap_sync_clk_src = {
3170	.mult = 1,
3171	.div = 4,
3172	.hw.init = &(const struct clk_init_data) {
3173		.name = "qdss_dap_sync_clk_src",
3174		.parent_hws = (const struct clk_hw *[]) {
3175			&qdss_tsctr_clk_src.clkr.hw
3176		},
3177		.num_parents = 1,
3178		.ops = &clk_fixed_factor_ops,
3179	},
3180};
3181
3182static struct clk_branch gcc_qdss_tsctr_div4_clk = {
3183	.halt_reg = 0x2d04c,
3184	.clkr = {
3185		.enable_reg = 0x2d04c,
3186		.enable_mask = BIT(0),
3187		.hw.init = &(const struct clk_init_data) {
3188			.name = "gcc_qdss_tsctr_div4_clk",
3189			.parent_hws = (const struct clk_hw *[]) {
3190				&qdss_dap_sync_clk_src.hw
3191			},
3192			.num_parents = 1,
3193			.flags = CLK_SET_RATE_PARENT,
3194			.ops = &clk_branch2_ops,
3195		},
3196	},
3197};
3198
3199static struct clk_fixed_factor qdss_tsctr_div8_clk_src = {
3200	.mult = 1,
3201	.div = 8,
3202	.hw.init = &(const struct clk_init_data) {
3203		.name = "qdss_tsctr_div8_clk_src",
3204		.parent_hws = (const struct clk_hw *[]) {
3205			&qdss_tsctr_clk_src.clkr.hw
3206		},
3207		.num_parents = 1,
3208		.ops = &clk_fixed_factor_ops,
3209	},
3210};
3211
3212static struct clk_branch gcc_nss_ts_clk = {
3213	.halt_reg = 0x17018,
3214	.clkr = {
3215		.enable_reg = 0x17018,
3216		.enable_mask = BIT(0),
3217		.hw.init = &(const struct clk_init_data) {
3218			.name = "gcc_nss_ts_clk",
3219			.parent_hws = (const struct clk_hw *[]) {
3220				&nss_ts_clk_src.clkr.hw
3221			},
3222			.num_parents = 1,
3223			.flags = CLK_SET_RATE_PARENT,
3224			.ops = &clk_branch2_ops,
3225		},
3226	},
3227};
3228
3229static struct clk_branch gcc_qdss_tsctr_div8_clk = {
3230	.halt_reg = 0x2d050,
3231	.clkr = {
3232		.enable_reg = 0x2d050,
3233		.enable_mask = BIT(0),
3234		.hw.init = &(const struct clk_init_data) {
3235			.name = "gcc_qdss_tsctr_div8_clk",
3236			.parent_hws = (const struct clk_hw *[]) {
3237				&qdss_tsctr_div8_clk_src.hw
3238			},
3239			.num_parents = 1,
3240			.flags = CLK_SET_RATE_PARENT,
3241			.ops = &clk_branch2_ops,
3242		},
3243	},
3244};
3245
3246static struct clk_fixed_factor qdss_tsctr_div16_clk_src = {
3247	.mult = 1,
3248	.div = 16,
3249	.hw.init = &(const struct clk_init_data) {
3250		.name = "qdss_tsctr_div16_clk_src",
3251		.parent_hws = (const struct clk_hw *[]) {
3252			&qdss_tsctr_clk_src.clkr.hw
3253		},
3254		.num_parents = 1,
3255		.ops = &clk_fixed_factor_ops,
3256	},
3257};
3258
3259static struct clk_branch gcc_qdss_tsctr_div16_clk = {
3260	.halt_reg = 0x2d054,
3261	.clkr = {
3262		.enable_reg = 0x2d054,
3263		.enable_mask = BIT(0),
3264		.hw.init = &(const struct clk_init_data) {
3265			.name = "gcc_qdss_tsctr_div16_clk",
3266			.parent_hws = (const struct clk_hw *[]) {
3267				&qdss_tsctr_div16_clk_src.hw
3268			},
3269			.num_parents = 1,
3270			.flags = CLK_SET_RATE_PARENT,
3271			.ops = &clk_branch2_ops,
3272		},
3273	},
3274};
3275
3276static struct clk_branch gcc_q6ss_pclkdbg_clk = {
3277	.halt_reg = 0x25024,
3278	.clkr = {
3279		.enable_reg = 0x25024,
3280		.enable_mask = BIT(0),
3281		.hw.init = &(const struct clk_init_data) {
3282			.name = "gcc_q6ss_pclkdbg_clk",
3283			.parent_hws = (const struct clk_hw *[]) {
3284				&qdss_dap_sync_clk_src.hw
3285			},
3286			.num_parents = 1,
3287			.flags = CLK_SET_RATE_PARENT,
3288			.ops = &clk_branch2_ops,
3289		},
3290	},
3291};
3292
3293static struct clk_branch gcc_q6ss_trig_clk = {
3294	.halt_reg = 0x25068,
3295	.clkr = {
3296		.enable_reg = 0x25068,
3297		.enable_mask = BIT(0),
3298		.hw.init = &(const struct clk_init_data) {
3299			.name = "gcc_q6ss_trig_clk",
3300			.parent_hws = (const struct clk_hw *[]) {
3301				&qdss_dap_sync_clk_src.hw
3302			},
3303			.num_parents = 1,
3304			.flags = CLK_SET_RATE_PARENT,
3305			.ops = &clk_branch2_ops,
3306		},
3307	},
3308};
3309
3310static struct clk_branch gcc_wcss_dbg_ifc_apb_clk = {
3311	.halt_reg = 0x25038,
3312	.clkr = {
3313		.enable_reg = 0x25038,
3314		.enable_mask = BIT(0),
3315		.hw.init = &(const struct clk_init_data) {
3316			.name = "gcc_wcss_dbg_ifc_apb_clk",
3317			.parent_hws = (const struct clk_hw *[]) {
3318				&qdss_dap_sync_clk_src.hw
3319			},
3320			.num_parents = 1,
3321			.flags = CLK_SET_RATE_PARENT,
3322			.ops = &clk_branch2_ops,
3323		},
3324	},
3325};
3326
3327static struct clk_branch gcc_wcss_dbg_ifc_dapbus_clk = {
3328	.halt_reg = 0x25044,
3329	.clkr = {
3330		.enable_reg = 0x25044,
3331		.enable_mask = BIT(0),
3332		.hw.init = &(const struct clk_init_data) {
3333			.name = "gcc_wcss_dbg_ifc_dapbus_clk",
3334			.parent_hws = (const struct clk_hw *[]) {
3335				&qdss_dap_sync_clk_src.hw
3336			},
3337			.num_parents = 1,
3338			.flags = CLK_SET_RATE_PARENT,
3339			.ops = &clk_branch2_ops,
3340		},
3341	},
3342};
3343
3344static struct clk_branch gcc_qdss_dap_clk = {
3345	.halt_reg = 0x2d058,
3346	.clkr = {
3347		.enable_reg = 0x2d058,
3348		.enable_mask = BIT(0),
3349		.hw.init = &(const struct clk_init_data) {
3350			.name = "gcc_qdss_dap_clk",
3351			.parent_hws = (const struct clk_hw *[]) {
3352				&qdss_dap_sync_clk_src.hw
3353			},
3354			.num_parents = 1,
3355			.flags = CLK_SET_RATE_PARENT,
3356			.ops = &clk_branch2_ops,
3357		},
3358	},
3359};
3360
3361static struct clk_branch gcc_qdss_apb2jtag_clk = {
3362	.halt_reg = 0x2d05c,
3363	.clkr = {
3364		.enable_reg = 0x2d05c,
3365		.enable_mask = BIT(0),
3366		.hw.init = &(const struct clk_init_data) {
3367			.name = "gcc_qdss_apb2jtag_clk",
3368			.parent_hws = (const struct clk_hw *[]) {
3369				&qdss_dap_sync_clk_src.hw
3370			},
3371			.num_parents = 1,
3372			.flags = CLK_SET_RATE_PARENT,
3373			.ops = &clk_branch2_ops,
3374		},
3375	},
3376};
3377
3378static struct clk_fixed_factor qdss_tsctr_div3_clk_src = {
3379	.mult = 1,
3380	.div = 3,
3381	.hw.init = &(const struct clk_init_data) {
3382		.name = "qdss_tsctr_div3_clk_src",
3383		.parent_hws = (const struct clk_hw *[]) {
3384			&qdss_tsctr_clk_src.clkr.hw
3385		},
3386		.num_parents = 1,
3387		.ops = &clk_fixed_factor_ops,
3388	},
3389};
3390
3391static struct clk_branch gcc_qdss_tsctr_div3_clk = {
3392	.halt_reg = 0x2d048,
3393	.clkr = {
3394		.enable_reg = 0x2d048,
3395		.enable_mask = BIT(0),
3396		.hw.init = &(const struct clk_init_data) {
3397			.name = "gcc_qdss_tsctr_div3_clk",
3398			.parent_hws = (const struct clk_hw *[]) {
3399				&qdss_tsctr_div3_clk_src.hw
3400			},
3401			.num_parents = 1,
3402			.flags = CLK_SET_RATE_PARENT,
3403			.ops = &clk_branch2_ops,
3404		},
3405	},
3406};
3407
3408static const struct freq_tbl ftbl_qpic_io_macro_clk_src[] = {
3409	F(24000000, P_XO, 1, 0, 0),
3410	F(100000000, P_GPLL0, 8, 0, 0),
3411	F(200000000, P_GPLL0, 4, 0, 0),
3412	F(320000000, P_GPLL0, 2.5, 0, 0),
3413	F(400000000, P_GPLL0, 2, 0, 0),
3414	{ }
3415};
3416
3417static struct clk_rcg2 qpic_io_macro_clk_src = {
3418	.cmd_rcgr = 0x32004,
3419	.freq_tbl = ftbl_qpic_io_macro_clk_src,
3420	.hid_width = 5,
3421	.parent_map = gcc_xo_gpll0_gpll2_map,
3422	.clkr.hw.init = &(const struct clk_init_data) {
3423		.name = "qpic_io_macro_clk_src",
3424		.parent_data = gcc_xo_gpll0_gpll2,
3425		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
3426		.ops = &clk_rcg2_ops,
3427	},
3428};
3429
3430static struct clk_branch gcc_qpic_io_macro_clk = {
3431	.halt_reg = 0x3200c,
3432	.clkr = {
3433		.enable_reg = 0x3200c,
3434		.enable_mask = BIT(0),
3435		.hw.init = &(const struct clk_init_data){
3436			.name = "gcc_qpic_io_macro_clk",
3437			.parent_hws = (const struct clk_hw *[]){
3438				&qpic_io_macro_clk_src.clkr.hw
3439			},
3440			.num_parents = 1,
3441			.flags = CLK_SET_RATE_PARENT,
3442			.ops = &clk_branch2_ops,
3443		},
3444	},
3445};
3446
3447static const struct freq_tbl ftbl_q6_axi_clk_src[] = {
3448	F(533333333, P_GPLL0, 1.5, 0, 0),
3449	{ }
3450};
3451
3452static struct clk_rcg2 q6_axi_clk_src = {
3453	.cmd_rcgr = 0x25004,
3454	.freq_tbl = ftbl_q6_axi_clk_src,
3455	.hid_width = 5,
3456	.parent_map = gcc_xo_gpll0_gpll2_gpll4_pi_sleep_map,
3457	.clkr.hw.init = &(const struct clk_init_data) {
3458		.name = "q6_axi_clk_src",
3459		.parent_data = gcc_xo_gpll0_gpll2_gpll4_pi_sleep,
3460		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll4_pi_sleep),
3461		.ops = &clk_rcg2_ops,
3462	},
3463};
3464
3465static struct clk_branch gcc_q6_axim_clk = {
3466	.halt_reg = 0x2500c,
3467	.clkr = {
3468		.enable_reg = 0x2500c,
3469		.enable_mask = BIT(0),
3470		.hw.init = &(const struct clk_init_data) {
3471			.name = "gcc_q6_axim_clk",
3472			.parent_hws = (const struct clk_hw *[]) {
3473				&q6_axi_clk_src.clkr.hw
3474			},
3475			.num_parents = 1,
3476			.flags = CLK_SET_RATE_PARENT,
3477			.ops = &clk_branch2_ops,
3478		},
3479	},
3480};
3481
3482static struct clk_branch gcc_wcss_q6_tbu_clk = {
3483	.halt_reg = 0x12050,
3484	.halt_check = BRANCH_HALT_DELAY,
3485	.clkr = {
3486		.enable_reg = 0xb00c,
3487		.enable_mask = BIT(6),
3488		.hw.init = &(const struct clk_init_data) {
3489			.name = "gcc_wcss_q6_tbu_clk",
3490			.parent_hws = (const struct clk_hw *[]) {
3491				&q6_axi_clk_src.clkr.hw
3492			},
3493			.num_parents = 1,
3494			.flags = CLK_SET_RATE_PARENT,
3495			.ops = &clk_branch2_ops,
3496		},
3497	},
3498};
3499
3500static struct clk_branch gcc_mem_noc_q6_axi_clk = {
3501	.halt_reg = 0x19010,
3502	.clkr = {
3503		.enable_reg = 0x19010,
3504		.enable_mask = BIT(0),
3505		.hw.init = &(const struct clk_init_data) {
3506			.name = "gcc_mem_noc_q6_axi_clk",
3507			.parent_hws = (const struct clk_hw *[]) {
3508				&q6_axi_clk_src.clkr.hw
3509			},
3510			.num_parents = 1,
3511			.flags = CLK_SET_RATE_PARENT,
3512			.ops = &clk_branch2_ops,
3513		},
3514	},
3515};
3516
3517static const struct freq_tbl ftbl_q6_axim2_clk_src[] = {
3518	F(342857143, P_GPLL4, 3.5, 0, 0),
3519	{ }
3520};
3521
3522static const struct parent_map gcc_xo_gpll0_gpll4_bias_pll_ubinc_clk_map[] = {
3523	{ P_XO, 0 },
3524	{ P_GPLL0, 1 },
3525	{ P_GPLL4, 2 },
3526	{ P_BIAS_PLL_UBI_NC_CLK, 4 },
3527};
3528
3529static struct clk_rcg2 q6_axim2_clk_src = {
3530	.cmd_rcgr = 0x25028,
3531	.freq_tbl = ftbl_q6_axim2_clk_src,
3532	.hid_width = 5,
3533	.parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubinc_clk_map,
3534	.clkr.hw.init = &(const struct clk_init_data) {
3535		.name = "q6_axim2_clk_src",
3536		.parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk,
3537		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk),
3538		.ops = &clk_rcg2_ops,
3539	},
3540};
3541
3542static const struct freq_tbl ftbl_nssnoc_memnoc_bfdcd_clk_src[] = {
3543	F(533333333, P_GPLL0, 1.5, 0, 0),
3544	{ }
3545};
3546
3547static struct clk_rcg2 nssnoc_memnoc_bfdcd_clk_src = {
3548	.cmd_rcgr = 0x17004,
3549	.freq_tbl = ftbl_nssnoc_memnoc_bfdcd_clk_src,
3550	.hid_width = 5,
3551	.parent_map = gcc_xo_gpll0_gpll0_aux_gpll2_map,
3552	.clkr.hw.init = &(const struct clk_init_data) {
3553		.name = "nssnoc_memnoc_bfdcd_clk_src",
3554		.parent_data = gcc_xo_gpll0_gpll0_aux_gpll2,
3555		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_aux_gpll2),
3556		.ops = &clk_rcg2_ops,
3557	},
3558};
3559
3560static struct clk_branch gcc_nssnoc_memnoc_clk = {
3561	.halt_reg = 0x17024,
3562	.clkr = {
3563		.enable_reg = 0x17024,
3564		.enable_mask = BIT(0),
3565		.hw.init = &(const struct clk_init_data) {
3566			.name = "gcc_nssnoc_memnoc_clk",
3567			.parent_hws = (const struct clk_hw *[]) {
3568				&nssnoc_memnoc_bfdcd_clk_src.clkr.hw
3569			},
3570			.num_parents = 1,
3571			.flags = CLK_SET_RATE_PARENT,
3572			.ops = &clk_branch2_ops,
3573		},
3574	},
3575};
3576
3577static struct clk_branch gcc_nssnoc_mem_noc_1_clk = {
3578	.halt_reg = 0x17084,
3579	.clkr = {
3580		.enable_reg = 0x17084,
3581		.enable_mask = BIT(0),
3582		.hw.init = &(const struct clk_init_data) {
3583			.name = "gcc_nssnoc_mem_noc_1_clk",
3584			.parent_hws = (const struct clk_hw *[]) {
3585				&nssnoc_memnoc_bfdcd_clk_src.clkr.hw
3586			},
3587			.num_parents = 1,
3588			.flags = CLK_SET_RATE_PARENT,
3589			.ops = &clk_branch2_ops,
3590		},
3591	},
3592};
3593
3594static struct clk_branch gcc_nss_tbu_clk = {
3595	.halt_reg = 0x12040,
3596	.clkr = {
3597		.enable_reg = 0xb00c,
3598		.enable_mask = BIT(4),
3599		.hw.init = &(const struct clk_init_data) {
3600			.name = "gcc_nss_tbu_clk",
3601			.parent_hws = (const struct clk_hw *[]) {
3602				&nssnoc_memnoc_bfdcd_clk_src.clkr.hw
3603			},
3604			.num_parents = 1,
3605			.flags = CLK_SET_RATE_PARENT,
3606			.ops = &clk_branch2_ops,
3607		},
3608	},
3609};
3610
3611static struct clk_branch gcc_mem_noc_nssnoc_clk = {
3612	.halt_reg = 0x19014,
3613	.clkr = {
3614		.enable_reg = 0x19014,
3615		.enable_mask = BIT(0),
3616		.hw.init = &(const struct clk_init_data) {
3617			.name = "gcc_mem_noc_nssnoc_clk",
3618			.parent_hws = (const struct clk_hw *[]) {
3619				&nssnoc_memnoc_bfdcd_clk_src.clkr.hw
3620			},
3621			.num_parents = 1,
3622			.flags = CLK_SET_RATE_PARENT,
3623			.ops = &clk_branch2_ops,
3624		},
3625	},
3626};
3627
3628static const struct freq_tbl ftbl_lpass_axim_clk_src[] = {
3629	F(133333333, P_GPLL0, 6, 0, 0),
3630	{ }
3631};
3632
3633static struct clk_rcg2 lpass_axim_clk_src = {
3634	.cmd_rcgr = 0x2700c,
3635	.freq_tbl = ftbl_lpass_axim_clk_src,
3636	.hid_width = 5,
3637	.parent_map = gcc_xo_gpll0_map,
3638	.clkr.hw.init = &(const struct clk_init_data) {
3639		.name = "lpass_axim_clk_src",
3640		.parent_data = gcc_xo_gpll0,
3641		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
3642		.ops = &clk_rcg2_ops,
3643	},
3644};
3645
3646static struct clk_rcg2 lpass_sway_clk_src = {
3647	.cmd_rcgr = 0x27004,
3648	.freq_tbl = ftbl_lpass_axim_clk_src,
3649	.hid_width = 5,
3650	.parent_map = gcc_xo_gpll0_map,
3651	.clkr.hw.init = &(const struct clk_init_data) {
3652		.name = "lpass_sway_clk_src",
3653		.parent_data = gcc_xo_gpll0,
3654		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
3655		.ops = &clk_rcg2_ops,
3656	},
3657};
3658
3659static const struct freq_tbl ftbl_adss_pwm_clk_src[] = {
3660	F(24000000, P_XO, 1, 0, 0),
3661	F(100000000, P_GPLL0, 8, 0, 0),
3662	{ }
3663};
3664
3665static struct clk_rcg2 adss_pwm_clk_src = {
3666	.cmd_rcgr = 0x1c004,
3667	.freq_tbl = ftbl_adss_pwm_clk_src,
3668	.hid_width = 5,
3669	.parent_map = gcc_xo_gpll0_map,
3670	.clkr.hw.init = &(const struct clk_init_data) {
3671		.name = "adss_pwm_clk_src",
3672		.parent_data = gcc_xo_gpll0,
3673		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
3674		.ops = &clk_rcg2_ops,
3675	},
3676};
3677
3678static struct clk_branch gcc_adss_pwm_clk = {
3679	.halt_reg = 0x1c00c,
3680	.clkr = {
3681		.enable_reg = 0x1c00c,
3682		.enable_mask = BIT(0),
3683		.hw.init = &(const struct clk_init_data) {
3684			.name = "gcc_adss_pwm_clk",
3685			.parent_hws = (const struct clk_hw *[]) {
3686				&adss_pwm_clk_src.clkr.hw
3687			},
3688			.num_parents = 1,
3689			.flags = CLK_SET_RATE_PARENT,
3690			.ops = &clk_branch2_ops,
3691		},
3692	},
3693};
3694
3695static const struct freq_tbl ftbl_gp1_clk_src[] = {
3696	F(24000000, P_XO, 1, 0, 0),
3697	F(200000000, P_GPLL0, 4, 0, 0),
3698	{ }
3699};
3700
3701static struct clk_rcg2 gp1_clk_src = {
3702	.cmd_rcgr = 0x8004,
3703	.freq_tbl = ftbl_gp1_clk_src,
3704	.hid_width = 5,
3705	.parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map,
3706	.clkr.hw.init = &(const struct clk_init_data) {
3707		.name = "gp1_clk_src",
3708		.parent_data = gcc_xo_gpll0_gpll0_sleep_clk,
3709		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk),
3710		.ops = &clk_rcg2_ops,
3711	},
3712};
3713
3714static struct clk_rcg2 gp2_clk_src = {
3715	.cmd_rcgr = 0x9004,
3716	.freq_tbl = ftbl_gp1_clk_src,
3717	.hid_width = 5,
3718	.parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map,
3719	.clkr.hw.init = &(const struct clk_init_data) {
3720		.name = "gp2_clk_src",
3721		.parent_data = gcc_xo_gpll0_gpll0_sleep_clk,
3722		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk),
3723		.ops = &clk_rcg2_ops,
3724	},
3725};
3726
3727static struct clk_rcg2 gp3_clk_src = {
3728	.cmd_rcgr = 0xa004,
3729	.freq_tbl = ftbl_gp1_clk_src,
3730	.hid_width = 5,
3731	.parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map,
3732	.clkr.hw.init = &(const struct clk_init_data) {
3733		.name = "gp3_clk_src",
3734		.parent_data = gcc_xo_gpll0_gpll0_sleep_clk,
3735		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk),
3736		.ops = &clk_rcg2_ops,
3737	},
3738};
3739
3740static struct clk_branch gcc_xo_clk_src = {
3741	.halt_reg = 0x34004,
3742	.clkr = {
3743		.enable_reg = 0x34004,
3744		.enable_mask = BIT(1),
3745		.hw.init = &(const struct clk_init_data) {
3746			.name = "gcc_xo_clk_src",
3747			.parent_data = gcc_xo_data,
3748			.num_parents = ARRAY_SIZE(gcc_xo_data),
3749			.flags = CLK_SET_RATE_PARENT,
3750			.ops = &clk_branch2_ops,
3751		},
3752	},
3753};
3754
3755static struct clk_branch gcc_nssnoc_xo_dcd_clk = {
3756	.halt_reg = 0x17074,
3757	.clkr = {
3758		.enable_reg = 0x17074,
3759		.enable_mask = BIT(0),
3760		.hw.init = &(const struct clk_init_data) {
3761			.name = "gcc_nssnoc_xo_dcd_clk",
3762			.parent_hws = (const struct clk_hw *[]) {
3763				&gcc_xo_clk_src.clkr.hw
3764			},
3765			.num_parents = 1,
3766			.flags = CLK_SET_RATE_PARENT,
3767			.ops = &clk_branch2_ops,
3768		},
3769	},
3770};
3771
3772static struct clk_branch gcc_xo_clk = {
3773	.halt_reg = 0x34018,
3774	.clkr = {
3775		.enable_reg = 0x34018,
3776		.enable_mask = BIT(0),
3777		.hw.init = &(const struct clk_init_data) {
3778			.name = "gcc_xo_clk",
3779			.parent_hws = (const struct clk_hw *[]) {
3780				&gcc_xo_clk_src.clkr.hw
3781			},
3782			.num_parents = 1,
3783			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
3784			.ops = &clk_branch2_ops,
3785		},
3786	},
3787};
3788
3789static struct clk_branch gcc_uniphy0_sys_clk = {
3790	.halt_reg = 0x17048,
3791	.clkr = {
3792		.enable_reg = 0x17048,
3793		.enable_mask = BIT(0),
3794		.hw.init = &(const struct clk_init_data) {
3795			.name = "gcc_uniphy0_sys_clk",
3796			.parent_hws = (const struct clk_hw *[]) {
3797				&uniphy_sys_clk_src.clkr.hw
3798			},
3799			.num_parents = 1,
3800			.flags = CLK_SET_RATE_PARENT,
3801			.ops = &clk_branch2_ops,
3802		},
3803	},
3804};
3805
3806static struct clk_branch gcc_uniphy1_sys_clk = {
3807	.halt_reg = 0x17058,
3808	.clkr = {
3809		.enable_reg = 0x17058,
3810		.enable_mask = BIT(0),
3811		.hw.init = &(const struct clk_init_data) {
3812			.name = "gcc_uniphy1_sys_clk",
3813			.parent_hws = (const struct clk_hw *[]) {
3814				&uniphy_sys_clk_src.clkr.hw
3815			},
3816			.num_parents = 1,
3817			.flags = CLK_SET_RATE_PARENT,
3818			.ops = &clk_branch2_ops,
3819		},
3820	},
3821};
3822
3823static struct clk_branch gcc_uniphy2_sys_clk = {
3824	.halt_reg = 0x17068,
3825	.clkr = {
3826		.enable_reg = 0x17068,
3827		.enable_mask = BIT(0),
3828		.hw.init = &(const struct clk_init_data) {
3829			.name = "gcc_uniphy2_sys_clk",
3830			.parent_hws = (const struct clk_hw *[]) {
3831				&uniphy_sys_clk_src.clkr.hw
3832			},
3833			.num_parents = 1,
3834			.flags = CLK_SET_RATE_PARENT,
3835			.ops = &clk_branch2_ops,
3836		},
3837	},
3838};
3839
3840static struct clk_branch gcc_cmn_12gpll_sys_clk = {
3841	.halt_reg = 0x3a008,
3842	.clkr = {
3843		.enable_reg = 0x3a008,
3844		.enable_mask = BIT(0),
3845		.hw.init = &(const struct clk_init_data) {
3846			.name = "gcc_cmn_12gpll_sys_clk",
3847			.parent_hws = (const struct clk_hw *[]) {
3848				&uniphy_sys_clk_src.clkr.hw
3849			},
3850			.num_parents = 1,
3851			.flags = CLK_SET_RATE_PARENT,
3852			.ops = &clk_branch2_ops,
3853		},
3854	},
3855};
3856
3857static struct clk_fixed_factor gcc_xo_div4_clk_src = {
3858	.mult = 1,
3859	.div = 4,
3860	.hw.init = &(const struct clk_init_data) {
3861		.name = "gcc_xo_div4_clk_src",
3862		.parent_hws = (const struct clk_hw *[]) {
3863			&gcc_xo_clk_src.clkr.hw
3864		},
3865		.num_parents = 1,
3866		.flags = CLK_SET_RATE_PARENT,
3867		.ops = &clk_fixed_factor_ops,
3868	},
3869};
3870
3871static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
3872	.halt_reg = 0x1701c,
3873	.clkr = {
3874		.enable_reg = 0x1701c,
3875		.enable_mask = BIT(0),
3876		.hw.init = &(const struct clk_init_data) {
3877			.name = "gcc_nssnoc_qosgen_ref_clk",
3878			.parent_hws = (const struct clk_hw *[]) {
3879				&gcc_xo_div4_clk_src.hw
3880			},
3881			.num_parents = 1,
3882			.flags = CLK_SET_RATE_PARENT,
3883			.ops = &clk_branch2_ops,
3884		},
3885	},
3886};
3887
3888static struct clk_branch gcc_nssnoc_timeout_ref_clk = {
3889	.halt_reg = 0x17020,
3890	.clkr = {
3891		.enable_reg = 0x17020,
3892		.enable_mask = BIT(0),
3893		.hw.init = &(const struct clk_init_data) {
3894			.name = "gcc_nssnoc_timeout_ref_clk",
3895			.parent_hws = (const struct clk_hw *[]) {
3896				&gcc_xo_div4_clk_src.hw
3897			},
3898			.num_parents = 1,
3899			.flags = CLK_SET_RATE_PARENT,
3900			.ops = &clk_branch2_ops,
3901		},
3902	},
3903};
3904
3905static struct clk_branch gcc_xo_div4_clk = {
3906	.halt_reg = 0x3401c,
3907	.clkr = {
3908		.enable_reg = 0x3401c,
3909		.enable_mask = BIT(0),
3910		.hw.init = &(const struct clk_init_data) {
3911			.name = "gcc_xo_div4_clk",
3912			.parent_hws = (const struct clk_hw *[]) {
3913				&gcc_xo_div4_clk_src.hw
3914			},
3915			.num_parents = 1,
3916			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
3917			.ops = &clk_branch2_ops,
3918		},
3919	},
3920};
3921
3922static struct clk_hw *gcc_ipq9574_hws[] = {
3923	&gpll0_out_main_div2.hw,
3924	&gcc_xo_div4_clk_src.hw,
3925	&qdss_dap_sync_clk_src.hw,
3926	&qdss_tsctr_div2_clk_src.hw,
3927	&qdss_tsctr_div8_clk_src.hw,
3928	&qdss_tsctr_div16_clk_src.hw,
3929	&qdss_tsctr_div3_clk_src.hw,
3930	&gcc_eud_at_div_clk_src.hw,
3931};
3932
3933static struct clk_regmap *gcc_ipq9574_clks[] = {
3934	[GPLL0_MAIN] = &gpll0_main.clkr,
3935	[GPLL0] = &gpll0.clkr,
3936	[GPLL4_MAIN] = &gpll4_main.clkr,
3937	[GPLL4] = &gpll4.clkr,
3938	[GPLL2_MAIN] = &gpll2_main.clkr,
3939	[GPLL2] = &gpll2.clkr,
3940	[GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
3941	[APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
3942	[APSS_AXI_CLK_SRC] = &apss_axi_clk_src.clkr,
3943	[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
3944	[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
3945	[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3946	[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3947	[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3948	[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3949	[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
3950	[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
3951	[BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
3952	[BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
3953	[BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
3954	[BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
3955	[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3956	[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3957	[BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
3958	[BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
3959	[BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
3960	[BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
3961	[GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,
3962	[GCC_APSS_AXI_CLK] = &gcc_apss_axi_clk.clkr,
3963	[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3964	[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3965	[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3966	[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3967	[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3968	[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3969	[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
3970	[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
3971	[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
3972	[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
3973	[GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
3974	[GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
3975	[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3976	[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3977	[GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
3978	[GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
3979	[GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
3980	[GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
3981	[GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
3982	[GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
3983	[GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
3984	[GCC_CRYPTO_CLK_SRC] = &gcc_crypto_clk_src.clkr,
3985	[PCIE0_AXI_M_CLK_SRC] = &pcie0_axi_m_clk_src.clkr,
3986	[GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
3987	[PCIE1_AXI_M_CLK_SRC] = &pcie1_axi_m_clk_src.clkr,
3988	[GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr,
3989	[PCIE2_AXI_M_CLK_SRC] = &pcie2_axi_m_clk_src.clkr,
3990	[GCC_PCIE2_AXI_M_CLK] = &gcc_pcie2_axi_m_clk.clkr,
3991	[PCIE3_AXI_M_CLK_SRC] = &pcie3_axi_m_clk_src.clkr,
3992	[GCC_PCIE3_AXI_M_CLK] = &gcc_pcie3_axi_m_clk.clkr,
3993	[PCIE0_AXI_S_CLK_SRC] = &pcie0_axi_s_clk_src.clkr,
3994	[GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
3995	[GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
3996	[PCIE1_AXI_S_CLK_SRC] = &pcie1_axi_s_clk_src.clkr,
3997	[GCC_PCIE1_AXI_S_BRIDGE_CLK] = &gcc_pcie1_axi_s_bridge_clk.clkr,
3998	[GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr,
3999	[PCIE2_AXI_S_CLK_SRC] = &pcie2_axi_s_clk_src.clkr,
4000	[GCC_PCIE2_AXI_S_BRIDGE_CLK] = &gcc_pcie2_axi_s_bridge_clk.clkr,
4001	[GCC_PCIE2_AXI_S_CLK] = &gcc_pcie2_axi_s_clk.clkr,
4002	[PCIE3_AXI_S_CLK_SRC] = &pcie3_axi_s_clk_src.clkr,
4003	[GCC_PCIE3_AXI_S_BRIDGE_CLK] = &gcc_pcie3_axi_s_bridge_clk.clkr,
4004	[GCC_PCIE3_AXI_S_CLK] = &gcc_pcie3_axi_s_clk.clkr,
4005	[PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
4006	[PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr,
4007	[PCIE2_PIPE_CLK_SRC] = &pcie2_pipe_clk_src.clkr,
4008	[PCIE3_PIPE_CLK_SRC] = &pcie3_pipe_clk_src.clkr,
4009	[PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
4010	[GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
4011	[GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,
4012	[GCC_PCIE2_AUX_CLK] = &gcc_pcie2_aux_clk.clkr,
4013	[GCC_PCIE3_AUX_CLK] = &gcc_pcie3_aux_clk.clkr,
4014	[PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
4015	[GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
4016	[PCIE1_RCHNG_CLK_SRC] = &pcie1_rchng_clk_src.clkr,
4017	[GCC_PCIE1_RCHNG_CLK] = &gcc_pcie1_rchng_clk.clkr,
4018	[PCIE2_RCHNG_CLK_SRC] = &pcie2_rchng_clk_src.clkr,
4019	[GCC_PCIE2_RCHNG_CLK] = &gcc_pcie2_rchng_clk.clkr,
4020	[PCIE3_RCHNG_CLK_SRC] = &pcie3_rchng_clk_src.clkr,
4021	[GCC_PCIE3_RCHNG_CLK] = &gcc_pcie3_rchng_clk.clkr,
4022	[GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
4023	[GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr,
4024	[GCC_PCIE2_AHB_CLK] = &gcc_pcie2_ahb_clk.clkr,
4025	[GCC_PCIE3_AHB_CLK] = &gcc_pcie3_ahb_clk.clkr,
4026	[USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,
4027	[GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
4028	[USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,
4029	[GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
4030	[GCC_SNOC_USB_CLK] = &gcc_snoc_usb_clk.clkr,
4031	[GCC_ANOC_USB_AXI_CLK] = &gcc_anoc_usb_axi_clk.clkr,
4032	[USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,
4033	[USB0_MOCK_UTMI_DIV_CLK_SRC] = &usb0_mock_utmi_div_clk_src.clkr,
4034	[GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
4035	[USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
4036	[GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
4037	[GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
4038	[GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
4039	[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
4040	[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
4041	[SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
4042	[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
4043	[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
4044	[PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
4045	[GCC_NSSCFG_CLK] = &gcc_nsscfg_clk.clkr,
4046	[GCC_NSSNOC_NSSCC_CLK] = &gcc_nssnoc_nsscc_clk.clkr,
4047	[GCC_NSSCC_CLK] = &gcc_nsscc_clk.clkr,
4048	[GCC_NSSNOC_PCNOC_1_CLK] = &gcc_nssnoc_pcnoc_1_clk.clkr,
4049	[GCC_QDSS_DAP_AHB_CLK] = &gcc_qdss_dap_ahb_clk.clkr,
4050	[GCC_QDSS_CFG_AHB_CLK] = &gcc_qdss_cfg_ahb_clk.clkr,
4051	[GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
4052	[GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
4053	[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
4054	[GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
4055	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
4056	[GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
4057	[GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
4058	[GCC_UNIPHY2_AHB_CLK] = &gcc_uniphy2_ahb_clk.clkr,
4059	[GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
4060	[GCC_CMN_12GPLL_APU_CLK] = &gcc_cmn_12gpll_apu_clk.clkr,
4061	[SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
4062	[GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
4063	[GCC_NSSNOC_SNOC_1_CLK] = &gcc_nssnoc_snoc_1_clk.clkr,
4064	[GCC_QDSS_ETR_USB_CLK] = &gcc_qdss_etr_usb_clk.clkr,
4065	[WCSS_AHB_CLK_SRC] = &wcss_ahb_clk_src.clkr,
4066	[GCC_Q6_AHB_CLK] = &gcc_q6_ahb_clk.clkr,
4067	[GCC_Q6_AHB_S_CLK] = &gcc_q6_ahb_s_clk.clkr,
4068	[GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr,
4069	[GCC_WCSS_ACMT_CLK] = &gcc_wcss_acmt_clk.clkr,
4070	[GCC_SYS_NOC_WCSS_AHB_CLK] = &gcc_sys_noc_wcss_ahb_clk.clkr,
4071	[WCSS_AXI_M_CLK_SRC] = &wcss_axi_m_clk_src.clkr,
4072	[GCC_ANOC_WCSS_AXI_M_CLK] = &gcc_anoc_wcss_axi_m_clk.clkr,
4073	[QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr,
4074	[GCC_Q6SS_ATBM_CLK] = &gcc_q6ss_atbm_clk.clkr,
4075	[GCC_WCSS_DBG_IFC_ATB_CLK] = &gcc_wcss_dbg_ifc_atb_clk.clkr,
4076	[GCC_NSSNOC_ATB_CLK] = &gcc_nssnoc_atb_clk.clkr,
4077	[GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,
4078	[GCC_SYS_NOC_AT_CLK] = &gcc_sys_noc_at_clk.clkr,
4079	[GCC_PCNOC_AT_CLK] = &gcc_pcnoc_at_clk.clkr,
4080	[GCC_USB0_EUD_AT_CLK] = &gcc_usb0_eud_at_clk.clkr,
4081	[GCC_QDSS_EUD_AT_CLK] = &gcc_qdss_eud_at_clk.clkr,
4082	[QDSS_STM_CLK_SRC] = &qdss_stm_clk_src.clkr,
4083	[GCC_QDSS_STM_CLK] = &gcc_qdss_stm_clk.clkr,
4084	[GCC_SYS_NOC_QDSS_STM_AXI_CLK] = &gcc_sys_noc_qdss_stm_axi_clk.clkr,
4085	[QDSS_TRACECLKIN_CLK_SRC] = &qdss_traceclkin_clk_src.clkr,
4086	[GCC_QDSS_TRACECLKIN_CLK] = &gcc_qdss_traceclkin_clk.clkr,
4087	[QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr,
4088	[GCC_Q6_TSCTR_1TO2_CLK] = &gcc_q6_tsctr_1to2_clk.clkr,
4089	[GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr,
4090	[GCC_QDSS_TSCTR_DIV2_CLK] = &gcc_qdss_tsctr_div2_clk.clkr,
4091	[GCC_QDSS_TS_CLK] = &gcc_qdss_ts_clk.clkr,
4092	[GCC_QDSS_TSCTR_DIV4_CLK] = &gcc_qdss_tsctr_div4_clk.clkr,
4093	[GCC_NSS_TS_CLK] = &gcc_nss_ts_clk.clkr,
4094	[GCC_QDSS_TSCTR_DIV8_CLK] = &gcc_qdss_tsctr_div8_clk.clkr,
4095	[GCC_QDSS_TSCTR_DIV16_CLK] = &gcc_qdss_tsctr_div16_clk.clkr,
4096	[GCC_Q6SS_PCLKDBG_CLK] = &gcc_q6ss_pclkdbg_clk.clkr,
4097	[GCC_Q6SS_TRIG_CLK] = &gcc_q6ss_trig_clk.clkr,
4098	[GCC_WCSS_DBG_IFC_APB_CLK] = &gcc_wcss_dbg_ifc_apb_clk.clkr,
4099	[GCC_WCSS_DBG_IFC_DAPBUS_CLK] = &gcc_wcss_dbg_ifc_dapbus_clk.clkr,
4100	[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
4101	[GCC_QDSS_APB2JTAG_CLK] = &gcc_qdss_apb2jtag_clk.clkr,
4102	[GCC_QDSS_TSCTR_DIV3_CLK] = &gcc_qdss_tsctr_div3_clk.clkr,
4103	[QPIC_IO_MACRO_CLK_SRC] = &qpic_io_macro_clk_src.clkr,
4104	[GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr,
4105	[Q6_AXI_CLK_SRC] = &q6_axi_clk_src.clkr,
4106	[GCC_Q6_AXIM_CLK] = &gcc_q6_axim_clk.clkr,
4107	[GCC_WCSS_Q6_TBU_CLK] = &gcc_wcss_q6_tbu_clk.clkr,
4108	[GCC_MEM_NOC_Q6_AXI_CLK] = &gcc_mem_noc_q6_axi_clk.clkr,
4109	[Q6_AXIM2_CLK_SRC] = &q6_axim2_clk_src.clkr,
4110	[NSSNOC_MEMNOC_BFDCD_CLK_SRC] = &nssnoc_memnoc_bfdcd_clk_src.clkr,
4111	[GCC_NSSNOC_MEMNOC_CLK] = &gcc_nssnoc_memnoc_clk.clkr,
4112	[GCC_NSSNOC_MEM_NOC_1_CLK] = &gcc_nssnoc_mem_noc_1_clk.clkr,
4113	[GCC_NSS_TBU_CLK] = &gcc_nss_tbu_clk.clkr,
4114	[GCC_MEM_NOC_NSSNOC_CLK] = &gcc_mem_noc_nssnoc_clk.clkr,
4115	[LPASS_AXIM_CLK_SRC] = &lpass_axim_clk_src.clkr,
4116	[LPASS_SWAY_CLK_SRC] = &lpass_sway_clk_src.clkr,
4117	[ADSS_PWM_CLK_SRC] = &adss_pwm_clk_src.clkr,
4118	[GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
4119	[GP1_CLK_SRC] = &gp1_clk_src.clkr,
4120	[GP2_CLK_SRC] = &gp2_clk_src.clkr,
4121	[GP3_CLK_SRC] = &gp3_clk_src.clkr,
4122	[GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
4123	[GCC_NSSNOC_XO_DCD_CLK] = &gcc_nssnoc_xo_dcd_clk.clkr,
4124	[GCC_XO_CLK] = &gcc_xo_clk.clkr,
4125	[GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
4126	[GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
4127	[GCC_XO_DIV4_CLK] = &gcc_xo_div4_clk.clkr,
4128	[GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
4129	[GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
4130	[GCC_UNIPHY2_SYS_CLK] = &gcc_uniphy2_sys_clk.clkr,
4131	[GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
4132	[GCC_Q6SS_BOOT_CLK] = &gcc_q6ss_boot_clk.clkr,
4133	[UNIPHY_SYS_CLK_SRC] = &uniphy_sys_clk_src.clkr,
4134	[NSS_TS_CLK_SRC] = &nss_ts_clk_src.clkr,
4135	[GCC_ANOC_PCIE0_1LANE_M_CLK] = &gcc_anoc_pcie0_1lane_m_clk.clkr,
4136	[GCC_ANOC_PCIE1_1LANE_M_CLK] = &gcc_anoc_pcie1_1lane_m_clk.clkr,
4137	[GCC_ANOC_PCIE2_2LANE_M_CLK] = &gcc_anoc_pcie2_2lane_m_clk.clkr,
4138	[GCC_ANOC_PCIE3_2LANE_M_CLK] = &gcc_anoc_pcie3_2lane_m_clk.clkr,
4139	[GCC_SNOC_PCIE0_1LANE_S_CLK] = &gcc_snoc_pcie0_1lane_s_clk.clkr,
4140	[GCC_SNOC_PCIE1_1LANE_S_CLK] = &gcc_snoc_pcie1_1lane_s_clk.clkr,
4141	[GCC_SNOC_PCIE2_2LANE_S_CLK] = &gcc_snoc_pcie2_2lane_s_clk.clkr,
4142	[GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr,
4143};
4144
4145static const struct qcom_reset_map gcc_ipq9574_resets[] = {
4146	[GCC_ADSS_BCR] = { 0x1c000, 0 },
4147	[GCC_ANOC0_TBU_BCR] = { 0x1203c, 0 },
4148	[GCC_ANOC1_TBU_BCR] = { 0x1204c, 0 },
4149	[GCC_ANOC_BCR] = { 0x2e074, 0 },
4150	[GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x38000, 0 },
4151	[GCC_APSS_TCU_BCR] = { 0x12014, 0 },
4152	[GCC_BLSP1_BCR] = { 0x01000, 0 },
4153	[GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
4154	[GCC_BLSP1_QUP2_BCR] = { 0x03000, 0 },
4155	[GCC_BLSP1_QUP3_BCR] = { 0x04000, 0 },
4156	[GCC_BLSP1_QUP4_BCR] = { 0x05000, 0 },
4157	[GCC_BLSP1_QUP5_BCR] = { 0x06000, 0 },
4158	[GCC_BLSP1_QUP6_BCR] = { 0x07000, 0 },
4159	[GCC_BLSP1_UART1_BCR] = { 0x02028, 0 },
4160	[GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
4161	[GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
4162	[GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
4163	[GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
4164	[GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
4165	[GCC_BOOT_ROM_BCR] = { 0x13028, 0 },
4166	[GCC_CMN_BLK_BCR] = { 0x3a000, 0 },
4167	[GCC_CMN_BLK_AHB_ARES] = { 0x3a010, 0 },
4168	[GCC_CMN_BLK_SYS_ARES] = { 0x3a010, 1 },
4169	[GCC_CMN_BLK_APU_ARES] = { 0x3a010, 2 },
4170	[GCC_CRYPTO_BCR] = { 0x16000, 0 },
4171	[GCC_DCC_BCR] = { 0x35000, 0 },
4172	[GCC_DDRSS_BCR] = { 0x11000, 0 },
4173	[GCC_IMEM_BCR] = { 0x0e000, 0 },
4174	[GCC_LPASS_BCR] = { 0x27000, 0 },
4175	[GCC_MDIO_BCR] = { 0x1703c, 0 },
4176	[GCC_MPM_BCR] = { 0x37000, 0 },
4177	[GCC_MSG_RAM_BCR] = { 0x26000, 0 },
4178	[GCC_NSS_BCR] = { 0x17000, 0 },
4179	[GCC_NSS_TBU_BCR] = { 0x12044, 0 },
4180	[GCC_NSSNOC_MEMNOC_1_ARES] = { 0x17038, 13 },
4181	[GCC_NSSNOC_PCNOC_1_ARES] = { 0x17038, 12 },
4182	[GCC_NSSNOC_SNOC_1_ARES] = { 0x17038,  11 },
4183	[GCC_NSSNOC_XO_DCD_ARES] = { 0x17038,  10 },
4184	[GCC_NSSNOC_TS_ARES] = { 0x17038, 9 },
4185	[GCC_NSSCC_ARES] = { 0x17038, 8 },
4186	[GCC_NSSNOC_NSSCC_ARES] = { 0x17038, 7 },
4187	[GCC_NSSNOC_ATB_ARES] = { 0x17038, 6 },
4188	[GCC_NSSNOC_MEMNOC_ARES] = { 0x17038, 5 },
4189	[GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x17038, 4 },
4190	[GCC_NSSNOC_SNOC_ARES] = { 0x17038, 3 },
4191	[GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x17038, 2 },
4192	[GCC_NSS_CFG_ARES] = { 0x17038, 1 },
4193	[GCC_UBI0_DBG_ARES] = { 0x17038, 0 },
4194	[GCC_PCIE0PHY_PHY_BCR] = { 0x2805c, 0 },
4195	[GCC_PCIE0_AHB_ARES] = { 0x28058, 7 },
4196	[GCC_PCIE0_AUX_ARES] = { 0x28058, 6 },
4197	[GCC_PCIE0_AXI_M_ARES] = { 0x28058, 5 },
4198	[GCC_PCIE0_AXI_M_STICKY_ARES] = { 0x28058, 4 },
4199	[GCC_PCIE0_AXI_S_ARES] = { 0x28058, 3 },
4200	[GCC_PCIE0_AXI_S_STICKY_ARES] = { 0x28058, 2 },
4201	[GCC_PCIE0_CORE_STICKY_ARES] = { 0x28058, 1 },
4202	[GCC_PCIE0_PIPE_ARES] = { 0x28058, 0 },
4203	[GCC_PCIE1_AHB_ARES] = { 0x29058, 7 },
4204	[GCC_PCIE1_AUX_ARES] = { 0x29058, 6 },
4205	[GCC_PCIE1_AXI_M_ARES] = { 0x29058, 5 },
4206	[GCC_PCIE1_AXI_M_STICKY_ARES] = { 0x29058, 4 },
4207	[GCC_PCIE1_AXI_S_ARES] = { 0x29058, 3 },
4208	[GCC_PCIE1_AXI_S_STICKY_ARES] = { 0x29058, 2 },
4209	[GCC_PCIE1_CORE_STICKY_ARES] = { 0x29058, 1 },
4210	[GCC_PCIE1_PIPE_ARES] = { 0x29058, 0 },
4211	[GCC_PCIE2_AHB_ARES] = { 0x2a058, 7 },
4212	[GCC_PCIE2_AUX_ARES] = { 0x2a058, 6 },
4213	[GCC_PCIE2_AXI_M_ARES] = { 0x2a058, 5 },
4214	[GCC_PCIE2_AXI_M_STICKY_ARES] = { 0x2a058, 4 },
4215	[GCC_PCIE2_AXI_S_ARES] = { 0x2a058, 3 },
4216	[GCC_PCIE2_AXI_S_STICKY_ARES] = { 0x2a058, 2 },
4217	[GCC_PCIE2_CORE_STICKY_ARES] = { 0x2a058, 1 },
4218	[GCC_PCIE2_PIPE_ARES] = { 0x2a058, 0 },
4219	[GCC_PCIE3_AHB_ARES] = { 0x2b058, 7 },
4220	[GCC_PCIE3_AUX_ARES] = { 0x2b058, 6 },
4221	[GCC_PCIE3_AXI_M_ARES] = { 0x2b058, 5 },
4222	[GCC_PCIE3_AXI_M_STICKY_ARES] = { 0x2b058, 4 },
4223	[GCC_PCIE3_AXI_S_ARES] = { 0x2b058, 3 },
4224	[GCC_PCIE3_AXI_S_STICKY_ARES] = { 0x2b058, 2 },
4225	[GCC_PCIE3_CORE_STICKY_ARES] = { 0x2b058, 1 },
4226	[GCC_PCIE3_PIPE_ARES] = { 0x2b058, 0 },
4227	[GCC_PCIE0_BCR] = { 0x28000, 0 },
4228	[GCC_PCIE0_LINK_DOWN_BCR] = { 0x28054, 0 },
4229	[GCC_PCIE0_PHY_BCR] = { 0x28060, 0 },
4230	[GCC_PCIE1_BCR] = { 0x29000, 0 },
4231	[GCC_PCIE1_LINK_DOWN_BCR] = { 0x29054, 0 },
4232	[GCC_PCIE1_PHY_BCR] = { 0x29060, 0 },
4233	[GCC_PCIE1PHY_PHY_BCR] = { 0x2905c, 0 },
4234	[GCC_PCIE2_BCR] = { 0x2a000, 0 },
4235	[GCC_PCIE2_LINK_DOWN_BCR] = { 0x2a054, 0 },
4236	[GCC_PCIE2_PHY_BCR] = { 0x2a060, 0 },
4237	[GCC_PCIE2PHY_PHY_BCR] = { 0x2a05c, 0 },
4238	[GCC_PCIE3_BCR] = { 0x2b000, 0 },
4239	[GCC_PCIE3_LINK_DOWN_BCR] = { 0x2b054, 0 },
4240	[GCC_PCIE3PHY_PHY_BCR] = { 0x2b05c, 0 },
4241	[GCC_PCIE3_PHY_BCR] = { 0x2b060, 0 },
4242	[GCC_PCNOC_BCR] = { 0x31000, 0 },
4243	[GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x31030, 0 },
4244	[GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x31038, 0 },
4245	[GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x31040, 0 },
4246	[GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x31048, 0 },
4247	[GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x31050, 0 },
4248	[GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x31058, 0 },
4249	[GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x31060, 0 },
4250	[GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x31068, 0 },
4251	[GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x31070, 0 },
4252	[GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x31078, 0 },
4253	[GCC_PCNOC_TBU_BCR] = { 0x12034, 0 },
4254	[GCC_PRNG_BCR] = { 0x13020, 0 },
4255	[GCC_Q6SS_DBG_ARES] = { 0x2506c, 4 },
4256	[GCC_Q6_AHB_ARES] = { 0x2506c, 3 },
4257	[GCC_Q6_AHB_S_ARES] = { 0x2506c, 2 },
4258	[GCC_Q6_AXIM2_ARES] = { 0x2506c, 1 },
4259	[GCC_Q6_AXIM_ARES] = { 0x2506c, 0 },
4260	[GCC_QDSS_BCR] = { 0x2d000, 0 },
4261	[GCC_QPIC_BCR] = { 0x32000, 0 },
4262	[GCC_QPIC_AHB_ARES] = { 0x3201c, 1 },
4263	[GCC_QPIC_ARES] = { 0x3201c, 0 },
4264	[GCC_QUSB2_0_PHY_BCR] = { 0x2c068, 0 },
4265	[GCC_RBCPR_BCR] = { 0x39000, 0 },
4266	[GCC_RBCPR_MX_BCR] = { 0x39014, 0 },
4267	[GCC_SDCC_BCR] = { 0x33000, 0 },
4268	[GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
4269	[GCC_SMMU_CFG_BCR] = { 0x1202c, 0 },
4270	[GCC_SNOC_BCR] = { 0x2e000, 0 },
4271	[GCC_SPDM_BCR] = { 0x36000, 0 },
4272	[GCC_TCSR_BCR] = { 0x3d000, 0 },
4273	[GCC_TLMM_BCR] = { 0x3e000, 0 },
4274	[GCC_TME_BCR] = { 0x10000, 0 },
4275	[GCC_UNIPHY0_BCR] = { 0x17044, 0 },
4276	[GCC_UNIPHY0_SYS_RESET] = { 0x17050, 0 },
4277	[GCC_UNIPHY0_AHB_RESET] = { 0x17050, 1 },
4278	[GCC_UNIPHY0_XPCS_RESET] = { 0x17050, 2 },
4279	[GCC_UNIPHY1_SYS_RESET] = { 0x17060, 0 },
4280	[GCC_UNIPHY1_AHB_RESET] = { 0x17060, 1 },
4281	[GCC_UNIPHY1_XPCS_RESET] = { 0x17060, 2 },
4282	[GCC_UNIPHY2_SYS_RESET] = { 0x17070, 0 },
4283	[GCC_UNIPHY2_AHB_RESET] = { 0x17070, 1 },
4284	[GCC_UNIPHY2_XPCS_RESET] = { 0x17070, 2 },
4285	[GCC_UNIPHY1_BCR] = { 0x17054, 0 },
4286	[GCC_UNIPHY2_BCR] = { 0x17064, 0 },
4287	[GCC_USB0_PHY_BCR] = { 0x2c06c, 0 },
4288	[GCC_USB3PHY_0_PHY_BCR] = { 0x2c070, 0 },
4289	[GCC_USB_BCR] = { 0x2c000, 0 },
4290	[GCC_USB_MISC_RESET] = { 0x2c064, 0 },
4291	[GCC_WCSSAON_RESET] = { 0x25074, 0 },
4292	[GCC_WCSS_ACMT_ARES] = { 0x25070, 5 },
4293	[GCC_WCSS_AHB_S_ARES] = { 0x25070, 4 },
4294	[GCC_WCSS_AXI_M_ARES] = { 0x25070, 3 },
4295	[GCC_WCSS_BCR] = { 0x18004, 0 },
4296	[GCC_WCSS_DBG_ARES] = { 0x25070, 2 },
4297	[GCC_WCSS_DBG_BDG_ARES] = { 0x25070, 1 },
4298	[GCC_WCSS_ECAHB_ARES] = { 0x25070, 0 },
4299	[GCC_WCSS_Q6_BCR] = { 0x18000, 0 },
4300	[GCC_WCSS_Q6_TBU_BCR] = { 0x12054, 0 },
4301};
4302
4303static const struct of_device_id gcc_ipq9574_match_table[] = {
4304	{ .compatible = "qcom,ipq9574-gcc" },
4305	{ }
4306};
4307MODULE_DEVICE_TABLE(of, gcc_ipq9574_match_table);
4308
4309static const struct regmap_config gcc_ipq9574_regmap_config = {
4310	.reg_bits       = 32,
4311	.reg_stride     = 4,
4312	.val_bits       = 32,
4313	.max_register   = 0x7fffc,
4314	.fast_io	= true,
4315};
4316
4317static const struct qcom_cc_desc gcc_ipq9574_desc = {
4318	.config = &gcc_ipq9574_regmap_config,
4319	.clks = gcc_ipq9574_clks,
4320	.num_clks = ARRAY_SIZE(gcc_ipq9574_clks),
4321	.resets = gcc_ipq9574_resets,
4322	.num_resets = ARRAY_SIZE(gcc_ipq9574_resets),
4323	.clk_hws = gcc_ipq9574_hws,
4324	.num_clk_hws = ARRAY_SIZE(gcc_ipq9574_hws),
4325};
4326
4327static int gcc_ipq9574_probe(struct platform_device *pdev)
4328{
4329	return qcom_cc_probe(pdev, &gcc_ipq9574_desc);
4330}
4331
4332static struct platform_driver gcc_ipq9574_driver = {
4333	.probe = gcc_ipq9574_probe,
4334	.driver = {
4335		.name   = "qcom,gcc-ipq9574",
4336		.of_match_table = gcc_ipq9574_match_table,
4337	},
4338};
4339
4340static int __init gcc_ipq9574_init(void)
4341{
4342	return platform_driver_register(&gcc_ipq9574_driver);
4343}
4344core_initcall(gcc_ipq9574_init);
4345
4346static void __exit gcc_ipq9574_exit(void)
4347{
4348	platform_driver_unregister(&gcc_ipq9574_driver);
4349}
4350module_exit(gcc_ipq9574_exit);
4351
4352MODULE_DESCRIPTION("Qualcomm Technologies, Inc. GCC IPQ9574 Driver");
4353MODULE_LICENSE("GPL");