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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved
4 * Copyright (c) 2023, Linaro Ltd.
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/err.h>
9#include <linux/kernel.h>
10#include <linux/mod_devicetable.h>
11#include <linux/module.h>
12#include <linux/platform_device.h>
13#include <linux/pm_runtime.h>
14#include <linux/regmap.h>
15
16#include <dt-bindings/clock/qcom,sm8650-dispcc.h>
17
18#include "common.h"
19#include "clk-alpha-pll.h"
20#include "clk-branch.h"
21#include "clk-pll.h"
22#include "clk-rcg.h"
23#include "clk-regmap.h"
24#include "clk-regmap-divider.h"
25#include "reset.h"
26#include "gdsc.h"
27
28/* Need to match the order of clocks in DT binding */
29enum {
30 DT_BI_TCXO,
31 DT_BI_TCXO_AO,
32 DT_AHB_CLK,
33 DT_SLEEP_CLK,
34
35 DT_DSI0_PHY_PLL_OUT_BYTECLK,
36 DT_DSI0_PHY_PLL_OUT_DSICLK,
37 DT_DSI1_PHY_PLL_OUT_BYTECLK,
38 DT_DSI1_PHY_PLL_OUT_DSICLK,
39
40 DT_DP0_PHY_PLL_LINK_CLK,
41 DT_DP0_PHY_PLL_VCO_DIV_CLK,
42 DT_DP1_PHY_PLL_LINK_CLK,
43 DT_DP1_PHY_PLL_VCO_DIV_CLK,
44 DT_DP2_PHY_PLL_LINK_CLK,
45 DT_DP2_PHY_PLL_VCO_DIV_CLK,
46 DT_DP3_PHY_PLL_LINK_CLK,
47 DT_DP3_PHY_PLL_VCO_DIV_CLK,
48};
49
50#define DISP_CC_MISC_CMD 0xF000
51
52enum {
53 P_BI_TCXO,
54 P_DISP_CC_PLL0_OUT_MAIN,
55 P_DISP_CC_PLL1_OUT_EVEN,
56 P_DISP_CC_PLL1_OUT_MAIN,
57 P_DP0_PHY_PLL_LINK_CLK,
58 P_DP0_PHY_PLL_VCO_DIV_CLK,
59 P_DP1_PHY_PLL_LINK_CLK,
60 P_DP1_PHY_PLL_VCO_DIV_CLK,
61 P_DP2_PHY_PLL_LINK_CLK,
62 P_DP2_PHY_PLL_VCO_DIV_CLK,
63 P_DP3_PHY_PLL_LINK_CLK,
64 P_DP3_PHY_PLL_VCO_DIV_CLK,
65 P_DSI0_PHY_PLL_OUT_BYTECLK,
66 P_DSI0_PHY_PLL_OUT_DSICLK,
67 P_DSI1_PHY_PLL_OUT_BYTECLK,
68 P_DSI1_PHY_PLL_OUT_DSICLK,
69 P_SLEEP_CLK,
70};
71
72static struct pll_vco lucid_ole_vco[] = {
73 { 249600000, 2100000000, 0 },
74};
75
76static const struct alpha_pll_config disp_cc_pll0_config = {
77 .l = 0xd,
78 .alpha = 0x6492,
79 .config_ctl_val = 0x20485699,
80 .config_ctl_hi_val = 0x00182261,
81 .config_ctl_hi1_val = 0x82aa299c,
82 .test_ctl_val = 0x00000000,
83 .test_ctl_hi_val = 0x00000003,
84 .test_ctl_hi1_val = 0x00009000,
85 .test_ctl_hi2_val = 0x00000034,
86 .user_ctl_val = 0x00000000,
87 .user_ctl_hi_val = 0x00000005,
88};
89
90static struct clk_alpha_pll disp_cc_pll0 = {
91 .offset = 0x0,
92 .vco_table = lucid_ole_vco,
93 .num_vco = ARRAY_SIZE(lucid_ole_vco),
94 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
95 .clkr = {
96 .hw.init = &(const struct clk_init_data) {
97 .name = "disp_cc_pll0",
98 .parent_data = &(const struct clk_parent_data) {
99 .index = DT_BI_TCXO,
100 },
101 .num_parents = 1,
102 .ops = &clk_alpha_pll_reset_lucid_ole_ops,
103 },
104 },
105};
106
107static const struct alpha_pll_config disp_cc_pll1_config = {
108 .l = 0x1f,
109 .alpha = 0x4000,
110 .config_ctl_val = 0x20485699,
111 .config_ctl_hi_val = 0x00182261,
112 .config_ctl_hi1_val = 0x82aa299c,
113 .test_ctl_val = 0x00000000,
114 .test_ctl_hi_val = 0x00000003,
115 .test_ctl_hi1_val = 0x00009000,
116 .test_ctl_hi2_val = 0x00000034,
117 .user_ctl_val = 0x00000000,
118 .user_ctl_hi_val = 0x00000005,
119};
120
121static struct clk_alpha_pll disp_cc_pll1 = {
122 .offset = 0x1000,
123 .vco_table = lucid_ole_vco,
124 .num_vco = ARRAY_SIZE(lucid_ole_vco),
125 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
126 .clkr = {
127 .hw.init = &(const struct clk_init_data) {
128 .name = "disp_cc_pll1",
129 .parent_data = &(const struct clk_parent_data) {
130 .index = DT_BI_TCXO,
131 },
132 .num_parents = 1,
133 .ops = &clk_alpha_pll_reset_lucid_ole_ops,
134 },
135 },
136};
137
138static const struct parent_map disp_cc_parent_map_0[] = {
139 { P_BI_TCXO, 0 },
140};
141
142static const struct clk_parent_data disp_cc_parent_data_0[] = {
143 { .index = DT_BI_TCXO },
144};
145
146static const struct clk_parent_data disp_cc_parent_data_0_ao[] = {
147 { .index = DT_BI_TCXO_AO },
148};
149
150static const struct parent_map disp_cc_parent_map_1[] = {
151 { P_BI_TCXO, 0 },
152 { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 },
153 { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 },
154 { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 },
155};
156
157static const struct clk_parent_data disp_cc_parent_data_1[] = {
158 { .index = DT_BI_TCXO },
159 { .index = DT_DP3_PHY_PLL_VCO_DIV_CLK },
160 { .index = DT_DP1_PHY_PLL_VCO_DIV_CLK },
161 { .index = DT_DP2_PHY_PLL_VCO_DIV_CLK },
162};
163
164static const struct parent_map disp_cc_parent_map_2[] = {
165 { P_BI_TCXO, 0 },
166 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
167 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
168 { P_DSI1_PHY_PLL_OUT_DSICLK, 3 },
169 { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },
170};
171
172static const struct clk_parent_data disp_cc_parent_data_2[] = {
173 { .index = DT_BI_TCXO },
174 { .index = DT_DSI0_PHY_PLL_OUT_DSICLK },
175 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
176 { .index = DT_DSI1_PHY_PLL_OUT_DSICLK },
177 { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK },
178};
179
180static const struct parent_map disp_cc_parent_map_3[] = {
181 { P_BI_TCXO, 0 },
182 { P_DP1_PHY_PLL_LINK_CLK, 2 },
183 { P_DP2_PHY_PLL_LINK_CLK, 3 },
184 { P_DP3_PHY_PLL_LINK_CLK, 4 },
185};
186
187static const struct clk_parent_data disp_cc_parent_data_3[] = {
188 { .index = DT_BI_TCXO },
189 { .index = DT_DP1_PHY_PLL_LINK_CLK },
190 { .index = DT_DP2_PHY_PLL_LINK_CLK },
191 { .index = DT_DP3_PHY_PLL_LINK_CLK },
192};
193
194static const struct parent_map disp_cc_parent_map_4[] = {
195 { P_BI_TCXO, 0 },
196 { P_DP0_PHY_PLL_LINK_CLK, 1 },
197 { P_DP0_PHY_PLL_VCO_DIV_CLK, 2 },
198 { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 },
199 { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 },
200 { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 },
201};
202
203static const struct clk_parent_data disp_cc_parent_data_4[] = {
204 { .index = DT_BI_TCXO },
205 { .index = DT_DP0_PHY_PLL_LINK_CLK },
206 { .index = DT_DP0_PHY_PLL_VCO_DIV_CLK },
207 { .index = DT_DP3_PHY_PLL_VCO_DIV_CLK },
208 { .index = DT_DP1_PHY_PLL_VCO_DIV_CLK },
209 { .index = DT_DP2_PHY_PLL_VCO_DIV_CLK },
210};
211
212static const struct parent_map disp_cc_parent_map_5[] = {
213 { P_BI_TCXO, 0 },
214 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
215 { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },
216};
217
218static const struct clk_parent_data disp_cc_parent_data_5[] = {
219 { .index = DT_BI_TCXO },
220 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
221 { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK },
222};
223
224static const struct parent_map disp_cc_parent_map_6[] = {
225 { P_BI_TCXO, 0 },
226 { P_DISP_CC_PLL1_OUT_MAIN, 4 },
227 { P_DISP_CC_PLL1_OUT_EVEN, 6 },
228};
229
230static const struct clk_parent_data disp_cc_parent_data_6[] = {
231 { .index = DT_BI_TCXO },
232 { .hw = &disp_cc_pll1.clkr.hw },
233 { .hw = &disp_cc_pll1.clkr.hw },
234};
235
236static const struct parent_map disp_cc_parent_map_7[] = {
237 { P_BI_TCXO, 0 },
238 { P_DP0_PHY_PLL_LINK_CLK, 1 },
239 { P_DP1_PHY_PLL_LINK_CLK, 2 },
240 { P_DP2_PHY_PLL_LINK_CLK, 3 },
241 { P_DP3_PHY_PLL_LINK_CLK, 4 },
242};
243
244static const struct clk_parent_data disp_cc_parent_data_7[] = {
245 { .index = DT_BI_TCXO },
246 { .index = DT_DP0_PHY_PLL_LINK_CLK },
247 { .index = DT_DP1_PHY_PLL_LINK_CLK },
248 { .index = DT_DP2_PHY_PLL_LINK_CLK },
249 { .index = DT_DP3_PHY_PLL_LINK_CLK },
250};
251
252static const struct parent_map disp_cc_parent_map_8[] = {
253 { P_BI_TCXO, 0 },
254 { P_DISP_CC_PLL0_OUT_MAIN, 1 },
255 { P_DISP_CC_PLL1_OUT_MAIN, 4 },
256 { P_DISP_CC_PLL1_OUT_EVEN, 6 },
257};
258
259static const struct clk_parent_data disp_cc_parent_data_8[] = {
260 { .index = DT_BI_TCXO },
261 { .hw = &disp_cc_pll0.clkr.hw },
262 { .hw = &disp_cc_pll1.clkr.hw },
263 { .hw = &disp_cc_pll1.clkr.hw },
264};
265
266static const struct parent_map disp_cc_parent_map_9[] = {
267 { P_SLEEP_CLK, 0 },
268};
269
270static const struct clk_parent_data disp_cc_parent_data_9[] = {
271 { .index = DT_SLEEP_CLK },
272};
273
274static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
275 F(19200000, P_BI_TCXO, 1, 0, 0),
276 F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
277 F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),
278 { }
279};
280
281static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
282 .cmd_rcgr = 0x82e8,
283 .mnd_width = 0,
284 .hid_width = 5,
285 .parent_map = disp_cc_parent_map_6,
286 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
287 .clkr.hw.init = &(const struct clk_init_data) {
288 .name = "disp_cc_mdss_ahb_clk_src",
289 .parent_data = disp_cc_parent_data_6,
290 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
291 .flags = CLK_SET_RATE_PARENT,
292 .ops = &clk_rcg2_shared_ops,
293 },
294};
295
296static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = {
297 F(19200000, P_BI_TCXO, 1, 0, 0),
298 { }
299};
300
301static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
302 .cmd_rcgr = 0x8108,
303 .mnd_width = 0,
304 .hid_width = 5,
305 .parent_map = disp_cc_parent_map_2,
306 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
307 .clkr.hw.init = &(const struct clk_init_data) {
308 .name = "disp_cc_mdss_byte0_clk_src",
309 .parent_data = disp_cc_parent_data_2,
310 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
311 .flags = CLK_SET_RATE_PARENT,
312 .ops = &clk_byte2_ops,
313 },
314};
315
316static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
317 .cmd_rcgr = 0x8124,
318 .mnd_width = 0,
319 .hid_width = 5,
320 .parent_map = disp_cc_parent_map_2,
321 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
322 .clkr.hw.init = &(const struct clk_init_data) {
323 .name = "disp_cc_mdss_byte1_clk_src",
324 .parent_data = disp_cc_parent_data_2,
325 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
326 .flags = CLK_SET_RATE_PARENT,
327 .ops = &clk_byte2_ops,
328 },
329};
330
331static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = {
332 .cmd_rcgr = 0x81bc,
333 .mnd_width = 0,
334 .hid_width = 5,
335 .parent_map = disp_cc_parent_map_0,
336 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
337 .clkr.hw.init = &(const struct clk_init_data) {
338 .name = "disp_cc_mdss_dptx0_aux_clk_src",
339 .parent_data = disp_cc_parent_data_0,
340 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
341 .flags = CLK_SET_RATE_PARENT,
342 .ops = &clk_rcg2_ops,
343 },
344};
345
346static const struct freq_tbl ftbl_disp_cc_mdss_dptx0_link_clk_src[] = {
347 F(162000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
348 F(270000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
349 F(540000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
350 F(810000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0),
351 { }
352};
353
354static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = {
355 .cmd_rcgr = 0x8170,
356 .mnd_width = 0,
357 .hid_width = 5,
358 .parent_map = disp_cc_parent_map_7,
359 .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
360 .clkr.hw.init = &(const struct clk_init_data) {
361 .name = "disp_cc_mdss_dptx0_link_clk_src",
362 .parent_data = disp_cc_parent_data_7,
363 .num_parents = ARRAY_SIZE(disp_cc_parent_data_7),
364 .flags = CLK_SET_RATE_PARENT,
365 .ops = &clk_rcg2_ops,
366 },
367};
368
369static struct clk_rcg2 disp_cc_mdss_dptx0_pixel0_clk_src = {
370 .cmd_rcgr = 0x818c,
371 .mnd_width = 16,
372 .hid_width = 5,
373 .parent_map = disp_cc_parent_map_4,
374 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
375 .clkr.hw.init = &(const struct clk_init_data) {
376 .name = "disp_cc_mdss_dptx0_pixel0_clk_src",
377 .parent_data = disp_cc_parent_data_4,
378 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
379 .flags = CLK_SET_RATE_PARENT,
380 .ops = &clk_dp_ops,
381 },
382};
383
384static struct clk_rcg2 disp_cc_mdss_dptx0_pixel1_clk_src = {
385 .cmd_rcgr = 0x81a4,
386 .mnd_width = 16,
387 .hid_width = 5,
388 .parent_map = disp_cc_parent_map_4,
389 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
390 .clkr.hw.init = &(const struct clk_init_data) {
391 .name = "disp_cc_mdss_dptx0_pixel1_clk_src",
392 .parent_data = disp_cc_parent_data_4,
393 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
394 .flags = CLK_SET_RATE_PARENT,
395 .ops = &clk_dp_ops,
396 },
397};
398
399static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = {
400 .cmd_rcgr = 0x8220,
401 .mnd_width = 0,
402 .hid_width = 5,
403 .parent_map = disp_cc_parent_map_0,
404 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
405 .clkr.hw.init = &(const struct clk_init_data) {
406 .name = "disp_cc_mdss_dptx1_aux_clk_src",
407 .parent_data = disp_cc_parent_data_0,
408 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
409 .flags = CLK_SET_RATE_PARENT,
410 .ops = &clk_dp_ops,
411 },
412};
413
414static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = {
415 .cmd_rcgr = 0x8204,
416 .mnd_width = 0,
417 .hid_width = 5,
418 .parent_map = disp_cc_parent_map_3,
419 .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
420 .clkr.hw.init = &(const struct clk_init_data) {
421 .name = "disp_cc_mdss_dptx1_link_clk_src",
422 .parent_data = disp_cc_parent_data_3,
423 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
424 .flags = CLK_SET_RATE_PARENT,
425 .ops = &clk_rcg2_ops,
426 },
427};
428
429static struct clk_rcg2 disp_cc_mdss_dptx1_pixel0_clk_src = {
430 .cmd_rcgr = 0x81d4,
431 .mnd_width = 16,
432 .hid_width = 5,
433 .parent_map = disp_cc_parent_map_1,
434 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
435 .clkr.hw.init = &(const struct clk_init_data) {
436 .name = "disp_cc_mdss_dptx1_pixel0_clk_src",
437 .parent_data = disp_cc_parent_data_1,
438 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
439 .flags = CLK_SET_RATE_PARENT,
440 .ops = &clk_dp_ops,
441 },
442};
443
444static struct clk_rcg2 disp_cc_mdss_dptx1_pixel1_clk_src = {
445 .cmd_rcgr = 0x81ec,
446 .mnd_width = 16,
447 .hid_width = 5,
448 .parent_map = disp_cc_parent_map_1,
449 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
450 .clkr.hw.init = &(const struct clk_init_data) {
451 .name = "disp_cc_mdss_dptx1_pixel1_clk_src",
452 .parent_data = disp_cc_parent_data_1,
453 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
454 .flags = CLK_SET_RATE_PARENT,
455 .ops = &clk_dp_ops,
456 },
457};
458
459static struct clk_rcg2 disp_cc_mdss_dptx2_aux_clk_src = {
460 .cmd_rcgr = 0x8284,
461 .mnd_width = 0,
462 .hid_width = 5,
463 .parent_map = disp_cc_parent_map_0,
464 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
465 .clkr.hw.init = &(const struct clk_init_data) {
466 .name = "disp_cc_mdss_dptx2_aux_clk_src",
467 .parent_data = disp_cc_parent_data_0,
468 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
469 .flags = CLK_SET_RATE_PARENT,
470 .ops = &clk_rcg2_ops,
471 },
472};
473
474static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = {
475 .cmd_rcgr = 0x8238,
476 .mnd_width = 0,
477 .hid_width = 5,
478 .parent_map = disp_cc_parent_map_3,
479 .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
480 .clkr.hw.init = &(const struct clk_init_data) {
481 .name = "disp_cc_mdss_dptx2_link_clk_src",
482 .parent_data = disp_cc_parent_data_3,
483 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
484 .flags = CLK_SET_RATE_PARENT,
485 .ops = &clk_rcg2_ops,
486 },
487};
488
489static struct clk_rcg2 disp_cc_mdss_dptx2_pixel0_clk_src = {
490 .cmd_rcgr = 0x8254,
491 .mnd_width = 16,
492 .hid_width = 5,
493 .parent_map = disp_cc_parent_map_1,
494 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
495 .clkr.hw.init = &(const struct clk_init_data) {
496 .name = "disp_cc_mdss_dptx2_pixel0_clk_src",
497 .parent_data = disp_cc_parent_data_1,
498 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
499 .flags = CLK_SET_RATE_PARENT,
500 .ops = &clk_dp_ops,
501 },
502};
503
504static struct clk_rcg2 disp_cc_mdss_dptx2_pixel1_clk_src = {
505 .cmd_rcgr = 0x826c,
506 .mnd_width = 16,
507 .hid_width = 5,
508 .parent_map = disp_cc_parent_map_1,
509 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
510 .clkr.hw.init = &(const struct clk_init_data) {
511 .name = "disp_cc_mdss_dptx2_pixel1_clk_src",
512 .parent_data = disp_cc_parent_data_1,
513 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
514 .flags = CLK_SET_RATE_PARENT,
515 .ops = &clk_dp_ops,
516 },
517};
518
519static struct clk_rcg2 disp_cc_mdss_dptx3_aux_clk_src = {
520 .cmd_rcgr = 0x82d0,
521 .mnd_width = 0,
522 .hid_width = 5,
523 .parent_map = disp_cc_parent_map_0,
524 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
525 .clkr.hw.init = &(const struct clk_init_data) {
526 .name = "disp_cc_mdss_dptx3_aux_clk_src",
527 .parent_data = disp_cc_parent_data_0,
528 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
529 .flags = CLK_SET_RATE_PARENT,
530 .ops = &clk_rcg2_ops,
531 },
532};
533
534static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = {
535 .cmd_rcgr = 0x82b4,
536 .mnd_width = 0,
537 .hid_width = 5,
538 .parent_map = disp_cc_parent_map_3,
539 .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src,
540 .clkr.hw.init = &(const struct clk_init_data) {
541 .name = "disp_cc_mdss_dptx3_link_clk_src",
542 .parent_data = disp_cc_parent_data_3,
543 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
544 .flags = CLK_SET_RATE_PARENT,
545 .ops = &clk_rcg2_ops,
546 },
547};
548
549static struct clk_rcg2 disp_cc_mdss_dptx3_pixel0_clk_src = {
550 .cmd_rcgr = 0x829c,
551 .mnd_width = 16,
552 .hid_width = 5,
553 .parent_map = disp_cc_parent_map_1,
554 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
555 .clkr.hw.init = &(const struct clk_init_data) {
556 .name = "disp_cc_mdss_dptx3_pixel0_clk_src",
557 .parent_data = disp_cc_parent_data_1,
558 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
559 .flags = CLK_SET_RATE_PARENT,
560 .ops = &clk_dp_ops,
561 },
562};
563
564static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
565 .cmd_rcgr = 0x8140,
566 .mnd_width = 0,
567 .hid_width = 5,
568 .parent_map = disp_cc_parent_map_5,
569 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
570 .clkr.hw.init = &(const struct clk_init_data) {
571 .name = "disp_cc_mdss_esc0_clk_src",
572 .parent_data = disp_cc_parent_data_5,
573 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
574 .flags = CLK_SET_RATE_PARENT,
575 .ops = &clk_rcg2_ops,
576 },
577};
578
579static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {
580 .cmd_rcgr = 0x8158,
581 .mnd_width = 0,
582 .hid_width = 5,
583 .parent_map = disp_cc_parent_map_5,
584 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
585 .clkr.hw.init = &(const struct clk_init_data) {
586 .name = "disp_cc_mdss_esc1_clk_src",
587 .parent_data = disp_cc_parent_data_5,
588 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
589 .flags = CLK_SET_RATE_PARENT,
590 .ops = &clk_rcg2_ops,
591 },
592};
593
594static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
595 F(19200000, P_BI_TCXO, 1, 0, 0),
596 F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
597 F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
598 F(150000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
599 F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
600 F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
601 F(402000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
602 F(514000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
603 { }
604};
605
606static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
607 .cmd_rcgr = 0x80d8,
608 .mnd_width = 0,
609 .hid_width = 5,
610 .parent_map = disp_cc_parent_map_8,
611 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
612 .clkr.hw.init = &(const struct clk_init_data) {
613 .name = "disp_cc_mdss_mdp_clk_src",
614 .parent_data = disp_cc_parent_data_8,
615 .num_parents = ARRAY_SIZE(disp_cc_parent_data_8),
616 .flags = CLK_SET_RATE_PARENT,
617 .ops = &clk_rcg2_shared_ops,
618 },
619};
620
621static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
622 .cmd_rcgr = 0x80a8,
623 .mnd_width = 8,
624 .hid_width = 5,
625 .parent_map = disp_cc_parent_map_2,
626 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
627 .clkr.hw.init = &(const struct clk_init_data) {
628 .name = "disp_cc_mdss_pclk0_clk_src",
629 .parent_data = disp_cc_parent_data_2,
630 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
631 .flags = CLK_SET_RATE_PARENT,
632 .ops = &clk_pixel_ops,
633 },
634};
635
636static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = {
637 .cmd_rcgr = 0x80c0,
638 .mnd_width = 8,
639 .hid_width = 5,
640 .parent_map = disp_cc_parent_map_2,
641 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
642 .clkr.hw.init = &(const struct clk_init_data) {
643 .name = "disp_cc_mdss_pclk1_clk_src",
644 .parent_data = disp_cc_parent_data_2,
645 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
646 .flags = CLK_SET_RATE_PARENT,
647 .ops = &clk_pixel_ops,
648 },
649};
650
651static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
652 .cmd_rcgr = 0x80f0,
653 .mnd_width = 0,
654 .hid_width = 5,
655 .parent_map = disp_cc_parent_map_0,
656 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
657 .clkr.hw.init = &(const struct clk_init_data) {
658 .name = "disp_cc_mdss_vsync_clk_src",
659 .parent_data = disp_cc_parent_data_0,
660 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
661 .flags = CLK_SET_RATE_PARENT,
662 .ops = &clk_rcg2_ops,
663 },
664};
665
666static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = {
667 F(32000, P_SLEEP_CLK, 1, 0, 0),
668 { }
669};
670
671static struct clk_rcg2 disp_cc_sleep_clk_src = {
672 .cmd_rcgr = 0xe05c,
673 .mnd_width = 0,
674 .hid_width = 5,
675 .parent_map = disp_cc_parent_map_9,
676 .freq_tbl = ftbl_disp_cc_sleep_clk_src,
677 .clkr.hw.init = &(const struct clk_init_data) {
678 .name = "disp_cc_sleep_clk_src",
679 .parent_data = disp_cc_parent_data_9,
680 .num_parents = ARRAY_SIZE(disp_cc_parent_data_9),
681 .flags = CLK_SET_RATE_PARENT,
682 .ops = &clk_rcg2_ops,
683 },
684};
685
686static struct clk_rcg2 disp_cc_xo_clk_src = {
687 .cmd_rcgr = 0xe03c,
688 .mnd_width = 0,
689 .hid_width = 5,
690 .parent_map = disp_cc_parent_map_0,
691 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
692 .clkr.hw.init = &(const struct clk_init_data) {
693 .name = "disp_cc_xo_clk_src",
694 .parent_data = disp_cc_parent_data_0_ao,
695 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0_ao),
696 .flags = CLK_SET_RATE_PARENT,
697 .ops = &clk_rcg2_ops,
698 },
699};
700
701static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
702 .reg = 0x8120,
703 .shift = 0,
704 .width = 4,
705 .clkr.hw.init = &(const struct clk_init_data) {
706 .name = "disp_cc_mdss_byte0_div_clk_src",
707 .parent_hws = (const struct clk_hw*[]) {
708 &disp_cc_mdss_byte0_clk_src.clkr.hw,
709 },
710 .num_parents = 1,
711 .ops = &clk_regmap_div_ops,
712 },
713};
714
715static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = {
716 .reg = 0x813c,
717 .shift = 0,
718 .width = 4,
719 .clkr.hw.init = &(const struct clk_init_data) {
720 .name = "disp_cc_mdss_byte1_div_clk_src",
721 .parent_hws = (const struct clk_hw*[]) {
722 &disp_cc_mdss_byte1_clk_src.clkr.hw,
723 },
724 .num_parents = 1,
725 .ops = &clk_regmap_div_ops,
726 },
727};
728
729static struct clk_regmap_div disp_cc_mdss_dptx0_link_div_clk_src = {
730 .reg = 0x8188,
731 .shift = 0,
732 .width = 4,
733 .clkr.hw.init = &(const struct clk_init_data) {
734 .name = "disp_cc_mdss_dptx0_link_div_clk_src",
735 .parent_hws = (const struct clk_hw*[]) {
736 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
737 },
738 .num_parents = 1,
739 .flags = CLK_SET_RATE_PARENT,
740 .ops = &clk_regmap_div_ro_ops,
741 },
742};
743
744static struct clk_regmap_div disp_cc_mdss_dptx1_link_div_clk_src = {
745 .reg = 0x821c,
746 .shift = 0,
747 .width = 4,
748 .clkr.hw.init = &(const struct clk_init_data) {
749 .name = "disp_cc_mdss_dptx1_link_div_clk_src",
750 .parent_hws = (const struct clk_hw*[]) {
751 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
752 },
753 .num_parents = 1,
754 .flags = CLK_SET_RATE_PARENT,
755 .ops = &clk_regmap_div_ro_ops,
756 },
757};
758
759static struct clk_regmap_div disp_cc_mdss_dptx2_link_div_clk_src = {
760 .reg = 0x8250,
761 .shift = 0,
762 .width = 4,
763 .clkr.hw.init = &(const struct clk_init_data) {
764 .name = "disp_cc_mdss_dptx2_link_div_clk_src",
765 .parent_hws = (const struct clk_hw*[]) {
766 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
767 },
768 .num_parents = 1,
769 .flags = CLK_SET_RATE_PARENT,
770 .ops = &clk_regmap_div_ro_ops,
771 },
772};
773
774static struct clk_regmap_div disp_cc_mdss_dptx3_link_div_clk_src = {
775 .reg = 0x82cc,
776 .shift = 0,
777 .width = 4,
778 .clkr.hw.init = &(const struct clk_init_data) {
779 .name = "disp_cc_mdss_dptx3_link_div_clk_src",
780 .parent_hws = (const struct clk_hw*[]) {
781 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
782 },
783 .num_parents = 1,
784 .flags = CLK_SET_RATE_PARENT,
785 .ops = &clk_regmap_div_ro_ops,
786 },
787};
788
789static struct clk_branch disp_cc_mdss_accu_clk = {
790 .halt_reg = 0xe058,
791 .halt_check = BRANCH_HALT_VOTED,
792 .clkr = {
793 .enable_reg = 0xe058,
794 .enable_mask = BIT(0),
795 .hw.init = &(const struct clk_init_data) {
796 .name = "disp_cc_mdss_accu_clk",
797 .parent_hws = (const struct clk_hw*[]) {
798 &disp_cc_xo_clk_src.clkr.hw,
799 },
800 .num_parents = 1,
801 .flags = CLK_SET_RATE_PARENT,
802 .ops = &clk_branch2_ops,
803 },
804 },
805};
806
807static struct clk_branch disp_cc_mdss_ahb1_clk = {
808 .halt_reg = 0xa020,
809 .halt_check = BRANCH_HALT,
810 .clkr = {
811 .enable_reg = 0xa020,
812 .enable_mask = BIT(0),
813 .hw.init = &(const struct clk_init_data) {
814 .name = "disp_cc_mdss_ahb1_clk",
815 .parent_hws = (const struct clk_hw*[]) {
816 &disp_cc_mdss_ahb_clk_src.clkr.hw,
817 },
818 .num_parents = 1,
819 .flags = CLK_SET_RATE_PARENT,
820 .ops = &clk_branch2_ops,
821 },
822 },
823};
824
825static struct clk_branch disp_cc_mdss_ahb_clk = {
826 .halt_reg = 0x80a4,
827 .halt_check = BRANCH_HALT,
828 .clkr = {
829 .enable_reg = 0x80a4,
830 .enable_mask = BIT(0),
831 .hw.init = &(const struct clk_init_data) {
832 .name = "disp_cc_mdss_ahb_clk",
833 .parent_hws = (const struct clk_hw*[]) {
834 &disp_cc_mdss_ahb_clk_src.clkr.hw,
835 },
836 .num_parents = 1,
837 .flags = CLK_SET_RATE_PARENT,
838 .ops = &clk_branch2_ops,
839 },
840 },
841};
842
843static struct clk_branch disp_cc_mdss_byte0_clk = {
844 .halt_reg = 0x8028,
845 .halt_check = BRANCH_HALT,
846 .clkr = {
847 .enable_reg = 0x8028,
848 .enable_mask = BIT(0),
849 .hw.init = &(const struct clk_init_data) {
850 .name = "disp_cc_mdss_byte0_clk",
851 .parent_hws = (const struct clk_hw*[]) {
852 &disp_cc_mdss_byte0_clk_src.clkr.hw,
853 },
854 .num_parents = 1,
855 .flags = CLK_SET_RATE_PARENT,
856 .ops = &clk_branch2_ops,
857 },
858 },
859};
860
861static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
862 .halt_reg = 0x802c,
863 .halt_check = BRANCH_HALT,
864 .clkr = {
865 .enable_reg = 0x802c,
866 .enable_mask = BIT(0),
867 .hw.init = &(const struct clk_init_data) {
868 .name = "disp_cc_mdss_byte0_intf_clk",
869 .parent_hws = (const struct clk_hw*[]) {
870 &disp_cc_mdss_byte0_div_clk_src.clkr.hw,
871 },
872 .num_parents = 1,
873 .flags = CLK_SET_RATE_PARENT,
874 .ops = &clk_branch2_ops,
875 },
876 },
877};
878
879static struct clk_branch disp_cc_mdss_byte1_clk = {
880 .halt_reg = 0x8030,
881 .halt_check = BRANCH_HALT,
882 .clkr = {
883 .enable_reg = 0x8030,
884 .enable_mask = BIT(0),
885 .hw.init = &(const struct clk_init_data) {
886 .name = "disp_cc_mdss_byte1_clk",
887 .parent_hws = (const struct clk_hw*[]) {
888 &disp_cc_mdss_byte1_clk_src.clkr.hw,
889 },
890 .num_parents = 1,
891 .flags = CLK_SET_RATE_PARENT,
892 .ops = &clk_branch2_ops,
893 },
894 },
895};
896
897static struct clk_branch disp_cc_mdss_byte1_intf_clk = {
898 .halt_reg = 0x8034,
899 .halt_check = BRANCH_HALT,
900 .clkr = {
901 .enable_reg = 0x8034,
902 .enable_mask = BIT(0),
903 .hw.init = &(const struct clk_init_data) {
904 .name = "disp_cc_mdss_byte1_intf_clk",
905 .parent_hws = (const struct clk_hw*[]) {
906 &disp_cc_mdss_byte1_div_clk_src.clkr.hw,
907 },
908 .num_parents = 1,
909 .flags = CLK_SET_RATE_PARENT,
910 .ops = &clk_branch2_ops,
911 },
912 },
913};
914
915static struct clk_branch disp_cc_mdss_dptx0_aux_clk = {
916 .halt_reg = 0x8058,
917 .halt_check = BRANCH_HALT,
918 .clkr = {
919 .enable_reg = 0x8058,
920 .enable_mask = BIT(0),
921 .hw.init = &(const struct clk_init_data) {
922 .name = "disp_cc_mdss_dptx0_aux_clk",
923 .parent_hws = (const struct clk_hw*[]) {
924 &disp_cc_mdss_dptx0_aux_clk_src.clkr.hw,
925 },
926 .num_parents = 1,
927 .flags = CLK_SET_RATE_PARENT,
928 .ops = &clk_branch2_ops,
929 },
930 },
931};
932
933static struct clk_branch disp_cc_mdss_dptx0_crypto_clk = {
934 .halt_reg = 0x804c,
935 .halt_check = BRANCH_HALT,
936 .clkr = {
937 .enable_reg = 0x804c,
938 .enable_mask = BIT(0),
939 .hw.init = &(const struct clk_init_data) {
940 .name = "disp_cc_mdss_dptx0_crypto_clk",
941 .parent_hws = (const struct clk_hw*[]) {
942 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
943 },
944 .num_parents = 1,
945 .flags = CLK_SET_RATE_PARENT,
946 .ops = &clk_branch2_ops,
947 },
948 },
949};
950
951static struct clk_branch disp_cc_mdss_dptx0_link_clk = {
952 .halt_reg = 0x8040,
953 .halt_check = BRANCH_HALT,
954 .clkr = {
955 .enable_reg = 0x8040,
956 .enable_mask = BIT(0),
957 .hw.init = &(const struct clk_init_data) {
958 .name = "disp_cc_mdss_dptx0_link_clk",
959 .parent_hws = (const struct clk_hw*[]) {
960 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
961 },
962 .num_parents = 1,
963 .flags = CLK_SET_RATE_PARENT,
964 .ops = &clk_branch2_ops,
965 },
966 },
967};
968
969static struct clk_branch disp_cc_mdss_dptx0_link_intf_clk = {
970 .halt_reg = 0x8048,
971 .halt_check = BRANCH_HALT,
972 .clkr = {
973 .enable_reg = 0x8048,
974 .enable_mask = BIT(0),
975 .hw.init = &(const struct clk_init_data) {
976 .name = "disp_cc_mdss_dptx0_link_intf_clk",
977 .parent_hws = (const struct clk_hw*[]) {
978 &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
979 },
980 .num_parents = 1,
981 .flags = CLK_SET_RATE_PARENT,
982 .ops = &clk_branch2_ops,
983 },
984 },
985};
986
987static struct clk_branch disp_cc_mdss_dptx0_pixel0_clk = {
988 .halt_reg = 0x8050,
989 .halt_check = BRANCH_HALT,
990 .clkr = {
991 .enable_reg = 0x8050,
992 .enable_mask = BIT(0),
993 .hw.init = &(const struct clk_init_data) {
994 .name = "disp_cc_mdss_dptx0_pixel0_clk",
995 .parent_hws = (const struct clk_hw*[]) {
996 &disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw,
997 },
998 .num_parents = 1,
999 .flags = CLK_SET_RATE_PARENT,
1000 .ops = &clk_branch2_ops,
1001 },
1002 },
1003};
1004
1005static struct clk_branch disp_cc_mdss_dptx0_pixel1_clk = {
1006 .halt_reg = 0x8054,
1007 .halt_check = BRANCH_HALT,
1008 .clkr = {
1009 .enable_reg = 0x8054,
1010 .enable_mask = BIT(0),
1011 .hw.init = &(const struct clk_init_data) {
1012 .name = "disp_cc_mdss_dptx0_pixel1_clk",
1013 .parent_hws = (const struct clk_hw*[]) {
1014 &disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw,
1015 },
1016 .num_parents = 1,
1017 .flags = CLK_SET_RATE_PARENT,
1018 .ops = &clk_branch2_ops,
1019 },
1020 },
1021};
1022
1023static struct clk_branch disp_cc_mdss_dptx0_usb_router_link_intf_clk = {
1024 .halt_reg = 0x8044,
1025 .halt_check = BRANCH_HALT,
1026 .clkr = {
1027 .enable_reg = 0x8044,
1028 .enable_mask = BIT(0),
1029 .hw.init = &(const struct clk_init_data) {
1030 .name = "disp_cc_mdss_dptx0_usb_router_link_intf_clk",
1031 .parent_hws = (const struct clk_hw*[]) {
1032 &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
1033 },
1034 .num_parents = 1,
1035 .flags = CLK_SET_RATE_PARENT,
1036 .ops = &clk_branch2_ops,
1037 },
1038 },
1039};
1040
1041static struct clk_branch disp_cc_mdss_dptx1_aux_clk = {
1042 .halt_reg = 0x8074,
1043 .halt_check = BRANCH_HALT,
1044 .clkr = {
1045 .enable_reg = 0x8074,
1046 .enable_mask = BIT(0),
1047 .hw.init = &(const struct clk_init_data) {
1048 .name = "disp_cc_mdss_dptx1_aux_clk",
1049 .parent_hws = (const struct clk_hw*[]) {
1050 &disp_cc_mdss_dptx1_aux_clk_src.clkr.hw,
1051 },
1052 .num_parents = 1,
1053 .flags = CLK_SET_RATE_PARENT,
1054 .ops = &clk_branch2_ops,
1055 },
1056 },
1057};
1058
1059static struct clk_branch disp_cc_mdss_dptx1_crypto_clk = {
1060 .halt_reg = 0x8070,
1061 .halt_check = BRANCH_HALT,
1062 .clkr = {
1063 .enable_reg = 0x8070,
1064 .enable_mask = BIT(0),
1065 .hw.init = &(const struct clk_init_data) {
1066 .name = "disp_cc_mdss_dptx1_crypto_clk",
1067 .parent_hws = (const struct clk_hw*[]) {
1068 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
1069 },
1070 .num_parents = 1,
1071 .flags = CLK_SET_RATE_PARENT,
1072 .ops = &clk_branch2_ops,
1073 },
1074 },
1075};
1076
1077static struct clk_branch disp_cc_mdss_dptx1_link_clk = {
1078 .halt_reg = 0x8064,
1079 .halt_check = BRANCH_HALT,
1080 .clkr = {
1081 .enable_reg = 0x8064,
1082 .enable_mask = BIT(0),
1083 .hw.init = &(const struct clk_init_data) {
1084 .name = "disp_cc_mdss_dptx1_link_clk",
1085 .parent_hws = (const struct clk_hw*[]) {
1086 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
1087 },
1088 .num_parents = 1,
1089 .flags = CLK_SET_RATE_PARENT,
1090 .ops = &clk_branch2_ops,
1091 },
1092 },
1093};
1094
1095static struct clk_branch disp_cc_mdss_dptx1_link_intf_clk = {
1096 .halt_reg = 0x806c,
1097 .halt_check = BRANCH_HALT,
1098 .clkr = {
1099 .enable_reg = 0x806c,
1100 .enable_mask = BIT(0),
1101 .hw.init = &(const struct clk_init_data) {
1102 .name = "disp_cc_mdss_dptx1_link_intf_clk",
1103 .parent_hws = (const struct clk_hw*[]) {
1104 &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw,
1105 },
1106 .num_parents = 1,
1107 .flags = CLK_SET_RATE_PARENT,
1108 .ops = &clk_branch2_ops,
1109 },
1110 },
1111};
1112
1113static struct clk_branch disp_cc_mdss_dptx1_pixel0_clk = {
1114 .halt_reg = 0x805c,
1115 .halt_check = BRANCH_HALT,
1116 .clkr = {
1117 .enable_reg = 0x805c,
1118 .enable_mask = BIT(0),
1119 .hw.init = &(const struct clk_init_data) {
1120 .name = "disp_cc_mdss_dptx1_pixel0_clk",
1121 .parent_hws = (const struct clk_hw*[]) {
1122 &disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw,
1123 },
1124 .num_parents = 1,
1125 .flags = CLK_SET_RATE_PARENT,
1126 .ops = &clk_branch2_ops,
1127 },
1128 },
1129};
1130
1131static struct clk_branch disp_cc_mdss_dptx1_pixel1_clk = {
1132 .halt_reg = 0x8060,
1133 .halt_check = BRANCH_HALT,
1134 .clkr = {
1135 .enable_reg = 0x8060,
1136 .enable_mask = BIT(0),
1137 .hw.init = &(const struct clk_init_data) {
1138 .name = "disp_cc_mdss_dptx1_pixel1_clk",
1139 .parent_hws = (const struct clk_hw*[]) {
1140 &disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw,
1141 },
1142 .num_parents = 1,
1143 .flags = CLK_SET_RATE_PARENT,
1144 .ops = &clk_branch2_ops,
1145 },
1146 },
1147};
1148
1149static struct clk_branch disp_cc_mdss_dptx1_usb_router_link_intf_clk = {
1150 .halt_reg = 0x8068,
1151 .halt_check = BRANCH_HALT,
1152 .clkr = {
1153 .enable_reg = 0x8068,
1154 .enable_mask = BIT(0),
1155 .hw.init = &(const struct clk_init_data) {
1156 .name = "disp_cc_mdss_dptx1_usb_router_link_intf_clk",
1157 .parent_hws = (const struct clk_hw*[]) {
1158 &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw,
1159 },
1160 .num_parents = 1,
1161 .flags = CLK_SET_RATE_PARENT,
1162 .ops = &clk_branch2_ops,
1163 },
1164 },
1165};
1166
1167static struct clk_branch disp_cc_mdss_dptx2_aux_clk = {
1168 .halt_reg = 0x808c,
1169 .halt_check = BRANCH_HALT,
1170 .clkr = {
1171 .enable_reg = 0x808c,
1172 .enable_mask = BIT(0),
1173 .hw.init = &(const struct clk_init_data) {
1174 .name = "disp_cc_mdss_dptx2_aux_clk",
1175 .parent_hws = (const struct clk_hw*[]) {
1176 &disp_cc_mdss_dptx2_aux_clk_src.clkr.hw,
1177 },
1178 .num_parents = 1,
1179 .flags = CLK_SET_RATE_PARENT,
1180 .ops = &clk_branch2_ops,
1181 },
1182 },
1183};
1184
1185static struct clk_branch disp_cc_mdss_dptx2_crypto_clk = {
1186 .halt_reg = 0x8088,
1187 .halt_check = BRANCH_HALT,
1188 .clkr = {
1189 .enable_reg = 0x8088,
1190 .enable_mask = BIT(0),
1191 .hw.init = &(const struct clk_init_data) {
1192 .name = "disp_cc_mdss_dptx2_crypto_clk",
1193 .parent_hws = (const struct clk_hw*[]) {
1194 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
1195 },
1196 .num_parents = 1,
1197 .flags = CLK_SET_RATE_PARENT,
1198 .ops = &clk_branch2_ops,
1199 },
1200 },
1201};
1202
1203static struct clk_branch disp_cc_mdss_dptx2_link_clk = {
1204 .halt_reg = 0x8080,
1205 .halt_check = BRANCH_HALT,
1206 .clkr = {
1207 .enable_reg = 0x8080,
1208 .enable_mask = BIT(0),
1209 .hw.init = &(const struct clk_init_data) {
1210 .name = "disp_cc_mdss_dptx2_link_clk",
1211 .parent_hws = (const struct clk_hw*[]) {
1212 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
1213 },
1214 .num_parents = 1,
1215 .flags = CLK_SET_RATE_PARENT,
1216 .ops = &clk_branch2_ops,
1217 },
1218 },
1219};
1220
1221static struct clk_branch disp_cc_mdss_dptx2_link_intf_clk = {
1222 .halt_reg = 0x8084,
1223 .halt_check = BRANCH_HALT,
1224 .clkr = {
1225 .enable_reg = 0x8084,
1226 .enable_mask = BIT(0),
1227 .hw.init = &(const struct clk_init_data) {
1228 .name = "disp_cc_mdss_dptx2_link_intf_clk",
1229 .parent_hws = (const struct clk_hw*[]) {
1230 &disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw,
1231 },
1232 .num_parents = 1,
1233 .flags = CLK_SET_RATE_PARENT,
1234 .ops = &clk_branch2_ops,
1235 },
1236 },
1237};
1238
1239static struct clk_branch disp_cc_mdss_dptx2_pixel0_clk = {
1240 .halt_reg = 0x8078,
1241 .halt_check = BRANCH_HALT,
1242 .clkr = {
1243 .enable_reg = 0x8078,
1244 .enable_mask = BIT(0),
1245 .hw.init = &(const struct clk_init_data) {
1246 .name = "disp_cc_mdss_dptx2_pixel0_clk",
1247 .parent_hws = (const struct clk_hw*[]) {
1248 &disp_cc_mdss_dptx2_pixel0_clk_src.clkr.hw,
1249 },
1250 .num_parents = 1,
1251 .flags = CLK_SET_RATE_PARENT,
1252 .ops = &clk_branch2_ops,
1253 },
1254 },
1255};
1256
1257static struct clk_branch disp_cc_mdss_dptx2_pixel1_clk = {
1258 .halt_reg = 0x807c,
1259 .halt_check = BRANCH_HALT,
1260 .clkr = {
1261 .enable_reg = 0x807c,
1262 .enable_mask = BIT(0),
1263 .hw.init = &(const struct clk_init_data) {
1264 .name = "disp_cc_mdss_dptx2_pixel1_clk",
1265 .parent_hws = (const struct clk_hw*[]) {
1266 &disp_cc_mdss_dptx2_pixel1_clk_src.clkr.hw,
1267 },
1268 .num_parents = 1,
1269 .flags = CLK_SET_RATE_PARENT,
1270 .ops = &clk_branch2_ops,
1271 },
1272 },
1273};
1274
1275static struct clk_branch disp_cc_mdss_dptx3_aux_clk = {
1276 .halt_reg = 0x809c,
1277 .halt_check = BRANCH_HALT,
1278 .clkr = {
1279 .enable_reg = 0x809c,
1280 .enable_mask = BIT(0),
1281 .hw.init = &(const struct clk_init_data) {
1282 .name = "disp_cc_mdss_dptx3_aux_clk",
1283 .parent_hws = (const struct clk_hw*[]) {
1284 &disp_cc_mdss_dptx3_aux_clk_src.clkr.hw,
1285 },
1286 .num_parents = 1,
1287 .flags = CLK_SET_RATE_PARENT,
1288 .ops = &clk_branch2_ops,
1289 },
1290 },
1291};
1292
1293static struct clk_branch disp_cc_mdss_dptx3_crypto_clk = {
1294 .halt_reg = 0x80a0,
1295 .halt_check = BRANCH_HALT,
1296 .clkr = {
1297 .enable_reg = 0x80a0,
1298 .enable_mask = BIT(0),
1299 .hw.init = &(const struct clk_init_data) {
1300 .name = "disp_cc_mdss_dptx3_crypto_clk",
1301 .parent_hws = (const struct clk_hw*[]) {
1302 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
1303 },
1304 .num_parents = 1,
1305 .flags = CLK_SET_RATE_PARENT,
1306 .ops = &clk_branch2_ops,
1307 },
1308 },
1309};
1310
1311static struct clk_branch disp_cc_mdss_dptx3_link_clk = {
1312 .halt_reg = 0x8094,
1313 .halt_check = BRANCH_HALT,
1314 .clkr = {
1315 .enable_reg = 0x8094,
1316 .enable_mask = BIT(0),
1317 .hw.init = &(const struct clk_init_data) {
1318 .name = "disp_cc_mdss_dptx3_link_clk",
1319 .parent_hws = (const struct clk_hw*[]) {
1320 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
1321 },
1322 .num_parents = 1,
1323 .flags = CLK_SET_RATE_PARENT,
1324 .ops = &clk_branch2_ops,
1325 },
1326 },
1327};
1328
1329static struct clk_branch disp_cc_mdss_dptx3_link_intf_clk = {
1330 .halt_reg = 0x8098,
1331 .halt_check = BRANCH_HALT,
1332 .clkr = {
1333 .enable_reg = 0x8098,
1334 .enable_mask = BIT(0),
1335 .hw.init = &(const struct clk_init_data) {
1336 .name = "disp_cc_mdss_dptx3_link_intf_clk",
1337 .parent_hws = (const struct clk_hw*[]) {
1338 &disp_cc_mdss_dptx3_link_div_clk_src.clkr.hw,
1339 },
1340 .num_parents = 1,
1341 .flags = CLK_SET_RATE_PARENT,
1342 .ops = &clk_branch2_ops,
1343 },
1344 },
1345};
1346
1347static struct clk_branch disp_cc_mdss_dptx3_pixel0_clk = {
1348 .halt_reg = 0x8090,
1349 .halt_check = BRANCH_HALT,
1350 .clkr = {
1351 .enable_reg = 0x8090,
1352 .enable_mask = BIT(0),
1353 .hw.init = &(const struct clk_init_data) {
1354 .name = "disp_cc_mdss_dptx3_pixel0_clk",
1355 .parent_hws = (const struct clk_hw*[]) {
1356 &disp_cc_mdss_dptx3_pixel0_clk_src.clkr.hw,
1357 },
1358 .num_parents = 1,
1359 .flags = CLK_SET_RATE_PARENT,
1360 .ops = &clk_branch2_ops,
1361 },
1362 },
1363};
1364
1365static struct clk_branch disp_cc_mdss_esc0_clk = {
1366 .halt_reg = 0x8038,
1367 .halt_check = BRANCH_HALT,
1368 .clkr = {
1369 .enable_reg = 0x8038,
1370 .enable_mask = BIT(0),
1371 .hw.init = &(const struct clk_init_data) {
1372 .name = "disp_cc_mdss_esc0_clk",
1373 .parent_hws = (const struct clk_hw*[]) {
1374 &disp_cc_mdss_esc0_clk_src.clkr.hw,
1375 },
1376 .num_parents = 1,
1377 .flags = CLK_SET_RATE_PARENT,
1378 .ops = &clk_branch2_ops,
1379 },
1380 },
1381};
1382
1383static struct clk_branch disp_cc_mdss_esc1_clk = {
1384 .halt_reg = 0x803c,
1385 .halt_check = BRANCH_HALT,
1386 .clkr = {
1387 .enable_reg = 0x803c,
1388 .enable_mask = BIT(0),
1389 .hw.init = &(const struct clk_init_data) {
1390 .name = "disp_cc_mdss_esc1_clk",
1391 .parent_hws = (const struct clk_hw*[]) {
1392 &disp_cc_mdss_esc1_clk_src.clkr.hw,
1393 },
1394 .num_parents = 1,
1395 .flags = CLK_SET_RATE_PARENT,
1396 .ops = &clk_branch2_ops,
1397 },
1398 },
1399};
1400
1401static struct clk_branch disp_cc_mdss_mdp1_clk = {
1402 .halt_reg = 0xa004,
1403 .halt_check = BRANCH_HALT,
1404 .clkr = {
1405 .enable_reg = 0xa004,
1406 .enable_mask = BIT(0),
1407 .hw.init = &(const struct clk_init_data) {
1408 .name = "disp_cc_mdss_mdp1_clk",
1409 .parent_hws = (const struct clk_hw*[]) {
1410 &disp_cc_mdss_mdp_clk_src.clkr.hw,
1411 },
1412 .num_parents = 1,
1413 .flags = CLK_SET_RATE_PARENT,
1414 .ops = &clk_branch2_ops,
1415 },
1416 },
1417};
1418
1419static struct clk_branch disp_cc_mdss_mdp_clk = {
1420 .halt_reg = 0x800c,
1421 .halt_check = BRANCH_HALT,
1422 .clkr = {
1423 .enable_reg = 0x800c,
1424 .enable_mask = BIT(0),
1425 .hw.init = &(const struct clk_init_data) {
1426 .name = "disp_cc_mdss_mdp_clk",
1427 .parent_hws = (const struct clk_hw*[]) {
1428 &disp_cc_mdss_mdp_clk_src.clkr.hw,
1429 },
1430 .num_parents = 1,
1431 .flags = CLK_SET_RATE_PARENT,
1432 .ops = &clk_branch2_ops,
1433 },
1434 },
1435};
1436
1437static struct clk_branch disp_cc_mdss_mdp_lut1_clk = {
1438 .halt_reg = 0xa010,
1439 .halt_check = BRANCH_HALT,
1440 .clkr = {
1441 .enable_reg = 0xa010,
1442 .enable_mask = BIT(0),
1443 .hw.init = &(const struct clk_init_data) {
1444 .name = "disp_cc_mdss_mdp_lut1_clk",
1445 .parent_hws = (const struct clk_hw*[]) {
1446 &disp_cc_mdss_mdp_clk_src.clkr.hw,
1447 },
1448 .num_parents = 1,
1449 .flags = CLK_SET_RATE_PARENT,
1450 .ops = &clk_branch2_ops,
1451 },
1452 },
1453};
1454
1455static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
1456 .halt_reg = 0x8018,
1457 .halt_check = BRANCH_HALT_VOTED,
1458 .clkr = {
1459 .enable_reg = 0x8018,
1460 .enable_mask = BIT(0),
1461 .hw.init = &(const struct clk_init_data) {
1462 .name = "disp_cc_mdss_mdp_lut_clk",
1463 .parent_hws = (const struct clk_hw*[]) {
1464 &disp_cc_mdss_mdp_clk_src.clkr.hw,
1465 },
1466 .num_parents = 1,
1467 .flags = CLK_SET_RATE_PARENT,
1468 .ops = &clk_branch2_ops,
1469 },
1470 },
1471};
1472
1473static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
1474 .halt_reg = 0xc004,
1475 .halt_check = BRANCH_HALT_VOTED,
1476 .clkr = {
1477 .enable_reg = 0xc004,
1478 .enable_mask = BIT(0),
1479 .hw.init = &(const struct clk_init_data) {
1480 .name = "disp_cc_mdss_non_gdsc_ahb_clk",
1481 .parent_hws = (const struct clk_hw*[]) {
1482 &disp_cc_mdss_ahb_clk_src.clkr.hw,
1483 },
1484 .num_parents = 1,
1485 .flags = CLK_SET_RATE_PARENT,
1486 .ops = &clk_branch2_ops,
1487 },
1488 },
1489};
1490
1491static struct clk_branch disp_cc_mdss_pclk0_clk = {
1492 .halt_reg = 0x8004,
1493 .halt_check = BRANCH_HALT,
1494 .clkr = {
1495 .enable_reg = 0x8004,
1496 .enable_mask = BIT(0),
1497 .hw.init = &(const struct clk_init_data) {
1498 .name = "disp_cc_mdss_pclk0_clk",
1499 .parent_hws = (const struct clk_hw*[]) {
1500 &disp_cc_mdss_pclk0_clk_src.clkr.hw,
1501 },
1502 .num_parents = 1,
1503 .flags = CLK_SET_RATE_PARENT,
1504 .ops = &clk_branch2_ops,
1505 },
1506 },
1507};
1508
1509static struct clk_branch disp_cc_mdss_pclk1_clk = {
1510 .halt_reg = 0x8008,
1511 .halt_check = BRANCH_HALT,
1512 .clkr = {
1513 .enable_reg = 0x8008,
1514 .enable_mask = BIT(0),
1515 .hw.init = &(const struct clk_init_data) {
1516 .name = "disp_cc_mdss_pclk1_clk",
1517 .parent_hws = (const struct clk_hw*[]) {
1518 &disp_cc_mdss_pclk1_clk_src.clkr.hw,
1519 },
1520 .num_parents = 1,
1521 .flags = CLK_SET_RATE_PARENT,
1522 .ops = &clk_branch2_ops,
1523 },
1524 },
1525};
1526
1527static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
1528 .halt_reg = 0xc00c,
1529 .halt_check = BRANCH_HALT,
1530 .clkr = {
1531 .enable_reg = 0xc00c,
1532 .enable_mask = BIT(0),
1533 .hw.init = &(const struct clk_init_data) {
1534 .name = "disp_cc_mdss_rscc_ahb_clk",
1535 .parent_hws = (const struct clk_hw*[]) {
1536 &disp_cc_mdss_ahb_clk_src.clkr.hw,
1537 },
1538 .num_parents = 1,
1539 .flags = CLK_SET_RATE_PARENT,
1540 .ops = &clk_branch2_ops,
1541 },
1542 },
1543};
1544
1545static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
1546 .halt_reg = 0xc008,
1547 .halt_check = BRANCH_HALT,
1548 .clkr = {
1549 .enable_reg = 0xc008,
1550 .enable_mask = BIT(0),
1551 .hw.init = &(const struct clk_init_data) {
1552 .name = "disp_cc_mdss_rscc_vsync_clk",
1553 .parent_hws = (const struct clk_hw*[]) {
1554 &disp_cc_mdss_vsync_clk_src.clkr.hw,
1555 },
1556 .num_parents = 1,
1557 .flags = CLK_SET_RATE_PARENT,
1558 .ops = &clk_branch2_ops,
1559 },
1560 },
1561};
1562
1563static struct clk_branch disp_cc_mdss_vsync1_clk = {
1564 .halt_reg = 0xa01c,
1565 .halt_check = BRANCH_HALT,
1566 .clkr = {
1567 .enable_reg = 0xa01c,
1568 .enable_mask = BIT(0),
1569 .hw.init = &(const struct clk_init_data) {
1570 .name = "disp_cc_mdss_vsync1_clk",
1571 .parent_hws = (const struct clk_hw*[]) {
1572 &disp_cc_mdss_vsync_clk_src.clkr.hw,
1573 },
1574 .num_parents = 1,
1575 .flags = CLK_SET_RATE_PARENT,
1576 .ops = &clk_branch2_ops,
1577 },
1578 },
1579};
1580
1581static struct clk_branch disp_cc_mdss_vsync_clk = {
1582 .halt_reg = 0x8024,
1583 .halt_check = BRANCH_HALT,
1584 .clkr = {
1585 .enable_reg = 0x8024,
1586 .enable_mask = BIT(0),
1587 .hw.init = &(const struct clk_init_data) {
1588 .name = "disp_cc_mdss_vsync_clk",
1589 .parent_hws = (const struct clk_hw*[]) {
1590 &disp_cc_mdss_vsync_clk_src.clkr.hw,
1591 },
1592 .num_parents = 1,
1593 .flags = CLK_SET_RATE_PARENT,
1594 .ops = &clk_branch2_ops,
1595 },
1596 },
1597};
1598
1599static struct clk_branch disp_cc_sleep_clk = {
1600 .halt_reg = 0xe074,
1601 .halt_check = BRANCH_HALT,
1602 .clkr = {
1603 .enable_reg = 0xe074,
1604 .enable_mask = BIT(0),
1605 .hw.init = &(const struct clk_init_data) {
1606 .name = "disp_cc_sleep_clk",
1607 .parent_hws = (const struct clk_hw*[]) {
1608 &disp_cc_sleep_clk_src.clkr.hw,
1609 },
1610 .num_parents = 1,
1611 .flags = CLK_SET_RATE_PARENT,
1612 .ops = &clk_branch2_ops,
1613 },
1614 },
1615};
1616
1617static struct gdsc mdss_gdsc = {
1618 .gdscr = 0x9000,
1619 .pd = {
1620 .name = "mdss_gdsc",
1621 },
1622 .pwrsts = PWRSTS_OFF_ON,
1623 .flags = HW_CTRL | RETAIN_FF_ENABLE,
1624};
1625
1626static struct gdsc mdss_int2_gdsc = {
1627 .gdscr = 0xb000,
1628 .pd = {
1629 .name = "mdss_int2_gdsc",
1630 },
1631 .pwrsts = PWRSTS_OFF_ON,
1632 .flags = HW_CTRL | RETAIN_FF_ENABLE,
1633};
1634
1635static struct clk_regmap *disp_cc_sm8650_clocks[] = {
1636 [DISP_CC_MDSS_ACCU_CLK] = &disp_cc_mdss_accu_clk.clkr,
1637 [DISP_CC_MDSS_AHB1_CLK] = &disp_cc_mdss_ahb1_clk.clkr,
1638 [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
1639 [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
1640 [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
1641 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
1642 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
1643 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
1644 [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr,
1645 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr,
1646 [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr,
1647 [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr,
1648 [DISP_CC_MDSS_DPTX0_AUX_CLK] = &disp_cc_mdss_dptx0_aux_clk.clkr,
1649 [DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &disp_cc_mdss_dptx0_aux_clk_src.clkr,
1650 [DISP_CC_MDSS_DPTX0_CRYPTO_CLK] = &disp_cc_mdss_dptx0_crypto_clk.clkr,
1651 [DISP_CC_MDSS_DPTX0_LINK_CLK] = &disp_cc_mdss_dptx0_link_clk.clkr,
1652 [DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &disp_cc_mdss_dptx0_link_clk_src.clkr,
1653 [DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx0_link_div_clk_src.clkr,
1654 [DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &disp_cc_mdss_dptx0_link_intf_clk.clkr,
1655 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &disp_cc_mdss_dptx0_pixel0_clk.clkr,
1656 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx0_pixel0_clk_src.clkr,
1657 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp_cc_mdss_dptx0_pixel1_clk.clkr,
1658 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx0_pixel1_clk_src.clkr,
1659 [DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] =
1660 &disp_cc_mdss_dptx0_usb_router_link_intf_clk.clkr,
1661 [DISP_CC_MDSS_DPTX1_AUX_CLK] = &disp_cc_mdss_dptx1_aux_clk.clkr,
1662 [DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &disp_cc_mdss_dptx1_aux_clk_src.clkr,
1663 [DISP_CC_MDSS_DPTX1_CRYPTO_CLK] = &disp_cc_mdss_dptx1_crypto_clk.clkr,
1664 [DISP_CC_MDSS_DPTX1_LINK_CLK] = &disp_cc_mdss_dptx1_link_clk.clkr,
1665 [DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &disp_cc_mdss_dptx1_link_clk_src.clkr,
1666 [DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx1_link_div_clk_src.clkr,
1667 [DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &disp_cc_mdss_dptx1_link_intf_clk.clkr,
1668 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &disp_cc_mdss_dptx1_pixel0_clk.clkr,
1669 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx1_pixel0_clk_src.clkr,
1670 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &disp_cc_mdss_dptx1_pixel1_clk.clkr,
1671 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx1_pixel1_clk_src.clkr,
1672 [DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] =
1673 &disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr,
1674 [DISP_CC_MDSS_DPTX2_AUX_CLK] = &disp_cc_mdss_dptx2_aux_clk.clkr,
1675 [DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] = &disp_cc_mdss_dptx2_aux_clk_src.clkr,
1676 [DISP_CC_MDSS_DPTX2_CRYPTO_CLK] = &disp_cc_mdss_dptx2_crypto_clk.clkr,
1677 [DISP_CC_MDSS_DPTX2_LINK_CLK] = &disp_cc_mdss_dptx2_link_clk.clkr,
1678 [DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] = &disp_cc_mdss_dptx2_link_clk_src.clkr,
1679 [DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx2_link_div_clk_src.clkr,
1680 [DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] = &disp_cc_mdss_dptx2_link_intf_clk.clkr,
1681 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK] = &disp_cc_mdss_dptx2_pixel0_clk.clkr,
1682 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx2_pixel0_clk_src.clkr,
1683 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &disp_cc_mdss_dptx2_pixel1_clk.clkr,
1684 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx2_pixel1_clk_src.clkr,
1685 [DISP_CC_MDSS_DPTX3_AUX_CLK] = &disp_cc_mdss_dptx3_aux_clk.clkr,
1686 [DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] = &disp_cc_mdss_dptx3_aux_clk_src.clkr,
1687 [DISP_CC_MDSS_DPTX3_CRYPTO_CLK] = &disp_cc_mdss_dptx3_crypto_clk.clkr,
1688 [DISP_CC_MDSS_DPTX3_LINK_CLK] = &disp_cc_mdss_dptx3_link_clk.clkr,
1689 [DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] = &disp_cc_mdss_dptx3_link_clk_src.clkr,
1690 [DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx3_link_div_clk_src.clkr,
1691 [DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] = &disp_cc_mdss_dptx3_link_intf_clk.clkr,
1692 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK] = &disp_cc_mdss_dptx3_pixel0_clk.clkr,
1693 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx3_pixel0_clk_src.clkr,
1694 [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
1695 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
1696 [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr,
1697 [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr,
1698 [DISP_CC_MDSS_MDP1_CLK] = &disp_cc_mdss_mdp1_clk.clkr,
1699 [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
1700 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
1701 [DISP_CC_MDSS_MDP_LUT1_CLK] = &disp_cc_mdss_mdp_lut1_clk.clkr,
1702 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
1703 [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
1704 [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
1705 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
1706 [DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr,
1707 [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr,
1708 [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
1709 [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
1710 [DISP_CC_MDSS_VSYNC1_CLK] = &disp_cc_mdss_vsync1_clk.clkr,
1711 [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
1712 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
1713 [DISP_CC_PLL0] = &disp_cc_pll0.clkr,
1714 [DISP_CC_PLL1] = &disp_cc_pll1.clkr,
1715 [DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr,
1716 [DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr,
1717 [DISP_CC_XO_CLK_SRC] = &disp_cc_xo_clk_src.clkr,
1718};
1719
1720static const struct qcom_reset_map disp_cc_sm8650_resets[] = {
1721 [DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
1722 [DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 },
1723 [DISP_CC_MDSS_RSCC_BCR] = { 0xc000 },
1724};
1725
1726static struct gdsc *disp_cc_sm8650_gdscs[] = {
1727 [MDSS_GDSC] = &mdss_gdsc,
1728 [MDSS_INT2_GDSC] = &mdss_int2_gdsc,
1729};
1730
1731static const struct regmap_config disp_cc_sm8650_regmap_config = {
1732 .reg_bits = 32,
1733 .reg_stride = 4,
1734 .val_bits = 32,
1735 .max_register = 0x11008,
1736 .fast_io = true,
1737};
1738
1739static struct qcom_cc_desc disp_cc_sm8650_desc = {
1740 .config = &disp_cc_sm8650_regmap_config,
1741 .clks = disp_cc_sm8650_clocks,
1742 .num_clks = ARRAY_SIZE(disp_cc_sm8650_clocks),
1743 .resets = disp_cc_sm8650_resets,
1744 .num_resets = ARRAY_SIZE(disp_cc_sm8650_resets),
1745 .gdscs = disp_cc_sm8650_gdscs,
1746 .num_gdscs = ARRAY_SIZE(disp_cc_sm8650_gdscs),
1747};
1748
1749static const struct of_device_id disp_cc_sm8650_match_table[] = {
1750 { .compatible = "qcom,sm8650-dispcc" },
1751 { }
1752};
1753MODULE_DEVICE_TABLE(of, disp_cc_sm8650_match_table);
1754
1755static int disp_cc_sm8650_probe(struct platform_device *pdev)
1756{
1757 struct regmap *regmap;
1758 int ret;
1759
1760 ret = devm_pm_runtime_enable(&pdev->dev);
1761 if (ret)
1762 return ret;
1763
1764 ret = pm_runtime_resume_and_get(&pdev->dev);
1765 if (ret)
1766 return ret;
1767
1768 regmap = qcom_cc_map(pdev, &disp_cc_sm8650_desc);
1769 if (IS_ERR(regmap)) {
1770 ret = PTR_ERR(regmap);
1771 goto err_put_rpm;
1772 }
1773
1774 clk_lucid_ole_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
1775 clk_lucid_ole_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
1776
1777 /* Enable clock gating for MDP clocks */
1778 regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10);
1779
1780 /* Keep clocks always enabled */
1781 regmap_update_bits(regmap, 0xe054, BIT(0), BIT(0)); /* disp_cc_xo_clk */
1782
1783 ret = qcom_cc_really_probe(pdev, &disp_cc_sm8650_desc, regmap);
1784 if (ret)
1785 goto err_put_rpm;
1786
1787 pm_runtime_put(&pdev->dev);
1788
1789 return 0;
1790
1791err_put_rpm:
1792 pm_runtime_put_sync(&pdev->dev);
1793
1794 return ret;
1795}
1796
1797static struct platform_driver disp_cc_sm8650_driver = {
1798 .probe = disp_cc_sm8650_probe,
1799 .driver = {
1800 .name = "disp_cc-sm8650",
1801 .of_match_table = disp_cc_sm8650_match_table,
1802 },
1803};
1804
1805static int __init disp_cc_sm8650_init(void)
1806{
1807 return platform_driver_register(&disp_cc_sm8650_driver);
1808}
1809subsys_initcall(disp_cc_sm8650_init);
1810
1811static void __exit disp_cc_sm8650_exit(void)
1812{
1813 platform_driver_unregister(&disp_cc_sm8650_driver);
1814}
1815module_exit(disp_cc_sm8650_exit);
1816
1817MODULE_DESCRIPTION("QTI DISPCC SM8650 Driver");
1818MODULE_LICENSE("GPL");