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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/clk-provider.h>
7#include <linux/module.h>
8#include <linux/platform_device.h>
9#include <linux/regmap.h>
10#include <linux/reset-controller.h>
11
12#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
13
14#include "clk-alpha-pll.h"
15#include "clk-branch.h"
16#include "clk-rcg.h"
17#include "clk-regmap-divider.h"
18#include "common.h"
19#include "gdsc.h"
20#include "reset.h"
21
22enum {
23 P_BI_TCXO,
24 P_DISP_CC_PLL0_OUT_MAIN,
25 P_DSI0_PHY_PLL_OUT_BYTECLK,
26 P_DSI0_PHY_PLL_OUT_DSICLK,
27 P_DSI1_PHY_PLL_OUT_BYTECLK,
28 P_DSI1_PHY_PLL_OUT_DSICLK,
29 P_GPLL0_OUT_MAIN,
30 P_GPLL0_OUT_MAIN_DIV,
31 P_DP_PHY_PLL_LINK_CLK,
32 P_DP_PHY_PLL_VCO_DIV_CLK,
33};
34
35static struct clk_alpha_pll disp_cc_pll0 = {
36 .offset = 0x0,
37 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
38 .clkr = {
39 .hw.init = &(struct clk_init_data){
40 .name = "disp_cc_pll0",
41 .parent_data = &(const struct clk_parent_data){
42 .fw_name = "bi_tcxo", .name = "bi_tcxo",
43 },
44 .num_parents = 1,
45 .ops = &clk_alpha_pll_fabia_ops,
46 },
47 },
48};
49
50static const struct parent_map disp_cc_parent_map_0[] = {
51 { P_BI_TCXO, 0 },
52 { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
53 { P_DSI1_PHY_PLL_OUT_BYTECLK, 2 },
54};
55
56static const struct clk_parent_data disp_cc_parent_data_0[] = {
57 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
58 { .fw_name = "dsi0_phy_pll_out_byteclk", .name = "dsi0_phy_pll_out_byteclk" },
59 { .fw_name = "dsi1_phy_pll_out_byteclk", .name = "dsi1_phy_pll_out_byteclk" },
60};
61
62static const struct parent_map disp_cc_parent_map_1[] = {
63 { P_BI_TCXO, 0 },
64 { P_DP_PHY_PLL_LINK_CLK, 1 },
65 { P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
66};
67
68static const struct clk_parent_data disp_cc_parent_data_1[] = {
69 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
70 { .fw_name = "dp_link_clk_divsel_ten", .name = "dp_link_clk_divsel_ten" },
71 { .fw_name = "dp_vco_divided_clk_src_mux", .name = "dp_vco_divided_clk_src_mux" },
72};
73
74static const struct parent_map disp_cc_parent_map_2[] = {
75 { P_BI_TCXO, 0 },
76};
77
78static const struct clk_parent_data disp_cc_parent_data_2[] = {
79 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
80};
81
82static const struct parent_map disp_cc_parent_map_3[] = {
83 { P_BI_TCXO, 0 },
84 { P_DISP_CC_PLL0_OUT_MAIN, 1 },
85 { P_GPLL0_OUT_MAIN, 4 },
86 { P_GPLL0_OUT_MAIN_DIV, 5 },
87};
88
89static const struct clk_parent_data disp_cc_parent_data_3[] = {
90 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
91 { .hw = &disp_cc_pll0.clkr.hw },
92 { .fw_name = "gcc_disp_gpll0_clk_src", .name = "gcc_disp_gpll0_clk_src" },
93 { .fw_name = "gcc_disp_gpll0_div_clk_src", .name = "gcc_disp_gpll0_div_clk_src" },
94};
95
96static const struct parent_map disp_cc_parent_map_4[] = {
97 { P_BI_TCXO, 0 },
98 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
99 { P_DSI1_PHY_PLL_OUT_DSICLK, 2 },
100};
101
102static const struct clk_parent_data disp_cc_parent_data_4[] = {
103 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
104 { .fw_name = "dsi0_phy_pll_out_dsiclk", .name = "dsi0_phy_pll_out_dsiclk" },
105 { .fw_name = "dsi1_phy_pll_out_dsiclk", .name = "dsi1_phy_pll_out_dsiclk" },
106};
107
108/* Return the HW recalc rate for idle use case */
109static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
110 .cmd_rcgr = 0x20d0,
111 .mnd_width = 0,
112 .hid_width = 5,
113 .parent_map = disp_cc_parent_map_0,
114 .clkr.hw.init = &(struct clk_init_data){
115 .name = "disp_cc_mdss_byte0_clk_src",
116 .parent_data = disp_cc_parent_data_0,
117 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
118 .flags = CLK_SET_RATE_PARENT,
119 .ops = &clk_byte2_ops,
120 },
121};
122
123/* Return the HW recalc rate for idle use case */
124static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
125 .cmd_rcgr = 0x20ec,
126 .mnd_width = 0,
127 .hid_width = 5,
128 .parent_map = disp_cc_parent_map_0,
129 .clkr.hw.init = &(struct clk_init_data){
130 .name = "disp_cc_mdss_byte1_clk_src",
131 .parent_data = disp_cc_parent_data_0,
132 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
133 .flags = CLK_SET_RATE_PARENT,
134 .ops = &clk_byte2_ops,
135 },
136};
137
138static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = {
139 F(19200000, P_BI_TCXO, 1, 0, 0),
140 { }
141};
142
143static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
144 .cmd_rcgr = 0x219c,
145 .mnd_width = 0,
146 .hid_width = 5,
147 .parent_map = disp_cc_parent_map_2,
148 .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
149 .clkr.hw.init = &(struct clk_init_data){
150 .name = "disp_cc_mdss_dp_aux_clk_src",
151 .parent_data = disp_cc_parent_data_2,
152 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
153 .flags = CLK_SET_RATE_PARENT,
154 .ops = &clk_rcg2_ops,
155 },
156};
157
158static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
159 .cmd_rcgr = 0x2154,
160 .mnd_width = 0,
161 .hid_width = 5,
162 .parent_map = disp_cc_parent_map_1,
163 .clkr.hw.init = &(struct clk_init_data){
164 .name = "disp_cc_mdss_dp_crypto_clk_src",
165 .parent_data = disp_cc_parent_data_1,
166 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
167 .ops = &clk_byte2_ops,
168 },
169};
170
171static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
172 .cmd_rcgr = 0x2138,
173 .mnd_width = 0,
174 .hid_width = 5,
175 .parent_map = disp_cc_parent_map_1,
176 .clkr.hw.init = &(struct clk_init_data){
177 .name = "disp_cc_mdss_dp_link_clk_src",
178 .parent_data = disp_cc_parent_data_1,
179 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
180 .flags = CLK_SET_RATE_PARENT,
181 .ops = &clk_byte2_ops,
182 },
183};
184
185static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = {
186 .cmd_rcgr = 0x2184,
187 .mnd_width = 16,
188 .hid_width = 5,
189 .parent_map = disp_cc_parent_map_1,
190 .clkr.hw.init = &(struct clk_init_data){
191 .name = "disp_cc_mdss_dp_pixel1_clk_src",
192 .parent_data = disp_cc_parent_data_1,
193 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
194 .flags = CLK_SET_RATE_PARENT,
195 .ops = &clk_dp_ops,
196 },
197};
198
199static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
200 .cmd_rcgr = 0x216c,
201 .mnd_width = 16,
202 .hid_width = 5,
203 .parent_map = disp_cc_parent_map_1,
204 .clkr.hw.init = &(struct clk_init_data){
205 .name = "disp_cc_mdss_dp_pixel_clk_src",
206 .parent_data = disp_cc_parent_data_1,
207 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
208 .flags = CLK_SET_RATE_PARENT,
209 .ops = &clk_dp_ops,
210 },
211};
212
213static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = {
214 F(19200000, P_BI_TCXO, 1, 0, 0),
215 { }
216};
217
218static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
219 .cmd_rcgr = 0x2108,
220 .mnd_width = 0,
221 .hid_width = 5,
222 .parent_map = disp_cc_parent_map_0,
223 .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
224 .clkr.hw.init = &(struct clk_init_data){
225 .name = "disp_cc_mdss_esc0_clk_src",
226 .parent_data = disp_cc_parent_data_0,
227 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
228 .ops = &clk_rcg2_ops,
229 },
230};
231
232static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {
233 .cmd_rcgr = 0x2120,
234 .mnd_width = 0,
235 .hid_width = 5,
236 .parent_map = disp_cc_parent_map_0,
237 .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
238 .clkr.hw.init = &(struct clk_init_data){
239 .name = "disp_cc_mdss_esc1_clk_src",
240 .parent_data = disp_cc_parent_data_0,
241 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
242 .ops = &clk_rcg2_ops,
243 },
244};
245
246static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
247 F(19200000, P_BI_TCXO, 1, 0, 0),
248 F(85714286, P_GPLL0_OUT_MAIN, 7, 0, 0),
249 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
250 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
251 F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
252 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
253 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
254 F(344000000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
255 F(430000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
256 { }
257};
258
259static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
260 .cmd_rcgr = 0x2088,
261 .mnd_width = 0,
262 .hid_width = 5,
263 .parent_map = disp_cc_parent_map_3,
264 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
265 .clkr.hw.init = &(struct clk_init_data){
266 .name = "disp_cc_mdss_mdp_clk_src",
267 .parent_data = disp_cc_parent_data_3,
268 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
269 .ops = &clk_rcg2_shared_ops,
270 },
271};
272
273/* Return the HW recalc rate for idle use case */
274static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
275 .cmd_rcgr = 0x2058,
276 .mnd_width = 8,
277 .hid_width = 5,
278 .parent_map = disp_cc_parent_map_4,
279 .clkr.hw.init = &(struct clk_init_data){
280 .name = "disp_cc_mdss_pclk0_clk_src",
281 .parent_data = disp_cc_parent_data_4,
282 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
283 .flags = CLK_SET_RATE_PARENT,
284 .ops = &clk_pixel_ops,
285 },
286};
287
288/* Return the HW recalc rate for idle use case */
289static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = {
290 .cmd_rcgr = 0x2070,
291 .mnd_width = 8,
292 .hid_width = 5,
293 .parent_map = disp_cc_parent_map_4,
294 .clkr.hw.init = &(struct clk_init_data){
295 .name = "disp_cc_mdss_pclk1_clk_src",
296 .parent_data = disp_cc_parent_data_4,
297 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
298 .flags = CLK_SET_RATE_PARENT,
299 .ops = &clk_pixel_ops,
300 },
301};
302
303static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = {
304 F(19200000, P_BI_TCXO, 1, 0, 0),
305 F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
306 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
307 F(344000000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
308 F(430000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
309 { }
310};
311
312static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
313 .cmd_rcgr = 0x20a0,
314 .mnd_width = 0,
315 .hid_width = 5,
316 .parent_map = disp_cc_parent_map_3,
317 .freq_tbl = ftbl_disp_cc_mdss_rot_clk_src,
318 .clkr.hw.init = &(struct clk_init_data){
319 .name = "disp_cc_mdss_rot_clk_src",
320 .parent_data = disp_cc_parent_data_3,
321 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
322 .ops = &clk_rcg2_shared_ops,
323 },
324};
325
326static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
327 .cmd_rcgr = 0x20b8,
328 .mnd_width = 0,
329 .hid_width = 5,
330 .parent_map = disp_cc_parent_map_2,
331 .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
332 .clkr.hw.init = &(struct clk_init_data){
333 .name = "disp_cc_mdss_vsync_clk_src",
334 .parent_data = disp_cc_parent_data_2,
335 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
336 .ops = &clk_rcg2_ops,
337 },
338};
339
340static struct clk_branch disp_cc_mdss_ahb_clk = {
341 .halt_reg = 0x4004,
342 .halt_check = BRANCH_HALT,
343 .clkr = {
344 .enable_reg = 0x4004,
345 .enable_mask = BIT(0),
346 .hw.init = &(struct clk_init_data){
347 .name = "disp_cc_mdss_ahb_clk",
348 .ops = &clk_branch2_ops,
349 },
350 },
351};
352
353static struct clk_branch disp_cc_mdss_axi_clk = {
354 .halt_reg = 0x4008,
355 .halt_check = BRANCH_HALT,
356 .clkr = {
357 .enable_reg = 0x4008,
358 .enable_mask = BIT(0),
359 .hw.init = &(struct clk_init_data){
360 .name = "disp_cc_mdss_axi_clk",
361 .ops = &clk_branch2_ops,
362 },
363 },
364};
365
366/* Return the HW recalc rate for idle use case */
367static struct clk_branch disp_cc_mdss_byte0_clk = {
368 .halt_reg = 0x2028,
369 .halt_check = BRANCH_HALT,
370 .clkr = {
371 .enable_reg = 0x2028,
372 .enable_mask = BIT(0),
373 .hw.init = &(struct clk_init_data){
374 .name = "disp_cc_mdss_byte0_clk",
375 .parent_hws = (const struct clk_hw*[]){
376 &disp_cc_mdss_byte0_clk_src.clkr.hw,
377 },
378 .num_parents = 1,
379 .flags = CLK_SET_RATE_PARENT,
380 .ops = &clk_branch2_ops,
381 },
382 },
383};
384
385/* Return the HW recalc rate for idle use case */
386static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
387 .reg = 0x20e8,
388 .shift = 0,
389 .width = 2,
390 .clkr = {
391 .hw.init = &(struct clk_init_data){
392 .name = "disp_cc_mdss_byte0_div_clk_src",
393 .parent_hws = (const struct clk_hw*[]){
394 &disp_cc_mdss_byte0_clk_src.clkr.hw,
395 },
396 .num_parents = 1,
397 .ops = &clk_regmap_div_ops,
398 },
399 },
400};
401
402/* Return the HW recalc rate for idle use case */
403static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
404 .halt_reg = 0x202c,
405 .halt_check = BRANCH_HALT,
406 .clkr = {
407 .enable_reg = 0x202c,
408 .enable_mask = BIT(0),
409 .hw.init = &(struct clk_init_data){
410 .name = "disp_cc_mdss_byte0_intf_clk",
411 .parent_hws = (const struct clk_hw*[]){
412 &disp_cc_mdss_byte0_div_clk_src.clkr.hw,
413 },
414 .num_parents = 1,
415 .flags = CLK_SET_RATE_PARENT,
416 .ops = &clk_branch2_ops,
417 },
418 },
419};
420
421/* Return the HW recalc rate for idle use case */
422static struct clk_branch disp_cc_mdss_byte1_clk = {
423 .halt_reg = 0x2030,
424 .halt_check = BRANCH_HALT,
425 .clkr = {
426 .enable_reg = 0x2030,
427 .enable_mask = BIT(0),
428 .hw.init = &(struct clk_init_data){
429 .name = "disp_cc_mdss_byte1_clk",
430 .parent_hws = (const struct clk_hw*[]){
431 &disp_cc_mdss_byte1_clk_src.clkr.hw,
432 },
433 .num_parents = 1,
434 .flags = CLK_SET_RATE_PARENT,
435 .ops = &clk_branch2_ops,
436 },
437 },
438};
439
440/* Return the HW recalc rate for idle use case */
441static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = {
442 .reg = 0x2104,
443 .shift = 0,
444 .width = 2,
445 .clkr = {
446 .hw.init = &(struct clk_init_data){
447 .name = "disp_cc_mdss_byte1_div_clk_src",
448 .parent_hws = (const struct clk_hw*[]){
449 &disp_cc_mdss_byte1_clk_src.clkr.hw,
450 },
451 .num_parents = 1,
452 .ops = &clk_regmap_div_ops,
453 },
454 },
455};
456
457/* Return the HW recalc rate for idle use case */
458static struct clk_branch disp_cc_mdss_byte1_intf_clk = {
459 .halt_reg = 0x2034,
460 .halt_check = BRANCH_HALT,
461 .clkr = {
462 .enable_reg = 0x2034,
463 .enable_mask = BIT(0),
464 .hw.init = &(struct clk_init_data){
465 .name = "disp_cc_mdss_byte1_intf_clk",
466 .parent_hws = (const struct clk_hw*[]){
467 &disp_cc_mdss_byte1_div_clk_src.clkr.hw,
468 },
469 .num_parents = 1,
470 .flags = CLK_SET_RATE_PARENT,
471 .ops = &clk_branch2_ops,
472 },
473 },
474};
475
476static struct clk_branch disp_cc_mdss_dp_aux_clk = {
477 .halt_reg = 0x2054,
478 .halt_check = BRANCH_HALT,
479 .clkr = {
480 .enable_reg = 0x2054,
481 .enable_mask = BIT(0),
482 .hw.init = &(struct clk_init_data){
483 .name = "disp_cc_mdss_dp_aux_clk",
484 .parent_hws = (const struct clk_hw*[]){
485 &disp_cc_mdss_dp_aux_clk_src.clkr.hw,
486 },
487 .num_parents = 1,
488 .flags = CLK_SET_RATE_PARENT,
489 .ops = &clk_branch2_ops,
490 },
491 },
492};
493
494static struct clk_branch disp_cc_mdss_dp_crypto_clk = {
495 .halt_reg = 0x2048,
496 .halt_check = BRANCH_HALT,
497 .clkr = {
498 .enable_reg = 0x2048,
499 .enable_mask = BIT(0),
500 .hw.init = &(struct clk_init_data){
501 .name = "disp_cc_mdss_dp_crypto_clk",
502 .parent_hws = (const struct clk_hw*[]){
503 &disp_cc_mdss_dp_crypto_clk_src.clkr.hw,
504 },
505 .num_parents = 1,
506 .flags = CLK_SET_RATE_PARENT,
507 .ops = &clk_branch2_ops,
508 },
509 },
510};
511
512static struct clk_branch disp_cc_mdss_dp_link_clk = {
513 .halt_reg = 0x2040,
514 .halt_check = BRANCH_HALT,
515 .clkr = {
516 .enable_reg = 0x2040,
517 .enable_mask = BIT(0),
518 .hw.init = &(struct clk_init_data){
519 .name = "disp_cc_mdss_dp_link_clk",
520 .parent_hws = (const struct clk_hw*[]){
521 &disp_cc_mdss_dp_link_clk_src.clkr.hw,
522 },
523 .num_parents = 1,
524 .flags = CLK_SET_RATE_PARENT,
525 .ops = &clk_branch2_ops,
526 },
527 },
528};
529
530/* reset state of disp_cc_mdss_dp_link_div_clk_src divider is 0x3 (div 4) */
531static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
532 .halt_reg = 0x2044,
533 .halt_check = BRANCH_HALT,
534 .clkr = {
535 .enable_reg = 0x2044,
536 .enable_mask = BIT(0),
537 .hw.init = &(struct clk_init_data){
538 .name = "disp_cc_mdss_dp_link_intf_clk",
539 .parent_hws = (const struct clk_hw*[]){
540 &disp_cc_mdss_dp_link_clk_src.clkr.hw,
541 },
542 .num_parents = 1,
543 .ops = &clk_branch2_ops,
544 },
545 },
546};
547
548static struct clk_branch disp_cc_mdss_dp_pixel1_clk = {
549 .halt_reg = 0x2050,
550 .halt_check = BRANCH_HALT,
551 .clkr = {
552 .enable_reg = 0x2050,
553 .enable_mask = BIT(0),
554 .hw.init = &(struct clk_init_data){
555 .name = "disp_cc_mdss_dp_pixel1_clk",
556 .parent_hws = (const struct clk_hw*[]){
557 &disp_cc_mdss_dp_pixel1_clk_src.clkr.hw,
558 },
559 .num_parents = 1,
560 .flags = CLK_SET_RATE_PARENT,
561 .ops = &clk_branch2_ops,
562 },
563 },
564};
565
566static struct clk_branch disp_cc_mdss_dp_pixel_clk = {
567 .halt_reg = 0x204c,
568 .halt_check = BRANCH_HALT,
569 .clkr = {
570 .enable_reg = 0x204c,
571 .enable_mask = BIT(0),
572 .hw.init = &(struct clk_init_data){
573 .name = "disp_cc_mdss_dp_pixel_clk",
574 .parent_hws = (const struct clk_hw*[]){
575 &disp_cc_mdss_dp_pixel_clk_src.clkr.hw,
576 },
577 .num_parents = 1,
578 .flags = CLK_SET_RATE_PARENT,
579 .ops = &clk_branch2_ops,
580 },
581 },
582};
583
584static struct clk_branch disp_cc_mdss_esc0_clk = {
585 .halt_reg = 0x2038,
586 .halt_check = BRANCH_HALT,
587 .clkr = {
588 .enable_reg = 0x2038,
589 .enable_mask = BIT(0),
590 .hw.init = &(struct clk_init_data){
591 .name = "disp_cc_mdss_esc0_clk",
592 .parent_hws = (const struct clk_hw*[]){
593 &disp_cc_mdss_esc0_clk_src.clkr.hw,
594 },
595 .num_parents = 1,
596 .flags = CLK_SET_RATE_PARENT,
597 .ops = &clk_branch2_ops,
598 },
599 },
600};
601
602static struct clk_branch disp_cc_mdss_esc1_clk = {
603 .halt_reg = 0x203c,
604 .halt_check = BRANCH_HALT,
605 .clkr = {
606 .enable_reg = 0x203c,
607 .enable_mask = BIT(0),
608 .hw.init = &(struct clk_init_data){
609 .name = "disp_cc_mdss_esc1_clk",
610 .parent_hws = (const struct clk_hw*[]){
611 &disp_cc_mdss_esc1_clk_src.clkr.hw,
612 },
613 .num_parents = 1,
614 .flags = CLK_SET_RATE_PARENT,
615 .ops = &clk_branch2_ops,
616 },
617 },
618};
619
620static struct clk_branch disp_cc_mdss_mdp_clk = {
621 .halt_reg = 0x200c,
622 .halt_check = BRANCH_HALT,
623 .clkr = {
624 .enable_reg = 0x200c,
625 .enable_mask = BIT(0),
626 .hw.init = &(struct clk_init_data){
627 .name = "disp_cc_mdss_mdp_clk",
628 .parent_hws = (const struct clk_hw*[]){
629 &disp_cc_mdss_mdp_clk_src.clkr.hw,
630 },
631 .num_parents = 1,
632 .flags = CLK_SET_RATE_PARENT,
633 .ops = &clk_branch2_ops,
634 },
635 },
636};
637
638static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
639 .halt_reg = 0x201c,
640 .halt_check = BRANCH_HALT,
641 .clkr = {
642 .enable_reg = 0x201c,
643 .enable_mask = BIT(0),
644 .hw.init = &(struct clk_init_data){
645 .name = "disp_cc_mdss_mdp_lut_clk",
646 .parent_hws = (const struct clk_hw*[]){
647 &disp_cc_mdss_mdp_clk_src.clkr.hw,
648 },
649 .num_parents = 1,
650 .ops = &clk_branch2_ops,
651 },
652 },
653};
654
655/* Return the HW recalc rate for idle use case */
656static struct clk_branch disp_cc_mdss_pclk0_clk = {
657 .halt_reg = 0x2004,
658 .halt_check = BRANCH_HALT,
659 .clkr = {
660 .enable_reg = 0x2004,
661 .enable_mask = BIT(0),
662 .hw.init = &(struct clk_init_data){
663 .name = "disp_cc_mdss_pclk0_clk",
664 .parent_hws = (const struct clk_hw*[]){
665 &disp_cc_mdss_pclk0_clk_src.clkr.hw,
666 },
667 .num_parents = 1,
668 .flags = CLK_SET_RATE_PARENT,
669 .ops = &clk_branch2_ops,
670 },
671 },
672};
673
674/* Return the HW recalc rate for idle use case */
675static struct clk_branch disp_cc_mdss_pclk1_clk = {
676 .halt_reg = 0x2008,
677 .halt_check = BRANCH_HALT,
678 .clkr = {
679 .enable_reg = 0x2008,
680 .enable_mask = BIT(0),
681 .hw.init = &(struct clk_init_data){
682 .name = "disp_cc_mdss_pclk1_clk",
683 .parent_hws = (const struct clk_hw*[]){
684 &disp_cc_mdss_pclk1_clk_src.clkr.hw,
685 },
686 .num_parents = 1,
687 .flags = CLK_SET_RATE_PARENT,
688 .ops = &clk_branch2_ops,
689 },
690 },
691};
692
693static struct clk_branch disp_cc_mdss_rot_clk = {
694 .halt_reg = 0x2014,
695 .halt_check = BRANCH_HALT,
696 .clkr = {
697 .enable_reg = 0x2014,
698 .enable_mask = BIT(0),
699 .hw.init = &(struct clk_init_data){
700 .name = "disp_cc_mdss_rot_clk",
701 .parent_hws = (const struct clk_hw*[]){
702 &disp_cc_mdss_rot_clk_src.clkr.hw,
703 },
704 .num_parents = 1,
705 .flags = CLK_SET_RATE_PARENT,
706 .ops = &clk_branch2_ops,
707 },
708 },
709};
710
711static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
712 .halt_reg = 0x5004,
713 .halt_check = BRANCH_HALT,
714 .clkr = {
715 .enable_reg = 0x5004,
716 .enable_mask = BIT(0),
717 .hw.init = &(struct clk_init_data){
718 .name = "disp_cc_mdss_rscc_ahb_clk",
719 .ops = &clk_branch2_ops,
720 },
721 },
722};
723
724static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
725 .halt_reg = 0x5008,
726 .halt_check = BRANCH_HALT,
727 .clkr = {
728 .enable_reg = 0x5008,
729 .enable_mask = BIT(0),
730 .hw.init = &(struct clk_init_data){
731 .name = "disp_cc_mdss_rscc_vsync_clk",
732 .parent_hws = (const struct clk_hw*[]){
733 &disp_cc_mdss_vsync_clk_src.clkr.hw,
734 },
735 .num_parents = 1,
736 .flags = CLK_SET_RATE_PARENT,
737 .ops = &clk_branch2_ops,
738 },
739 },
740};
741
742static struct clk_branch disp_cc_mdss_vsync_clk = {
743 .halt_reg = 0x2024,
744 .halt_check = BRANCH_HALT,
745 .clkr = {
746 .enable_reg = 0x2024,
747 .enable_mask = BIT(0),
748 .hw.init = &(struct clk_init_data){
749 .name = "disp_cc_mdss_vsync_clk",
750 .parent_hws = (const struct clk_hw*[]){
751 &disp_cc_mdss_vsync_clk_src.clkr.hw,
752 },
753 .num_parents = 1,
754 .flags = CLK_SET_RATE_PARENT,
755 .ops = &clk_branch2_ops,
756 },
757 },
758};
759
760static struct gdsc mdss_gdsc = {
761 .gdscr = 0x3000,
762 .pd = {
763 .name = "mdss_gdsc",
764 },
765 .pwrsts = PWRSTS_OFF_ON,
766 .flags = HW_CTRL | POLL_CFG_GDSCR,
767};
768
769static struct clk_regmap *disp_cc_sdm845_clocks[] = {
770 [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
771 [DISP_CC_MDSS_AXI_CLK] = &disp_cc_mdss_axi_clk.clkr,
772 [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
773 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
774 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
775 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] =
776 &disp_cc_mdss_byte0_div_clk_src.clkr,
777 [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr,
778 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr,
779 [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr,
780 [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] =
781 &disp_cc_mdss_byte1_div_clk_src.clkr,
782 [DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr,
783 [DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr,
784 [DISP_CC_MDSS_DP_CRYPTO_CLK] = &disp_cc_mdss_dp_crypto_clk.clkr,
785 [DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] =
786 &disp_cc_mdss_dp_crypto_clk_src.clkr,
787 [DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr,
788 [DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr,
789 [DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr,
790 [DISP_CC_MDSS_DP_PIXEL1_CLK] = &disp_cc_mdss_dp_pixel1_clk.clkr,
791 [DISP_CC_MDSS_DP_PIXEL1_CLK_SRC] =
792 &disp_cc_mdss_dp_pixel1_clk_src.clkr,
793 [DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr,
794 [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr,
795 [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
796 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
797 [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr,
798 [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr,
799 [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
800 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
801 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
802 [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
803 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
804 [DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr,
805 [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr,
806 [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
807 [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
808 [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
809 [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
810 [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
811 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
812 [DISP_CC_PLL0] = &disp_cc_pll0.clkr,
813};
814
815static const struct qcom_reset_map disp_cc_sdm845_resets[] = {
816 [DISP_CC_MDSS_RSCC_BCR] = { 0x5000 },
817};
818
819static struct gdsc *disp_cc_sdm845_gdscs[] = {
820 [MDSS_GDSC] = &mdss_gdsc,
821};
822
823static const struct regmap_config disp_cc_sdm845_regmap_config = {
824 .reg_bits = 32,
825 .reg_stride = 4,
826 .val_bits = 32,
827 .max_register = 0x10000,
828 .fast_io = true,
829};
830
831static const struct qcom_cc_desc disp_cc_sdm845_desc = {
832 .config = &disp_cc_sdm845_regmap_config,
833 .clks = disp_cc_sdm845_clocks,
834 .num_clks = ARRAY_SIZE(disp_cc_sdm845_clocks),
835 .resets = disp_cc_sdm845_resets,
836 .num_resets = ARRAY_SIZE(disp_cc_sdm845_resets),
837 .gdscs = disp_cc_sdm845_gdscs,
838 .num_gdscs = ARRAY_SIZE(disp_cc_sdm845_gdscs),
839};
840
841static const struct of_device_id disp_cc_sdm845_match_table[] = {
842 { .compatible = "qcom,sdm845-dispcc" },
843 { }
844};
845MODULE_DEVICE_TABLE(of, disp_cc_sdm845_match_table);
846
847static int disp_cc_sdm845_probe(struct platform_device *pdev)
848{
849 struct regmap *regmap;
850 struct alpha_pll_config disp_cc_pll0_config = {};
851
852 regmap = qcom_cc_map(pdev, &disp_cc_sdm845_desc);
853 if (IS_ERR(regmap))
854 return PTR_ERR(regmap);
855
856 disp_cc_pll0_config.l = 0x2c;
857 disp_cc_pll0_config.alpha = 0xcaaa;
858
859 clk_fabia_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
860
861 /* Enable hardware clock gating for DSI and MDP clocks */
862 regmap_update_bits(regmap, 0x8000, 0x7f0, 0x7f0);
863
864 return qcom_cc_really_probe(pdev, &disp_cc_sdm845_desc, regmap);
865}
866
867static struct platform_driver disp_cc_sdm845_driver = {
868 .probe = disp_cc_sdm845_probe,
869 .driver = {
870 .name = "disp_cc-sdm845",
871 .of_match_table = disp_cc_sdm845_match_table,
872 },
873};
874
875static int __init disp_cc_sdm845_init(void)
876{
877 return platform_driver_register(&disp_cc_sdm845_driver);
878}
879subsys_initcall(disp_cc_sdm845_init);
880
881static void __exit disp_cc_sdm845_exit(void)
882{
883 platform_driver_unregister(&disp_cc_sdm845_driver);
884}
885module_exit(disp_cc_sdm845_exit);
886
887MODULE_LICENSE("GPL v2");
888MODULE_DESCRIPTION("QTI DISPCC SDM845 Driver");