1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
   4 * Copyright (c) 2022, Linaro Ltd.
   5 */
   6
   7#include <linux/clk-provider.h>
   8#include <linux/module.h>
   9#include <linux/platform_device.h>
  10#include <linux/property.h>
  11#include <linux/pm_clock.h>
  12#include <linux/pm_runtime.h>
  13#include <linux/regmap.h>
  14#include <linux/reset-controller.h>
  15
  16#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
  17
  18#include "clk-alpha-pll.h"
  19#include "clk-branch.h"
  20#include "clk-rcg.h"
  21#include "clk-regmap-divider.h"
  22#include "common.h"
  23#include "gdsc.h"
  24#include "reset.h"
  25
  26/* Need to match the order of clocks in DT binding */
  27enum {
  28	DT_IFACE,
  29	DT_BI_TCXO,
  30	DT_SLEEP_CLK,
  31	DT_DP0_PHY_PLL_LINK_CLK,
  32	DT_DP0_PHY_PLL_VCO_DIV_CLK,
  33	DT_DP1_PHY_PLL_LINK_CLK,
  34	DT_DP1_PHY_PLL_VCO_DIV_CLK,
  35	DT_DP2_PHY_PLL_LINK_CLK,
  36	DT_DP2_PHY_PLL_VCO_DIV_CLK,
  37	DT_DP3_PHY_PLL_LINK_CLK,
  38	DT_DP3_PHY_PLL_VCO_DIV_CLK,
  39	DT_DSI0_PHY_PLL_OUT_BYTECLK,
  40	DT_DSI0_PHY_PLL_OUT_DSICLK,
  41	DT_DSI1_PHY_PLL_OUT_BYTECLK,
  42	DT_DSI1_PHY_PLL_OUT_DSICLK,
  43};
  44
  45enum {
  46	P_BI_TCXO,
  47	P_DP0_PHY_PLL_LINK_CLK,
  48	P_DP0_PHY_PLL_VCO_DIV_CLK,
  49	P_DP1_PHY_PLL_LINK_CLK,
  50	P_DP1_PHY_PLL_VCO_DIV_CLK,
  51	P_DP2_PHY_PLL_LINK_CLK,
  52	P_DP2_PHY_PLL_VCO_DIV_CLK,
  53	P_DP3_PHY_PLL_LINK_CLK,
  54	P_DP3_PHY_PLL_VCO_DIV_CLK,
  55	P_DSI0_PHY_PLL_OUT_BYTECLK,
  56	P_DSI0_PHY_PLL_OUT_DSICLK,
  57	P_DSI1_PHY_PLL_OUT_BYTECLK,
  58	P_DSI1_PHY_PLL_OUT_DSICLK,
  59	P_DISPn_CC_PLL0_OUT_MAIN,
  60	P_DISPn_CC_PLL1_OUT_EVEN,
  61	P_DISPn_CC_PLL1_OUT_MAIN,
  62	P_DISPn_CC_PLL2_OUT_MAIN,
  63	P_SLEEP_CLK,
  64};
  65
  66static const struct clk_parent_data parent_data_tcxo = { .index = DT_BI_TCXO };
  67
  68static const struct pll_vco lucid_5lpe_vco[] = {
  69	{ 249600000, 1800000000, 0 },
  70};
  71
  72static const struct alpha_pll_config disp_cc_pll0_config = {
  73	.l = 0x4e,
  74	.alpha = 0x2000,
  75	.config_ctl_val = 0x20485699,
  76	.config_ctl_hi_val = 0x00002261,
  77	.config_ctl_hi1_val = 0x2a9a699c,
  78	.test_ctl_val = 0x00000000,
  79	.test_ctl_hi_val = 0x00000000,
  80	.test_ctl_hi1_val = 0x01800000,
  81	.user_ctl_val = 0x00000000,
  82	.user_ctl_hi_val = 0x00000805,
  83	.user_ctl_hi1_val = 0x00000000,
  84};
  85
  86static struct clk_alpha_pll disp0_cc_pll0 = {
  87	.offset = 0x0,
  88	.vco_table = lucid_5lpe_vco,
  89	.num_vco = ARRAY_SIZE(lucid_5lpe_vco),
  90	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
  91	.clkr = {
  92		.hw.init = &(const struct clk_init_data) {
  93			.name = "disp0_cc_pll0",
  94			.parent_data = &parent_data_tcxo,
  95			.num_parents = 1,
  96			.ops = &clk_alpha_pll_lucid_5lpe_ops,
  97		},
  98	},
  99};
 100
 101static struct clk_alpha_pll disp1_cc_pll0 = {
 102	.offset = 0x0,
 103	.vco_table = lucid_5lpe_vco,
 104	.num_vco = ARRAY_SIZE(lucid_5lpe_vco),
 105	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
 106	.clkr = {
 107		.hw.init = &(const struct clk_init_data) {
 108			.name = "disp1_cc_pll0",
 109			.parent_data = &parent_data_tcxo,
 110			.num_parents = 1,
 111			.ops = &clk_alpha_pll_lucid_5lpe_ops,
 112		},
 113	},
 114};
 115
 116static const struct alpha_pll_config disp_cc_pll1_config = {
 117	.l = 0x1f,
 118	.alpha = 0x4000,
 119	.config_ctl_val = 0x20485699,
 120	.config_ctl_hi_val = 0x00002261,
 121	.config_ctl_hi1_val = 0x2a9a699c,
 122	.test_ctl_val = 0x00000000,
 123	.test_ctl_hi_val = 0x00000000,
 124	.test_ctl_hi1_val = 0x01800000,
 125	.user_ctl_val = 0x00000100,
 126	.user_ctl_hi_val = 0x00000805,
 127	.user_ctl_hi1_val = 0x00000000,
 128};
 129
 130static struct clk_alpha_pll disp0_cc_pll1 = {
 131	.offset = 0x1000,
 132	.vco_table = lucid_5lpe_vco,
 133	.num_vco = ARRAY_SIZE(lucid_5lpe_vco),
 134	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
 135	.clkr = {
 136		.hw.init = &(const struct clk_init_data) {
 137			.name = "disp0_cc_pll1",
 138			.parent_data = &parent_data_tcxo,
 139			.num_parents = 1,
 140			.ops = &clk_alpha_pll_lucid_5lpe_ops,
 141		},
 142	},
 143};
 144
 145static struct clk_alpha_pll disp1_cc_pll1 = {
 146	.offset = 0x1000,
 147	.vco_table = lucid_5lpe_vco,
 148	.num_vco = ARRAY_SIZE(lucid_5lpe_vco),
 149	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
 150	.clkr = {
 151		.hw.init = &(const struct clk_init_data) {
 152			.name = "disp1_cc_pll1",
 153			.parent_data = &parent_data_tcxo,
 154			.num_parents = 1,
 155			.ops = &clk_alpha_pll_lucid_5lpe_ops,
 156		},
 157	},
 158};
 159
 160static const struct clk_div_table post_div_table_disp_cc_pll1_out_even[] = {
 161	{ 0x1, 2 },
 162	{ }
 163};
 164
 165static struct clk_alpha_pll_postdiv disp0_cc_pll1_out_even = {
 166	.offset = 0x1000,
 167	.post_div_shift = 8,
 168	.post_div_table = post_div_table_disp_cc_pll1_out_even,
 169	.num_post_div = ARRAY_SIZE(post_div_table_disp_cc_pll1_out_even),
 170	.width = 4,
 171	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
 172	.clkr.hw.init = &(const struct clk_init_data) {
 173		.name = "disp0_cc_pll1_out_even",
 174		.parent_hws = (const struct clk_hw*[]){
 175			&disp0_cc_pll1.clkr.hw,
 176		},
 177		.num_parents = 1,
 178		.ops = &clk_alpha_pll_postdiv_lucid_5lpe_ops,
 179	},
 180};
 181
 182static struct clk_alpha_pll_postdiv disp1_cc_pll1_out_even = {
 183	.offset = 0x1000,
 184	.post_div_shift = 8,
 185	.post_div_table = post_div_table_disp_cc_pll1_out_even,
 186	.num_post_div = ARRAY_SIZE(post_div_table_disp_cc_pll1_out_even),
 187	.width = 4,
 188	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
 189	.clkr.hw.init = &(const struct clk_init_data) {
 190		.name = "disp1_cc_pll1_out_even",
 191		.parent_hws = (const struct clk_hw*[]){
 192			&disp1_cc_pll1.clkr.hw,
 193		},
 194		.num_parents = 1,
 195		.ops = &clk_alpha_pll_postdiv_lucid_5lpe_ops,
 196	},
 197};
 198
 199static const struct alpha_pll_config disp_cc_pll2_config = {
 200	.l = 0x46,
 201	.alpha = 0x5000,
 202	.config_ctl_val = 0x20485699,
 203	.config_ctl_hi_val = 0x00002261,
 204	.config_ctl_hi1_val = 0x2a9a699c,
 205	.test_ctl_val = 0x00000000,
 206	.test_ctl_hi_val = 0x00000000,
 207	.test_ctl_hi1_val = 0x01800000,
 208	.user_ctl_val = 0x00000000,
 209	.user_ctl_hi_val = 0x00000805,
 210	.user_ctl_hi1_val = 0x00000000,
 211};
 212
 213static struct clk_alpha_pll disp0_cc_pll2 = {
 214	.offset = 0x9000,
 215	.vco_table = lucid_5lpe_vco,
 216	.num_vco = ARRAY_SIZE(lucid_5lpe_vco),
 217	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
 218	.clkr = {
 219		.hw.init = &(const struct clk_init_data) {
 220			.name = "disp0_cc_pll2",
 221			.parent_data = &parent_data_tcxo,
 222			.num_parents = 1,
 223			.ops = &clk_alpha_pll_lucid_5lpe_ops,
 224		},
 225	},
 226};
 227
 228static struct clk_alpha_pll disp1_cc_pll2 = {
 229	.offset = 0x9000,
 230	.vco_table = lucid_5lpe_vco,
 231	.num_vco = ARRAY_SIZE(lucid_5lpe_vco),
 232	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
 233	.clkr = {
 234		.hw.init = &(const struct clk_init_data) {
 235			.name = "disp1_cc_pll2",
 236			.parent_data = &parent_data_tcxo,
 237			.num_parents = 1,
 238			.ops = &clk_alpha_pll_lucid_5lpe_ops,
 239		},
 240	},
 241};
 242
 243static const struct parent_map disp_cc_parent_map_0[] = {
 244	{ P_BI_TCXO, 0 },
 245	{ P_DP0_PHY_PLL_LINK_CLK, 1 },
 246	{ P_DP1_PHY_PLL_LINK_CLK, 2 },
 247	{ P_DP2_PHY_PLL_LINK_CLK, 3 },
 248	{ P_DP3_PHY_PLL_LINK_CLK, 4 },
 249	{ P_DISPn_CC_PLL2_OUT_MAIN, 5 },
 250};
 251
 252static const struct clk_parent_data disp0_cc_parent_data_0[] = {
 253	{ .index = DT_BI_TCXO },
 254	{ .index = DT_DP0_PHY_PLL_LINK_CLK },
 255	{ .index = DT_DP1_PHY_PLL_LINK_CLK },
 256	{ .index = DT_DP2_PHY_PLL_LINK_CLK },
 257	{ .index = DT_DP3_PHY_PLL_LINK_CLK },
 258	{ .hw = &disp0_cc_pll2.clkr.hw },
 259};
 260
 261static const struct clk_parent_data disp1_cc_parent_data_0[] = {
 262	{ .index = DT_BI_TCXO },
 263	{ .index = DT_DP0_PHY_PLL_LINK_CLK },
 264	{ .index = DT_DP1_PHY_PLL_LINK_CLK },
 265	{ .index = DT_DP2_PHY_PLL_LINK_CLK },
 266	{ .index = DT_DP3_PHY_PLL_LINK_CLK },
 267	{ .hw = &disp1_cc_pll2.clkr.hw },
 268};
 269
 270static const struct parent_map disp_cc_parent_map_1[] = {
 271	{ P_BI_TCXO, 0 },
 272	{ P_DP0_PHY_PLL_LINK_CLK, 1 },
 273	{ P_DP0_PHY_PLL_VCO_DIV_CLK, 2 },
 274	{ P_DP3_PHY_PLL_VCO_DIV_CLK, 3 },
 275	{ P_DP1_PHY_PLL_VCO_DIV_CLK, 4 },
 276	{ P_DISPn_CC_PLL2_OUT_MAIN, 5 },
 277	{ P_DP2_PHY_PLL_VCO_DIV_CLK, 6 },
 278};
 279
 280static const struct clk_parent_data disp0_cc_parent_data_1[] = {
 281	{ .index = DT_BI_TCXO },
 282	{ .index = DT_DP0_PHY_PLL_LINK_CLK },
 283	{ .index = DT_DP0_PHY_PLL_VCO_DIV_CLK },
 284	{ .index = DT_DP3_PHY_PLL_VCO_DIV_CLK },
 285	{ .index = DT_DP1_PHY_PLL_VCO_DIV_CLK },
 286	{ .hw = &disp0_cc_pll2.clkr.hw },
 287	{ .index = DT_DP2_PHY_PLL_VCO_DIV_CLK },
 288};
 289
 290static const struct clk_parent_data disp1_cc_parent_data_1[] = {
 291	{ .index = DT_BI_TCXO },
 292	{ .index = DT_DP0_PHY_PLL_LINK_CLK },
 293	{ .index = DT_DP0_PHY_PLL_VCO_DIV_CLK },
 294	{ .index = DT_DP3_PHY_PLL_VCO_DIV_CLK },
 295	{ .index = DT_DP1_PHY_PLL_VCO_DIV_CLK },
 296	{ .hw = &disp1_cc_pll2.clkr.hw },
 297	{ .index = DT_DP2_PHY_PLL_VCO_DIV_CLK },
 298};
 299
 300static const struct parent_map disp_cc_parent_map_2[] = {
 301	{ P_BI_TCXO, 0 },
 302};
 303
 304static const struct clk_parent_data disp_cc_parent_data_2[] = {
 305	{ .index = DT_BI_TCXO },
 306};
 307
 308static const struct parent_map disp_cc_parent_map_3[] = {
 309	{ P_BI_TCXO, 0 },
 310	{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
 311	{ P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
 312	{ P_DSI1_PHY_PLL_OUT_DSICLK, 3 },
 313	{ P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },
 314};
 315
 316static const struct clk_parent_data disp_cc_parent_data_3[] = {
 317	{ .index = DT_BI_TCXO },
 318	{ .index = DT_DSI0_PHY_PLL_OUT_DSICLK },
 319	{ .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
 320	{ .index = DT_DSI1_PHY_PLL_OUT_DSICLK },
 321	{ .index = DT_DSI1_PHY_PLL_OUT_BYTECLK },
 322};
 323
 324static const struct parent_map disp_cc_parent_map_4[] = {
 325	{ P_BI_TCXO, 0 },
 326	{ P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
 327	{ P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },
 328};
 329
 330static const struct clk_parent_data disp_cc_parent_data_4[] = {
 331	{ .index = DT_BI_TCXO },
 332	{ .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
 333	{ .index = DT_DSI1_PHY_PLL_OUT_BYTECLK },
 334};
 335
 336static const struct parent_map disp_cc_parent_map_5[] = {
 337	{ P_BI_TCXO, 0 },
 338	{ P_DISPn_CC_PLL0_OUT_MAIN, 1 },
 339	{ P_DISPn_CC_PLL1_OUT_MAIN, 4 },
 340	{ P_DISPn_CC_PLL2_OUT_MAIN, 5 },
 341	{ P_DISPn_CC_PLL1_OUT_EVEN, 6 },
 342};
 343
 344static const struct clk_parent_data disp0_cc_parent_data_5[] = {
 345	{ .index = DT_BI_TCXO },
 346	{ .hw = &disp0_cc_pll0.clkr.hw },
 347	{ .hw = &disp0_cc_pll1.clkr.hw },
 348	{ .hw = &disp0_cc_pll2.clkr.hw },
 349	{ .hw = &disp0_cc_pll1_out_even.clkr.hw },
 350};
 351
 352static const struct clk_parent_data disp1_cc_parent_data_5[] = {
 353	{ .index = DT_BI_TCXO },
 354	{ .hw = &disp1_cc_pll0.clkr.hw },
 355	{ .hw = &disp1_cc_pll1.clkr.hw },
 356	{ .hw = &disp1_cc_pll2.clkr.hw },
 357	{ .hw = &disp1_cc_pll1_out_even.clkr.hw },
 358};
 359
 360static const struct parent_map disp_cc_parent_map_6[] = {
 361	{ P_BI_TCXO, 0 },
 362	{ P_DISPn_CC_PLL1_OUT_MAIN, 4 },
 363	{ P_DISPn_CC_PLL1_OUT_EVEN, 6 },
 364};
 365
 366static const struct clk_parent_data disp0_cc_parent_data_6[] = {
 367	{ .index = DT_BI_TCXO },
 368	{ .hw = &disp0_cc_pll1.clkr.hw },
 369	{ .hw = &disp0_cc_pll1_out_even.clkr.hw },
 370};
 371
 372static const struct clk_parent_data disp1_cc_parent_data_6[] = {
 373	{ .index = DT_BI_TCXO },
 374	{ .hw = &disp1_cc_pll1.clkr.hw },
 375	{ .hw = &disp1_cc_pll1_out_even.clkr.hw },
 376};
 377
 378static const struct parent_map disp_cc_parent_map_7[] = {
 379	{ P_SLEEP_CLK, 0 },
 380};
 381
 382static const struct clk_parent_data disp_cc_parent_data_7[] = {
 383	{ .index = DT_SLEEP_CLK },
 384};
 385
 386static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
 387	F(19200000, P_BI_TCXO, 1, 0, 0),
 388	F(37500000, P_DISPn_CC_PLL1_OUT_EVEN, 8, 0, 0),
 389	F(75000000, P_DISPn_CC_PLL1_OUT_MAIN, 8, 0, 0),
 390	{ }
 391};
 392
 393static struct clk_rcg2 disp0_cc_mdss_ahb_clk_src = {
 394	.cmd_rcgr = 0x2364,
 395	.mnd_width = 0,
 396	.hid_width = 5,
 397	.parent_map = disp_cc_parent_map_6,
 398	.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
 399	.clkr.hw.init = &(const struct clk_init_data) {
 400		.name = "disp0_cc_mdss_ahb_clk_src",
 401		.parent_data = disp0_cc_parent_data_6,
 402		.num_parents = ARRAY_SIZE(disp0_cc_parent_data_6),
 403		.ops = &clk_rcg2_shared_ops,
 404	},
 405};
 406
 407static struct clk_rcg2 disp1_cc_mdss_ahb_clk_src = {
 408	.cmd_rcgr = 0x2364,
 409	.mnd_width = 0,
 410	.hid_width = 5,
 411	.parent_map = disp_cc_parent_map_6,
 412	.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
 413	.clkr.hw.init = &(const struct clk_init_data) {
 414		.name = "disp1_cc_mdss_ahb_clk_src",
 415		.parent_data = disp1_cc_parent_data_6,
 416		.num_parents = ARRAY_SIZE(disp1_cc_parent_data_6),
 417		.ops = &clk_rcg2_shared_ops,
 418	},
 419};
 420
 421static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = {
 422	F(19200000, P_BI_TCXO, 1, 0, 0),
 423	{ }
 424};
 425
 426static struct clk_rcg2 disp0_cc_mdss_byte0_clk_src = {
 427	.cmd_rcgr = 0x213c,
 428	.mnd_width = 0,
 429	.hid_width = 5,
 430	.parent_map = disp_cc_parent_map_3,
 431	.clkr.hw.init = &(const struct clk_init_data) {
 432		.name = "disp0_cc_mdss_byte0_clk_src",
 433		.parent_data = disp_cc_parent_data_3,
 434		.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
 435		.flags = CLK_SET_RATE_PARENT,
 436		.ops = &clk_byte2_ops,
 437	},
 438};
 439
 440static struct clk_rcg2 disp1_cc_mdss_byte0_clk_src = {
 441	.cmd_rcgr = 0x213c,
 442	.mnd_width = 0,
 443	.hid_width = 5,
 444	.parent_map = disp_cc_parent_map_3,
 445	.clkr.hw.init = &(const struct clk_init_data) {
 446		.name = "disp1_cc_mdss_byte0_clk_src",
 447		.parent_data = disp_cc_parent_data_3,
 448		.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
 449		.flags = CLK_SET_RATE_PARENT,
 450		.ops = &clk_byte2_ops,
 451	},
 452};
 453
 454static struct clk_rcg2 disp0_cc_mdss_byte1_clk_src = {
 455	.cmd_rcgr = 0x2158,
 456	.mnd_width = 0,
 457	.hid_width = 5,
 458	.parent_map = disp_cc_parent_map_3,
 459	.clkr.hw.init = &(const struct clk_init_data) {
 460		.name = "disp0_cc_mdss_byte1_clk_src",
 461		.parent_data = disp_cc_parent_data_3,
 462		.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
 463		.flags = CLK_SET_RATE_PARENT,
 464		.ops = &clk_byte2_ops,
 465	},
 466};
 467
 468static struct clk_rcg2 disp1_cc_mdss_byte1_clk_src = {
 469	.cmd_rcgr = 0x2158,
 470	.mnd_width = 0,
 471	.hid_width = 5,
 472	.parent_map = disp_cc_parent_map_3,
 473	.clkr.hw.init = &(const struct clk_init_data) {
 474		.name = "disp1_cc_mdss_byte1_clk_src",
 475		.parent_data = disp_cc_parent_data_3,
 476		.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
 477		.flags = CLK_SET_RATE_PARENT,
 478		.ops = &clk_byte2_ops,
 479	},
 480};
 481
 482static struct clk_rcg2 disp0_cc_mdss_dptx0_aux_clk_src = {
 483	.cmd_rcgr = 0x2238,
 484	.mnd_width = 0,
 485	.hid_width = 5,
 486	.parent_map = disp_cc_parent_map_2,
 487	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 488	.clkr.hw.init = &(const struct clk_init_data) {
 489		.name = "disp0_cc_mdss_dptx0_aux_clk_src",
 490		.parent_data = disp_cc_parent_data_2,
 491		.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
 492		.ops = &clk_rcg2_ops,
 493	},
 494};
 495
 496static struct clk_rcg2 disp1_cc_mdss_dptx0_aux_clk_src = {
 497	.cmd_rcgr = 0x2238,
 498	.mnd_width = 0,
 499	.hid_width = 5,
 500	.parent_map = disp_cc_parent_map_2,
 501	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 502	.clkr.hw.init = &(const struct clk_init_data) {
 503		.name = "disp1_cc_mdss_dptx0_aux_clk_src",
 504		.parent_data = disp_cc_parent_data_2,
 505		.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
 506		.ops = &clk_rcg2_ops,
 507	},
 508};
 509
 510static struct clk_rcg2 disp0_cc_mdss_dptx0_link_clk_src = {
 511	.cmd_rcgr = 0x21a4,
 512	.mnd_width = 0,
 513	.hid_width = 5,
 514	.parent_map = disp_cc_parent_map_0,
 515	.clkr.hw.init = &(const struct clk_init_data) {
 516		.name = "disp0_cc_mdss_dptx0_link_clk_src",
 517		.parent_data = disp0_cc_parent_data_0,
 518		.num_parents = ARRAY_SIZE(disp0_cc_parent_data_0),
 519		.flags = CLK_SET_RATE_PARENT,
 520		.ops = &clk_byte2_ops,
 521	},
 522};
 523
 524static struct clk_rcg2 disp1_cc_mdss_dptx0_link_clk_src = {
 525	.cmd_rcgr = 0x21a4,
 526	.mnd_width = 0,
 527	.hid_width = 5,
 528	.parent_map = disp_cc_parent_map_0,
 529	.clkr.hw.init = &(const struct clk_init_data) {
 530		.name = "disp1_cc_mdss_dptx0_link_clk_src",
 531		.parent_data = disp1_cc_parent_data_0,
 532		.num_parents = ARRAY_SIZE(disp1_cc_parent_data_0),
 533		.flags = CLK_SET_RATE_PARENT,
 534		.ops = &clk_byte2_ops,
 535	},
 536};
 537
 538static struct clk_rcg2 disp0_cc_mdss_dptx0_pixel0_clk_src = {
 539	.cmd_rcgr = 0x21d8,
 540	.mnd_width = 16,
 541	.hid_width = 5,
 542	.parent_map = disp_cc_parent_map_1,
 543	.clkr.hw.init = &(const struct clk_init_data) {
 544		.name = "disp0_cc_mdss_dptx0_pixel0_clk_src",
 545		.parent_data = disp0_cc_parent_data_1,
 546		.num_parents = ARRAY_SIZE(disp0_cc_parent_data_1),
 547		.flags = CLK_SET_RATE_PARENT,
 548		.ops = &clk_dp_ops,
 549	},
 550};
 551
 552static struct clk_rcg2 disp1_cc_mdss_dptx0_pixel0_clk_src = {
 553	.cmd_rcgr = 0x21d8,
 554	.mnd_width = 16,
 555	.hid_width = 5,
 556	.parent_map = disp_cc_parent_map_1,
 557	.clkr.hw.init = &(const struct clk_init_data) {
 558		.name = "disp1_cc_mdss_dptx0_pixel0_clk_src",
 559		.parent_data = disp1_cc_parent_data_1,
 560		.num_parents = ARRAY_SIZE(disp1_cc_parent_data_1),
 561		.flags = CLK_SET_RATE_PARENT,
 562		.ops = &clk_dp_ops,
 563	},
 564};
 565
 566static struct clk_rcg2 disp0_cc_mdss_dptx0_pixel1_clk_src = {
 567	.cmd_rcgr = 0x21f0,
 568	.mnd_width = 16,
 569	.hid_width = 5,
 570	.parent_map = disp_cc_parent_map_1,
 571	.clkr.hw.init = &(const struct clk_init_data) {
 572		.name = "disp0_cc_mdss_dptx0_pixel1_clk_src",
 573		.parent_data = disp0_cc_parent_data_1,
 574		.num_parents = ARRAY_SIZE(disp0_cc_parent_data_1),
 575		.flags = CLK_SET_RATE_PARENT,
 576		.ops = &clk_dp_ops,
 577	},
 578};
 579
 580static struct clk_rcg2 disp1_cc_mdss_dptx0_pixel1_clk_src = {
 581	.cmd_rcgr = 0x21f0,
 582	.mnd_width = 16,
 583	.hid_width = 5,
 584	.parent_map = disp_cc_parent_map_1,
 585	.clkr.hw.init = &(const struct clk_init_data) {
 586		.name = "disp1_cc_mdss_dptx0_pixel1_clk_src",
 587		.parent_data = disp1_cc_parent_data_1,
 588		.num_parents = ARRAY_SIZE(disp1_cc_parent_data_1),
 589		.flags = CLK_SET_RATE_PARENT,
 590		.ops = &clk_dp_ops,
 591	},
 592};
 593
 594static struct clk_rcg2 disp0_cc_mdss_dptx1_aux_clk_src = {
 595	.cmd_rcgr = 0x22d0,
 596	.mnd_width = 0,
 597	.hid_width = 5,
 598	.parent_map = disp_cc_parent_map_2,
 599	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 600	.clkr.hw.init = &(const struct clk_init_data) {
 601		.name = "disp0_cc_mdss_dptx1_aux_clk_src",
 602		.parent_data = disp_cc_parent_data_2,
 603		.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
 604		.ops = &clk_rcg2_ops,
 605	},
 606};
 607
 608static struct clk_rcg2 disp1_cc_mdss_dptx1_aux_clk_src = {
 609	.cmd_rcgr = 0x22d0,
 610	.mnd_width = 0,
 611	.hid_width = 5,
 612	.parent_map = disp_cc_parent_map_2,
 613	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 614	.clkr.hw.init = &(const struct clk_init_data) {
 615		.name = "disp1_cc_mdss_dptx1_aux_clk_src",
 616		.parent_data = disp_cc_parent_data_2,
 617		.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
 618		.ops = &clk_rcg2_ops,
 619	},
 620};
 621
 622static struct clk_rcg2 disp0_cc_mdss_dptx1_link_clk_src = {
 623	.cmd_rcgr = 0x2268,
 624	.mnd_width = 0,
 625	.hid_width = 5,
 626	.parent_map = disp_cc_parent_map_0,
 627	.clkr.hw.init = &(const struct clk_init_data) {
 628		.name = "disp0_cc_mdss_dptx1_link_clk_src",
 629		.parent_data = disp0_cc_parent_data_0,
 630		.num_parents = ARRAY_SIZE(disp0_cc_parent_data_0),
 631		.flags = CLK_SET_RATE_PARENT,
 632		.ops = &clk_byte2_ops,
 633	},
 634};
 635
 636static struct clk_rcg2 disp1_cc_mdss_dptx1_link_clk_src = {
 637	.cmd_rcgr = 0x2268,
 638	.mnd_width = 0,
 639	.hid_width = 5,
 640	.parent_map = disp_cc_parent_map_0,
 641	.clkr.hw.init = &(const struct clk_init_data) {
 642		.name = "disp1_cc_mdss_dptx1_link_clk_src",
 643		.parent_data = disp1_cc_parent_data_0,
 644		.num_parents = ARRAY_SIZE(disp1_cc_parent_data_0),
 645		.flags = CLK_SET_RATE_PARENT,
 646		.ops = &clk_byte2_ops,
 647	},
 648};
 649
 650static struct clk_rcg2 disp0_cc_mdss_dptx1_pixel0_clk_src = {
 651	.cmd_rcgr = 0x2250,
 652	.mnd_width = 16,
 653	.hid_width = 5,
 654	.parent_map = disp_cc_parent_map_1,
 655	.clkr.hw.init = &(const struct clk_init_data) {
 656		.name = "disp0_cc_mdss_dptx1_pixel0_clk_src",
 657		.parent_data = disp0_cc_parent_data_1,
 658		.num_parents = ARRAY_SIZE(disp0_cc_parent_data_1),
 659		.flags = CLK_SET_RATE_PARENT,
 660		.ops = &clk_dp_ops,
 661	},
 662};
 663
 664static struct clk_rcg2 disp1_cc_mdss_dptx1_pixel0_clk_src = {
 665	.cmd_rcgr = 0x2250,
 666	.mnd_width = 16,
 667	.hid_width = 5,
 668	.parent_map = disp_cc_parent_map_1,
 669	.clkr.hw.init = &(const struct clk_init_data) {
 670		.name = "disp1_cc_mdss_dptx1_pixel0_clk_src",
 671		.parent_data = disp1_cc_parent_data_1,
 672		.num_parents = ARRAY_SIZE(disp1_cc_parent_data_1),
 673		.flags = CLK_SET_RATE_PARENT,
 674		.ops = &clk_dp_ops,
 675	},
 676};
 677
 678static struct clk_rcg2 disp0_cc_mdss_dptx1_pixel1_clk_src = {
 679	.cmd_rcgr = 0x2370,
 680	.mnd_width = 16,
 681	.hid_width = 5,
 682	.parent_map = disp_cc_parent_map_1,
 683	.clkr.hw.init = &(const struct clk_init_data) {
 684		.name = "disp0_cc_mdss_dptx1_pixel1_clk_src",
 685		.parent_data = disp0_cc_parent_data_1,
 686		.num_parents = ARRAY_SIZE(disp0_cc_parent_data_1),
 687		.flags = CLK_SET_RATE_PARENT,
 688		.ops = &clk_dp_ops,
 689	},
 690};
 691
 692static struct clk_rcg2 disp1_cc_mdss_dptx1_pixel1_clk_src = {
 693	.cmd_rcgr = 0x2370,
 694	.mnd_width = 16,
 695	.hid_width = 5,
 696	.parent_map = disp_cc_parent_map_1,
 697	.clkr.hw.init = &(const struct clk_init_data) {
 698		.name = "disp1_cc_mdss_dptx1_pixel1_clk_src",
 699		.parent_data = disp1_cc_parent_data_1,
 700		.num_parents = ARRAY_SIZE(disp1_cc_parent_data_1),
 701		.flags = CLK_SET_RATE_PARENT,
 702		.ops = &clk_dp_ops,
 703	},
 704};
 705
 706static struct clk_rcg2 disp0_cc_mdss_dptx2_aux_clk_src = {
 707	.cmd_rcgr = 0x22e8,
 708	.mnd_width = 0,
 709	.hid_width = 5,
 710	.parent_map = disp_cc_parent_map_2,
 711	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 712	.clkr.hw.init = &(const struct clk_init_data) {
 713		.name = "disp0_cc_mdss_dptx2_aux_clk_src",
 714		.parent_data = disp_cc_parent_data_2,
 715		.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
 716		.ops = &clk_rcg2_ops,
 717	},
 718};
 719
 720static struct clk_rcg2 disp1_cc_mdss_dptx2_aux_clk_src = {
 721	.cmd_rcgr = 0x22e8,
 722	.mnd_width = 0,
 723	.hid_width = 5,
 724	.parent_map = disp_cc_parent_map_2,
 725	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 726	.clkr.hw.init = &(const struct clk_init_data) {
 727		.name = "disp1_cc_mdss_dptx2_aux_clk_src",
 728		.parent_data = disp_cc_parent_data_2,
 729		.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
 730		.ops = &clk_rcg2_ops,
 731	},
 732};
 733
 734static struct clk_rcg2 disp0_cc_mdss_dptx2_link_clk_src = {
 735	.cmd_rcgr = 0x2284,
 736	.mnd_width = 0,
 737	.hid_width = 5,
 738	.parent_map = disp_cc_parent_map_0,
 739	.clkr.hw.init = &(const struct clk_init_data) {
 740		.name = "disp0_cc_mdss_dptx2_link_clk_src",
 741		.parent_data = disp0_cc_parent_data_0,
 742		.num_parents = ARRAY_SIZE(disp0_cc_parent_data_0),
 743		.flags = CLK_SET_RATE_PARENT,
 744		.ops = &clk_byte2_ops,
 745	},
 746};
 747
 748static struct clk_rcg2 disp1_cc_mdss_dptx2_link_clk_src = {
 749	.cmd_rcgr = 0x2284,
 750	.mnd_width = 0,
 751	.hid_width = 5,
 752	.parent_map = disp_cc_parent_map_0,
 753	.clkr.hw.init = &(const struct clk_init_data) {
 754		.name = "disp1_cc_mdss_dptx2_link_clk_src",
 755		.parent_data = disp1_cc_parent_data_0,
 756		.num_parents = ARRAY_SIZE(disp1_cc_parent_data_0),
 757		.flags = CLK_SET_RATE_PARENT,
 758		.ops = &clk_byte2_ops,
 759	},
 760};
 761
 762static struct clk_rcg2 disp0_cc_mdss_dptx2_pixel0_clk_src = {
 763	.cmd_rcgr = 0x2208,
 764	.mnd_width = 16,
 765	.hid_width = 5,
 766	.parent_map = disp_cc_parent_map_1,
 767	.clkr.hw.init = &(const struct clk_init_data) {
 768		.name = "disp0_cc_mdss_dptx2_pixel0_clk_src",
 769		.parent_data = disp0_cc_parent_data_1,
 770		.num_parents = ARRAY_SIZE(disp0_cc_parent_data_1),
 771		.flags = CLK_SET_RATE_PARENT,
 772		.ops = &clk_dp_ops,
 773	},
 774};
 775
 776static struct clk_rcg2 disp1_cc_mdss_dptx2_pixel0_clk_src = {
 777	.cmd_rcgr = 0x2208,
 778	.mnd_width = 16,
 779	.hid_width = 5,
 780	.parent_map = disp_cc_parent_map_1,
 781	.clkr.hw.init = &(const struct clk_init_data) {
 782		.name = "disp1_cc_mdss_dptx2_pixel0_clk_src",
 783		.parent_data = disp1_cc_parent_data_1,
 784		.num_parents = ARRAY_SIZE(disp1_cc_parent_data_1),
 785		.flags = CLK_SET_RATE_PARENT,
 786		.ops = &clk_dp_ops,
 787	},
 788};
 789
 790static struct clk_rcg2 disp0_cc_mdss_dptx2_pixel1_clk_src = {
 791	.cmd_rcgr = 0x2220,
 792	.mnd_width = 16,
 793	.hid_width = 5,
 794	.parent_map = disp_cc_parent_map_1,
 795	.clkr.hw.init = &(const struct clk_init_data) {
 796		.name = "disp0_cc_mdss_dptx2_pixel1_clk_src",
 797		.parent_data = disp0_cc_parent_data_1,
 798		.num_parents = ARRAY_SIZE(disp0_cc_parent_data_1),
 799		.flags = CLK_SET_RATE_PARENT,
 800		.ops = &clk_dp_ops,
 801	},
 802};
 803
 804static struct clk_rcg2 disp1_cc_mdss_dptx2_pixel1_clk_src = {
 805	.cmd_rcgr = 0x2220,
 806	.mnd_width = 16,
 807	.hid_width = 5,
 808	.parent_map = disp_cc_parent_map_1,
 809	.clkr.hw.init = &(const struct clk_init_data) {
 810		.name = "disp1_cc_mdss_dptx2_pixel1_clk_src",
 811		.parent_data = disp1_cc_parent_data_1,
 812		.num_parents = ARRAY_SIZE(disp1_cc_parent_data_1),
 813		.flags = CLK_SET_RATE_PARENT,
 814		.ops = &clk_dp_ops,
 815	},
 816};
 817
 818static struct clk_rcg2 disp0_cc_mdss_dptx3_aux_clk_src = {
 819	.cmd_rcgr = 0x234c,
 820	.mnd_width = 0,
 821	.hid_width = 5,
 822	.parent_map = disp_cc_parent_map_2,
 823	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 824	.clkr.hw.init = &(const struct clk_init_data) {
 825		.name = "disp0_cc_mdss_dptx3_aux_clk_src",
 826		.parent_data = disp_cc_parent_data_2,
 827		.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
 828		.ops = &clk_rcg2_ops,
 829	},
 830};
 831
 832static struct clk_rcg2 disp1_cc_mdss_dptx3_aux_clk_src = {
 833	.cmd_rcgr = 0x234c,
 834	.mnd_width = 0,
 835	.hid_width = 5,
 836	.parent_map = disp_cc_parent_map_2,
 837	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 838	.clkr.hw.init = &(const struct clk_init_data) {
 839		.name = "disp1_cc_mdss_dptx3_aux_clk_src",
 840		.parent_data = disp_cc_parent_data_2,
 841		.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
 842		.ops = &clk_rcg2_ops,
 843	},
 844};
 845
 846static struct clk_rcg2 disp0_cc_mdss_dptx3_link_clk_src = {
 847	.cmd_rcgr = 0x2318,
 848	.mnd_width = 0,
 849	.hid_width = 5,
 850	.parent_map = disp_cc_parent_map_0,
 851	.clkr.hw.init = &(const struct clk_init_data) {
 852		.name = "disp0_cc_mdss_dptx3_link_clk_src",
 853		.parent_data = disp0_cc_parent_data_0,
 854		.num_parents = ARRAY_SIZE(disp0_cc_parent_data_0),
 855		.flags = CLK_SET_RATE_PARENT,
 856		.ops = &clk_byte2_ops,
 857	},
 858};
 859
 860static struct clk_rcg2 disp1_cc_mdss_dptx3_link_clk_src = {
 861	.cmd_rcgr = 0x2318,
 862	.mnd_width = 0,
 863	.hid_width = 5,
 864	.parent_map = disp_cc_parent_map_0,
 865	.clkr.hw.init = &(const struct clk_init_data) {
 866		.name = "disp1_cc_mdss_dptx3_link_clk_src",
 867		.parent_data = disp1_cc_parent_data_0,
 868		.num_parents = ARRAY_SIZE(disp1_cc_parent_data_0),
 869		.flags = CLK_SET_RATE_PARENT,
 870		.ops = &clk_byte2_ops,
 871	},
 872};
 873
 874static struct clk_rcg2 disp0_cc_mdss_dptx3_pixel0_clk_src = {
 875	.cmd_rcgr = 0x2300,
 876	.mnd_width = 16,
 877	.hid_width = 5,
 878	.parent_map = disp_cc_parent_map_1,
 879	.clkr.hw.init = &(const struct clk_init_data) {
 880		.name = "disp0_cc_mdss_dptx3_pixel0_clk_src",
 881		.parent_data = disp0_cc_parent_data_1,
 882		.num_parents = ARRAY_SIZE(disp0_cc_parent_data_1),
 883		.flags = CLK_SET_RATE_PARENT,
 884		.ops = &clk_dp_ops,
 885	},
 886};
 887
 888static struct clk_rcg2 disp1_cc_mdss_dptx3_pixel0_clk_src = {
 889	.cmd_rcgr = 0x2300,
 890	.mnd_width = 16,
 891	.hid_width = 5,
 892	.parent_map = disp_cc_parent_map_1,
 893	.clkr.hw.init = &(const struct clk_init_data) {
 894		.name = "disp1_cc_mdss_dptx3_pixel0_clk_src",
 895		.parent_data = disp1_cc_parent_data_1,
 896		.num_parents = ARRAY_SIZE(disp1_cc_parent_data_1),
 897		.flags = CLK_SET_RATE_PARENT,
 898		.ops = &clk_dp_ops,
 899	},
 900};
 901
 902static struct clk_rcg2 disp0_cc_mdss_esc0_clk_src = {
 903	.cmd_rcgr = 0x2174,
 904	.mnd_width = 0,
 905	.hid_width = 5,
 906	.parent_map = disp_cc_parent_map_4,
 907	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 908	.clkr.hw.init = &(const struct clk_init_data) {
 909		.name = "disp0_cc_mdss_esc0_clk_src",
 910		.parent_data = disp_cc_parent_data_4,
 911		.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
 912		.ops = &clk_rcg2_ops,
 913	},
 914};
 915
 916static struct clk_rcg2 disp1_cc_mdss_esc0_clk_src = {
 917	.cmd_rcgr = 0x2174,
 918	.mnd_width = 0,
 919	.hid_width = 5,
 920	.parent_map = disp_cc_parent_map_4,
 921	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 922	.clkr.hw.init = &(const struct clk_init_data) {
 923		.name = "disp1_cc_mdss_esc0_clk_src",
 924		.parent_data = disp_cc_parent_data_4,
 925		.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
 926		.ops = &clk_rcg2_ops,
 927	},
 928};
 929
 930static struct clk_rcg2 disp0_cc_mdss_esc1_clk_src = {
 931	.cmd_rcgr = 0x218c,
 932	.mnd_width = 0,
 933	.hid_width = 5,
 934	.parent_map = disp_cc_parent_map_4,
 935	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 936	.clkr.hw.init = &(const struct clk_init_data) {
 937		.name = "disp0_cc_mdss_esc1_clk_src",
 938		.parent_data = disp_cc_parent_data_4,
 939		.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
 940		.ops = &clk_rcg2_ops,
 941	},
 942};
 943
 944static struct clk_rcg2 disp1_cc_mdss_esc1_clk_src = {
 945	.cmd_rcgr = 0x218c,
 946	.mnd_width = 0,
 947	.hid_width = 5,
 948	.parent_map = disp_cc_parent_map_4,
 949	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 950	.clkr.hw.init = &(const struct clk_init_data) {
 951		.name = "disp1_cc_mdss_esc1_clk_src",
 952		.parent_data = disp_cc_parent_data_4,
 953		.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
 954		.ops = &clk_rcg2_ops,
 955	},
 956};
 957
 958static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
 959	F(19200000, P_BI_TCXO, 1, 0, 0),
 960	F(85714286, P_DISPn_CC_PLL1_OUT_MAIN, 7, 0, 0),
 961	F(100000000, P_DISPn_CC_PLL1_OUT_MAIN, 6, 0, 0),
 962	F(150000000, P_DISPn_CC_PLL1_OUT_MAIN, 4, 0, 0),
 963	F(200000000, P_DISPn_CC_PLL1_OUT_MAIN, 3, 0, 0),
 964	F(300000000, P_DISPn_CC_PLL1_OUT_MAIN, 2, 0, 0),
 965	F(375000000, P_DISPn_CC_PLL0_OUT_MAIN, 4, 0, 0),
 966	F(500000000, P_DISPn_CC_PLL0_OUT_MAIN, 3, 0, 0),
 967	F(600000000, P_DISPn_CC_PLL1_OUT_MAIN, 1, 0, 0),
 968	{ }
 969};
 970
 971static struct clk_rcg2 disp0_cc_mdss_mdp_clk_src = {
 972	.cmd_rcgr = 0x20f4,
 973	.mnd_width = 0,
 974	.hid_width = 5,
 975	.parent_map = disp_cc_parent_map_5,
 976	.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
 977	.clkr.hw.init = &(const struct clk_init_data) {
 978		.name = "disp0_cc_mdss_mdp_clk_src",
 979		.parent_data = disp0_cc_parent_data_5,
 980		.num_parents = ARRAY_SIZE(disp0_cc_parent_data_5),
 981		.ops = &clk_rcg2_shared_ops,
 982	},
 983};
 984
 985static struct clk_rcg2 disp1_cc_mdss_mdp_clk_src = {
 986	.cmd_rcgr = 0x20f4,
 987	.mnd_width = 0,
 988	.hid_width = 5,
 989	.parent_map = disp_cc_parent_map_5,
 990	.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
 991	.clkr.hw.init = &(const struct clk_init_data) {
 992		.name = "disp1_cc_mdss_mdp_clk_src",
 993		.parent_data = disp1_cc_parent_data_5,
 994		.num_parents = ARRAY_SIZE(disp1_cc_parent_data_5),
 995		.ops = &clk_rcg2_shared_ops,
 996	},
 997};
 998
 999static struct clk_rcg2 disp0_cc_mdss_pclk0_clk_src = {
1000	.cmd_rcgr = 0x20c4,
1001	.mnd_width = 8,
1002	.hid_width = 5,
1003	.parent_map = disp_cc_parent_map_3,
1004	.clkr.hw.init = &(const struct clk_init_data) {
1005		.name = "disp0_cc_mdss_pclk0_clk_src",
1006		.parent_data = disp_cc_parent_data_3,
1007		.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
1008		.flags = CLK_SET_RATE_PARENT,
1009		.ops = &clk_pixel_ops,
1010	},
1011};
1012
1013static struct clk_rcg2 disp1_cc_mdss_pclk0_clk_src = {
1014	.cmd_rcgr = 0x20c4,
1015	.mnd_width = 8,
1016	.hid_width = 5,
1017	.parent_map = disp_cc_parent_map_3,
1018	.clkr.hw.init = &(const struct clk_init_data) {
1019		.name = "disp1_cc_mdss_pclk0_clk_src",
1020		.parent_data = disp_cc_parent_data_3,
1021		.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
1022		.flags = CLK_SET_RATE_PARENT,
1023		.ops = &clk_pixel_ops,
1024	},
1025};
1026
1027static struct clk_rcg2 disp0_cc_mdss_pclk1_clk_src = {
1028	.cmd_rcgr = 0x20dc,
1029	.mnd_width = 8,
1030	.hid_width = 5,
1031	.parent_map = disp_cc_parent_map_3,
1032	.clkr.hw.init = &(const struct clk_init_data) {
1033		.name = "disp0_cc_mdss_pclk1_clk_src",
1034		.parent_data = disp_cc_parent_data_3,
1035		.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
1036		.flags = CLK_SET_RATE_PARENT,
1037		.ops = &clk_pixel_ops,
1038	},
1039};
1040
1041static struct clk_rcg2 disp1_cc_mdss_pclk1_clk_src = {
1042	.cmd_rcgr = 0x20dc,
1043	.mnd_width = 8,
1044	.hid_width = 5,
1045	.parent_map = disp_cc_parent_map_3,
1046	.clkr.hw.init = &(const struct clk_init_data) {
1047		.name = "disp1_cc_mdss_pclk1_clk_src",
1048		.parent_data = disp_cc_parent_data_3,
1049		.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
1050		.flags = CLK_SET_RATE_PARENT,
1051		.ops = &clk_pixel_ops,
1052	},
1053};
1054
1055static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = {
1056	F(19200000, P_BI_TCXO, 1, 0, 0),
1057	F(200000000, P_DISPn_CC_PLL1_OUT_MAIN, 3, 0, 0),
1058	F(300000000, P_DISPn_CC_PLL1_OUT_MAIN, 2, 0, 0),
1059	F(375000000, P_DISPn_CC_PLL0_OUT_MAIN, 4, 0, 0),
1060	F(500000000, P_DISPn_CC_PLL0_OUT_MAIN, 3, 0, 0),
1061	F(600000000, P_DISPn_CC_PLL1_OUT_MAIN, 1, 0, 0),
1062	{ }
1063};
1064
1065static struct clk_rcg2 disp0_cc_mdss_rot_clk_src = {
1066	.cmd_rcgr = 0x210c,
1067	.mnd_width = 0,
1068	.hid_width = 5,
1069	.parent_map = disp_cc_parent_map_5,
1070	.freq_tbl = ftbl_disp_cc_mdss_rot_clk_src,
1071	.clkr.hw.init = &(const struct clk_init_data) {
1072		.name = "disp0_cc_mdss_rot_clk_src",
1073		.parent_data = disp0_cc_parent_data_5,
1074		.num_parents = ARRAY_SIZE(disp0_cc_parent_data_5),
1075		.ops = &clk_rcg2_shared_ops,
1076	},
1077};
1078
1079static struct clk_rcg2 disp1_cc_mdss_rot_clk_src = {
1080	.cmd_rcgr = 0x210c,
1081	.mnd_width = 0,
1082	.hid_width = 5,
1083	.parent_map = disp_cc_parent_map_5,
1084	.freq_tbl = ftbl_disp_cc_mdss_rot_clk_src,
1085	.clkr.hw.init = &(const struct clk_init_data) {
1086		.name = "disp1_cc_mdss_rot_clk_src",
1087		.parent_data = disp1_cc_parent_data_5,
1088		.num_parents = ARRAY_SIZE(disp1_cc_parent_data_5),
1089		.ops = &clk_rcg2_shared_ops,
1090	},
1091};
1092
1093static struct clk_rcg2 disp0_cc_mdss_vsync_clk_src = {
1094	.cmd_rcgr = 0x2124,
1095	.mnd_width = 0,
1096	.hid_width = 5,
1097	.parent_map = disp_cc_parent_map_2,
1098	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
1099	.clkr.hw.init = &(const struct clk_init_data) {
1100		.name = "disp0_cc_mdss_vsync_clk_src",
1101		.parent_data = disp_cc_parent_data_2,
1102		.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
1103		.ops = &clk_rcg2_ops,
1104	},
1105};
1106
1107static struct clk_rcg2 disp1_cc_mdss_vsync_clk_src = {
1108	.cmd_rcgr = 0x2124,
1109	.mnd_width = 0,
1110	.hid_width = 5,
1111	.parent_map = disp_cc_parent_map_2,
1112	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
1113	.clkr.hw.init = &(const struct clk_init_data) {
1114		.name = "disp1_cc_mdss_vsync_clk_src",
1115		.parent_data = disp_cc_parent_data_2,
1116		.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
1117		.ops = &clk_rcg2_ops,
1118	},
1119};
1120
1121static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = {
1122	F(32000, P_SLEEP_CLK, 1, 0, 0),
1123	{ }
1124};
1125
1126static struct clk_rcg2 disp0_cc_sleep_clk_src = {
1127	.cmd_rcgr = 0x6060,
1128	.mnd_width = 0,
1129	.hid_width = 5,
1130	.parent_map = disp_cc_parent_map_7,
1131	.freq_tbl = ftbl_disp_cc_sleep_clk_src,
1132	.clkr.hw.init = &(const struct clk_init_data) {
1133		.name = "disp0_cc_sleep_clk_src",
1134		.parent_data = disp_cc_parent_data_7,
1135		.num_parents = ARRAY_SIZE(disp_cc_parent_data_7),
1136		.ops = &clk_rcg2_ops,
1137	},
1138};
1139
1140static struct clk_rcg2 disp1_cc_sleep_clk_src = {
1141	.cmd_rcgr = 0x6060,
1142	.mnd_width = 0,
1143	.hid_width = 5,
1144	.parent_map = disp_cc_parent_map_7,
1145	.freq_tbl = ftbl_disp_cc_sleep_clk_src,
1146	.clkr.hw.init = &(const struct clk_init_data) {
1147		.name = "disp1_cc_sleep_clk_src",
1148		.parent_data = disp_cc_parent_data_7,
1149		.num_parents = ARRAY_SIZE(disp_cc_parent_data_7),
1150		.ops = &clk_rcg2_ops,
1151	},
1152};
1153
1154static struct clk_regmap_div disp0_cc_mdss_byte0_div_clk_src = {
1155	.reg = 0x2154,
1156	.shift = 0,
1157	.width = 4,
1158	.clkr.hw.init = &(const struct clk_init_data) {
1159		.name = "disp0_cc_mdss_byte0_div_clk_src",
1160		.parent_hws = (const struct clk_hw*[]){
1161			&disp0_cc_mdss_byte0_clk_src.clkr.hw,
1162		},
1163		.num_parents = 1,
1164		.flags = CLK_SET_RATE_PARENT,
1165		.ops = &clk_regmap_div_ops,
1166	},
1167};
1168
1169static struct clk_regmap_div disp1_cc_mdss_byte0_div_clk_src = {
1170	.reg = 0x2154,
1171	.shift = 0,
1172	.width = 4,
1173	.clkr.hw.init = &(const struct clk_init_data) {
1174		.name = "disp1_cc_mdss_byte0_div_clk_src",
1175		.parent_hws = (const struct clk_hw*[]){
1176			&disp1_cc_mdss_byte0_clk_src.clkr.hw,
1177		},
1178		.num_parents = 1,
1179		.flags = CLK_SET_RATE_PARENT,
1180		.ops = &clk_regmap_div_ops,
1181	},
1182};
1183
1184static struct clk_regmap_div disp0_cc_mdss_byte1_div_clk_src = {
1185	.reg = 0x2170,
1186	.shift = 0,
1187	.width = 4,
1188	.clkr.hw.init = &(const struct clk_init_data) {
1189		.name = "disp0_cc_mdss_byte1_div_clk_src",
1190		.parent_hws = (const struct clk_hw*[]){
1191			&disp0_cc_mdss_byte1_clk_src.clkr.hw,
1192		},
1193		.num_parents = 1,
1194		.flags = CLK_SET_RATE_PARENT,
1195		.ops = &clk_regmap_div_ops,
1196	},
1197};
1198
1199static struct clk_regmap_div disp1_cc_mdss_byte1_div_clk_src = {
1200	.reg = 0x2170,
1201	.shift = 0,
1202	.width = 4,
1203	.clkr.hw.init = &(const struct clk_init_data) {
1204		.name = "disp1_cc_mdss_byte1_div_clk_src",
1205		.parent_hws = (const struct clk_hw*[]){
1206			&disp1_cc_mdss_byte1_clk_src.clkr.hw,
1207		},
1208		.num_parents = 1,
1209		.flags = CLK_SET_RATE_PARENT,
1210		.ops = &clk_regmap_div_ops,
1211	},
1212};
1213
1214static struct clk_regmap_div disp0_cc_mdss_dptx0_link_div_clk_src = {
1215	.reg = 0x21bc,
1216	.shift = 0,
1217	.width = 4,
1218	.clkr.hw.init = &(const struct clk_init_data) {
1219		.name = "disp0_cc_mdss_dptx0_link_div_clk_src",
1220		.parent_hws = (const struct clk_hw*[]){
1221			&disp0_cc_mdss_dptx0_link_clk_src.clkr.hw,
1222		},
1223		.num_parents = 1,
1224		.flags = CLK_SET_RATE_PARENT,
1225		.ops = &clk_regmap_div_ro_ops,
1226	},
1227};
1228
1229static struct clk_regmap_div disp1_cc_mdss_dptx0_link_div_clk_src = {
1230	.reg = 0x21bc,
1231	.shift = 0,
1232	.width = 4,
1233	.clkr.hw.init = &(const struct clk_init_data) {
1234		.name = "disp1_cc_mdss_dptx0_link_div_clk_src",
1235		.parent_hws = (const struct clk_hw*[]){
1236			&disp1_cc_mdss_dptx0_link_clk_src.clkr.hw,
1237		},
1238		.num_parents = 1,
1239		.flags = CLK_SET_RATE_PARENT,
1240		.ops = &clk_regmap_div_ro_ops,
1241	},
1242};
1243
1244static struct clk_regmap_div disp0_cc_mdss_dptx1_link_div_clk_src = {
1245	.reg = 0x2280,
1246	.shift = 0,
1247	.width = 4,
1248	.clkr.hw.init = &(const struct clk_init_data) {
1249		.name = "disp0_cc_mdss_dptx1_link_div_clk_src",
1250		.parent_hws = (const struct clk_hw*[]){
1251			&disp0_cc_mdss_dptx1_link_clk_src.clkr.hw,
1252		},
1253		.num_parents = 1,
1254		.flags = CLK_SET_RATE_PARENT,
1255		.ops = &clk_regmap_div_ro_ops,
1256	},
1257};
1258
1259static struct clk_regmap_div disp1_cc_mdss_dptx1_link_div_clk_src = {
1260	.reg = 0x2280,
1261	.shift = 0,
1262	.width = 4,
1263	.clkr.hw.init = &(const struct clk_init_data) {
1264		.name = "disp1_cc_mdss_dptx1_link_div_clk_src",
1265		.parent_hws = (const struct clk_hw*[]){
1266			&disp1_cc_mdss_dptx1_link_clk_src.clkr.hw,
1267		},
1268		.num_parents = 1,
1269		.flags = CLK_SET_RATE_PARENT,
1270		.ops = &clk_regmap_div_ro_ops,
1271	},
1272};
1273
1274static struct clk_regmap_div disp0_cc_mdss_dptx2_link_div_clk_src = {
1275	.reg = 0x229c,
1276	.shift = 0,
1277	.width = 4,
1278	.clkr.hw.init = &(const struct clk_init_data) {
1279		.name = "disp0_cc_mdss_dptx2_link_div_clk_src",
1280		.parent_hws = (const struct clk_hw*[]){
1281			&disp0_cc_mdss_dptx2_link_clk_src.clkr.hw,
1282		},
1283		.num_parents = 1,
1284		.flags = CLK_SET_RATE_PARENT,
1285		.ops = &clk_regmap_div_ro_ops,
1286	},
1287};
1288
1289static struct clk_regmap_div disp1_cc_mdss_dptx2_link_div_clk_src = {
1290	.reg = 0x229c,
1291	.shift = 0,
1292	.width = 4,
1293	.clkr.hw.init = &(const struct clk_init_data) {
1294		.name = "disp1_cc_mdss_dptx2_link_div_clk_src",
1295		.parent_hws = (const struct clk_hw*[]){
1296			&disp1_cc_mdss_dptx2_link_clk_src.clkr.hw,
1297		},
1298		.num_parents = 1,
1299		.flags = CLK_SET_RATE_PARENT,
1300		.ops = &clk_regmap_div_ro_ops,
1301	},
1302};
1303
1304static struct clk_regmap_div disp0_cc_mdss_dptx3_link_div_clk_src = {
1305	.reg = 0x2330,
1306	.shift = 0,
1307	.width = 4,
1308	.clkr.hw.init = &(const struct clk_init_data) {
1309		.name = "disp0_cc_mdss_dptx3_link_div_clk_src",
1310		.parent_hws = (const struct clk_hw*[]){
1311			&disp0_cc_mdss_dptx3_link_clk_src.clkr.hw,
1312		},
1313		.num_parents = 1,
1314		.flags = CLK_SET_RATE_PARENT,
1315		.ops = &clk_regmap_div_ro_ops,
1316	},
1317};
1318
1319static struct clk_regmap_div disp1_cc_mdss_dptx3_link_div_clk_src = {
1320	.reg = 0x2330,
1321	.shift = 0,
1322	.width = 4,
1323	.clkr.hw.init = &(const struct clk_init_data) {
1324		.name = "disp1_cc_mdss_dptx3_link_div_clk_src",
1325		.parent_hws = (const struct clk_hw*[]){
1326			&disp1_cc_mdss_dptx3_link_clk_src.clkr.hw,
1327		},
1328		.num_parents = 1,
1329		.flags = CLK_SET_RATE_PARENT,
1330		.ops = &clk_regmap_div_ro_ops,
1331	},
1332};
1333
1334static struct clk_branch disp0_cc_mdss_ahb1_clk = {
1335	.halt_reg = 0x20c0,
1336	.halt_check = BRANCH_HALT,
1337	.clkr = {
1338		.enable_reg = 0x20c0,
1339		.enable_mask = BIT(0),
1340		.hw.init = &(const struct clk_init_data) {
1341			.name = "disp0_cc_mdss_ahb1_clk",
1342			.parent_hws = (const struct clk_hw*[]){
1343				&disp0_cc_mdss_ahb_clk_src.clkr.hw,
1344			},
1345			.num_parents = 1,
1346			.flags = CLK_SET_RATE_PARENT,
1347			.ops = &clk_branch2_ops,
1348		},
1349	},
1350};
1351
1352static struct clk_branch disp1_cc_mdss_ahb1_clk = {
1353	.halt_reg = 0x20c0,
1354	.halt_check = BRANCH_HALT,
1355	.clkr = {
1356		.enable_reg = 0x20c0,
1357		.enable_mask = BIT(0),
1358		.hw.init = &(const struct clk_init_data) {
1359			.name = "disp1_cc_mdss_ahb1_clk",
1360			.parent_hws = (const struct clk_hw*[]){
1361				&disp1_cc_mdss_ahb_clk_src.clkr.hw,
1362			},
1363			.num_parents = 1,
1364			.flags = CLK_SET_RATE_PARENT,
1365			.ops = &clk_branch2_ops,
1366		},
1367	},
1368};
1369
1370static struct clk_branch disp0_cc_mdss_ahb_clk = {
1371	.halt_reg = 0x20bc,
1372	.halt_check = BRANCH_HALT,
1373	.clkr = {
1374		.enable_reg = 0x20bc,
1375		.enable_mask = BIT(0),
1376		.hw.init = &(const struct clk_init_data) {
1377			.name = "disp0_cc_mdss_ahb_clk",
1378			.parent_hws = (const struct clk_hw*[]){
1379				&disp0_cc_mdss_ahb_clk_src.clkr.hw,
1380			},
1381			.num_parents = 1,
1382			.flags = CLK_SET_RATE_PARENT,
1383			.ops = &clk_branch2_ops,
1384		},
1385	},
1386};
1387
1388static struct clk_branch disp1_cc_mdss_ahb_clk = {
1389	.halt_reg = 0x20bc,
1390	.halt_check = BRANCH_HALT,
1391	.clkr = {
1392		.enable_reg = 0x20bc,
1393		.enable_mask = BIT(0),
1394		.hw.init = &(const struct clk_init_data) {
1395			.name = "disp1_cc_mdss_ahb_clk",
1396			.parent_hws = (const struct clk_hw*[]){
1397				&disp1_cc_mdss_ahb_clk_src.clkr.hw,
1398			},
1399			.num_parents = 1,
1400			.flags = CLK_SET_RATE_PARENT,
1401			.ops = &clk_branch2_ops,
1402		},
1403	},
1404};
1405
1406static struct clk_branch disp0_cc_mdss_byte0_clk = {
1407	.halt_reg = 0x2044,
1408	.halt_check = BRANCH_HALT,
1409	.clkr = {
1410		.enable_reg = 0x2044,
1411		.enable_mask = BIT(0),
1412		.hw.init = &(const struct clk_init_data) {
1413			.name = "disp0_cc_mdss_byte0_clk",
1414			.parent_hws = (const struct clk_hw*[]){
1415				&disp0_cc_mdss_byte0_clk_src.clkr.hw,
1416			},
1417			.num_parents = 1,
1418			.flags = CLK_SET_RATE_PARENT,
1419			.ops = &clk_branch2_ops,
1420		},
1421	},
1422};
1423
1424static struct clk_branch disp1_cc_mdss_byte0_clk = {
1425	.halt_reg = 0x2044,
1426	.halt_check = BRANCH_HALT,
1427	.clkr = {
1428		.enable_reg = 0x2044,
1429		.enable_mask = BIT(0),
1430		.hw.init = &(const struct clk_init_data) {
1431			.name = "disp1_cc_mdss_byte0_clk",
1432			.parent_hws = (const struct clk_hw*[]){
1433				&disp1_cc_mdss_byte0_clk_src.clkr.hw,
1434			},
1435			.num_parents = 1,
1436			.flags = CLK_SET_RATE_PARENT,
1437			.ops = &clk_branch2_ops,
1438		},
1439	},
1440};
1441
1442static struct clk_branch disp0_cc_mdss_byte0_intf_clk = {
1443	.halt_reg = 0x2048,
1444	.halt_check = BRANCH_HALT,
1445	.clkr = {
1446		.enable_reg = 0x2048,
1447		.enable_mask = BIT(0),
1448		.hw.init = &(const struct clk_init_data) {
1449			.name = "disp0_cc_mdss_byte0_intf_clk",
1450			.parent_hws = (const struct clk_hw*[]){
1451				&disp0_cc_mdss_byte0_div_clk_src.clkr.hw,
1452			},
1453			.num_parents = 1,
1454			.flags = CLK_SET_RATE_PARENT,
1455			.ops = &clk_branch2_ops,
1456		},
1457	},
1458};
1459
1460static struct clk_branch disp1_cc_mdss_byte0_intf_clk = {
1461	.halt_reg = 0x2048,
1462	.halt_check = BRANCH_HALT,
1463	.clkr = {
1464		.enable_reg = 0x2048,
1465		.enable_mask = BIT(0),
1466		.hw.init = &(const struct clk_init_data) {
1467			.name = "disp1_cc_mdss_byte0_intf_clk",
1468			.parent_hws = (const struct clk_hw*[]){
1469				&disp1_cc_mdss_byte0_div_clk_src.clkr.hw,
1470			},
1471			.num_parents = 1,
1472			.flags = CLK_SET_RATE_PARENT,
1473			.ops = &clk_branch2_ops,
1474		},
1475	},
1476};
1477
1478static struct clk_branch disp0_cc_mdss_byte1_clk = {
1479	.halt_reg = 0x204c,
1480	.halt_check = BRANCH_HALT,
1481	.clkr = {
1482		.enable_reg = 0x204c,
1483		.enable_mask = BIT(0),
1484		.hw.init = &(const struct clk_init_data) {
1485			.name = "disp0_cc_mdss_byte1_clk",
1486			.parent_hws = (const struct clk_hw*[]){
1487				&disp0_cc_mdss_byte1_clk_src.clkr.hw,
1488			},
1489			.num_parents = 1,
1490			.flags = CLK_SET_RATE_PARENT,
1491			.ops = &clk_branch2_ops,
1492		},
1493	},
1494};
1495
1496static struct clk_branch disp1_cc_mdss_byte1_clk = {
1497	.halt_reg = 0x204c,
1498	.halt_check = BRANCH_HALT,
1499	.clkr = {
1500		.enable_reg = 0x204c,
1501		.enable_mask = BIT(0),
1502		.hw.init = &(const struct clk_init_data) {
1503			.name = "disp1_cc_mdss_byte1_clk",
1504			.parent_hws = (const struct clk_hw*[]){
1505				&disp1_cc_mdss_byte1_clk_src.clkr.hw,
1506			},
1507			.num_parents = 1,
1508			.flags = CLK_SET_RATE_PARENT,
1509			.ops = &clk_branch2_ops,
1510		},
1511	},
1512};
1513
1514static struct clk_branch disp0_cc_mdss_byte1_intf_clk = {
1515	.halt_reg = 0x2050,
1516	.halt_check = BRANCH_HALT,
1517	.clkr = {
1518		.enable_reg = 0x2050,
1519		.enable_mask = BIT(0),
1520		.hw.init = &(const struct clk_init_data) {
1521			.name = "disp0_cc_mdss_byte1_intf_clk",
1522			.parent_hws = (const struct clk_hw*[]){
1523				&disp0_cc_mdss_byte1_div_clk_src.clkr.hw,
1524			},
1525			.num_parents = 1,
1526			.flags = CLK_SET_RATE_PARENT,
1527			.ops = &clk_branch2_ops,
1528		},
1529	},
1530};
1531
1532static struct clk_branch disp1_cc_mdss_byte1_intf_clk = {
1533	.halt_reg = 0x2050,
1534	.halt_check = BRANCH_HALT,
1535	.clkr = {
1536		.enable_reg = 0x2050,
1537		.enable_mask = BIT(0),
1538		.hw.init = &(const struct clk_init_data) {
1539			.name = "disp1_cc_mdss_byte1_intf_clk",
1540			.parent_hws = (const struct clk_hw*[]){
1541				&disp1_cc_mdss_byte1_div_clk_src.clkr.hw,
1542			},
1543			.num_parents = 1,
1544			.flags = CLK_SET_RATE_PARENT,
1545			.ops = &clk_branch2_ops,
1546		},
1547	},
1548};
1549
1550static struct clk_branch disp0_cc_mdss_dptx0_aux_clk = {
1551	.halt_reg = 0x206c,
1552	.halt_check = BRANCH_HALT,
1553	.clkr = {
1554		.enable_reg = 0x206c,
1555		.enable_mask = BIT(0),
1556		.hw.init = &(const struct clk_init_data) {
1557			.name = "disp0_cc_mdss_dptx0_aux_clk",
1558			.parent_hws = (const struct clk_hw*[]){
1559				&disp0_cc_mdss_dptx0_aux_clk_src.clkr.hw,
1560			},
1561			.num_parents = 1,
1562			.flags = CLK_SET_RATE_PARENT,
1563			.ops = &clk_branch2_ops,
1564		},
1565	},
1566};
1567
1568static struct clk_branch disp1_cc_mdss_dptx0_aux_clk = {
1569	.halt_reg = 0x206c,
1570	.halt_check = BRANCH_HALT,
1571	.clkr = {
1572		.enable_reg = 0x206c,
1573		.enable_mask = BIT(0),
1574		.hw.init = &(const struct clk_init_data) {
1575			.name = "disp1_cc_mdss_dptx0_aux_clk",
1576			.parent_hws = (const struct clk_hw*[]){
1577				&disp1_cc_mdss_dptx0_aux_clk_src.clkr.hw,
1578			},
1579			.num_parents = 1,
1580			.flags = CLK_SET_RATE_PARENT,
1581			.ops = &clk_branch2_ops,
1582		},
1583	},
1584};
1585
1586static struct clk_branch disp0_cc_mdss_dptx0_link_clk = {
1587	.halt_reg = 0x205c,
1588	.halt_check = BRANCH_HALT,
1589	.clkr = {
1590		.enable_reg = 0x205c,
1591		.enable_mask = BIT(0),
1592		.hw.init = &(const struct clk_init_data) {
1593			.name = "disp0_cc_mdss_dptx0_link_clk",
1594			.parent_hws = (const struct clk_hw*[]){
1595				&disp0_cc_mdss_dptx0_link_clk_src.clkr.hw,
1596			},
1597			.num_parents = 1,
1598			.flags = CLK_SET_RATE_PARENT,
1599			.ops = &clk_branch2_ops,
1600		},
1601	},
1602};
1603
1604static struct clk_branch disp1_cc_mdss_dptx0_link_clk = {
1605	.halt_reg = 0x205c,
1606	.halt_check = BRANCH_HALT,
1607	.clkr = {
1608		.enable_reg = 0x205c,
1609		.enable_mask = BIT(0),
1610		.hw.init = &(const struct clk_init_data) {
1611			.name = "disp1_cc_mdss_dptx0_link_clk",
1612			.parent_hws = (const struct clk_hw*[]){
1613				&disp1_cc_mdss_dptx0_link_clk_src.clkr.hw,
1614			},
1615			.num_parents = 1,
1616			.flags = CLK_SET_RATE_PARENT,
1617			.ops = &clk_branch2_ops,
1618		},
1619	},
1620};
1621
1622static struct clk_branch disp0_cc_mdss_dptx0_link_intf_clk = {
1623	.halt_reg = 0x2060,
1624	.halt_check = BRANCH_HALT,
1625	.clkr = {
1626		.enable_reg = 0x2060,
1627		.enable_mask = BIT(0),
1628		.hw.init = &(const struct clk_init_data) {
1629			.name = "disp0_cc_mdss_dptx0_link_intf_clk",
1630			.parent_hws = (const struct clk_hw*[]){
1631				&disp0_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
1632			},
1633			.num_parents = 1,
1634			.flags = CLK_SET_RATE_PARENT,
1635			.ops = &clk_branch2_ops,
1636		},
1637	},
1638};
1639
1640static struct clk_branch disp1_cc_mdss_dptx0_link_intf_clk = {
1641	.halt_reg = 0x2060,
1642	.halt_check = BRANCH_HALT,
1643	.clkr = {
1644		.enable_reg = 0x2060,
1645		.enable_mask = BIT(0),
1646		.hw.init = &(const struct clk_init_data) {
1647			.name = "disp1_cc_mdss_dptx0_link_intf_clk",
1648			.parent_hws = (const struct clk_hw*[]){
1649				&disp1_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
1650			},
1651			.num_parents = 1,
1652			.flags = CLK_SET_RATE_PARENT,
1653			.ops = &clk_branch2_ops,
1654		},
1655	},
1656};
1657
1658static struct clk_branch disp0_cc_mdss_dptx0_pixel0_clk = {
1659	.halt_reg = 0x2070,
1660	.halt_check = BRANCH_HALT,
1661	.clkr = {
1662		.enable_reg = 0x2070,
1663		.enable_mask = BIT(0),
1664		.hw.init = &(const struct clk_init_data) {
1665			.name = "disp0_cc_mdss_dptx0_pixel0_clk",
1666			.parent_hws = (const struct clk_hw*[]){
1667				&disp0_cc_mdss_dptx0_pixel0_clk_src.clkr.hw,
1668			},
1669			.num_parents = 1,
1670			.flags = CLK_SET_RATE_PARENT,
1671			.ops = &clk_branch2_ops,
1672		},
1673	},
1674};
1675
1676static struct clk_branch disp1_cc_mdss_dptx0_pixel0_clk = {
1677	.halt_reg = 0x2070,
1678	.halt_check = BRANCH_HALT,
1679	.clkr = {
1680		.enable_reg = 0x2070,
1681		.enable_mask = BIT(0),
1682		.hw.init = &(const struct clk_init_data) {
1683			.name = "disp1_cc_mdss_dptx0_pixel0_clk",
1684			.parent_hws = (const struct clk_hw*[]){
1685				&disp1_cc_mdss_dptx0_pixel0_clk_src.clkr.hw,
1686			},
1687			.num_parents = 1,
1688			.flags = CLK_SET_RATE_PARENT,
1689			.ops = &clk_branch2_ops,
1690		},
1691	},
1692};
1693
1694static struct clk_branch disp0_cc_mdss_dptx0_pixel1_clk = {
1695	.halt_reg = 0x2074,
1696	.halt_check = BRANCH_HALT,
1697	.clkr = {
1698		.enable_reg = 0x2074,
1699		.enable_mask = BIT(0),
1700		.hw.init = &(const struct clk_init_data) {
1701			.name = "disp0_cc_mdss_dptx0_pixel1_clk",
1702			.parent_hws = (const struct clk_hw*[]){
1703				&disp0_cc_mdss_dptx0_pixel1_clk_src.clkr.hw,
1704			},
1705			.num_parents = 1,
1706			.flags = CLK_SET_RATE_PARENT,
1707			.ops = &clk_branch2_ops,
1708		},
1709	},
1710};
1711
1712static struct clk_branch disp1_cc_mdss_dptx0_pixel1_clk = {
1713	.halt_reg = 0x2074,
1714	.halt_check = BRANCH_HALT,
1715	.clkr = {
1716		.enable_reg = 0x2074,
1717		.enable_mask = BIT(0),
1718		.hw.init = &(const struct clk_init_data) {
1719			.name = "disp1_cc_mdss_dptx0_pixel1_clk",
1720			.parent_hws = (const struct clk_hw*[]){
1721				&disp1_cc_mdss_dptx0_pixel1_clk_src.clkr.hw,
1722			},
1723			.num_parents = 1,
1724			.flags = CLK_SET_RATE_PARENT,
1725			.ops = &clk_branch2_ops,
1726		},
1727	},
1728};
1729
1730static struct clk_branch disp0_cc_mdss_dptx0_usb_router_link_intf_clk = {
1731	.halt_reg = 0x2064,
1732	.halt_check = BRANCH_HALT,
1733	.clkr = {
1734		.enable_reg = 0x2064,
1735		.enable_mask = BIT(0),
1736		.hw.init = &(const struct clk_init_data) {
1737			.name = "disp0_cc_mdss_dptx0_usb_router_link_intf_clk",
1738			.parent_hws = (const struct clk_hw*[]){
1739				&disp0_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
1740			},
1741			.num_parents = 1,
1742			.flags = CLK_SET_RATE_PARENT,
1743			.ops = &clk_branch2_ops,
1744		},
1745	},
1746};
1747
1748static struct clk_branch disp1_cc_mdss_dptx0_usb_router_link_intf_clk = {
1749	.halt_reg = 0x2064,
1750	.halt_check = BRANCH_HALT,
1751	.clkr = {
1752		.enable_reg = 0x2064,
1753		.enable_mask = BIT(0),
1754		.hw.init = &(const struct clk_init_data) {
1755			.name = "disp1_cc_mdss_dptx0_usb_router_link_intf_clk",
1756			.parent_hws = (const struct clk_hw*[]){
1757				&disp1_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
1758			},
1759			.num_parents = 1,
1760			.flags = CLK_SET_RATE_PARENT,
1761			.ops = &clk_branch2_ops,
1762		},
1763	},
1764};
1765
1766static struct clk_branch disp0_cc_mdss_dptx1_aux_clk = {
1767	.halt_reg = 0x20a0,
1768	.halt_check = BRANCH_HALT,
1769	.clkr = {
1770		.enable_reg = 0x20a0,
1771		.enable_mask = BIT(0),
1772		.hw.init = &(const struct clk_init_data) {
1773			.name = "disp0_cc_mdss_dptx1_aux_clk",
1774			.parent_hws = (const struct clk_hw*[]){
1775				&disp0_cc_mdss_dptx1_aux_clk_src.clkr.hw,
1776			},
1777			.num_parents = 1,
1778			.flags = CLK_SET_RATE_PARENT,
1779			.ops = &clk_branch2_ops,
1780		},
1781	},
1782};
1783
1784static struct clk_branch disp1_cc_mdss_dptx1_aux_clk = {
1785	.halt_reg = 0x20a0,
1786	.halt_check = BRANCH_HALT,
1787	.clkr = {
1788		.enable_reg = 0x20a0,
1789		.enable_mask = BIT(0),
1790		.hw.init = &(const struct clk_init_data) {
1791			.name = "disp1_cc_mdss_dptx1_aux_clk",
1792			.parent_hws = (const struct clk_hw*[]){
1793				&disp1_cc_mdss_dptx1_aux_clk_src.clkr.hw,
1794			},
1795			.num_parents = 1,
1796			.flags = CLK_SET_RATE_PARENT,
1797			.ops = &clk_branch2_ops,
1798		},
1799	},
1800};
1801
1802static struct clk_branch disp0_cc_mdss_dptx1_link_clk = {
1803	.halt_reg = 0x2084,
1804	.halt_check = BRANCH_HALT,
1805	.clkr = {
1806		.enable_reg = 0x2084,
1807		.enable_mask = BIT(0),
1808		.hw.init = &(const struct clk_init_data) {
1809			.name = "disp0_cc_mdss_dptx1_link_clk",
1810			.parent_hws = (const struct clk_hw*[]){
1811				&disp0_cc_mdss_dptx1_link_clk_src.clkr.hw,
1812			},
1813			.num_parents = 1,
1814			.flags = CLK_SET_RATE_PARENT,
1815			.ops = &clk_branch2_ops,
1816		},
1817	},
1818};
1819
1820static struct clk_branch disp1_cc_mdss_dptx1_link_clk = {
1821	.halt_reg = 0x2084,
1822	.halt_check = BRANCH_HALT,
1823	.clkr = {
1824		.enable_reg = 0x2084,
1825		.enable_mask = BIT(0),
1826		.hw.init = &(const struct clk_init_data) {
1827			.name = "disp1_cc_mdss_dptx1_link_clk",
1828			.parent_hws = (const struct clk_hw*[]){
1829				&disp1_cc_mdss_dptx1_link_clk_src.clkr.hw,
1830			},
1831			.num_parents = 1,
1832			.flags = CLK_SET_RATE_PARENT,
1833			.ops = &clk_branch2_ops,
1834		},
1835	},
1836};
1837
1838static struct clk_branch disp0_cc_mdss_dptx1_link_intf_clk = {
1839	.halt_reg = 0x2088,
1840	.halt_check = BRANCH_HALT,
1841	.clkr = {
1842		.enable_reg = 0x2088,
1843		.enable_mask = BIT(0),
1844		.hw.init = &(const struct clk_init_data) {
1845			.name = "disp0_cc_mdss_dptx1_link_intf_clk",
1846			.parent_hws = (const struct clk_hw*[]){
1847				&disp0_cc_mdss_dptx1_link_div_clk_src.clkr.hw,
1848			},
1849			.num_parents = 1,
1850			.flags = CLK_SET_RATE_PARENT,
1851			.ops = &clk_branch2_ops,
1852		},
1853	},
1854};
1855
1856static struct clk_branch disp1_cc_mdss_dptx1_link_intf_clk = {
1857	.halt_reg = 0x2088,
1858	.halt_check = BRANCH_HALT,
1859	.clkr = {
1860		.enable_reg = 0x2088,
1861		.enable_mask = BIT(0),
1862		.hw.init = &(const struct clk_init_data) {
1863			.name = "disp1_cc_mdss_dptx1_link_intf_clk",
1864			.parent_hws = (const struct clk_hw*[]){
1865				&disp1_cc_mdss_dptx1_link_div_clk_src.clkr.hw,
1866			},
1867			.num_parents = 1,
1868			.flags = CLK_SET_RATE_PARENT,
1869			.ops = &clk_branch2_ops,
1870		},
1871	},
1872};
1873
1874static struct clk_branch disp0_cc_mdss_dptx1_pixel0_clk = {
1875	.halt_reg = 0x2078,
1876	.halt_check = BRANCH_HALT,
1877	.clkr = {
1878		.enable_reg = 0x2078,
1879		.enable_mask = BIT(0),
1880		.hw.init = &(const struct clk_init_data) {
1881			.name = "disp0_cc_mdss_dptx1_pixel0_clk",
1882			.parent_hws = (const struct clk_hw*[]){
1883				&disp0_cc_mdss_dptx1_pixel0_clk_src.clkr.hw,
1884			},
1885			.num_parents = 1,
1886			.flags = CLK_SET_RATE_PARENT,
1887			.ops = &clk_branch2_ops,
1888		},
1889	},
1890};
1891
1892static struct clk_branch disp1_cc_mdss_dptx1_pixel0_clk = {
1893	.halt_reg = 0x2078,
1894	.halt_check = BRANCH_HALT,
1895	.clkr = {
1896		.enable_reg = 0x2078,
1897		.enable_mask = BIT(0),
1898		.hw.init = &(const struct clk_init_data) {
1899			.name = "disp1_cc_mdss_dptx1_pixel0_clk",
1900			.parent_hws = (const struct clk_hw*[]){
1901				&disp1_cc_mdss_dptx1_pixel0_clk_src.clkr.hw,
1902			},
1903			.num_parents = 1,
1904			.flags = CLK_SET_RATE_PARENT,
1905			.ops = &clk_branch2_ops,
1906		},
1907	},
1908};
1909
1910static struct clk_branch disp0_cc_mdss_dptx1_pixel1_clk = {
1911	.halt_reg = 0x236c,
1912	.halt_check = BRANCH_HALT,
1913	.clkr = {
1914		.enable_reg = 0x236c,
1915		.enable_mask = BIT(0),
1916		.hw.init = &(const struct clk_init_data) {
1917			.name = "disp0_cc_mdss_dptx1_pixel1_clk",
1918			.parent_hws = (const struct clk_hw*[]){
1919				&disp0_cc_mdss_dptx1_pixel1_clk_src.clkr.hw,
1920			},
1921			.num_parents = 1,
1922			.flags = CLK_SET_RATE_PARENT,
1923			.ops = &clk_branch2_ops,
1924		},
1925	},
1926};
1927
1928static struct clk_branch disp1_cc_mdss_dptx1_pixel1_clk = {
1929	.halt_reg = 0x236c,
1930	.halt_check = BRANCH_HALT,
1931	.clkr = {
1932		.enable_reg = 0x236c,
1933		.enable_mask = BIT(0),
1934		.hw.init = &(const struct clk_init_data) {
1935			.name = "disp1_cc_mdss_dptx1_pixel1_clk",
1936			.parent_hws = (const struct clk_hw*[]){
1937				&disp1_cc_mdss_dptx1_pixel1_clk_src.clkr.hw,
1938			},
1939			.num_parents = 1,
1940			.flags = CLK_SET_RATE_PARENT,
1941			.ops = &clk_branch2_ops,
1942		},
1943	},
1944};
1945
1946static struct clk_branch disp0_cc_mdss_dptx1_usb_router_link_intf_clk = {
1947	.halt_reg = 0x208c,
1948	.halt_check = BRANCH_HALT,
1949	.clkr = {
1950		.enable_reg = 0x208c,
1951		.enable_mask = BIT(0),
1952		.hw.init = &(const struct clk_init_data) {
1953			.name = "disp0_cc_mdss_dptx1_usb_router_link_intf_clk",
1954			.parent_hws = (const struct clk_hw*[]){
1955				&disp0_cc_mdss_dptx1_link_div_clk_src.clkr.hw,
1956			},
1957			.num_parents = 1,
1958			.flags = CLK_SET_RATE_PARENT,
1959			.ops = &clk_branch2_ops,
1960		},
1961	},
1962};
1963
1964static struct clk_branch disp1_cc_mdss_dptx1_usb_router_link_intf_clk = {
1965	.halt_reg = 0x208c,
1966	.halt_check = BRANCH_HALT,
1967	.clkr = {
1968		.enable_reg = 0x208c,
1969		.enable_mask = BIT(0),
1970		.hw.init = &(const struct clk_init_data) {
1971			.name = "disp1_cc_mdss_dptx1_usb_router_link_intf_clk",
1972			.parent_hws = (const struct clk_hw*[]){
1973				&disp1_cc_mdss_dptx1_link_div_clk_src.clkr.hw,
1974			},
1975			.num_parents = 1,
1976			.flags = CLK_SET_RATE_PARENT,
1977			.ops = &clk_branch2_ops,
1978		},
1979	},
1980};
1981
1982static struct clk_branch disp0_cc_mdss_dptx2_aux_clk = {
1983	.halt_reg = 0x20a4,
1984	.halt_check = BRANCH_HALT,
1985	.clkr = {
1986		.enable_reg = 0x20a4,
1987		.enable_mask = BIT(0),
1988		.hw.init = &(const struct clk_init_data) {
1989			.name = "disp0_cc_mdss_dptx2_aux_clk",
1990			.parent_hws = (const struct clk_hw*[]){
1991				&disp0_cc_mdss_dptx2_aux_clk_src.clkr.hw,
1992			},
1993			.num_parents = 1,
1994			.flags = CLK_SET_RATE_PARENT,
1995			.ops = &clk_branch2_ops,
1996		},
1997	},
1998};
1999
2000static struct clk_branch disp1_cc_mdss_dptx2_aux_clk = {
2001	.halt_reg = 0x20a4,
2002	.halt_check = BRANCH_HALT,
2003	.clkr = {
2004		.enable_reg = 0x20a4,
2005		.enable_mask = BIT(0),
2006		.hw.init = &(const struct clk_init_data) {
2007			.name = "disp1_cc_mdss_dptx2_aux_clk",
2008			.parent_hws = (const struct clk_hw*[]){
2009				&disp1_cc_mdss_dptx2_aux_clk_src.clkr.hw,
2010			},
2011			.num_parents = 1,
2012			.flags = CLK_SET_RATE_PARENT,
2013			.ops = &clk_branch2_ops,
2014		},
2015	},
2016};
2017
2018static struct clk_branch disp0_cc_mdss_dptx2_link_clk = {
2019	.halt_reg = 0x2090,
2020	.halt_check = BRANCH_HALT,
2021	.clkr = {
2022		.enable_reg = 0x2090,
2023		.enable_mask = BIT(0),
2024		.hw.init = &(const struct clk_init_data) {
2025			.name = "disp0_cc_mdss_dptx2_link_clk",
2026			.parent_hws = (const struct clk_hw*[]){
2027				&disp0_cc_mdss_dptx2_link_clk_src.clkr.hw,
2028			},
2029			.num_parents = 1,
2030			.flags = CLK_SET_RATE_PARENT,
2031			.ops = &clk_branch2_ops,
2032		},
2033	},
2034};
2035
2036static struct clk_branch disp1_cc_mdss_dptx2_link_clk = {
2037	.halt_reg = 0x2090,
2038	.halt_check = BRANCH_HALT,
2039	.clkr = {
2040		.enable_reg = 0x2090,
2041		.enable_mask = BIT(0),
2042		.hw.init = &(const struct clk_init_data) {
2043			.name = "disp1_cc_mdss_dptx2_link_clk",
2044			.parent_hws = (const struct clk_hw*[]){
2045				&disp1_cc_mdss_dptx2_link_clk_src.clkr.hw,
2046			},
2047			.num_parents = 1,
2048			.flags = CLK_SET_RATE_PARENT,
2049			.ops = &clk_branch2_ops,
2050		},
2051	},
2052};
2053
2054static struct clk_branch disp0_cc_mdss_dptx2_link_intf_clk = {
2055	.halt_reg = 0x2094,
2056	.halt_check = BRANCH_HALT,
2057	.clkr = {
2058		.enable_reg = 0x2094,
2059		.enable_mask = BIT(0),
2060		.hw.init = &(const struct clk_init_data) {
2061			.name = "disp0_cc_mdss_dptx2_link_intf_clk",
2062			.parent_hws = (const struct clk_hw*[]){
2063				&disp0_cc_mdss_dptx2_link_div_clk_src.clkr.hw,
2064			},
2065			.num_parents = 1,
2066			.flags = CLK_SET_RATE_PARENT,
2067			.ops = &clk_branch2_ops,
2068		},
2069	},
2070};
2071
2072static struct clk_branch disp1_cc_mdss_dptx2_link_intf_clk = {
2073	.halt_reg = 0x2094,
2074	.halt_check = BRANCH_HALT,
2075	.clkr = {
2076		.enable_reg = 0x2094,
2077		.enable_mask = BIT(0),
2078		.hw.init = &(const struct clk_init_data) {
2079			.name = "disp1_cc_mdss_dptx2_link_intf_clk",
2080			.parent_hws = (const struct clk_hw*[]){
2081				&disp1_cc_mdss_dptx2_link_div_clk_src.clkr.hw,
2082			},
2083			.num_parents = 1,
2084			.flags = CLK_SET_RATE_PARENT,
2085			.ops = &clk_branch2_ops,
2086		},
2087	},
2088};
2089
2090static struct clk_branch disp0_cc_mdss_dptx2_pixel0_clk = {
2091	.halt_reg = 0x207c,
2092	.halt_check = BRANCH_HALT,
2093	.clkr = {
2094		.enable_reg = 0x207c,
2095		.enable_mask = BIT(0),
2096		.hw.init = &(const struct clk_init_data) {
2097			.name = "disp0_cc_mdss_dptx2_pixel0_clk",
2098			.parent_hws = (const struct clk_hw*[]){
2099				&disp0_cc_mdss_dptx2_pixel0_clk_src.clkr.hw,
2100			},
2101			.num_parents = 1,
2102			.flags = CLK_SET_RATE_PARENT,
2103			.ops = &clk_branch2_ops,
2104		},
2105	},
2106};
2107
2108static struct clk_branch disp1_cc_mdss_dptx2_pixel0_clk = {
2109	.halt_reg = 0x207c,
2110	.halt_check = BRANCH_HALT,
2111	.clkr = {
2112		.enable_reg = 0x207c,
2113		.enable_mask = BIT(0),
2114		.hw.init = &(const struct clk_init_data) {
2115			.name = "disp1_cc_mdss_dptx2_pixel0_clk",
2116			.parent_hws = (const struct clk_hw*[]){
2117				&disp1_cc_mdss_dptx2_pixel0_clk_src.clkr.hw,
2118			},
2119			.num_parents = 1,
2120			.flags = CLK_SET_RATE_PARENT,
2121			.ops = &clk_branch2_ops,
2122		},
2123	},
2124};
2125
2126static struct clk_branch disp0_cc_mdss_dptx2_pixel1_clk = {
2127	.halt_reg = 0x2080,
2128	.halt_check = BRANCH_HALT,
2129	.clkr = {
2130		.enable_reg = 0x2080,
2131		.enable_mask = BIT(0),
2132		.hw.init = &(const struct clk_init_data) {
2133			.name = "disp0_cc_mdss_dptx2_pixel1_clk",
2134			.parent_hws = (const struct clk_hw*[]){
2135				&disp0_cc_mdss_dptx2_pixel1_clk_src.clkr.hw,
2136			},
2137			.num_parents = 1,
2138			.flags = CLK_SET_RATE_PARENT,
2139			.ops = &clk_branch2_ops,
2140		},
2141	},
2142};
2143
2144static struct clk_branch disp1_cc_mdss_dptx2_pixel1_clk = {
2145	.halt_reg = 0x2080,
2146	.halt_check = BRANCH_HALT,
2147	.clkr = {
2148		.enable_reg = 0x2080,
2149		.enable_mask = BIT(0),
2150		.hw.init = &(const struct clk_init_data) {
2151			.name = "disp1_cc_mdss_dptx2_pixel1_clk",
2152			.parent_hws = (const struct clk_hw*[]){
2153				&disp1_cc_mdss_dptx2_pixel1_clk_src.clkr.hw,
2154			},
2155			.num_parents = 1,
2156			.flags = CLK_SET_RATE_PARENT,
2157			.ops = &clk_branch2_ops,
2158		},
2159	},
2160};
2161
2162static struct clk_branch disp0_cc_mdss_dptx3_aux_clk = {
2163	.halt_reg = 0x20b8,
2164	.halt_check = BRANCH_HALT,
2165	.clkr = {
2166		.enable_reg = 0x20b8,
2167		.enable_mask = BIT(0),
2168		.hw.init = &(const struct clk_init_data) {
2169			.name = "disp0_cc_mdss_dptx3_aux_clk",
2170			.parent_hws = (const struct clk_hw*[]){
2171				&disp0_cc_mdss_dptx3_aux_clk_src.clkr.hw,
2172			},
2173			.num_parents = 1,
2174			.flags = CLK_SET_RATE_PARENT,
2175			.ops = &clk_branch2_ops,
2176		},
2177	},
2178};
2179
2180static struct clk_branch disp1_cc_mdss_dptx3_aux_clk = {
2181	.halt_reg = 0x20b8,
2182	.halt_check = BRANCH_HALT,
2183	.clkr = {
2184		.enable_reg = 0x20b8,
2185		.enable_mask = BIT(0),
2186		.hw.init = &(const struct clk_init_data) {
2187			.name = "disp1_cc_mdss_dptx3_aux_clk",
2188			.parent_hws = (const struct clk_hw*[]){
2189				&disp1_cc_mdss_dptx3_aux_clk_src.clkr.hw,
2190			},
2191			.num_parents = 1,
2192			.flags = CLK_SET_RATE_PARENT,
2193			.ops = &clk_branch2_ops,
2194		},
2195	},
2196};
2197
2198static struct clk_branch disp0_cc_mdss_dptx3_link_clk = {
2199	.halt_reg = 0x20ac,
2200	.halt_check = BRANCH_HALT,
2201	.clkr = {
2202		.enable_reg = 0x20ac,
2203		.enable_mask = BIT(0),
2204		.hw.init = &(const struct clk_init_data) {
2205			.name = "disp0_cc_mdss_dptx3_link_clk",
2206			.parent_hws = (const struct clk_hw*[]){
2207				&disp0_cc_mdss_dptx3_link_clk_src.clkr.hw,
2208			},
2209			.num_parents = 1,
2210			.flags = CLK_SET_RATE_PARENT,
2211			.ops = &clk_branch2_ops,
2212		},
2213	},
2214};
2215
2216static struct clk_branch disp1_cc_mdss_dptx3_link_clk = {
2217	.halt_reg = 0x20ac,
2218	.halt_check = BRANCH_HALT,
2219	.clkr = {
2220		.enable_reg = 0x20ac,
2221		.enable_mask = BIT(0),
2222		.hw.init = &(const struct clk_init_data) {
2223			.name = "disp1_cc_mdss_dptx3_link_clk",
2224			.parent_hws = (const struct clk_hw*[]){
2225				&disp1_cc_mdss_dptx3_link_clk_src.clkr.hw,
2226			},
2227			.num_parents = 1,
2228			.flags = CLK_SET_RATE_PARENT,
2229			.ops = &clk_branch2_ops,
2230		},
2231	},
2232};
2233
2234static struct clk_branch disp0_cc_mdss_dptx3_link_intf_clk = {
2235	.halt_reg = 0x20b0,
2236	.halt_check = BRANCH_HALT,
2237	.clkr = {
2238		.enable_reg = 0x20b0,
2239		.enable_mask = BIT(0),
2240		.hw.init = &(const struct clk_init_data) {
2241			.name = "disp0_cc_mdss_dptx3_link_intf_clk",
2242			.parent_hws = (const struct clk_hw*[]){
2243				&disp0_cc_mdss_dptx3_link_div_clk_src.clkr.hw,
2244			},
2245			.num_parents = 1,
2246			.flags = CLK_SET_RATE_PARENT,
2247			.ops = &clk_branch2_ops,
2248		},
2249	},
2250};
2251
2252static struct clk_branch disp1_cc_mdss_dptx3_link_intf_clk = {
2253	.halt_reg = 0x20b0,
2254	.halt_check = BRANCH_HALT,
2255	.clkr = {
2256		.enable_reg = 0x20b0,
2257		.enable_mask = BIT(0),
2258		.hw.init = &(const struct clk_init_data) {
2259			.name = "disp1_cc_mdss_dptx3_link_intf_clk",
2260			.parent_hws = (const struct clk_hw*[]){
2261				&disp1_cc_mdss_dptx3_link_div_clk_src.clkr.hw,
2262			},
2263			.num_parents = 1,
2264			.flags = CLK_SET_RATE_PARENT,
2265			.ops = &clk_branch2_ops,
2266		},
2267	},
2268};
2269
2270static struct clk_branch disp0_cc_mdss_dptx3_pixel0_clk = {
2271	.halt_reg = 0x20a8,
2272	.halt_check = BRANCH_HALT,
2273	.clkr = {
2274		.enable_reg = 0x20a8,
2275		.enable_mask = BIT(0),
2276		.hw.init = &(const struct clk_init_data) {
2277			.name = "disp0_cc_mdss_dptx3_pixel0_clk",
2278			.parent_hws = (const struct clk_hw*[]){
2279				&disp0_cc_mdss_dptx3_pixel0_clk_src.clkr.hw,
2280			},
2281			.num_parents = 1,
2282			.flags = CLK_SET_RATE_PARENT,
2283			.ops = &clk_branch2_ops,
2284		},
2285	},
2286};
2287
2288static struct clk_branch disp1_cc_mdss_dptx3_pixel0_clk = {
2289	.halt_reg = 0x20a8,
2290	.halt_check = BRANCH_HALT,
2291	.clkr = {
2292		.enable_reg = 0x20a8,
2293		.enable_mask = BIT(0),
2294		.hw.init = &(const struct clk_init_data) {
2295			.name = "disp1_cc_mdss_dptx3_pixel0_clk",
2296			.parent_hws = (const struct clk_hw*[]){
2297				&disp1_cc_mdss_dptx3_pixel0_clk_src.clkr.hw,
2298			},
2299			.num_parents = 1,
2300			.flags = CLK_SET_RATE_PARENT,
2301			.ops = &clk_branch2_ops,
2302		},
2303	},
2304};
2305
2306static struct clk_branch disp0_cc_mdss_esc0_clk = {
2307	.halt_reg = 0x2054,
2308	.halt_check = BRANCH_HALT,
2309	.clkr = {
2310		.enable_reg = 0x2054,
2311		.enable_mask = BIT(0),
2312		.hw.init = &(const struct clk_init_data) {
2313			.name = "disp0_cc_mdss_esc0_clk",
2314			.parent_hws = (const struct clk_hw*[]){
2315				&disp0_cc_mdss_esc0_clk_src.clkr.hw,
2316			},
2317			.num_parents = 1,
2318			.flags = CLK_SET_RATE_PARENT,
2319			.ops = &clk_branch2_ops,
2320		},
2321	},
2322};
2323
2324static struct clk_branch disp1_cc_mdss_esc0_clk = {
2325	.halt_reg = 0x2054,
2326	.halt_check = BRANCH_HALT,
2327	.clkr = {
2328		.enable_reg = 0x2054,
2329		.enable_mask = BIT(0),
2330		.hw.init = &(const struct clk_init_data) {
2331			.name = "disp1_cc_mdss_esc0_clk",
2332			.parent_hws = (const struct clk_hw*[]){
2333				&disp1_cc_mdss_esc0_clk_src.clkr.hw,
2334			},
2335			.num_parents = 1,
2336			.flags = CLK_SET_RATE_PARENT,
2337			.ops = &clk_branch2_ops,
2338		},
2339	},
2340};
2341
2342static struct clk_branch disp0_cc_mdss_esc1_clk = {
2343	.halt_reg = 0x2058,
2344	.halt_check = BRANCH_HALT,
2345	.clkr = {
2346		.enable_reg = 0x2058,
2347		.enable_mask = BIT(0),
2348		.hw.init = &(const struct clk_init_data) {
2349			.name = "disp0_cc_mdss_esc1_clk",
2350			.parent_hws = (const struct clk_hw*[]){
2351				&disp0_cc_mdss_esc1_clk_src.clkr.hw,
2352			},
2353			.num_parents = 1,
2354			.flags = CLK_SET_RATE_PARENT,
2355			.ops = &clk_branch2_ops,
2356		},
2357	},
2358};
2359
2360static struct clk_branch disp1_cc_mdss_esc1_clk = {
2361	.halt_reg = 0x2058,
2362	.halt_check = BRANCH_HALT,
2363	.clkr = {
2364		.enable_reg = 0x2058,
2365		.enable_mask = BIT(0),
2366		.hw.init = &(const struct clk_init_data) {
2367			.name = "disp1_cc_mdss_esc1_clk",
2368			.parent_hws = (const struct clk_hw*[]){
2369				&disp1_cc_mdss_esc1_clk_src.clkr.hw,
2370			},
2371			.num_parents = 1,
2372			.flags = CLK_SET_RATE_PARENT,
2373			.ops = &clk_branch2_ops,
2374		},
2375	},
2376};
2377
2378static struct clk_branch disp0_cc_mdss_mdp1_clk = {
2379	.halt_reg = 0x2014,
2380	.halt_check = BRANCH_HALT,
2381	.clkr = {
2382		.enable_reg = 0x2014,
2383		.enable_mask = BIT(0),
2384		.hw.init = &(const struct clk_init_data) {
2385			.name = "disp0_cc_mdss_mdp1_clk",
2386			.parent_hws = (const struct clk_hw*[]){
2387				&disp0_cc_mdss_mdp_clk_src.clkr.hw,
2388			},
2389			.num_parents = 1,
2390			.flags = CLK_SET_RATE_PARENT,
2391			.ops = &clk_branch2_ops,
2392		},
2393	},
2394};
2395
2396static struct clk_branch disp1_cc_mdss_mdp1_clk = {
2397	.halt_reg = 0x2014,
2398	.halt_check = BRANCH_HALT,
2399	.clkr = {
2400		.enable_reg = 0x2014,
2401		.enable_mask = BIT(0),
2402		.hw.init = &(const struct clk_init_data) {
2403			.name = "disp1_cc_mdss_mdp1_clk",
2404			.parent_hws = (const struct clk_hw*[]){
2405				&disp1_cc_mdss_mdp_clk_src.clkr.hw,
2406			},
2407			.num_parents = 1,
2408			.flags = CLK_SET_RATE_PARENT,
2409			.ops = &clk_branch2_ops,
2410		},
2411	},
2412};
2413
2414static struct clk_branch disp0_cc_mdss_mdp_clk = {
2415	.halt_reg = 0x200c,
2416	.halt_check = BRANCH_HALT,
2417	.clkr = {
2418		.enable_reg = 0x200c,
2419		.enable_mask = BIT(0),
2420		.hw.init = &(const struct clk_init_data) {
2421			.name = "disp0_cc_mdss_mdp_clk",
2422			.parent_hws = (const struct clk_hw*[]){
2423				&disp0_cc_mdss_mdp_clk_src.clkr.hw,
2424			},
2425			.num_parents = 1,
2426			.flags = CLK_SET_RATE_PARENT,
2427			.ops = &clk_branch2_ops,
2428		},
2429	},
2430};
2431
2432static struct clk_branch disp1_cc_mdss_mdp_clk = {
2433	.halt_reg = 0x200c,
2434	.halt_check = BRANCH_HALT,
2435	.clkr = {
2436		.enable_reg = 0x200c,
2437		.enable_mask = BIT(0),
2438		.hw.init = &(const struct clk_init_data) {
2439			.name = "disp1_cc_mdss_mdp_clk",
2440			.parent_hws = (const struct clk_hw*[]){
2441				&disp1_cc_mdss_mdp_clk_src.clkr.hw,
2442			},
2443			.num_parents = 1,
2444			.flags = CLK_SET_RATE_PARENT,
2445			.ops = &clk_branch2_ops,
2446		},
2447	},
2448};
2449
2450static struct clk_branch disp0_cc_mdss_mdp_lut1_clk = {
2451	.halt_reg = 0x2034,
2452	.halt_check = BRANCH_HALT,
2453	.clkr = {
2454		.enable_reg = 0x2034,
2455		.enable_mask = BIT(0),
2456		.hw.init = &(const struct clk_init_data) {
2457			.name = "disp0_cc_mdss_mdp_lut1_clk",
2458			.parent_hws = (const struct clk_hw*[]){
2459				&disp0_cc_mdss_mdp_clk_src.clkr.hw,
2460			},
2461			.num_parents = 1,
2462			.flags = CLK_SET_RATE_PARENT,
2463			.ops = &clk_branch2_ops,
2464		},
2465	},
2466};
2467
2468static struct clk_branch disp1_cc_mdss_mdp_lut1_clk = {
2469	.halt_reg = 0x2034,
2470	.halt_check = BRANCH_HALT,
2471	.clkr = {
2472		.enable_reg = 0x2034,
2473		.enable_mask = BIT(0),
2474		.hw.init = &(const struct clk_init_data) {
2475			.name = "disp1_cc_mdss_mdp_lut1_clk",
2476			.parent_hws = (const struct clk_hw*[]){
2477				&disp1_cc_mdss_mdp_clk_src.clkr.hw,
2478			},
2479			.num_parents = 1,
2480			.flags = CLK_SET_RATE_PARENT,
2481			.ops = &clk_branch2_ops,
2482		},
2483	},
2484};
2485
2486static struct clk_branch disp0_cc_mdss_mdp_lut_clk = {
2487	.halt_reg = 0x202c,
2488	.halt_check = BRANCH_HALT_VOTED,
2489	.clkr = {
2490		.enable_reg = 0x202c,
2491		.enable_mask = BIT(0),
2492		.hw.init = &(const struct clk_init_data) {
2493			.name = "disp0_cc_mdss_mdp_lut_clk",
2494			.parent_hws = (const struct clk_hw*[]){
2495				&disp0_cc_mdss_mdp_clk_src.clkr.hw,
2496			},
2497			.num_parents = 1,
2498			.flags = CLK_SET_RATE_PARENT,
2499			.ops = &clk_branch2_ops,
2500		},
2501	},
2502};
2503
2504static struct clk_branch disp1_cc_mdss_mdp_lut_clk = {
2505	.halt_reg = 0x202c,
2506	.halt_check = BRANCH_HALT_VOTED,
2507	.clkr = {
2508		.enable_reg = 0x202c,
2509		.enable_mask = BIT(0),
2510		.hw.init = &(const struct clk_init_data) {
2511			.name = "disp1_cc_mdss_mdp_lut_clk",
2512			.parent_hws = (const struct clk_hw*[]){
2513				&disp1_cc_mdss_mdp_clk_src.clkr.hw,
2514			},
2515			.num_parents = 1,
2516			.flags = CLK_SET_RATE_PARENT,
2517			.ops = &clk_branch2_ops,
2518		},
2519	},
2520};
2521
2522static struct clk_branch disp0_cc_mdss_non_gdsc_ahb_clk = {
2523	.halt_reg = 0x4004,
2524	.halt_check = BRANCH_HALT_VOTED,
2525	.clkr = {
2526		.enable_reg = 0x4004,
2527		.enable_mask = BIT(0),
2528		.hw.init = &(const struct clk_init_data) {
2529			.name = "disp0_cc_mdss_non_gdsc_ahb_clk",
2530			.parent_hws = (const struct clk_hw*[]){
2531				&disp0_cc_mdss_ahb_clk_src.clkr.hw,
2532			},
2533			.num_parents = 1,
2534			.flags = CLK_SET_RATE_PARENT,
2535			.ops = &clk_branch2_ops,
2536		},
2537	},
2538};
2539
2540static struct clk_branch disp1_cc_mdss_non_gdsc_ahb_clk = {
2541	.halt_reg = 0x4004,
2542	.halt_check = BRANCH_HALT_VOTED,
2543	.clkr = {
2544		.enable_reg = 0x4004,
2545		.enable_mask = BIT(0),
2546		.hw.init = &(const struct clk_init_data) {
2547			.name = "disp1_cc_mdss_non_gdsc_ahb_clk",
2548			.parent_hws = (const struct clk_hw*[]){
2549				&disp1_cc_mdss_ahb_clk_src.clkr.hw,
2550			},
2551			.num_parents = 1,
2552			.flags = CLK_SET_RATE_PARENT,
2553			.ops = &clk_branch2_ops,
2554		},
2555	},
2556};
2557
2558static struct clk_branch disp0_cc_mdss_pclk0_clk = {
2559	.halt_reg = 0x2004,
2560	.halt_check = BRANCH_HALT,
2561	.clkr = {
2562		.enable_reg = 0x2004,
2563		.enable_mask = BIT(0),
2564		.hw.init = &(const struct clk_init_data) {
2565			.name = "disp0_cc_mdss_pclk0_clk",
2566			.parent_hws = (const struct clk_hw*[]){
2567				&disp0_cc_mdss_pclk0_clk_src.clkr.hw,
2568			},
2569			.num_parents = 1,
2570			.flags = CLK_SET_RATE_PARENT,
2571			.ops = &clk_branch2_ops,
2572		},
2573	},
2574};
2575
2576static struct clk_branch disp1_cc_mdss_pclk0_clk = {
2577	.halt_reg = 0x2004,
2578	.halt_check = BRANCH_HALT,
2579	.clkr = {
2580		.enable_reg = 0x2004,
2581		.enable_mask = BIT(0),
2582		.hw.init = &(const struct clk_init_data) {
2583			.name = "disp1_cc_mdss_pclk0_clk",
2584			.parent_hws = (const struct clk_hw*[]){
2585				&disp1_cc_mdss_pclk0_clk_src.clkr.hw,
2586			},
2587			.num_parents = 1,
2588			.flags = CLK_SET_RATE_PARENT,
2589			.ops = &clk_branch2_ops,
2590		},
2591	},
2592};
2593
2594static struct clk_branch disp0_cc_mdss_pclk1_clk = {
2595	.halt_reg = 0x2008,
2596	.halt_check = BRANCH_HALT,
2597	.clkr = {
2598		.enable_reg = 0x2008,
2599		.enable_mask = BIT(0),
2600		.hw.init = &(const struct clk_init_data) {
2601			.name = "disp0_cc_mdss_pclk1_clk",
2602			.parent_hws = (const struct clk_hw*[]){
2603				&disp0_cc_mdss_pclk1_clk_src.clkr.hw,
2604			},
2605			.num_parents = 1,
2606			.flags = CLK_SET_RATE_PARENT,
2607			.ops = &clk_branch2_ops,
2608		},
2609	},
2610};
2611
2612static struct clk_branch disp1_cc_mdss_pclk1_clk = {
2613	.halt_reg = 0x2008,
2614	.halt_check = BRANCH_HALT,
2615	.clkr = {
2616		.enable_reg = 0x2008,
2617		.enable_mask = BIT(0),
2618		.hw.init = &(const struct clk_init_data) {
2619			.name = "disp1_cc_mdss_pclk1_clk",
2620			.parent_hws = (const struct clk_hw*[]){
2621				&disp1_cc_mdss_pclk1_clk_src.clkr.hw,
2622			},
2623			.num_parents = 1,
2624			.flags = CLK_SET_RATE_PARENT,
2625			.ops = &clk_branch2_ops,
2626		},
2627	},
2628};
2629
2630static struct clk_branch disp0_cc_mdss_rot1_clk = {
2631	.halt_reg = 0x2024,
2632	.halt_check = BRANCH_HALT,
2633	.clkr = {
2634		.enable_reg = 0x2024,
2635		.enable_mask = BIT(0),
2636		.hw.init = &(const struct clk_init_data) {
2637			.name = "disp0_cc_mdss_rot1_clk",
2638			.parent_hws = (const struct clk_hw*[]){
2639				&disp0_cc_mdss_rot_clk_src.clkr.hw,
2640			},
2641			.num_parents = 1,
2642			.flags = CLK_SET_RATE_PARENT,
2643			.ops = &clk_branch2_ops,
2644		},
2645	},
2646};
2647
2648static struct clk_branch disp1_cc_mdss_rot1_clk = {
2649	.halt_reg = 0x2024,
2650	.halt_check = BRANCH_HALT,
2651	.clkr = {
2652		.enable_reg = 0x2024,
2653		.enable_mask = BIT(0),
2654		.hw.init = &(const struct clk_init_data) {
2655			.name = "disp1_cc_mdss_rot1_clk",
2656			.parent_hws = (const struct clk_hw*[]){
2657				&disp1_cc_mdss_rot_clk_src.clkr.hw,
2658			},
2659			.num_parents = 1,
2660			.flags = CLK_SET_RATE_PARENT,
2661			.ops = &clk_branch2_ops,
2662		},
2663	},
2664};
2665
2666static struct clk_branch disp0_cc_mdss_rot_clk = {
2667	.halt_reg = 0x201c,
2668	.halt_check = BRANCH_HALT,
2669	.clkr = {
2670		.enable_reg = 0x201c,
2671		.enable_mask = BIT(0),
2672		.hw.init = &(const struct clk_init_data) {
2673			.name = "disp0_cc_mdss_rot_clk",
2674			.parent_hws = (const struct clk_hw*[]){
2675				&disp0_cc_mdss_rot_clk_src.clkr.hw,
2676			},
2677			.num_parents = 1,
2678			.flags = CLK_SET_RATE_PARENT,
2679			.ops = &clk_branch2_ops,
2680		},
2681	},
2682};
2683
2684static struct clk_branch disp1_cc_mdss_rot_clk = {
2685	.halt_reg = 0x201c,
2686	.halt_check = BRANCH_HALT,
2687	.clkr = {
2688		.enable_reg = 0x201c,
2689		.enable_mask = BIT(0),
2690		.hw.init = &(const struct clk_init_data) {
2691			.name = "disp1_cc_mdss_rot_clk",
2692			.parent_hws = (const struct clk_hw*[]){
2693				&disp1_cc_mdss_rot_clk_src.clkr.hw,
2694			},
2695			.num_parents = 1,
2696			.flags = CLK_SET_RATE_PARENT,
2697			.ops = &clk_branch2_ops,
2698		},
2699	},
2700};
2701
2702static struct clk_branch disp0_cc_mdss_rscc_ahb_clk = {
2703	.halt_reg = 0x400c,
2704	.halt_check = BRANCH_HALT,
2705	.clkr = {
2706		.enable_reg = 0x400c,
2707		.enable_mask = BIT(0),
2708		.hw.init = &(const struct clk_init_data) {
2709			.name = "disp0_cc_mdss_rscc_ahb_clk",
2710			.parent_hws = (const struct clk_hw*[]){
2711				&disp0_cc_mdss_ahb_clk_src.clkr.hw,
2712			},
2713			.num_parents = 1,
2714			.flags = CLK_SET_RATE_PARENT,
2715			.ops = &clk_branch2_ops,
2716		},
2717	},
2718};
2719
2720static struct clk_branch disp1_cc_mdss_rscc_ahb_clk = {
2721	.halt_reg = 0x400c,
2722	.halt_check = BRANCH_HALT,
2723	.clkr = {
2724		.enable_reg = 0x400c,
2725		.enable_mask = BIT(0),
2726		.hw.init = &(const struct clk_init_data) {
2727			.name = "disp1_cc_mdss_rscc_ahb_clk",
2728			.parent_hws = (const struct clk_hw*[]){
2729				&disp1_cc_mdss_ahb_clk_src.clkr.hw,
2730			},
2731			.num_parents = 1,
2732			.flags = CLK_SET_RATE_PARENT,
2733			.ops = &clk_branch2_ops,
2734		},
2735	},
2736};
2737
2738static struct clk_branch disp0_cc_mdss_rscc_vsync_clk = {
2739	.halt_reg = 0x4008,
2740	.halt_check = BRANCH_HALT,
2741	.clkr = {
2742		.enable_reg = 0x4008,
2743		.enable_mask = BIT(0),
2744		.hw.init = &(const struct clk_init_data) {
2745			.name = "disp0_cc_mdss_rscc_vsync_clk",
2746			.parent_hws = (const struct clk_hw*[]){
2747				&disp0_cc_mdss_vsync_clk_src.clkr.hw,
2748			},
2749			.num_parents = 1,
2750			.flags = CLK_SET_RATE_PARENT,
2751			.ops = &clk_branch2_ops,
2752		},
2753	},
2754};
2755
2756static struct clk_branch disp1_cc_mdss_rscc_vsync_clk = {
2757	.halt_reg = 0x4008,
2758	.halt_check = BRANCH_HALT,
2759	.clkr = {
2760		.enable_reg = 0x4008,
2761		.enable_mask = BIT(0),
2762		.hw.init = &(const struct clk_init_data) {
2763			.name = "disp1_cc_mdss_rscc_vsync_clk",
2764			.parent_hws = (const struct clk_hw*[]){
2765				&disp1_cc_mdss_vsync_clk_src.clkr.hw,
2766			},
2767			.num_parents = 1,
2768			.flags = CLK_SET_RATE_PARENT,
2769			.ops = &clk_branch2_ops,
2770		},
2771	},
2772};
2773
2774static struct clk_branch disp0_cc_mdss_vsync1_clk = {
2775	.halt_reg = 0x2040,
2776	.halt_check = BRANCH_HALT,
2777	.clkr = {
2778		.enable_reg = 0x2040,
2779		.enable_mask = BIT(0),
2780		.hw.init = &(const struct clk_init_data) {
2781			.name = "disp0_cc_mdss_vsync1_clk",
2782			.parent_hws = (const struct clk_hw*[]){
2783				&disp0_cc_mdss_vsync_clk_src.clkr.hw,
2784			},
2785			.num_parents = 1,
2786			.flags = CLK_SET_RATE_PARENT,
2787			.ops = &clk_branch2_ops,
2788		},
2789	},
2790};
2791
2792static struct clk_branch disp1_cc_mdss_vsync1_clk = {
2793	.halt_reg = 0x2040,
2794	.halt_check = BRANCH_HALT,
2795	.clkr = {
2796		.enable_reg = 0x2040,
2797		.enable_mask = BIT(0),
2798		.hw.init = &(const struct clk_init_data) {
2799			.name = "disp1_cc_mdss_vsync1_clk",
2800			.parent_hws = (const struct clk_hw*[]){
2801				&disp1_cc_mdss_vsync_clk_src.clkr.hw,
2802			},
2803			.num_parents = 1,
2804			.flags = CLK_SET_RATE_PARENT,
2805			.ops = &clk_branch2_ops,
2806		},
2807	},
2808};
2809
2810static struct clk_branch disp0_cc_mdss_vsync_clk = {
2811	.halt_reg = 0x203c,
2812	.halt_check = BRANCH_HALT,
2813	.clkr = {
2814		.enable_reg = 0x203c,
2815		.enable_mask = BIT(0),
2816		.hw.init = &(const struct clk_init_data) {
2817			.name = "disp0_cc_mdss_vsync_clk",
2818			.parent_hws = (const struct clk_hw*[]){
2819				&disp0_cc_mdss_vsync_clk_src.clkr.hw,
2820			},
2821			.num_parents = 1,
2822			.flags = CLK_SET_RATE_PARENT,
2823			.ops = &clk_branch2_ops,
2824		},
2825	},
2826};
2827
2828static struct clk_branch disp1_cc_mdss_vsync_clk = {
2829	.halt_reg = 0x203c,
2830	.halt_check = BRANCH_HALT,
2831	.clkr = {
2832		.enable_reg = 0x203c,
2833		.enable_mask = BIT(0),
2834		.hw.init = &(const struct clk_init_data) {
2835			.name = "disp1_cc_mdss_vsync_clk",
2836			.parent_hws = (const struct clk_hw*[]){
2837				&disp1_cc_mdss_vsync_clk_src.clkr.hw,
2838			},
2839			.num_parents = 1,
2840			.flags = CLK_SET_RATE_PARENT,
2841			.ops = &clk_branch2_ops,
2842		},
2843	},
2844};
2845
2846static struct clk_branch disp0_cc_sleep_clk = {
2847	.halt_reg = 0x6078,
2848	.halt_check = BRANCH_HALT,
2849	.clkr = {
2850		.enable_reg = 0x6078,
2851		.enable_mask = BIT(0),
2852		.hw.init = &(const struct clk_init_data) {
2853			.name = "disp0_cc_sleep_clk",
2854			.parent_hws = (const struct clk_hw*[]){
2855				&disp0_cc_sleep_clk_src.clkr.hw,
2856			},
2857			.num_parents = 1,
2858			.flags = CLK_SET_RATE_PARENT,
2859			.ops = &clk_branch2_ops,
2860		},
2861	},
2862};
2863
2864static struct clk_branch disp1_cc_sleep_clk = {
2865	.halt_reg = 0x6078,
2866	.halt_check = BRANCH_HALT,
2867	.clkr = {
2868		.enable_reg = 0x6078,
2869		.enable_mask = BIT(0),
2870		.hw.init = &(const struct clk_init_data) {
2871			.name = "disp1_cc_sleep_clk",
2872			.parent_hws = (const struct clk_hw*[]){
2873				&disp1_cc_sleep_clk_src.clkr.hw,
2874			},
2875			.num_parents = 1,
2876			.flags = CLK_SET_RATE_PARENT,
2877			.ops = &clk_branch2_ops,
2878		},
2879	},
2880};
2881
2882static struct clk_regmap *disp0_cc_sc8280xp_clocks[] = {
2883	[DISP_CC_MDSS_AHB1_CLK] = &disp0_cc_mdss_ahb1_clk.clkr,
2884	[DISP_CC_MDSS_AHB_CLK] = &disp0_cc_mdss_ahb_clk.clkr,
2885	[DISP_CC_MDSS_AHB_CLK_SRC] = &disp0_cc_mdss_ahb_clk_src.clkr,
2886	[DISP_CC_MDSS_BYTE0_CLK] = &disp0_cc_mdss_byte0_clk.clkr,
2887	[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp0_cc_mdss_byte0_clk_src.clkr,
2888	[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp0_cc_mdss_byte0_div_clk_src.clkr,
2889	[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp0_cc_mdss_byte0_intf_clk.clkr,
2890	[DISP_CC_MDSS_BYTE1_CLK] = &disp0_cc_mdss_byte1_clk.clkr,
2891	[DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp0_cc_mdss_byte1_clk_src.clkr,
2892	[DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp0_cc_mdss_byte1_div_clk_src.clkr,
2893	[DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp0_cc_mdss_byte1_intf_clk.clkr,
2894	[DISP_CC_MDSS_DPTX0_AUX_CLK] = &disp0_cc_mdss_dptx0_aux_clk.clkr,
2895	[DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &disp0_cc_mdss_dptx0_aux_clk_src.clkr,
2896	[DISP_CC_MDSS_DPTX0_LINK_CLK] = &disp0_cc_mdss_dptx0_link_clk.clkr,
2897	[DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &disp0_cc_mdss_dptx0_link_clk_src.clkr,
2898	[DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] = &disp0_cc_mdss_dptx0_link_div_clk_src.clkr,
2899	[DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &disp0_cc_mdss_dptx0_link_intf_clk.clkr,
2900	[DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &disp0_cc_mdss_dptx0_pixel0_clk.clkr,
2901	[DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &disp0_cc_mdss_dptx0_pixel0_clk_src.clkr,
2902	[DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp0_cc_mdss_dptx0_pixel1_clk.clkr,
2903	[DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp0_cc_mdss_dptx0_pixel1_clk_src.clkr,
2904	[DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] = &disp0_cc_mdss_dptx0_usb_router_link_intf_clk.clkr,
2905	[DISP_CC_MDSS_DPTX1_AUX_CLK] = &disp0_cc_mdss_dptx1_aux_clk.clkr,
2906	[DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &disp0_cc_mdss_dptx1_aux_clk_src.clkr,
2907	[DISP_CC_MDSS_DPTX1_LINK_CLK] = &disp0_cc_mdss_dptx1_link_clk.clkr,
2908	[DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &disp0_cc_mdss_dptx1_link_clk_src.clkr,
2909	[DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] = &disp0_cc_mdss_dptx1_link_div_clk_src.clkr,
2910	[DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &disp0_cc_mdss_dptx1_link_intf_clk.clkr,
2911	[DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &disp0_cc_mdss_dptx1_pixel0_clk.clkr,
2912	[DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &disp0_cc_mdss_dptx1_pixel0_clk_src.clkr,
2913	[DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &disp0_cc_mdss_dptx1_pixel1_clk.clkr,
2914	[DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &disp0_cc_mdss_dptx1_pixel1_clk_src.clkr,
2915	[DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] = &disp0_cc_mdss_dptx1_usb_router_link_intf_clk.clkr,
2916	[DISP_CC_MDSS_DPTX2_AUX_CLK] = &disp0_cc_mdss_dptx2_aux_clk.clkr,
2917	[DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] = &disp0_cc_mdss_dptx2_aux_clk_src.clkr,
2918	[DISP_CC_MDSS_DPTX2_LINK_CLK] = &disp0_cc_mdss_dptx2_link_clk.clkr,
2919	[DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] = &disp0_cc_mdss_dptx2_link_clk_src.clkr,
2920	[DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] = &disp0_cc_mdss_dptx2_link_div_clk_src.clkr,
2921	[DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] = &disp0_cc_mdss_dptx2_link_intf_clk.clkr,
2922	[DISP_CC_MDSS_DPTX2_PIXEL0_CLK] = &disp0_cc_mdss_dptx2_pixel0_clk.clkr,
2923	[DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] = &disp0_cc_mdss_dptx2_pixel0_clk_src.clkr,
2924	[DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &disp0_cc_mdss_dptx2_pixel1_clk.clkr,
2925	[DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &disp0_cc_mdss_dptx2_pixel1_clk_src.clkr,
2926	[DISP_CC_MDSS_DPTX3_AUX_CLK] = &disp0_cc_mdss_dptx3_aux_clk.clkr,
2927	[DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] = &disp0_cc_mdss_dptx3_aux_clk_src.clkr,
2928	[DISP_CC_MDSS_DPTX3_LINK_CLK] = &disp0_cc_mdss_dptx3_link_clk.clkr,
2929	[DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] = &disp0_cc_mdss_dptx3_link_clk_src.clkr,
2930	[DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] = &disp0_cc_mdss_dptx3_link_div_clk_src.clkr,
2931	[DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] = &disp0_cc_mdss_dptx3_link_intf_clk.clkr,
2932	[DISP_CC_MDSS_DPTX3_PIXEL0_CLK] = &disp0_cc_mdss_dptx3_pixel0_clk.clkr,
2933	[DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] = &disp0_cc_mdss_dptx3_pixel0_clk_src.clkr,
2934	[DISP_CC_MDSS_ESC0_CLK] = &disp0_cc_mdss_esc0_clk.clkr,
2935	[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp0_cc_mdss_esc0_clk_src.clkr,
2936	[DISP_CC_MDSS_ESC1_CLK] = &disp0_cc_mdss_esc1_clk.clkr,
2937	[DISP_CC_MDSS_ESC1_CLK_SRC] = &disp0_cc_mdss_esc1_clk_src.clkr,
2938	[DISP_CC_MDSS_MDP1_CLK] = &disp0_cc_mdss_mdp1_clk.clkr,
2939	[DISP_CC_MDSS_MDP_CLK] = &disp0_cc_mdss_mdp_clk.clkr,
2940	[DISP_CC_MDSS_MDP_CLK_SRC] = &disp0_cc_mdss_mdp_clk_src.clkr,
2941	[DISP_CC_MDSS_MDP_LUT1_CLK] = &disp0_cc_mdss_mdp_lut1_clk.clkr,
2942	[DISP_CC_MDSS_MDP_LUT_CLK] = &disp0_cc_mdss_mdp_lut_clk.clkr,
2943	[DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp0_cc_mdss_non_gdsc_ahb_clk.clkr,
2944	[DISP_CC_MDSS_PCLK0_CLK] = &disp0_cc_mdss_pclk0_clk.clkr,
2945	[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp0_cc_mdss_pclk0_clk_src.clkr,
2946	[DISP_CC_MDSS_PCLK1_CLK] = &disp0_cc_mdss_pclk1_clk.clkr,
2947	[DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp0_cc_mdss_pclk1_clk_src.clkr,
2948	[DISP_CC_MDSS_ROT1_CLK] = &disp0_cc_mdss_rot1_clk.clkr,
2949	[DISP_CC_MDSS_ROT_CLK] = &disp0_cc_mdss_rot_clk.clkr,
2950	[DISP_CC_MDSS_ROT_CLK_SRC] = &disp0_cc_mdss_rot_clk_src.clkr,
2951	[DISP_CC_MDSS_RSCC_AHB_CLK] = &disp0_cc_mdss_rscc_ahb_clk.clkr,
2952	[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp0_cc_mdss_rscc_vsync_clk.clkr,
2953	[DISP_CC_MDSS_VSYNC1_CLK] = &disp0_cc_mdss_vsync1_clk.clkr,
2954	[DISP_CC_MDSS_VSYNC_CLK] = &disp0_cc_mdss_vsync_clk.clkr,
2955	[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp0_cc_mdss_vsync_clk_src.clkr,
2956	[DISP_CC_PLL0] = &disp0_cc_pll0.clkr,
2957	[DISP_CC_PLL1] = &disp0_cc_pll1.clkr,
2958	[DISP_CC_PLL1_OUT_EVEN] = &disp0_cc_pll1_out_even.clkr,
2959	[DISP_CC_PLL2] = &disp0_cc_pll2.clkr,
2960	[DISP_CC_SLEEP_CLK] = &disp0_cc_sleep_clk.clkr,
2961	[DISP_CC_SLEEP_CLK_SRC] = &disp0_cc_sleep_clk_src.clkr,
2962};
2963
2964static struct clk_regmap *disp1_cc_sc8280xp_clocks[] = {
2965	[DISP_CC_MDSS_AHB1_CLK] = &disp1_cc_mdss_ahb1_clk.clkr,
2966	[DISP_CC_MDSS_AHB_CLK] = &disp1_cc_mdss_ahb_clk.clkr,
2967	[DISP_CC_MDSS_AHB_CLK_SRC] = &disp1_cc_mdss_ahb_clk_src.clkr,
2968	[DISP_CC_MDSS_BYTE0_CLK] = &disp1_cc_mdss_byte0_clk.clkr,
2969	[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp1_cc_mdss_byte0_clk_src.clkr,
2970	[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp1_cc_mdss_byte0_div_clk_src.clkr,
2971	[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp1_cc_mdss_byte0_intf_clk.clkr,
2972	[DISP_CC_MDSS_BYTE1_CLK] = &disp1_cc_mdss_byte1_clk.clkr,
2973	[DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp1_cc_mdss_byte1_clk_src.clkr,
2974	[DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp1_cc_mdss_byte1_div_clk_src.clkr,
2975	[DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp1_cc_mdss_byte1_intf_clk.clkr,
2976	[DISP_CC_MDSS_DPTX0_AUX_CLK] = &disp1_cc_mdss_dptx0_aux_clk.clkr,
2977	[DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &disp1_cc_mdss_dptx0_aux_clk_src.clkr,
2978	[DISP_CC_MDSS_DPTX0_LINK_CLK] = &disp1_cc_mdss_dptx0_link_clk.clkr,
2979	[DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &disp1_cc_mdss_dptx0_link_clk_src.clkr,
2980	[DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] = &disp1_cc_mdss_dptx0_link_div_clk_src.clkr,
2981	[DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &disp1_cc_mdss_dptx0_link_intf_clk.clkr,
2982	[DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &disp1_cc_mdss_dptx0_pixel0_clk.clkr,
2983	[DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &disp1_cc_mdss_dptx0_pixel0_clk_src.clkr,
2984	[DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp1_cc_mdss_dptx0_pixel1_clk.clkr,
2985	[DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp1_cc_mdss_dptx0_pixel1_clk_src.clkr,
2986	[DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] = &disp1_cc_mdss_dptx0_usb_router_link_intf_clk.clkr,
2987	[DISP_CC_MDSS_DPTX1_AUX_CLK] = &disp1_cc_mdss_dptx1_aux_clk.clkr,
2988	[DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &disp1_cc_mdss_dptx1_aux_clk_src.clkr,
2989	[DISP_CC_MDSS_DPTX1_LINK_CLK] = &disp1_cc_mdss_dptx1_link_clk.clkr,
2990	[DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &disp1_cc_mdss_dptx1_link_clk_src.clkr,
2991	[DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] = &disp1_cc_mdss_dptx1_link_div_clk_src.clkr,
2992	[DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &disp1_cc_mdss_dptx1_link_intf_clk.clkr,
2993	[DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &disp1_cc_mdss_dptx1_pixel0_clk.clkr,
2994	[DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &disp1_cc_mdss_dptx1_pixel0_clk_src.clkr,
2995	[DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &disp1_cc_mdss_dptx1_pixel1_clk.clkr,
2996	[DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &disp1_cc_mdss_dptx1_pixel1_clk_src.clkr,
2997	[DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] = &disp1_cc_mdss_dptx1_usb_router_link_intf_clk.clkr,
2998	[DISP_CC_MDSS_DPTX2_AUX_CLK] = &disp1_cc_mdss_dptx2_aux_clk.clkr,
2999	[DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] = &disp1_cc_mdss_dptx2_aux_clk_src.clkr,
3000	[DISP_CC_MDSS_DPTX2_LINK_CLK] = &disp1_cc_mdss_dptx2_link_clk.clkr,
3001	[DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] = &disp1_cc_mdss_dptx2_link_clk_src.clkr,
3002	[DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] = &disp1_cc_mdss_dptx2_link_div_clk_src.clkr,
3003	[DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] = &disp1_cc_mdss_dptx2_link_intf_clk.clkr,
3004	[DISP_CC_MDSS_DPTX2_PIXEL0_CLK] = &disp1_cc_mdss_dptx2_pixel0_clk.clkr,
3005	[DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] = &disp1_cc_mdss_dptx2_pixel0_clk_src.clkr,
3006	[DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &disp1_cc_mdss_dptx2_pixel1_clk.clkr,
3007	[DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &disp1_cc_mdss_dptx2_pixel1_clk_src.clkr,
3008	[DISP_CC_MDSS_DPTX3_AUX_CLK] = &disp1_cc_mdss_dptx3_aux_clk.clkr,
3009	[DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] = &disp1_cc_mdss_dptx3_aux_clk_src.clkr,
3010	[DISP_CC_MDSS_DPTX3_LINK_CLK] = &disp1_cc_mdss_dptx3_link_clk.clkr,
3011	[DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] = &disp1_cc_mdss_dptx3_link_clk_src.clkr,
3012	[DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] = &disp1_cc_mdss_dptx3_link_div_clk_src.clkr,
3013	[DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] = &disp1_cc_mdss_dptx3_link_intf_clk.clkr,
3014	[DISP_CC_MDSS_DPTX3_PIXEL0_CLK] = &disp1_cc_mdss_dptx3_pixel0_clk.clkr,
3015	[DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] = &disp1_cc_mdss_dptx3_pixel0_clk_src.clkr,
3016	[DISP_CC_MDSS_ESC0_CLK] = &disp1_cc_mdss_esc0_clk.clkr,
3017	[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp1_cc_mdss_esc0_clk_src.clkr,
3018	[DISP_CC_MDSS_ESC1_CLK] = &disp1_cc_mdss_esc1_clk.clkr,
3019	[DISP_CC_MDSS_ESC1_CLK_SRC] = &disp1_cc_mdss_esc1_clk_src.clkr,
3020	[DISP_CC_MDSS_MDP1_CLK] = &disp1_cc_mdss_mdp1_clk.clkr,
3021	[DISP_CC_MDSS_MDP_CLK] = &disp1_cc_mdss_mdp_clk.clkr,
3022	[DISP_CC_MDSS_MDP_CLK_SRC] = &disp1_cc_mdss_mdp_clk_src.clkr,
3023	[DISP_CC_MDSS_MDP_LUT1_CLK] = &disp1_cc_mdss_mdp_lut1_clk.clkr,
3024	[DISP_CC_MDSS_MDP_LUT_CLK] = &disp1_cc_mdss_mdp_lut_clk.clkr,
3025	[DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp1_cc_mdss_non_gdsc_ahb_clk.clkr,
3026	[DISP_CC_MDSS_PCLK0_CLK] = &disp1_cc_mdss_pclk0_clk.clkr,
3027	[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp1_cc_mdss_pclk0_clk_src.clkr,
3028	[DISP_CC_MDSS_PCLK1_CLK] = &disp1_cc_mdss_pclk1_clk.clkr,
3029	[DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp1_cc_mdss_pclk1_clk_src.clkr,
3030	[DISP_CC_MDSS_ROT1_CLK] = &disp1_cc_mdss_rot1_clk.clkr,
3031	[DISP_CC_MDSS_ROT_CLK] = &disp1_cc_mdss_rot_clk.clkr,
3032	[DISP_CC_MDSS_ROT_CLK_SRC] = &disp1_cc_mdss_rot_clk_src.clkr,
3033	[DISP_CC_MDSS_RSCC_AHB_CLK] = &disp1_cc_mdss_rscc_ahb_clk.clkr,
3034	[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp1_cc_mdss_rscc_vsync_clk.clkr,
3035	[DISP_CC_MDSS_VSYNC1_CLK] = &disp1_cc_mdss_vsync1_clk.clkr,
3036	[DISP_CC_MDSS_VSYNC_CLK] = &disp1_cc_mdss_vsync_clk.clkr,
3037	[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp1_cc_mdss_vsync_clk_src.clkr,
3038	[DISP_CC_PLL0] = &disp1_cc_pll0.clkr,
3039	[DISP_CC_PLL1] = &disp1_cc_pll1.clkr,
3040	[DISP_CC_PLL1_OUT_EVEN] = &disp1_cc_pll1_out_even.clkr,
3041	[DISP_CC_PLL2] = &disp1_cc_pll2.clkr,
3042	[DISP_CC_SLEEP_CLK] = &disp1_cc_sleep_clk.clkr,
3043	[DISP_CC_SLEEP_CLK_SRC] = &disp1_cc_sleep_clk_src.clkr,
3044};
3045
3046static const struct qcom_reset_map disp_cc_sc8280xp_resets[] = {
3047	[DISP_CC_MDSS_CORE_BCR] = { 0x2000 },
3048	[DISP_CC_MDSS_RSCC_BCR] = { 0x4000 },
3049};
3050
3051static struct gdsc disp0_mdss_gdsc = {
3052	.gdscr = 0x3000,
3053	.en_rest_wait_val = 0x2,
3054	.en_few_wait_val = 0x2,
3055	.clk_dis_wait_val = 0xf,
3056	.pd = {
3057		.name = "disp0_mdss_gdsc",
3058	},
3059	.pwrsts = PWRSTS_OFF_ON,
3060	.flags = HW_CTRL | RETAIN_FF_ENABLE,
3061};
3062
3063static struct gdsc disp1_mdss_gdsc = {
3064	.gdscr = 0x3000,
3065	.en_rest_wait_val = 0x2,
3066	.en_few_wait_val = 0x2,
3067	.clk_dis_wait_val = 0xf,
3068	.pd = {
3069		.name = "disp1_mdss_gdsc",
3070	},
3071	.pwrsts = PWRSTS_OFF_ON,
3072	.flags = HW_CTRL | RETAIN_FF_ENABLE,
3073};
3074
3075static struct gdsc disp0_mdss_int2_gdsc = {
3076	.gdscr = 0xa000,
3077	.en_rest_wait_val = 0x2,
3078	.en_few_wait_val = 0x2,
3079	.clk_dis_wait_val = 0xf,
3080	.pd = {
3081		.name = "disp0_mdss_int2_gdsc",
3082	},
3083	.pwrsts = PWRSTS_OFF_ON,
3084	.flags = HW_CTRL | RETAIN_FF_ENABLE,
3085};
3086
3087static struct gdsc disp1_mdss_int2_gdsc = {
3088	.gdscr = 0xa000,
3089	.en_rest_wait_val = 0x2,
3090	.en_few_wait_val = 0x2,
3091	.clk_dis_wait_val = 0xf,
3092	.pd = {
3093		.name = "disp1_mdss_int2_gdsc",
3094	},
3095	.pwrsts = PWRSTS_OFF_ON,
3096	.flags = HW_CTRL | RETAIN_FF_ENABLE,
3097};
3098
3099static struct gdsc *disp0_cc_sc8280xp_gdscs[] = {
3100	[MDSS_GDSC] = &disp0_mdss_gdsc,
3101	[MDSS_INT2_GDSC] = &disp0_mdss_int2_gdsc,
3102};
3103
3104static struct gdsc *disp1_cc_sc8280xp_gdscs[] = {
3105	[MDSS_GDSC] = &disp1_mdss_gdsc,
3106	[MDSS_INT2_GDSC] = &disp1_mdss_int2_gdsc,
3107};
3108
3109static const struct regmap_config disp_cc_sc8280xp_regmap_config = {
3110	.reg_bits = 32,
3111	.reg_stride = 4,
3112	.val_bits = 32,
3113	.max_register = 0x10000,
3114	.fast_io = true,
3115};
3116
3117static struct qcom_cc_desc disp0_cc_sc8280xp_desc = {
3118	.config = &disp_cc_sc8280xp_regmap_config,
3119	.clks = disp0_cc_sc8280xp_clocks,
3120	.num_clks = ARRAY_SIZE(disp0_cc_sc8280xp_clocks),
3121	.resets = disp_cc_sc8280xp_resets,
3122	.num_resets = ARRAY_SIZE(disp_cc_sc8280xp_resets),
3123	.gdscs = disp0_cc_sc8280xp_gdscs,
3124	.num_gdscs = ARRAY_SIZE(disp0_cc_sc8280xp_gdscs),
3125};
3126
3127static struct qcom_cc_desc disp1_cc_sc8280xp_desc = {
3128	.config = &disp_cc_sc8280xp_regmap_config,
3129	.clks = disp1_cc_sc8280xp_clocks,
3130	.num_clks = ARRAY_SIZE(disp1_cc_sc8280xp_clocks),
3131	.resets = disp_cc_sc8280xp_resets,
3132	.num_resets = ARRAY_SIZE(disp_cc_sc8280xp_resets),
3133	.gdscs = disp1_cc_sc8280xp_gdscs,
3134	.num_gdscs = ARRAY_SIZE(disp1_cc_sc8280xp_gdscs),
3135};
3136
3137#define clkr_to_alpha_clk_pll(_clkr) container_of(_clkr, struct clk_alpha_pll, clkr)
3138
3139static int disp_cc_sc8280xp_probe(struct platform_device *pdev)
3140{
3141	const struct qcom_cc_desc *desc;
3142	struct regmap *regmap;
3143	int ret;
3144
3145	desc = device_get_match_data(&pdev->dev);
3146
3147	ret = devm_pm_runtime_enable(&pdev->dev);
3148	if (ret)
3149		return ret;
3150
3151	ret = devm_pm_clk_create(&pdev->dev);
3152	if (ret)
3153		return ret;
3154
3155	ret = pm_clk_add(&pdev->dev, NULL);
3156	if (ret < 0) {
3157		dev_err(&pdev->dev, "failed to acquire ahb clock\n");
3158		return ret;
3159	}
3160
3161	ret = pm_runtime_resume_and_get(&pdev->dev);
3162	if (ret)
3163		return ret;
3164
3165	regmap = qcom_cc_map(pdev, desc);
3166	if (IS_ERR(regmap)) {
3167		ret = PTR_ERR(regmap);
3168		goto out_pm_runtime_put;
3169	}
3170
3171	clk_lucid_pll_configure(clkr_to_alpha_clk_pll(desc->clks[DISP_CC_PLL0]), regmap, &disp_cc_pll0_config);
3172	clk_lucid_pll_configure(clkr_to_alpha_clk_pll(desc->clks[DISP_CC_PLL1]), regmap, &disp_cc_pll1_config);
3173	clk_lucid_pll_configure(clkr_to_alpha_clk_pll(desc->clks[DISP_CC_PLL2]), regmap, &disp_cc_pll2_config);
3174
3175	ret = qcom_cc_really_probe(pdev, desc, regmap);
3176	if (ret) {
3177		dev_err(&pdev->dev, "Failed to register display clock controller\n");
3178		goto out_pm_runtime_put;
3179	}
3180
3181	/* DISP_CC_XO_CLK always-on */
3182	regmap_update_bits(regmap, 0x605c, BIT(0), BIT(0));
3183
3184out_pm_runtime_put:
3185	pm_runtime_put_sync(&pdev->dev);
3186
3187	return ret;
3188}
3189
3190static const struct of_device_id disp_cc_sc8280xp_match_table[] = {
3191	{ .compatible = "qcom,sc8280xp-dispcc0", .data = &disp0_cc_sc8280xp_desc },
3192	{ .compatible = "qcom,sc8280xp-dispcc1", .data = &disp1_cc_sc8280xp_desc },
3193	{ }
3194};
3195MODULE_DEVICE_TABLE(of, disp_cc_sc8280xp_match_table);
3196
3197static struct platform_driver disp_cc_sc8280xp_driver = {
3198	.probe = disp_cc_sc8280xp_probe,
3199	.driver = {
3200		.name = "disp_cc-sc8280xp",
3201		.of_match_table = disp_cc_sc8280xp_match_table,
3202	},
3203};
3204
3205static int __init disp_cc_sc8280xp_init(void)
3206{
3207	return platform_driver_register(&disp_cc_sc8280xp_driver);
3208}
3209subsys_initcall(disp_cc_sc8280xp_init);
3210
3211static void __exit disp_cc_sc8280xp_exit(void)
3212{
3213	platform_driver_unregister(&disp_cc_sc8280xp_driver);
3214}
3215module_exit(disp_cc_sc8280xp_exit);
3216
3217MODULE_DESCRIPTION("Qualcomm SC8280XP dispcc driver");
3218MODULE_LICENSE("GPL");