1/* SPDX-License-Identifier: GPL-2.0-only */
 2/*
 3 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
 4 */
 5
 6#ifndef __QCOM_CLK_PLL_H__
 7#define __QCOM_CLK_PLL_H__
 8
 9#include <linux/clk-provider.h>
10#include "clk-regmap.h"
11
12/**
13 * struct pll_freq_tbl - PLL frequency table
14 * @l: L value
15 * @m: M value
16 * @n: N value
17 * @ibits: internal values
18 */
19struct pll_freq_tbl {
20	unsigned long freq;
21	u16 l;
22	u16 m;
23	u16 n;
24	u32 ibits;
25};
26
27/**
28 * struct clk_pll - phase locked loop (PLL)
29 * @l_reg: L register
30 * @m_reg: M register
31 * @n_reg: N register
32 * @config_reg: config register
33 * @mode_reg: mode register
34 * @status_reg: status register
35 * @status_bit: ANDed with @status_reg to determine if PLL is enabled
36 * @freq_tbl: PLL frequency table
37 * @hw: handle between common and hardware-specific interfaces
38 */
39struct clk_pll {
40	u32	l_reg;
41	u32	m_reg;
42	u32	n_reg;
43	u32	config_reg;
44	u32	mode_reg;
45	u32	status_reg;
46	u8	status_bit;
47	u8	post_div_width;
48	u8	post_div_shift;
49
50	const struct pll_freq_tbl *freq_tbl;
51
52	struct clk_regmap clkr;
53};
54
55extern const struct clk_ops clk_pll_ops;
56extern const struct clk_ops clk_pll_vote_ops;
57extern const struct clk_ops clk_pll_sr2_ops;
58
59#define to_clk_pll(_hw) container_of(to_clk_regmap(_hw), struct clk_pll, clkr)
60
61struct pll_config {
62	u16 l;
63	u32 m;
64	u32 n;
65	u32 vco_val;
66	u32 vco_mask;
67	u32 pre_div_val;
68	u32 pre_div_mask;
69	u32 post_div_val;
70	u32 post_div_mask;
71	u32 mn_ena_mask;
72	u32 main_output_mask;
73	u32 aux_output_mask;
74};
75
76void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap,
77		const struct pll_config *config, bool fsm_mode);
78void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,
79		const struct pll_config *config, bool fsm_mode);
80
81#endif