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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2015, 2018, 2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7
8#ifndef __QCOM_CLK_ALPHA_PLL_H__
9#define __QCOM_CLK_ALPHA_PLL_H__
10
11#include <linux/clk-provider.h>
12#include "clk-regmap.h"
13
14/* Alpha PLL types */
15enum {
16 CLK_ALPHA_PLL_TYPE_DEFAULT,
17 CLK_ALPHA_PLL_TYPE_HUAYRA,
18 CLK_ALPHA_PLL_TYPE_BRAMMO,
19 CLK_ALPHA_PLL_TYPE_FABIA,
20 CLK_ALPHA_PLL_TYPE_TRION,
21 CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION,
22 CLK_ALPHA_PLL_TYPE_AGERA,
23 CLK_ALPHA_PLL_TYPE_ZONDA,
24 CLK_ALPHA_PLL_TYPE_LUCID_EVO,
25 CLK_ALPHA_PLL_TYPE_LUCID_OLE,
26 CLK_ALPHA_PLL_TYPE_RIVIAN_EVO,
27 CLK_ALPHA_PLL_TYPE_DEFAULT_EVO,
28 CLK_ALPHA_PLL_TYPE_BRAMMO_EVO,
29 CLK_ALPHA_PLL_TYPE_STROMER,
30 CLK_ALPHA_PLL_TYPE_STROMER_PLUS,
31 CLK_ALPHA_PLL_TYPE_MAX,
32};
33
34enum {
35 PLL_OFF_L_VAL,
36 PLL_OFF_CAL_L_VAL,
37 PLL_OFF_ALPHA_VAL,
38 PLL_OFF_ALPHA_VAL_U,
39 PLL_OFF_USER_CTL,
40 PLL_OFF_USER_CTL_U,
41 PLL_OFF_USER_CTL_U1,
42 PLL_OFF_CONFIG_CTL,
43 PLL_OFF_CONFIG_CTL_U,
44 PLL_OFF_CONFIG_CTL_U1,
45 PLL_OFF_TEST_CTL,
46 PLL_OFF_TEST_CTL_U,
47 PLL_OFF_TEST_CTL_U1,
48 PLL_OFF_TEST_CTL_U2,
49 PLL_OFF_STATE,
50 PLL_OFF_STATUS,
51 PLL_OFF_OPMODE,
52 PLL_OFF_FRAC,
53 PLL_OFF_CAL_VAL,
54 PLL_OFF_MAX_REGS
55};
56
57extern const u8 clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_MAX][PLL_OFF_MAX_REGS];
58
59struct pll_vco {
60 unsigned long min_freq;
61 unsigned long max_freq;
62 u32 val;
63};
64
65#define VCO(a, b, c) { \
66 .val = a,\
67 .min_freq = b,\
68 .max_freq = c,\
69}
70
71/**
72 * struct clk_alpha_pll - phase locked loop (PLL)
73 * @offset: base address of registers
74 * @vco_table: array of VCO settings
75 * @regs: alpha pll register map (see @clk_alpha_pll_regs)
76 * @clkr: regmap clock handle
77 */
78struct clk_alpha_pll {
79 u32 offset;
80 const u8 *regs;
81
82 const struct pll_vco *vco_table;
83 size_t num_vco;
84#define SUPPORTS_OFFLINE_REQ BIT(0)
85#define SUPPORTS_FSM_MODE BIT(2)
86#define SUPPORTS_DYNAMIC_UPDATE BIT(3)
87#define SUPPORTS_FSM_LEGACY_MODE BIT(4)
88 u8 flags;
89
90 struct clk_regmap clkr;
91};
92
93/**
94 * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
95 * @offset: base address of registers
96 * @regs: alpha pll register map (see @clk_alpha_pll_regs)
97 * @width: width of post-divider
98 * @post_div_shift: shift to differentiate between odd & even post-divider
99 * @post_div_table: table with PLL odd and even post-divider settings
100 * @num_post_div: Number of PLL post-divider settings
101 *
102 * @clkr: regmap clock handle
103 */
104struct clk_alpha_pll_postdiv {
105 u32 offset;
106 u8 width;
107 const u8 *regs;
108
109 struct clk_regmap clkr;
110 int post_div_shift;
111 const struct clk_div_table *post_div_table;
112 size_t num_post_div;
113};
114
115struct alpha_pll_config {
116 u32 l;
117 u32 alpha;
118 u32 alpha_hi;
119 u32 config_ctl_val;
120 u32 config_ctl_hi_val;
121 u32 config_ctl_hi1_val;
122 u32 user_ctl_val;
123 u32 user_ctl_hi_val;
124 u32 user_ctl_hi1_val;
125 u32 test_ctl_val;
126 u32 test_ctl_mask;
127 u32 test_ctl_hi_val;
128 u32 test_ctl_hi_mask;
129 u32 test_ctl_hi1_val;
130 u32 test_ctl_hi2_val;
131 u32 main_output_mask;
132 u32 aux_output_mask;
133 u32 aux2_output_mask;
134 u32 early_output_mask;
135 u32 alpha_en_mask;
136 u32 alpha_mode_mask;
137 u32 pre_div_val;
138 u32 pre_div_mask;
139 u32 post_div_val;
140 u32 post_div_mask;
141 u32 vco_val;
142 u32 vco_mask;
143 u32 status_val;
144 u32 status_mask;
145 u32 lock_det;
146};
147
148extern const struct clk_ops clk_alpha_pll_ops;
149extern const struct clk_ops clk_alpha_pll_fixed_ops;
150extern const struct clk_ops clk_alpha_pll_hwfsm_ops;
151extern const struct clk_ops clk_alpha_pll_postdiv_ops;
152extern const struct clk_ops clk_alpha_pll_huayra_ops;
153extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops;
154extern const struct clk_ops clk_alpha_pll_stromer_ops;
155extern const struct clk_ops clk_alpha_pll_stromer_plus_ops;
156
157extern const struct clk_ops clk_alpha_pll_fabia_ops;
158extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops;
159extern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops;
160
161extern const struct clk_ops clk_alpha_pll_trion_ops;
162extern const struct clk_ops clk_alpha_pll_fixed_trion_ops;
163extern const struct clk_ops clk_alpha_pll_postdiv_trion_ops;
164
165extern const struct clk_ops clk_alpha_pll_lucid_ops;
166#define clk_alpha_pll_fixed_lucid_ops clk_alpha_pll_fixed_trion_ops
167extern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops;
168extern const struct clk_ops clk_alpha_pll_agera_ops;
169
170extern const struct clk_ops clk_alpha_pll_lucid_5lpe_ops;
171extern const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops;
172extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops;
173
174extern const struct clk_ops clk_alpha_pll_zonda_ops;
175#define clk_alpha_pll_postdiv_zonda_ops clk_alpha_pll_postdiv_fabia_ops
176
177extern const struct clk_ops clk_alpha_pll_lucid_evo_ops;
178extern const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops;
179#define clk_alpha_pll_reset_lucid_ole_ops clk_alpha_pll_reset_lucid_evo_ops
180extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops;
181#define clk_alpha_pll_fixed_lucid_ole_ops clk_alpha_pll_fixed_lucid_evo_ops
182extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops;
183#define clk_alpha_pll_postdiv_lucid_ole_ops clk_alpha_pll_postdiv_lucid_evo_ops
184
185extern const struct clk_ops clk_alpha_pll_rivian_evo_ops;
186#define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_ops
187
188void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
189 const struct alpha_pll_config *config);
190void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
191 const struct alpha_pll_config *config);
192void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
193 const struct alpha_pll_config *config);
194void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
195 const struct alpha_pll_config *config);
196#define clk_lucid_pll_configure(pll, regmap, config) \
197 clk_trion_pll_configure(pll, regmap, config)
198
199void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
200 const struct alpha_pll_config *config);
201void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
202 const struct alpha_pll_config *config);
203void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
204 const struct alpha_pll_config *config);
205void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
206 const struct alpha_pll_config *config);
207void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
208 const struct alpha_pll_config *config);
209
210#endif