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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021, 2023, Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7#include <linux/kernel.h>
8#include <linux/export.h>
9#include <linux/clk-provider.h>
10#include <linux/regmap.h>
11#include <linux/delay.h>
12
13#include "clk-alpha-pll.h"
14#include "common.h"
15
16#define PLL_MODE(p) ((p)->offset + 0x0)
17# define PLL_OUTCTRL BIT(0)
18# define PLL_BYPASSNL BIT(1)
19# define PLL_RESET_N BIT(2)
20# define PLL_OFFLINE_REQ BIT(7)
21# define PLL_LOCK_COUNT_SHIFT 8
22# define PLL_LOCK_COUNT_MASK 0x3f
23# define PLL_BIAS_COUNT_SHIFT 14
24# define PLL_BIAS_COUNT_MASK 0x3f
25# define PLL_VOTE_FSM_ENA BIT(20)
26# define PLL_FSM_ENA BIT(20)
27# define PLL_VOTE_FSM_RESET BIT(21)
28# define PLL_UPDATE BIT(22)
29# define PLL_UPDATE_BYPASS BIT(23)
30# define PLL_FSM_LEGACY_MODE BIT(24)
31# define PLL_OFFLINE_ACK BIT(28)
32# define ALPHA_PLL_ACK_LATCH BIT(29)
33# define PLL_ACTIVE_FLAG BIT(30)
34# define PLL_LOCK_DET BIT(31)
35
36#define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
37#define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL])
38#define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
39#define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])
40
41#define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
42# define PLL_POST_DIV_SHIFT 8
43# define PLL_POST_DIV_MASK(p) GENMASK((p)->width, 0)
44# define PLL_ALPHA_EN BIT(24)
45# define PLL_ALPHA_MODE BIT(25)
46# define PLL_VCO_SHIFT 20
47# define PLL_VCO_MASK 0x3
48
49#define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U])
50#define PLL_USER_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U1])
51
52#define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL])
53#define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U])
54#define PLL_CONFIG_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1])
55#define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
56#define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
57#define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1])
58#define PLL_TEST_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U2])
59#define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS])
60#define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE])
61#define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC])
62
63const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
64 [CLK_ALPHA_PLL_TYPE_DEFAULT] = {
65 [PLL_OFF_L_VAL] = 0x04,
66 [PLL_OFF_ALPHA_VAL] = 0x08,
67 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
68 [PLL_OFF_USER_CTL] = 0x10,
69 [PLL_OFF_USER_CTL_U] = 0x14,
70 [PLL_OFF_CONFIG_CTL] = 0x18,
71 [PLL_OFF_TEST_CTL] = 0x1c,
72 [PLL_OFF_TEST_CTL_U] = 0x20,
73 [PLL_OFF_STATUS] = 0x24,
74 },
75 [CLK_ALPHA_PLL_TYPE_HUAYRA] = {
76 [PLL_OFF_L_VAL] = 0x04,
77 [PLL_OFF_ALPHA_VAL] = 0x08,
78 [PLL_OFF_USER_CTL] = 0x10,
79 [PLL_OFF_CONFIG_CTL] = 0x14,
80 [PLL_OFF_CONFIG_CTL_U] = 0x18,
81 [PLL_OFF_TEST_CTL] = 0x1c,
82 [PLL_OFF_TEST_CTL_U] = 0x20,
83 [PLL_OFF_STATUS] = 0x24,
84 },
85 [CLK_ALPHA_PLL_TYPE_BRAMMO] = {
86 [PLL_OFF_L_VAL] = 0x04,
87 [PLL_OFF_ALPHA_VAL] = 0x08,
88 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
89 [PLL_OFF_USER_CTL] = 0x10,
90 [PLL_OFF_CONFIG_CTL] = 0x18,
91 [PLL_OFF_TEST_CTL] = 0x1c,
92 [PLL_OFF_STATUS] = 0x24,
93 },
94 [CLK_ALPHA_PLL_TYPE_FABIA] = {
95 [PLL_OFF_L_VAL] = 0x04,
96 [PLL_OFF_USER_CTL] = 0x0c,
97 [PLL_OFF_USER_CTL_U] = 0x10,
98 [PLL_OFF_CONFIG_CTL] = 0x14,
99 [PLL_OFF_CONFIG_CTL_U] = 0x18,
100 [PLL_OFF_TEST_CTL] = 0x1c,
101 [PLL_OFF_TEST_CTL_U] = 0x20,
102 [PLL_OFF_STATUS] = 0x24,
103 [PLL_OFF_OPMODE] = 0x2c,
104 [PLL_OFF_FRAC] = 0x38,
105 },
106 [CLK_ALPHA_PLL_TYPE_TRION] = {
107 [PLL_OFF_L_VAL] = 0x04,
108 [PLL_OFF_CAL_L_VAL] = 0x08,
109 [PLL_OFF_USER_CTL] = 0x0c,
110 [PLL_OFF_USER_CTL_U] = 0x10,
111 [PLL_OFF_USER_CTL_U1] = 0x14,
112 [PLL_OFF_CONFIG_CTL] = 0x18,
113 [PLL_OFF_CONFIG_CTL_U] = 0x1c,
114 [PLL_OFF_CONFIG_CTL_U1] = 0x20,
115 [PLL_OFF_TEST_CTL] = 0x24,
116 [PLL_OFF_TEST_CTL_U] = 0x28,
117 [PLL_OFF_TEST_CTL_U1] = 0x2c,
118 [PLL_OFF_STATUS] = 0x30,
119 [PLL_OFF_OPMODE] = 0x38,
120 [PLL_OFF_ALPHA_VAL] = 0x40,
121 },
122 [CLK_ALPHA_PLL_TYPE_AGERA] = {
123 [PLL_OFF_L_VAL] = 0x04,
124 [PLL_OFF_ALPHA_VAL] = 0x08,
125 [PLL_OFF_USER_CTL] = 0x0c,
126 [PLL_OFF_CONFIG_CTL] = 0x10,
127 [PLL_OFF_CONFIG_CTL_U] = 0x14,
128 [PLL_OFF_TEST_CTL] = 0x18,
129 [PLL_OFF_TEST_CTL_U] = 0x1c,
130 [PLL_OFF_STATUS] = 0x2c,
131 },
132 [CLK_ALPHA_PLL_TYPE_ZONDA] = {
133 [PLL_OFF_L_VAL] = 0x04,
134 [PLL_OFF_ALPHA_VAL] = 0x08,
135 [PLL_OFF_USER_CTL] = 0x0c,
136 [PLL_OFF_CONFIG_CTL] = 0x10,
137 [PLL_OFF_CONFIG_CTL_U] = 0x14,
138 [PLL_OFF_CONFIG_CTL_U1] = 0x18,
139 [PLL_OFF_TEST_CTL] = 0x1c,
140 [PLL_OFF_TEST_CTL_U] = 0x20,
141 [PLL_OFF_TEST_CTL_U1] = 0x24,
142 [PLL_OFF_OPMODE] = 0x28,
143 [PLL_OFF_STATUS] = 0x38,
144 },
145 [CLK_ALPHA_PLL_TYPE_LUCID_EVO] = {
146 [PLL_OFF_OPMODE] = 0x04,
147 [PLL_OFF_STATUS] = 0x0c,
148 [PLL_OFF_L_VAL] = 0x10,
149 [PLL_OFF_ALPHA_VAL] = 0x14,
150 [PLL_OFF_USER_CTL] = 0x18,
151 [PLL_OFF_USER_CTL_U] = 0x1c,
152 [PLL_OFF_CONFIG_CTL] = 0x20,
153 [PLL_OFF_CONFIG_CTL_U] = 0x24,
154 [PLL_OFF_CONFIG_CTL_U1] = 0x28,
155 [PLL_OFF_TEST_CTL] = 0x2c,
156 [PLL_OFF_TEST_CTL_U] = 0x30,
157 [PLL_OFF_TEST_CTL_U1] = 0x34,
158 },
159 [CLK_ALPHA_PLL_TYPE_LUCID_OLE] = {
160 [PLL_OFF_OPMODE] = 0x04,
161 [PLL_OFF_STATE] = 0x08,
162 [PLL_OFF_STATUS] = 0x0c,
163 [PLL_OFF_L_VAL] = 0x10,
164 [PLL_OFF_ALPHA_VAL] = 0x14,
165 [PLL_OFF_USER_CTL] = 0x18,
166 [PLL_OFF_USER_CTL_U] = 0x1c,
167 [PLL_OFF_CONFIG_CTL] = 0x20,
168 [PLL_OFF_CONFIG_CTL_U] = 0x24,
169 [PLL_OFF_CONFIG_CTL_U1] = 0x28,
170 [PLL_OFF_TEST_CTL] = 0x2c,
171 [PLL_OFF_TEST_CTL_U] = 0x30,
172 [PLL_OFF_TEST_CTL_U1] = 0x34,
173 [PLL_OFF_TEST_CTL_U2] = 0x38,
174 },
175 [CLK_ALPHA_PLL_TYPE_RIVIAN_EVO] = {
176 [PLL_OFF_OPMODE] = 0x04,
177 [PLL_OFF_STATUS] = 0x0c,
178 [PLL_OFF_L_VAL] = 0x10,
179 [PLL_OFF_USER_CTL] = 0x14,
180 [PLL_OFF_USER_CTL_U] = 0x18,
181 [PLL_OFF_CONFIG_CTL] = 0x1c,
182 [PLL_OFF_CONFIG_CTL_U] = 0x20,
183 [PLL_OFF_CONFIG_CTL_U1] = 0x24,
184 [PLL_OFF_TEST_CTL] = 0x28,
185 [PLL_OFF_TEST_CTL_U] = 0x2c,
186 },
187 [CLK_ALPHA_PLL_TYPE_DEFAULT_EVO] = {
188 [PLL_OFF_L_VAL] = 0x04,
189 [PLL_OFF_ALPHA_VAL] = 0x08,
190 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
191 [PLL_OFF_TEST_CTL] = 0x10,
192 [PLL_OFF_TEST_CTL_U] = 0x14,
193 [PLL_OFF_USER_CTL] = 0x18,
194 [PLL_OFF_USER_CTL_U] = 0x1c,
195 [PLL_OFF_CONFIG_CTL] = 0x20,
196 [PLL_OFF_STATUS] = 0x24,
197 },
198 [CLK_ALPHA_PLL_TYPE_BRAMMO_EVO] = {
199 [PLL_OFF_L_VAL] = 0x04,
200 [PLL_OFF_ALPHA_VAL] = 0x08,
201 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
202 [PLL_OFF_TEST_CTL] = 0x10,
203 [PLL_OFF_TEST_CTL_U] = 0x14,
204 [PLL_OFF_USER_CTL] = 0x18,
205 [PLL_OFF_CONFIG_CTL] = 0x1C,
206 [PLL_OFF_STATUS] = 0x20,
207 },
208 [CLK_ALPHA_PLL_TYPE_STROMER] = {
209 [PLL_OFF_L_VAL] = 0x08,
210 [PLL_OFF_ALPHA_VAL] = 0x10,
211 [PLL_OFF_ALPHA_VAL_U] = 0x14,
212 [PLL_OFF_USER_CTL] = 0x18,
213 [PLL_OFF_USER_CTL_U] = 0x1c,
214 [PLL_OFF_CONFIG_CTL] = 0x20,
215 [PLL_OFF_CONFIG_CTL_U] = 0xff,
216 [PLL_OFF_TEST_CTL] = 0x30,
217 [PLL_OFF_TEST_CTL_U] = 0x34,
218 [PLL_OFF_STATUS] = 0x28,
219 },
220 [CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = {
221 [PLL_OFF_L_VAL] = 0x04,
222 [PLL_OFF_USER_CTL] = 0x08,
223 [PLL_OFF_USER_CTL_U] = 0x0c,
224 [PLL_OFF_CONFIG_CTL] = 0x10,
225 [PLL_OFF_TEST_CTL] = 0x14,
226 [PLL_OFF_TEST_CTL_U] = 0x18,
227 [PLL_OFF_STATUS] = 0x1c,
228 [PLL_OFF_ALPHA_VAL] = 0x24,
229 [PLL_OFF_ALPHA_VAL_U] = 0x28,
230 },
231};
232EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
233
234/*
235 * Even though 40 bits are present, use only 32 for ease of calculation.
236 */
237#define ALPHA_REG_BITWIDTH 40
238#define ALPHA_REG_16BIT_WIDTH 16
239#define ALPHA_BITWIDTH 32U
240#define ALPHA_SHIFT(w) min(w, ALPHA_BITWIDTH)
241
242#define ALPHA_PLL_STATUS_REG_SHIFT 8
243
244#define PLL_HUAYRA_M_WIDTH 8
245#define PLL_HUAYRA_M_SHIFT 8
246#define PLL_HUAYRA_M_MASK 0xff
247#define PLL_HUAYRA_N_SHIFT 0
248#define PLL_HUAYRA_N_MASK 0xff
249#define PLL_HUAYRA_ALPHA_WIDTH 16
250
251#define PLL_STANDBY 0x0
252#define PLL_RUN 0x1
253#define PLL_OUT_MASK 0x7
254#define PLL_RATE_MARGIN 500
255
256/* TRION PLL specific settings and offsets */
257#define TRION_PLL_CAL_VAL 0x44
258#define TRION_PCAL_DONE BIT(26)
259
260/* LUCID PLL specific settings and offsets */
261#define LUCID_PCAL_DONE BIT(27)
262
263/* LUCID 5LPE PLL specific settings and offsets */
264#define LUCID_5LPE_PCAL_DONE BIT(11)
265#define LUCID_5LPE_ALPHA_PLL_ACK_LATCH BIT(13)
266#define LUCID_5LPE_PLL_LATCH_INPUT BIT(14)
267#define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21)
268
269/* LUCID EVO PLL specific settings and offsets */
270#define LUCID_EVO_PCAL_NOT_DONE BIT(8)
271#define LUCID_EVO_ENABLE_VOTE_RUN BIT(25)
272#define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0)
273#define LUCID_EVO_PLL_CAL_L_VAL_SHIFT 16
274#define LUCID_OLE_PLL_RINGOSC_CAL_L_VAL_SHIFT 24
275
276/* ZONDA PLL specific */
277#define ZONDA_PLL_OUT_MASK 0xf
278#define ZONDA_STAY_IN_CFA BIT(16)
279#define ZONDA_PLL_FREQ_LOCK_DET BIT(29)
280
281#define pll_alpha_width(p) \
282 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
283 ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
284
285#define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4)
286
287#define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \
288 struct clk_alpha_pll, clkr)
289
290#define to_clk_alpha_pll_postdiv(_hw) container_of(to_clk_regmap(_hw), \
291 struct clk_alpha_pll_postdiv, clkr)
292
293static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
294 const char *action)
295{
296 u32 val;
297 int count;
298 int ret;
299 const char *name = clk_hw_get_name(&pll->clkr.hw);
300
301 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
302 if (ret)
303 return ret;
304
305 for (count = 200; count > 0; count--) {
306 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
307 if (ret)
308 return ret;
309 if (inverse && !(val & mask))
310 return 0;
311 else if ((val & mask) == mask)
312 return 0;
313
314 udelay(1);
315 }
316
317 WARN(1, "%s failed to %s!\n", name, action);
318 return -ETIMEDOUT;
319}
320
321#define wait_for_pll_enable_active(pll) \
322 wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable")
323
324#define wait_for_pll_enable_lock(pll) \
325 wait_for_pll(pll, PLL_LOCK_DET, 0, "enable")
326
327#define wait_for_zonda_pll_freq_lock(pll) \
328 wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable")
329
330#define wait_for_pll_disable(pll) \
331 wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable")
332
333#define wait_for_pll_offline(pll) \
334 wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline")
335
336#define wait_for_pll_update(pll) \
337 wait_for_pll(pll, PLL_UPDATE, 1, "update")
338
339#define wait_for_pll_update_ack_set(pll) \
340 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set")
341
342#define wait_for_pll_update_ack_clear(pll) \
343 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear")
344
345static void clk_alpha_pll_write_config(struct regmap *regmap, unsigned int reg,
346 unsigned int val)
347{
348 if (val)
349 regmap_write(regmap, reg, val);
350}
351
352void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
353 const struct alpha_pll_config *config)
354{
355 u32 val, mask;
356
357 regmap_write(regmap, PLL_L_VAL(pll), config->l);
358 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
359 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
360
361 if (pll_has_64bit_config(pll))
362 regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
363 config->config_ctl_hi_val);
364
365 if (pll_alpha_width(pll) > 32)
366 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi);
367
368 val = config->main_output_mask;
369 val |= config->aux_output_mask;
370 val |= config->aux2_output_mask;
371 val |= config->early_output_mask;
372 val |= config->pre_div_val;
373 val |= config->post_div_val;
374 val |= config->vco_val;
375 val |= config->alpha_en_mask;
376 val |= config->alpha_mode_mask;
377
378 mask = config->main_output_mask;
379 mask |= config->aux_output_mask;
380 mask |= config->aux2_output_mask;
381 mask |= config->early_output_mask;
382 mask |= config->pre_div_mask;
383 mask |= config->post_div_mask;
384 mask |= config->vco_mask;
385
386 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
387
388 if (config->test_ctl_mask)
389 regmap_update_bits(regmap, PLL_TEST_CTL(pll),
390 config->test_ctl_mask,
391 config->test_ctl_val);
392 else
393 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
394 config->test_ctl_val);
395
396 if (config->test_ctl_hi_mask)
397 regmap_update_bits(regmap, PLL_TEST_CTL_U(pll),
398 config->test_ctl_hi_mask,
399 config->test_ctl_hi_val);
400 else
401 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
402 config->test_ctl_hi_val);
403
404 if (pll->flags & SUPPORTS_FSM_MODE)
405 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
406}
407EXPORT_SYMBOL_GPL(clk_alpha_pll_configure);
408
409static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
410{
411 int ret;
412 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
413 u32 val;
414
415 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
416 if (ret)
417 return ret;
418
419 val |= PLL_FSM_ENA;
420
421 if (pll->flags & SUPPORTS_OFFLINE_REQ)
422 val &= ~PLL_OFFLINE_REQ;
423
424 ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val);
425 if (ret)
426 return ret;
427
428 /* Make sure enable request goes through before waiting for update */
429 mb();
430
431 return wait_for_pll_enable_active(pll);
432}
433
434static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw)
435{
436 int ret;
437 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
438 u32 val;
439
440 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
441 if (ret)
442 return;
443
444 if (pll->flags & SUPPORTS_OFFLINE_REQ) {
445 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
446 PLL_OFFLINE_REQ, PLL_OFFLINE_REQ);
447 if (ret)
448 return;
449
450 ret = wait_for_pll_offline(pll);
451 if (ret)
452 return;
453 }
454
455 /* Disable hwfsm */
456 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
457 PLL_FSM_ENA, 0);
458 if (ret)
459 return;
460
461 wait_for_pll_disable(pll);
462}
463
464static int pll_is_enabled(struct clk_hw *hw, u32 mask)
465{
466 int ret;
467 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
468 u32 val;
469
470 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
471 if (ret)
472 return ret;
473
474 return !!(val & mask);
475}
476
477static int clk_alpha_pll_hwfsm_is_enabled(struct clk_hw *hw)
478{
479 return pll_is_enabled(hw, PLL_ACTIVE_FLAG);
480}
481
482static int clk_alpha_pll_is_enabled(struct clk_hw *hw)
483{
484 return pll_is_enabled(hw, PLL_LOCK_DET);
485}
486
487static int clk_alpha_pll_enable(struct clk_hw *hw)
488{
489 int ret;
490 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
491 u32 val, mask;
492
493 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
494 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
495 if (ret)
496 return ret;
497
498 /* If in FSM mode, just vote for it */
499 if (val & PLL_VOTE_FSM_ENA) {
500 ret = clk_enable_regmap(hw);
501 if (ret)
502 return ret;
503 return wait_for_pll_enable_active(pll);
504 }
505
506 /* Skip if already enabled */
507 if ((val & mask) == mask)
508 return 0;
509
510 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
511 PLL_BYPASSNL, PLL_BYPASSNL);
512 if (ret)
513 return ret;
514
515 /*
516 * H/W requires a 5us delay between disabling the bypass and
517 * de-asserting the reset.
518 */
519 mb();
520 udelay(5);
521
522 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
523 PLL_RESET_N, PLL_RESET_N);
524 if (ret)
525 return ret;
526
527 ret = wait_for_pll_enable_lock(pll);
528 if (ret)
529 return ret;
530
531 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
532 PLL_OUTCTRL, PLL_OUTCTRL);
533
534 /* Ensure that the write above goes through before returning. */
535 mb();
536 return ret;
537}
538
539static void clk_alpha_pll_disable(struct clk_hw *hw)
540{
541 int ret;
542 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
543 u32 val, mask;
544
545 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
546 if (ret)
547 return;
548
549 /* If in FSM mode, just unvote it */
550 if (val & PLL_VOTE_FSM_ENA) {
551 clk_disable_regmap(hw);
552 return;
553 }
554
555 mask = PLL_OUTCTRL;
556 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
557
558 /* Delay of 2 output clock ticks required until output is disabled */
559 mb();
560 udelay(1);
561
562 mask = PLL_RESET_N | PLL_BYPASSNL;
563 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
564}
565
566static unsigned long
567alpha_pll_calc_rate(u64 prate, u32 l, u32 a, u32 alpha_width)
568{
569 return (prate * l) + ((prate * a) >> ALPHA_SHIFT(alpha_width));
570}
571
572static unsigned long
573alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a,
574 u32 alpha_width)
575{
576 u64 remainder;
577 u64 quotient;
578
579 quotient = rate;
580 remainder = do_div(quotient, prate);
581 *l = quotient;
582
583 if (!remainder) {
584 *a = 0;
585 return rate;
586 }
587
588 /* Upper ALPHA_BITWIDTH bits of Alpha */
589 quotient = remainder << ALPHA_SHIFT(alpha_width);
590
591 remainder = do_div(quotient, prate);
592
593 if (remainder)
594 quotient++;
595
596 *a = quotient;
597 return alpha_pll_calc_rate(prate, *l, *a, alpha_width);
598}
599
600static const struct pll_vco *
601alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate)
602{
603 const struct pll_vco *v = pll->vco_table;
604 const struct pll_vco *end = v + pll->num_vco;
605
606 for (; v < end; v++)
607 if (rate >= v->min_freq && rate <= v->max_freq)
608 return v;
609
610 return NULL;
611}
612
613static unsigned long
614clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
615{
616 u32 l, low, high, ctl;
617 u64 a = 0, prate = parent_rate;
618 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
619 u32 alpha_width = pll_alpha_width(pll);
620
621 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
622
623 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
624 if (ctl & PLL_ALPHA_EN) {
625 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low);
626 if (alpha_width > 32) {
627 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
628 &high);
629 a = (u64)high << 32 | low;
630 } else {
631 a = low & GENMASK(alpha_width - 1, 0);
632 }
633
634 if (alpha_width > ALPHA_BITWIDTH)
635 a >>= alpha_width - ALPHA_BITWIDTH;
636 }
637
638 return alpha_pll_calc_rate(prate, l, a, alpha_width);
639}
640
641
642static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll)
643{
644 int ret;
645 u32 mode;
646
647 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode);
648
649 /* Latch the input to the PLL */
650 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE,
651 PLL_UPDATE);
652
653 /* Wait for 2 reference cycle before checking ACK bit */
654 udelay(1);
655
656 /*
657 * PLL will latch the new L, Alpha and freq control word.
658 * PLL will respond by raising PLL_ACK_LATCH output when new programming
659 * has been latched in and PLL is being updated. When
660 * UPDATE_LOGIC_BYPASS bit is not set, PLL_UPDATE will be cleared
661 * automatically by hardware when PLL_ACK_LATCH is asserted by PLL.
662 */
663 if (mode & PLL_UPDATE_BYPASS) {
664 ret = wait_for_pll_update_ack_set(pll);
665 if (ret)
666 return ret;
667
668 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0);
669 } else {
670 ret = wait_for_pll_update(pll);
671 if (ret)
672 return ret;
673 }
674
675 ret = wait_for_pll_update_ack_clear(pll);
676 if (ret)
677 return ret;
678
679 /* Wait for PLL output to stabilize */
680 udelay(10);
681
682 return 0;
683}
684
685static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll,
686 int (*is_enabled)(struct clk_hw *))
687{
688 if (!is_enabled(&pll->clkr.hw) ||
689 !(pll->flags & SUPPORTS_DYNAMIC_UPDATE))
690 return 0;
691
692 return __clk_alpha_pll_update_latch(pll);
693}
694
695static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
696 unsigned long prate,
697 int (*is_enabled)(struct clk_hw *))
698{
699 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
700 const struct pll_vco *vco;
701 u32 l, alpha_width = pll_alpha_width(pll);
702 u64 a;
703
704 rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
705 vco = alpha_pll_find_vco(pll, rate);
706 if (pll->vco_table && !vco) {
707 pr_err("%s: alpha pll not in a valid vco range\n",
708 clk_hw_get_name(hw));
709 return -EINVAL;
710 }
711
712 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
713
714 if (alpha_width > ALPHA_BITWIDTH)
715 a <<= alpha_width - ALPHA_BITWIDTH;
716
717 if (alpha_width > 32)
718 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32);
719
720 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
721
722 if (vco) {
723 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
724 PLL_VCO_MASK << PLL_VCO_SHIFT,
725 vco->val << PLL_VCO_SHIFT);
726 }
727
728 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
729 PLL_ALPHA_EN, PLL_ALPHA_EN);
730
731 return clk_alpha_pll_update_latch(pll, is_enabled);
732}
733
734static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
735 unsigned long prate)
736{
737 return __clk_alpha_pll_set_rate(hw, rate, prate,
738 clk_alpha_pll_is_enabled);
739}
740
741static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw *hw, unsigned long rate,
742 unsigned long prate)
743{
744 return __clk_alpha_pll_set_rate(hw, rate, prate,
745 clk_alpha_pll_hwfsm_is_enabled);
746}
747
748static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate,
749 unsigned long *prate)
750{
751 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
752 u32 l, alpha_width = pll_alpha_width(pll);
753 u64 a;
754 unsigned long min_freq, max_freq;
755
756 rate = alpha_pll_round_rate(rate, *prate, &l, &a, alpha_width);
757 if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
758 return rate;
759
760 min_freq = pll->vco_table[0].min_freq;
761 max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
762
763 return clamp(rate, min_freq, max_freq);
764}
765
766static unsigned long
767alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a)
768{
769 /*
770 * a contains 16 bit alpha_val in two’s complement number in the range
771 * of [-0.5, 0.5).
772 */
773 if (a >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1))
774 l -= 1;
775
776 return (prate * l) + (prate * a >> PLL_HUAYRA_ALPHA_WIDTH);
777}
778
779static unsigned long
780alpha_huayra_pll_round_rate(unsigned long rate, unsigned long prate,
781 u32 *l, u32 *a)
782{
783 u64 remainder;
784 u64 quotient;
785
786 quotient = rate;
787 remainder = do_div(quotient, prate);
788 *l = quotient;
789
790 if (!remainder) {
791 *a = 0;
792 return rate;
793 }
794
795 quotient = remainder << PLL_HUAYRA_ALPHA_WIDTH;
796 remainder = do_div(quotient, prate);
797
798 if (remainder)
799 quotient++;
800
801 /*
802 * alpha_val should be in two’s complement number in the range
803 * of [-0.5, 0.5) so if quotient >= 0.5 then increment the l value
804 * since alpha value will be subtracted in this case.
805 */
806 if (quotient >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1))
807 *l += 1;
808
809 *a = quotient;
810 return alpha_huayra_pll_calc_rate(prate, *l, *a);
811}
812
813static unsigned long
814alpha_pll_huayra_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
815{
816 u64 rate = parent_rate, tmp;
817 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
818 u32 l, alpha = 0, ctl, alpha_m, alpha_n;
819
820 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
821 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
822
823 if (ctl & PLL_ALPHA_EN) {
824 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha);
825 /*
826 * Depending upon alpha_mode, it can be treated as M/N value or
827 * as a two’s complement number. When alpha_mode=1,
828 * pll_alpha_val<15:8>=M and pll_apla_val<7:0>=N
829 *
830 * Fout=FIN*(L+(M/N))
831 *
832 * M is a signed number (-128 to 127) and N is unsigned
833 * (0 to 255). M/N has to be within +/-0.5.
834 *
835 * When alpha_mode=0, it is a two’s complement number in the
836 * range [-0.5, 0.5).
837 *
838 * Fout=FIN*(L+(alpha_val)/2^16)
839 *
840 * where alpha_val is two’s complement number.
841 */
842 if (!(ctl & PLL_ALPHA_MODE))
843 return alpha_huayra_pll_calc_rate(rate, l, alpha);
844
845 alpha_m = alpha >> PLL_HUAYRA_M_SHIFT & PLL_HUAYRA_M_MASK;
846 alpha_n = alpha >> PLL_HUAYRA_N_SHIFT & PLL_HUAYRA_N_MASK;
847
848 rate *= l;
849 tmp = parent_rate;
850 if (alpha_m >= BIT(PLL_HUAYRA_M_WIDTH - 1)) {
851 alpha_m = BIT(PLL_HUAYRA_M_WIDTH) - alpha_m;
852 tmp *= alpha_m;
853 do_div(tmp, alpha_n);
854 rate -= tmp;
855 } else {
856 tmp *= alpha_m;
857 do_div(tmp, alpha_n);
858 rate += tmp;
859 }
860
861 return rate;
862 }
863
864 return alpha_huayra_pll_calc_rate(rate, l, alpha);
865}
866
867static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate,
868 unsigned long prate)
869{
870 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
871 u32 l, a, ctl, cur_alpha = 0;
872
873 rate = alpha_huayra_pll_round_rate(rate, prate, &l, &a);
874
875 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
876
877 if (ctl & PLL_ALPHA_EN)
878 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha);
879
880 /*
881 * Huayra PLL supports PLL dynamic programming. User can change L_VAL,
882 * without having to go through the power on sequence.
883 */
884 if (clk_alpha_pll_is_enabled(hw)) {
885 if (cur_alpha != a) {
886 pr_err("%s: clock needs to be gated\n",
887 clk_hw_get_name(hw));
888 return -EBUSY;
889 }
890
891 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
892 /* Ensure that the write above goes to detect L val change. */
893 mb();
894 return wait_for_pll_enable_lock(pll);
895 }
896
897 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
898 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
899
900 if (a == 0)
901 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
902 PLL_ALPHA_EN, 0x0);
903 else
904 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
905 PLL_ALPHA_EN | PLL_ALPHA_MODE, PLL_ALPHA_EN);
906
907 return 0;
908}
909
910static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,
911 unsigned long *prate)
912{
913 u32 l, a;
914
915 return alpha_huayra_pll_round_rate(rate, *prate, &l, &a);
916}
917
918static int trion_pll_is_enabled(struct clk_alpha_pll *pll,
919 struct regmap *regmap)
920{
921 u32 mode_val, opmode_val;
922 int ret;
923
924 ret = regmap_read(regmap, PLL_MODE(pll), &mode_val);
925 ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_val);
926 if (ret)
927 return 0;
928
929 return ((opmode_val & PLL_RUN) && (mode_val & PLL_OUTCTRL));
930}
931
932static int clk_trion_pll_is_enabled(struct clk_hw *hw)
933{
934 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
935
936 return trion_pll_is_enabled(pll, pll->clkr.regmap);
937}
938
939static int clk_trion_pll_enable(struct clk_hw *hw)
940{
941 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
942 struct regmap *regmap = pll->clkr.regmap;
943 u32 val;
944 int ret;
945
946 ret = regmap_read(regmap, PLL_MODE(pll), &val);
947 if (ret)
948 return ret;
949
950 /* If in FSM mode, just vote for it */
951 if (val & PLL_VOTE_FSM_ENA) {
952 ret = clk_enable_regmap(hw);
953 if (ret)
954 return ret;
955 return wait_for_pll_enable_active(pll);
956 }
957
958 /* Set operation mode to RUN */
959 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
960
961 ret = wait_for_pll_enable_lock(pll);
962 if (ret)
963 return ret;
964
965 /* Enable the PLL outputs */
966 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
967 PLL_OUT_MASK, PLL_OUT_MASK);
968 if (ret)
969 return ret;
970
971 /* Enable the global PLL outputs */
972 return regmap_update_bits(regmap, PLL_MODE(pll),
973 PLL_OUTCTRL, PLL_OUTCTRL);
974}
975
976static void clk_trion_pll_disable(struct clk_hw *hw)
977{
978 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
979 struct regmap *regmap = pll->clkr.regmap;
980 u32 val;
981 int ret;
982
983 ret = regmap_read(regmap, PLL_MODE(pll), &val);
984 if (ret)
985 return;
986
987 /* If in FSM mode, just unvote it */
988 if (val & PLL_VOTE_FSM_ENA) {
989 clk_disable_regmap(hw);
990 return;
991 }
992
993 /* Disable the global PLL output */
994 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
995 if (ret)
996 return;
997
998 /* Disable the PLL outputs */
999 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
1000 PLL_OUT_MASK, 0);
1001 if (ret)
1002 return;
1003
1004 /* Place the PLL mode in STANDBY */
1005 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1006 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1007}
1008
1009static unsigned long
1010clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
1011{
1012 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1013 u32 l, frac, alpha_width = pll_alpha_width(pll);
1014
1015 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
1016 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac);
1017
1018 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
1019}
1020
1021const struct clk_ops clk_alpha_pll_fixed_ops = {
1022 .enable = clk_alpha_pll_enable,
1023 .disable = clk_alpha_pll_disable,
1024 .is_enabled = clk_alpha_pll_is_enabled,
1025 .recalc_rate = clk_alpha_pll_recalc_rate,
1026};
1027EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_ops);
1028
1029const struct clk_ops clk_alpha_pll_ops = {
1030 .enable = clk_alpha_pll_enable,
1031 .disable = clk_alpha_pll_disable,
1032 .is_enabled = clk_alpha_pll_is_enabled,
1033 .recalc_rate = clk_alpha_pll_recalc_rate,
1034 .round_rate = clk_alpha_pll_round_rate,
1035 .set_rate = clk_alpha_pll_set_rate,
1036};
1037EXPORT_SYMBOL_GPL(clk_alpha_pll_ops);
1038
1039const struct clk_ops clk_alpha_pll_huayra_ops = {
1040 .enable = clk_alpha_pll_enable,
1041 .disable = clk_alpha_pll_disable,
1042 .is_enabled = clk_alpha_pll_is_enabled,
1043 .recalc_rate = alpha_pll_huayra_recalc_rate,
1044 .round_rate = alpha_pll_huayra_round_rate,
1045 .set_rate = alpha_pll_huayra_set_rate,
1046};
1047EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops);
1048
1049const struct clk_ops clk_alpha_pll_hwfsm_ops = {
1050 .enable = clk_alpha_pll_hwfsm_enable,
1051 .disable = clk_alpha_pll_hwfsm_disable,
1052 .is_enabled = clk_alpha_pll_hwfsm_is_enabled,
1053 .recalc_rate = clk_alpha_pll_recalc_rate,
1054 .round_rate = clk_alpha_pll_round_rate,
1055 .set_rate = clk_alpha_pll_hwfsm_set_rate,
1056};
1057EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);
1058
1059const struct clk_ops clk_alpha_pll_fixed_trion_ops = {
1060 .enable = clk_trion_pll_enable,
1061 .disable = clk_trion_pll_disable,
1062 .is_enabled = clk_trion_pll_is_enabled,
1063 .recalc_rate = clk_trion_pll_recalc_rate,
1064 .round_rate = clk_alpha_pll_round_rate,
1065};
1066EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_trion_ops);
1067
1068static unsigned long
1069clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
1070{
1071 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1072 u32 ctl;
1073
1074 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
1075
1076 ctl >>= PLL_POST_DIV_SHIFT;
1077 ctl &= PLL_POST_DIV_MASK(pll);
1078
1079 return parent_rate >> fls(ctl);
1080}
1081
1082static const struct clk_div_table clk_alpha_div_table[] = {
1083 { 0x0, 1 },
1084 { 0x1, 2 },
1085 { 0x3, 4 },
1086 { 0x7, 8 },
1087 { 0xf, 16 },
1088 { }
1089};
1090
1091static const struct clk_div_table clk_alpha_2bit_div_table[] = {
1092 { 0x0, 1 },
1093 { 0x1, 2 },
1094 { 0x3, 4 },
1095 { }
1096};
1097
1098static long
1099clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
1100 unsigned long *prate)
1101{
1102 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1103 const struct clk_div_table *table;
1104
1105 if (pll->width == 2)
1106 table = clk_alpha_2bit_div_table;
1107 else
1108 table = clk_alpha_div_table;
1109
1110 return divider_round_rate(hw, rate, prate, table,
1111 pll->width, CLK_DIVIDER_POWER_OF_TWO);
1112}
1113
1114static long
1115clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate,
1116 unsigned long *prate)
1117{
1118 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1119 u32 ctl, div;
1120
1121 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
1122
1123 ctl >>= PLL_POST_DIV_SHIFT;
1124 ctl &= BIT(pll->width) - 1;
1125 div = 1 << fls(ctl);
1126
1127 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)
1128 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), div * rate);
1129
1130 return DIV_ROUND_UP_ULL((u64)*prate, div);
1131}
1132
1133static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1134 unsigned long parent_rate)
1135{
1136 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1137 int div;
1138
1139 /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */
1140 div = DIV_ROUND_UP_ULL(parent_rate, rate) - 1;
1141
1142 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
1143 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
1144 div << PLL_POST_DIV_SHIFT);
1145}
1146
1147const struct clk_ops clk_alpha_pll_postdiv_ops = {
1148 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
1149 .round_rate = clk_alpha_pll_postdiv_round_rate,
1150 .set_rate = clk_alpha_pll_postdiv_set_rate,
1151};
1152EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops);
1153
1154const struct clk_ops clk_alpha_pll_postdiv_ro_ops = {
1155 .round_rate = clk_alpha_pll_postdiv_round_ro_rate,
1156 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
1157};
1158EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops);
1159
1160void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1161 const struct alpha_pll_config *config)
1162{
1163 u32 val, mask;
1164
1165 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1166 clk_alpha_pll_write_config(regmap, PLL_FRAC(pll), config->alpha);
1167 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
1168 config->config_ctl_val);
1169 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
1170 config->config_ctl_hi_val);
1171 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
1172 config->user_ctl_val);
1173 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll),
1174 config->user_ctl_hi_val);
1175 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
1176 config->test_ctl_val);
1177 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
1178 config->test_ctl_hi_val);
1179
1180 if (config->post_div_mask) {
1181 mask = config->post_div_mask;
1182 val = config->post_div_val;
1183 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
1184 }
1185
1186 if (pll->flags & SUPPORTS_FSM_LEGACY_MODE)
1187 regmap_update_bits(regmap, PLL_MODE(pll), PLL_FSM_LEGACY_MODE,
1188 PLL_FSM_LEGACY_MODE);
1189
1190 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
1191 PLL_UPDATE_BYPASS);
1192
1193 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1194}
1195EXPORT_SYMBOL_GPL(clk_fabia_pll_configure);
1196
1197static int alpha_pll_fabia_enable(struct clk_hw *hw)
1198{
1199 int ret;
1200 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1201 u32 val, opmode_val;
1202 struct regmap *regmap = pll->clkr.regmap;
1203
1204 ret = regmap_read(regmap, PLL_MODE(pll), &val);
1205 if (ret)
1206 return ret;
1207
1208 /* If in FSM mode, just vote for it */
1209 if (val & PLL_VOTE_FSM_ENA) {
1210 ret = clk_enable_regmap(hw);
1211 if (ret)
1212 return ret;
1213 return wait_for_pll_enable_active(pll);
1214 }
1215
1216 ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val);
1217 if (ret)
1218 return ret;
1219
1220 /* Skip If PLL is already running */
1221 if ((opmode_val & PLL_RUN) && (val & PLL_OUTCTRL))
1222 return 0;
1223
1224 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1225 if (ret)
1226 return ret;
1227
1228 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1229 if (ret)
1230 return ret;
1231
1232 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N,
1233 PLL_RESET_N);
1234 if (ret)
1235 return ret;
1236
1237 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
1238 if (ret)
1239 return ret;
1240
1241 ret = wait_for_pll_enable_lock(pll);
1242 if (ret)
1243 return ret;
1244
1245 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
1246 PLL_OUT_MASK, PLL_OUT_MASK);
1247 if (ret)
1248 return ret;
1249
1250 return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL,
1251 PLL_OUTCTRL);
1252}
1253
1254static void alpha_pll_fabia_disable(struct clk_hw *hw)
1255{
1256 int ret;
1257 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1258 u32 val;
1259 struct regmap *regmap = pll->clkr.regmap;
1260
1261 ret = regmap_read(regmap, PLL_MODE(pll), &val);
1262 if (ret)
1263 return;
1264
1265 /* If in FSM mode, just unvote it */
1266 if (val & PLL_FSM_ENA) {
1267 clk_disable_regmap(hw);
1268 return;
1269 }
1270
1271 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1272 if (ret)
1273 return;
1274
1275 /* Disable main outputs */
1276 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
1277 if (ret)
1278 return;
1279
1280 /* Place the PLL in STANDBY */
1281 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1282}
1283
1284static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw,
1285 unsigned long parent_rate)
1286{
1287 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1288 u32 l, frac, alpha_width = pll_alpha_width(pll);
1289
1290 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
1291 regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac);
1292
1293 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
1294}
1295
1296/*
1297 * Due to limited number of bits for fractional rate programming, the
1298 * rounded up rate could be marginally higher than the requested rate.
1299 */
1300static int alpha_pll_check_rate_margin(struct clk_hw *hw,
1301 unsigned long rrate, unsigned long rate)
1302{
1303 unsigned long rate_margin = rate + PLL_RATE_MARGIN;
1304
1305 if (rrate > rate_margin || rrate < rate) {
1306 pr_err("%s: Rounded rate %lu not within range [%lu, %lu)\n",
1307 clk_hw_get_name(hw), rrate, rate, rate_margin);
1308 return -EINVAL;
1309 }
1310
1311 return 0;
1312}
1313
1314static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate,
1315 unsigned long prate)
1316{
1317 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1318 u32 l, alpha_width = pll_alpha_width(pll);
1319 unsigned long rrate;
1320 int ret;
1321 u64 a;
1322
1323 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
1324
1325 ret = alpha_pll_check_rate_margin(hw, rrate, rate);
1326 if (ret < 0)
1327 return ret;
1328
1329 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
1330 regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a);
1331
1332 return __clk_alpha_pll_update_latch(pll);
1333}
1334
1335static int alpha_pll_fabia_prepare(struct clk_hw *hw)
1336{
1337 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1338 const struct pll_vco *vco;
1339 struct clk_hw *parent_hw;
1340 unsigned long cal_freq, rrate;
1341 u32 cal_l, val, alpha_width = pll_alpha_width(pll);
1342 const char *name = clk_hw_get_name(hw);
1343 u64 a;
1344 int ret;
1345
1346 /* Check if calibration needs to be done i.e. PLL is in reset */
1347 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1348 if (ret)
1349 return ret;
1350
1351 /* Return early if calibration is not needed. */
1352 if (val & PLL_RESET_N)
1353 return 0;
1354
1355 vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw));
1356 if (!vco) {
1357 pr_err("%s: alpha pll not in a valid vco range\n", name);
1358 return -EINVAL;
1359 }
1360
1361 cal_freq = DIV_ROUND_CLOSEST((pll->vco_table[0].min_freq +
1362 pll->vco_table[0].max_freq) * 54, 100);
1363
1364 parent_hw = clk_hw_get_parent(hw);
1365 if (!parent_hw)
1366 return -EINVAL;
1367
1368 rrate = alpha_pll_round_rate(cal_freq, clk_hw_get_rate(parent_hw),
1369 &cal_l, &a, alpha_width);
1370
1371 ret = alpha_pll_check_rate_margin(hw, rrate, cal_freq);
1372 if (ret < 0)
1373 return ret;
1374
1375 /* Setup PLL for calibration frequency */
1376 regmap_write(pll->clkr.regmap, PLL_CAL_L_VAL(pll), cal_l);
1377
1378 /* Bringup the PLL at calibration frequency */
1379 ret = clk_alpha_pll_enable(hw);
1380 if (ret) {
1381 pr_err("%s: alpha pll calibration failed\n", name);
1382 return ret;
1383 }
1384
1385 clk_alpha_pll_disable(hw);
1386
1387 return 0;
1388}
1389
1390const struct clk_ops clk_alpha_pll_fabia_ops = {
1391 .prepare = alpha_pll_fabia_prepare,
1392 .enable = alpha_pll_fabia_enable,
1393 .disable = alpha_pll_fabia_disable,
1394 .is_enabled = clk_alpha_pll_is_enabled,
1395 .set_rate = alpha_pll_fabia_set_rate,
1396 .recalc_rate = alpha_pll_fabia_recalc_rate,
1397 .round_rate = clk_alpha_pll_round_rate,
1398};
1399EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops);
1400
1401const struct clk_ops clk_alpha_pll_fixed_fabia_ops = {
1402 .enable = alpha_pll_fabia_enable,
1403 .disable = alpha_pll_fabia_disable,
1404 .is_enabled = clk_alpha_pll_is_enabled,
1405 .recalc_rate = alpha_pll_fabia_recalc_rate,
1406 .round_rate = clk_alpha_pll_round_rate,
1407};
1408EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops);
1409
1410static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw,
1411 unsigned long parent_rate)
1412{
1413 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1414 u32 i, div = 1, val;
1415 int ret;
1416
1417 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
1418 if (ret)
1419 return ret;
1420
1421 val >>= pll->post_div_shift;
1422 val &= BIT(pll->width) - 1;
1423
1424 for (i = 0; i < pll->num_post_div; i++) {
1425 if (pll->post_div_table[i].val == val) {
1426 div = pll->post_div_table[i].div;
1427 break;
1428 }
1429 }
1430
1431 return (parent_rate / div);
1432}
1433
1434static unsigned long
1435clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
1436{
1437 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1438 struct regmap *regmap = pll->clkr.regmap;
1439 u32 i, div = 1, val;
1440
1441 regmap_read(regmap, PLL_USER_CTL(pll), &val);
1442
1443 val >>= pll->post_div_shift;
1444 val &= PLL_POST_DIV_MASK(pll);
1445
1446 for (i = 0; i < pll->num_post_div; i++) {
1447 if (pll->post_div_table[i].val == val) {
1448 div = pll->post_div_table[i].div;
1449 break;
1450 }
1451 }
1452
1453 return (parent_rate / div);
1454}
1455
1456static long
1457clk_trion_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
1458 unsigned long *prate)
1459{
1460 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1461
1462 return divider_round_rate(hw, rate, prate, pll->post_div_table,
1463 pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1464};
1465
1466static int
1467clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1468 unsigned long parent_rate)
1469{
1470 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1471 struct regmap *regmap = pll->clkr.regmap;
1472 int i, val = 0, div;
1473
1474 div = DIV_ROUND_UP_ULL(parent_rate, rate);
1475 for (i = 0; i < pll->num_post_div; i++) {
1476 if (pll->post_div_table[i].div == div) {
1477 val = pll->post_div_table[i].val;
1478 break;
1479 }
1480 }
1481
1482 return regmap_update_bits(regmap, PLL_USER_CTL(pll),
1483 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
1484 val << PLL_POST_DIV_SHIFT);
1485}
1486
1487const struct clk_ops clk_alpha_pll_postdiv_trion_ops = {
1488 .recalc_rate = clk_trion_pll_postdiv_recalc_rate,
1489 .round_rate = clk_trion_pll_postdiv_round_rate,
1490 .set_rate = clk_trion_pll_postdiv_set_rate,
1491};
1492EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_trion_ops);
1493
1494static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw,
1495 unsigned long rate, unsigned long *prate)
1496{
1497 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1498
1499 return divider_round_rate(hw, rate, prate, pll->post_div_table,
1500 pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1501}
1502
1503static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw,
1504 unsigned long rate, unsigned long parent_rate)
1505{
1506 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1507 int i, val = 0, div, ret;
1508
1509 /*
1510 * If the PLL is in FSM mode, then treat set_rate callback as a
1511 * no-operation.
1512 */
1513 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1514 if (ret)
1515 return ret;
1516
1517 if (val & PLL_VOTE_FSM_ENA)
1518 return 0;
1519
1520 div = DIV_ROUND_UP_ULL(parent_rate, rate);
1521 for (i = 0; i < pll->num_post_div; i++) {
1522 if (pll->post_div_table[i].div == div) {
1523 val = pll->post_div_table[i].val;
1524 break;
1525 }
1526 }
1527
1528 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
1529 (BIT(pll->width) - 1) << pll->post_div_shift,
1530 val << pll->post_div_shift);
1531}
1532
1533const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = {
1534 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
1535 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
1536 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
1537};
1538EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops);
1539
1540/**
1541 * clk_trion_pll_configure - configure the trion pll
1542 *
1543 * @pll: clk alpha pll
1544 * @regmap: register map
1545 * @config: configuration to apply for pll
1546 */
1547void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1548 const struct alpha_pll_config *config)
1549{
1550 /*
1551 * If the bootloader left the PLL enabled it's likely that there are
1552 * RCGs that will lock up if we disable the PLL below.
1553 */
1554 if (trion_pll_is_enabled(pll, regmap)) {
1555 pr_debug("Trion PLL is already enabled, skipping configuration\n");
1556 return;
1557 }
1558
1559 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1560 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL);
1561 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
1562 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
1563 config->config_ctl_val);
1564 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
1565 config->config_ctl_hi_val);
1566 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll),
1567 config->config_ctl_hi1_val);
1568 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
1569 config->user_ctl_val);
1570 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll),
1571 config->user_ctl_hi_val);
1572 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll),
1573 config->user_ctl_hi1_val);
1574 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
1575 config->test_ctl_val);
1576 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
1577 config->test_ctl_hi_val);
1578 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll),
1579 config->test_ctl_hi1_val);
1580
1581 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
1582 PLL_UPDATE_BYPASS);
1583
1584 /* Disable PLL output */
1585 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1586
1587 /* Set operation mode to OFF */
1588 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1589
1590 /* Place the PLL in STANDBY mode */
1591 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1592}
1593EXPORT_SYMBOL_GPL(clk_trion_pll_configure);
1594
1595/*
1596 * The TRION PLL requires a power-on self-calibration which happens when the
1597 * PLL comes out of reset. Calibrate in case it is not completed.
1598 */
1599static int __alpha_pll_trion_prepare(struct clk_hw *hw, u32 pcal_done)
1600{
1601 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1602 u32 val;
1603 int ret;
1604
1605 /* Return early if calibration is not needed. */
1606 regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &val);
1607 if (val & pcal_done)
1608 return 0;
1609
1610 /* On/off to calibrate */
1611 ret = clk_trion_pll_enable(hw);
1612 if (!ret)
1613 clk_trion_pll_disable(hw);
1614
1615 return ret;
1616}
1617
1618static int alpha_pll_trion_prepare(struct clk_hw *hw)
1619{
1620 return __alpha_pll_trion_prepare(hw, TRION_PCAL_DONE);
1621}
1622
1623static int alpha_pll_lucid_prepare(struct clk_hw *hw)
1624{
1625 return __alpha_pll_trion_prepare(hw, LUCID_PCAL_DONE);
1626}
1627
1628static int __alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,
1629 unsigned long prate, u32 latch_bit, u32 latch_ack)
1630{
1631 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1632 unsigned long rrate;
1633 u32 val, l, alpha_width = pll_alpha_width(pll);
1634 u64 a;
1635 int ret;
1636
1637 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
1638
1639 ret = alpha_pll_check_rate_margin(hw, rrate, rate);
1640 if (ret < 0)
1641 return ret;
1642
1643 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
1644 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
1645
1646 /* Latch the PLL input */
1647 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, latch_bit);
1648 if (ret)
1649 return ret;
1650
1651 /* Wait for 2 reference cycles before checking the ACK bit. */
1652 udelay(1);
1653 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1654 if (!(val & latch_ack)) {
1655 pr_err("Lucid PLL latch failed. Output may be unstable!\n");
1656 return -EINVAL;
1657 }
1658
1659 /* Return the latch input to 0 */
1660 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, 0);
1661 if (ret)
1662 return ret;
1663
1664 if (clk_hw_is_enabled(hw)) {
1665 ret = wait_for_pll_enable_lock(pll);
1666 if (ret)
1667 return ret;
1668 }
1669
1670 /* Wait for PLL output to stabilize */
1671 udelay(100);
1672 return 0;
1673}
1674
1675static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,
1676 unsigned long prate)
1677{
1678 return __alpha_pll_trion_set_rate(hw, rate, prate, PLL_UPDATE, ALPHA_PLL_ACK_LATCH);
1679}
1680
1681const struct clk_ops clk_alpha_pll_trion_ops = {
1682 .prepare = alpha_pll_trion_prepare,
1683 .enable = clk_trion_pll_enable,
1684 .disable = clk_trion_pll_disable,
1685 .is_enabled = clk_trion_pll_is_enabled,
1686 .recalc_rate = clk_trion_pll_recalc_rate,
1687 .round_rate = clk_alpha_pll_round_rate,
1688 .set_rate = alpha_pll_trion_set_rate,
1689};
1690EXPORT_SYMBOL_GPL(clk_alpha_pll_trion_ops);
1691
1692const struct clk_ops clk_alpha_pll_lucid_ops = {
1693 .prepare = alpha_pll_lucid_prepare,
1694 .enable = clk_trion_pll_enable,
1695 .disable = clk_trion_pll_disable,
1696 .is_enabled = clk_trion_pll_is_enabled,
1697 .recalc_rate = clk_trion_pll_recalc_rate,
1698 .round_rate = clk_alpha_pll_round_rate,
1699 .set_rate = alpha_pll_trion_set_rate,
1700};
1701EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops);
1702
1703const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = {
1704 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
1705 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
1706 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
1707};
1708EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops);
1709
1710void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1711 const struct alpha_pll_config *config)
1712{
1713 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1714 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
1715 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
1716 config->user_ctl_val);
1717 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
1718 config->config_ctl_val);
1719 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
1720 config->config_ctl_hi_val);
1721 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
1722 config->test_ctl_val);
1723 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
1724 config->test_ctl_hi_val);
1725}
1726EXPORT_SYMBOL_GPL(clk_agera_pll_configure);
1727
1728static int clk_alpha_pll_agera_set_rate(struct clk_hw *hw, unsigned long rate,
1729 unsigned long prate)
1730{
1731 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1732 u32 l, alpha_width = pll_alpha_width(pll);
1733 int ret;
1734 unsigned long rrate;
1735 u64 a;
1736
1737 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
1738 ret = alpha_pll_check_rate_margin(hw, rrate, rate);
1739 if (ret < 0)
1740 return ret;
1741
1742 /* change L_VAL without having to go through the power on sequence */
1743 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
1744 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
1745
1746 if (clk_hw_is_enabled(hw))
1747 return wait_for_pll_enable_lock(pll);
1748
1749 return 0;
1750}
1751
1752const struct clk_ops clk_alpha_pll_agera_ops = {
1753 .enable = clk_alpha_pll_enable,
1754 .disable = clk_alpha_pll_disable,
1755 .is_enabled = clk_alpha_pll_is_enabled,
1756 .recalc_rate = alpha_pll_fabia_recalc_rate,
1757 .round_rate = clk_alpha_pll_round_rate,
1758 .set_rate = clk_alpha_pll_agera_set_rate,
1759};
1760EXPORT_SYMBOL_GPL(clk_alpha_pll_agera_ops);
1761
1762static int alpha_pll_lucid_5lpe_enable(struct clk_hw *hw)
1763{
1764 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1765 u32 val;
1766 int ret;
1767
1768 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
1769 if (ret)
1770 return ret;
1771
1772 /* If in FSM mode, just vote for it */
1773 if (val & LUCID_5LPE_ENABLE_VOTE_RUN) {
1774 ret = clk_enable_regmap(hw);
1775 if (ret)
1776 return ret;
1777 return wait_for_pll_enable_lock(pll);
1778 }
1779
1780 /* Check if PLL is already enabled, return if enabled */
1781 ret = trion_pll_is_enabled(pll, pll->clkr.regmap);
1782 if (ret < 0)
1783 return ret;
1784
1785 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1786 if (ret)
1787 return ret;
1788
1789 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN);
1790
1791 ret = wait_for_pll_enable_lock(pll);
1792 if (ret)
1793 return ret;
1794
1795 /* Enable the PLL outputs */
1796 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK);
1797 if (ret)
1798 return ret;
1799
1800 /* Enable the global PLL outputs */
1801 return regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
1802}
1803
1804static void alpha_pll_lucid_5lpe_disable(struct clk_hw *hw)
1805{
1806 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1807 u32 val;
1808 int ret;
1809
1810 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
1811 if (ret)
1812 return;
1813
1814 /* If in FSM mode, just unvote it */
1815 if (val & LUCID_5LPE_ENABLE_VOTE_RUN) {
1816 clk_disable_regmap(hw);
1817 return;
1818 }
1819
1820 /* Disable the global PLL output */
1821 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1822 if (ret)
1823 return;
1824
1825 /* Disable the PLL outputs */
1826 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
1827 if (ret)
1828 return;
1829
1830 /* Place the PLL mode in STANDBY */
1831 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY);
1832}
1833
1834/*
1835 * The Lucid 5LPE PLL requires a power-on self-calibration which happens
1836 * when the PLL comes out of reset. Calibrate in case it is not completed.
1837 */
1838static int alpha_pll_lucid_5lpe_prepare(struct clk_hw *hw)
1839{
1840 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1841 struct clk_hw *p;
1842 u32 val = 0;
1843 int ret;
1844
1845 /* Return early if calibration is not needed. */
1846 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1847 if (val & LUCID_5LPE_PCAL_DONE)
1848 return 0;
1849
1850 p = clk_hw_get_parent(hw);
1851 if (!p)
1852 return -EINVAL;
1853
1854 ret = alpha_pll_lucid_5lpe_enable(hw);
1855 if (ret)
1856 return ret;
1857
1858 alpha_pll_lucid_5lpe_disable(hw);
1859
1860 return 0;
1861}
1862
1863static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate,
1864 unsigned long prate)
1865{
1866 return __alpha_pll_trion_set_rate(hw, rate, prate,
1867 LUCID_5LPE_PLL_LATCH_INPUT,
1868 LUCID_5LPE_ALPHA_PLL_ACK_LATCH);
1869}
1870
1871static int __clk_lucid_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1872 unsigned long parent_rate,
1873 unsigned long enable_vote_run)
1874{
1875 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1876 struct regmap *regmap = pll->clkr.regmap;
1877 int i, val, div, ret;
1878 u32 mask;
1879
1880 /*
1881 * If the PLL is in FSM mode, then treat set_rate callback as a
1882 * no-operation.
1883 */
1884 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
1885 if (ret)
1886 return ret;
1887
1888 if (val & enable_vote_run)
1889 return 0;
1890
1891 if (!pll->post_div_table) {
1892 pr_err("Missing the post_div_table for the %s PLL\n",
1893 clk_hw_get_name(&pll->clkr.hw));
1894 return -EINVAL;
1895 }
1896
1897 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
1898 for (i = 0; i < pll->num_post_div; i++) {
1899 if (pll->post_div_table[i].div == div) {
1900 val = pll->post_div_table[i].val;
1901 break;
1902 }
1903 }
1904
1905 mask = GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift);
1906 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
1907 mask, val << pll->post_div_shift);
1908}
1909
1910static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1911 unsigned long parent_rate)
1912{
1913 return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_5LPE_ENABLE_VOTE_RUN);
1914}
1915
1916const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = {
1917 .prepare = alpha_pll_lucid_5lpe_prepare,
1918 .enable = alpha_pll_lucid_5lpe_enable,
1919 .disable = alpha_pll_lucid_5lpe_disable,
1920 .is_enabled = clk_trion_pll_is_enabled,
1921 .recalc_rate = clk_trion_pll_recalc_rate,
1922 .round_rate = clk_alpha_pll_round_rate,
1923 .set_rate = alpha_pll_lucid_5lpe_set_rate,
1924};
1925EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_5lpe_ops);
1926
1927const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = {
1928 .enable = alpha_pll_lucid_5lpe_enable,
1929 .disable = alpha_pll_lucid_5lpe_disable,
1930 .is_enabled = clk_trion_pll_is_enabled,
1931 .recalc_rate = clk_trion_pll_recalc_rate,
1932 .round_rate = clk_alpha_pll_round_rate,
1933};
1934EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_5lpe_ops);
1935
1936const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = {
1937 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
1938 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
1939 .set_rate = clk_lucid_5lpe_pll_postdiv_set_rate,
1940};
1941EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_5lpe_ops);
1942
1943void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1944 const struct alpha_pll_config *config)
1945{
1946 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1947 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
1948 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
1949 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
1950 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
1951 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
1952 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
1953 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val);
1954 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
1955 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
1956 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
1957
1958 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, 0);
1959
1960 /* Disable PLL output */
1961 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1962
1963 /* Set operation mode to OFF */
1964 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1965
1966 /* Place the PLL in STANDBY mode */
1967 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1968}
1969EXPORT_SYMBOL_GPL(clk_zonda_pll_configure);
1970
1971static int clk_zonda_pll_enable(struct clk_hw *hw)
1972{
1973 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1974 struct regmap *regmap = pll->clkr.regmap;
1975 u32 val;
1976 int ret;
1977
1978 regmap_read(regmap, PLL_MODE(pll), &val);
1979
1980 /* If in FSM mode, just vote for it */
1981 if (val & PLL_VOTE_FSM_ENA) {
1982 ret = clk_enable_regmap(hw);
1983 if (ret)
1984 return ret;
1985 return wait_for_pll_enable_active(pll);
1986 }
1987
1988 /* Get the PLL out of bypass mode */
1989 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL);
1990
1991 /*
1992 * H/W requires a 1us delay between disabling the bypass and
1993 * de-asserting the reset.
1994 */
1995 udelay(1);
1996
1997 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1998
1999 /* Set operation mode to RUN */
2000 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
2001
2002 regmap_read(regmap, PLL_TEST_CTL(pll), &val);
2003
2004 /* If cfa mode then poll for freq lock */
2005 if (val & ZONDA_STAY_IN_CFA)
2006 ret = wait_for_zonda_pll_freq_lock(pll);
2007 else
2008 ret = wait_for_pll_enable_lock(pll);
2009 if (ret)
2010 return ret;
2011
2012 /* Enable the PLL outputs */
2013 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK);
2014
2015 /* Enable the global PLL outputs */
2016 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
2017
2018 return 0;
2019}
2020
2021static void clk_zonda_pll_disable(struct clk_hw *hw)
2022{
2023 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2024 struct regmap *regmap = pll->clkr.regmap;
2025 u32 val;
2026
2027 regmap_read(regmap, PLL_MODE(pll), &val);
2028
2029 /* If in FSM mode, just unvote it */
2030 if (val & PLL_VOTE_FSM_ENA) {
2031 clk_disable_regmap(hw);
2032 return;
2033 }
2034
2035 /* Disable the global PLL output */
2036 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2037
2038 /* Disable the PLL outputs */
2039 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, 0);
2040
2041 /* Put the PLL in bypass and reset */
2042 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, 0);
2043
2044 /* Place the PLL mode in OFF state */
2045 regmap_write(regmap, PLL_OPMODE(pll), 0x0);
2046}
2047
2048static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate,
2049 unsigned long prate)
2050{
2051 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2052 unsigned long rrate;
2053 u32 test_ctl_val;
2054 u32 l, alpha_width = pll_alpha_width(pll);
2055 u64 a;
2056 int ret;
2057
2058 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
2059
2060 ret = alpha_pll_check_rate_margin(hw, rrate, rate);
2061 if (ret < 0)
2062 return ret;
2063
2064 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
2065 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
2066
2067 /* Wait before polling for the frequency latch */
2068 udelay(5);
2069
2070 /* Read stay in cfa mode */
2071 regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val);
2072
2073 /* If cfa mode then poll for freq lock */
2074 if (test_ctl_val & ZONDA_STAY_IN_CFA)
2075 ret = wait_for_zonda_pll_freq_lock(pll);
2076 else
2077 ret = wait_for_pll_enable_lock(pll);
2078 if (ret)
2079 return ret;
2080
2081 /* Wait for PLL output to stabilize */
2082 udelay(100);
2083 return 0;
2084}
2085
2086const struct clk_ops clk_alpha_pll_zonda_ops = {
2087 .enable = clk_zonda_pll_enable,
2088 .disable = clk_zonda_pll_disable,
2089 .is_enabled = clk_trion_pll_is_enabled,
2090 .recalc_rate = clk_trion_pll_recalc_rate,
2091 .round_rate = clk_alpha_pll_round_rate,
2092 .set_rate = clk_zonda_pll_set_rate,
2093};
2094EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops);
2095
2096void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2097 const struct alpha_pll_config *config)
2098{
2099 u32 lval = config->l;
2100
2101 lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT;
2102 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval);
2103 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
2104 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2105 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
2106 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
2107 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
2108 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
2109 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2110 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2111 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
2112 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val);
2113
2114 /* Disable PLL output */
2115 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2116
2117 /* Set operation mode to STANDBY and de-assert the reset */
2118 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2119 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2120}
2121EXPORT_SYMBOL_GPL(clk_lucid_evo_pll_configure);
2122
2123void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2124 const struct alpha_pll_config *config)
2125{
2126 u32 lval = config->l;
2127
2128 lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT;
2129 lval |= TRION_PLL_CAL_VAL << LUCID_OLE_PLL_RINGOSC_CAL_L_VAL_SHIFT;
2130 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval);
2131 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
2132 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2133 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
2134 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
2135 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
2136 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
2137 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2138 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2139 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
2140 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val);
2141
2142 /* Disable PLL output */
2143 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2144
2145 /* Set operation mode to STANDBY and de-assert the reset */
2146 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2147 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2148}
2149EXPORT_SYMBOL_GPL(clk_lucid_ole_pll_configure);
2150
2151static int alpha_pll_lucid_evo_enable(struct clk_hw *hw)
2152{
2153 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2154 struct regmap *regmap = pll->clkr.regmap;
2155 u32 val;
2156 int ret;
2157
2158 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
2159 if (ret)
2160 return ret;
2161
2162 /* If in FSM mode, just vote for it */
2163 if (val & LUCID_EVO_ENABLE_VOTE_RUN) {
2164 ret = clk_enable_regmap(hw);
2165 if (ret)
2166 return ret;
2167 return wait_for_pll_enable_lock(pll);
2168 }
2169
2170 /* Check if PLL is already enabled */
2171 ret = trion_pll_is_enabled(pll, regmap);
2172 if (ret < 0) {
2173 return ret;
2174 } else if (ret) {
2175 pr_warn("%s PLL is already enabled\n", clk_hw_get_name(&pll->clkr.hw));
2176 return 0;
2177 }
2178
2179 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2180 if (ret)
2181 return ret;
2182
2183 /* Set operation mode to RUN */
2184 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
2185
2186 ret = wait_for_pll_enable_lock(pll);
2187 if (ret)
2188 return ret;
2189
2190 /* Enable the PLL outputs */
2191 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK);
2192 if (ret)
2193 return ret;
2194
2195 /* Enable the global PLL outputs */
2196 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
2197 if (ret)
2198 return ret;
2199
2200 /* Ensure that the write above goes through before returning. */
2201 mb();
2202 return ret;
2203}
2204
2205static void _alpha_pll_lucid_evo_disable(struct clk_hw *hw, bool reset)
2206{
2207 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2208 struct regmap *regmap = pll->clkr.regmap;
2209 u32 val;
2210 int ret;
2211
2212 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
2213 if (ret)
2214 return;
2215
2216 /* If in FSM mode, just unvote it */
2217 if (val & LUCID_EVO_ENABLE_VOTE_RUN) {
2218 clk_disable_regmap(hw);
2219 return;
2220 }
2221
2222 /* Disable the global PLL output */
2223 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2224 if (ret)
2225 return;
2226
2227 /* Disable the PLL outputs */
2228 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
2229 if (ret)
2230 return;
2231
2232 /* Place the PLL mode in STANDBY */
2233 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2234
2235 if (reset)
2236 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 0);
2237}
2238
2239static int _alpha_pll_lucid_evo_prepare(struct clk_hw *hw, bool reset)
2240{
2241 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2242 struct clk_hw *p;
2243 u32 val = 0;
2244 int ret;
2245
2246 /* Return early if calibration is not needed. */
2247 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
2248 if (!(val & LUCID_EVO_PCAL_NOT_DONE))
2249 return 0;
2250
2251 p = clk_hw_get_parent(hw);
2252 if (!p)
2253 return -EINVAL;
2254
2255 ret = alpha_pll_lucid_evo_enable(hw);
2256 if (ret)
2257 return ret;
2258
2259 _alpha_pll_lucid_evo_disable(hw, reset);
2260
2261 return 0;
2262}
2263
2264static void alpha_pll_lucid_evo_disable(struct clk_hw *hw)
2265{
2266 _alpha_pll_lucid_evo_disable(hw, false);
2267}
2268
2269static int alpha_pll_lucid_evo_prepare(struct clk_hw *hw)
2270{
2271 return _alpha_pll_lucid_evo_prepare(hw, false);
2272}
2273
2274static void alpha_pll_reset_lucid_evo_disable(struct clk_hw *hw)
2275{
2276 _alpha_pll_lucid_evo_disable(hw, true);
2277}
2278
2279static int alpha_pll_reset_lucid_evo_prepare(struct clk_hw *hw)
2280{
2281 return _alpha_pll_lucid_evo_prepare(hw, true);
2282}
2283
2284static unsigned long alpha_pll_lucid_evo_recalc_rate(struct clk_hw *hw,
2285 unsigned long parent_rate)
2286{
2287 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2288 struct regmap *regmap = pll->clkr.regmap;
2289 u32 l, frac;
2290
2291 regmap_read(regmap, PLL_L_VAL(pll), &l);
2292 l &= LUCID_EVO_PLL_L_VAL_MASK;
2293 regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac);
2294
2295 return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll));
2296}
2297
2298static int clk_lucid_evo_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
2299 unsigned long parent_rate)
2300{
2301 return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_EVO_ENABLE_VOTE_RUN);
2302}
2303
2304const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops = {
2305 .enable = alpha_pll_lucid_evo_enable,
2306 .disable = alpha_pll_lucid_evo_disable,
2307 .is_enabled = clk_trion_pll_is_enabled,
2308 .recalc_rate = alpha_pll_lucid_evo_recalc_rate,
2309 .round_rate = clk_alpha_pll_round_rate,
2310};
2311EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_evo_ops);
2312
2313const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops = {
2314 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
2315 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
2316 .set_rate = clk_lucid_evo_pll_postdiv_set_rate,
2317};
2318EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_evo_ops);
2319
2320const struct clk_ops clk_alpha_pll_lucid_evo_ops = {
2321 .prepare = alpha_pll_lucid_evo_prepare,
2322 .enable = alpha_pll_lucid_evo_enable,
2323 .disable = alpha_pll_lucid_evo_disable,
2324 .is_enabled = clk_trion_pll_is_enabled,
2325 .recalc_rate = alpha_pll_lucid_evo_recalc_rate,
2326 .round_rate = clk_alpha_pll_round_rate,
2327 .set_rate = alpha_pll_lucid_5lpe_set_rate,
2328};
2329EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_evo_ops);
2330
2331const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops = {
2332 .prepare = alpha_pll_reset_lucid_evo_prepare,
2333 .enable = alpha_pll_lucid_evo_enable,
2334 .disable = alpha_pll_reset_lucid_evo_disable,
2335 .is_enabled = clk_trion_pll_is_enabled,
2336 .recalc_rate = alpha_pll_lucid_evo_recalc_rate,
2337 .round_rate = clk_alpha_pll_round_rate,
2338 .set_rate = alpha_pll_lucid_5lpe_set_rate,
2339};
2340EXPORT_SYMBOL_GPL(clk_alpha_pll_reset_lucid_evo_ops);
2341
2342void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2343 const struct alpha_pll_config *config)
2344{
2345 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2346 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
2347 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
2348 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2349 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2350 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
2351 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
2352 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
2353
2354 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2355
2356 regmap_update_bits(regmap, PLL_MODE(pll),
2357 PLL_RESET_N | PLL_BYPASSNL | PLL_OUTCTRL,
2358 PLL_RESET_N | PLL_BYPASSNL);
2359}
2360EXPORT_SYMBOL_GPL(clk_rivian_evo_pll_configure);
2361
2362static unsigned long clk_rivian_evo_pll_recalc_rate(struct clk_hw *hw,
2363 unsigned long parent_rate)
2364{
2365 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2366 u32 l;
2367
2368 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
2369
2370 return parent_rate * l;
2371}
2372
2373static long clk_rivian_evo_pll_round_rate(struct clk_hw *hw, unsigned long rate,
2374 unsigned long *prate)
2375{
2376 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2377 unsigned long min_freq, max_freq;
2378 u32 l;
2379 u64 a;
2380
2381 rate = alpha_pll_round_rate(rate, *prate, &l, &a, 0);
2382 if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
2383 return rate;
2384
2385 min_freq = pll->vco_table[0].min_freq;
2386 max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
2387
2388 return clamp(rate, min_freq, max_freq);
2389}
2390
2391const struct clk_ops clk_alpha_pll_rivian_evo_ops = {
2392 .enable = alpha_pll_lucid_5lpe_enable,
2393 .disable = alpha_pll_lucid_5lpe_disable,
2394 .is_enabled = clk_trion_pll_is_enabled,
2395 .recalc_rate = clk_rivian_evo_pll_recalc_rate,
2396 .round_rate = clk_rivian_evo_pll_round_rate,
2397};
2398EXPORT_SYMBOL_GPL(clk_alpha_pll_rivian_evo_ops);
2399
2400void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2401 const struct alpha_pll_config *config)
2402{
2403 u32 val, val_u, mask, mask_u;
2404
2405 regmap_write(regmap, PLL_L_VAL(pll), config->l);
2406 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
2407 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2408
2409 if (pll_has_64bit_config(pll))
2410 regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
2411 config->config_ctl_hi_val);
2412
2413 if (pll_alpha_width(pll) > 32)
2414 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi);
2415
2416 val = config->main_output_mask;
2417 val |= config->aux_output_mask;
2418 val |= config->aux2_output_mask;
2419 val |= config->early_output_mask;
2420 val |= config->pre_div_val;
2421 val |= config->post_div_val;
2422 val |= config->vco_val;
2423 val |= config->alpha_en_mask;
2424 val |= config->alpha_mode_mask;
2425
2426 mask = config->main_output_mask;
2427 mask |= config->aux_output_mask;
2428 mask |= config->aux2_output_mask;
2429 mask |= config->early_output_mask;
2430 mask |= config->pre_div_mask;
2431 mask |= config->post_div_mask;
2432 mask |= config->vco_mask;
2433 mask |= config->alpha_en_mask;
2434 mask |= config->alpha_mode_mask;
2435
2436 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
2437
2438 /* Stromer APSS PLL does not enable LOCK_DET by default, so enable it */
2439 val_u = config->status_val << ALPHA_PLL_STATUS_REG_SHIFT;
2440 val_u |= config->lock_det;
2441
2442 mask_u = config->status_mask;
2443 mask_u |= config->lock_det;
2444
2445 regmap_update_bits(regmap, PLL_USER_CTL_U(pll), mask_u, val_u);
2446 regmap_write(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2447 regmap_write(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2448
2449 if (pll->flags & SUPPORTS_FSM_MODE)
2450 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
2451}
2452EXPORT_SYMBOL_GPL(clk_stromer_pll_configure);
2453
2454static int clk_alpha_pll_stromer_determine_rate(struct clk_hw *hw,
2455 struct clk_rate_request *req)
2456{
2457 u32 l;
2458 u64 a;
2459
2460 req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate,
2461 &l, &a, ALPHA_REG_BITWIDTH);
2462
2463 return 0;
2464}
2465
2466static int clk_alpha_pll_stromer_set_rate(struct clk_hw *hw, unsigned long rate,
2467 unsigned long prate)
2468{
2469 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2470 int ret;
2471 u32 l;
2472 u64 a;
2473
2474 rate = alpha_pll_round_rate(rate, prate, &l, &a, ALPHA_REG_BITWIDTH);
2475
2476 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
2477 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
2478 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
2479 a >> ALPHA_BITWIDTH);
2480
2481 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
2482 PLL_ALPHA_EN, PLL_ALPHA_EN);
2483
2484 if (!clk_hw_is_enabled(hw))
2485 return 0;
2486
2487 /*
2488 * Stromer PLL supports Dynamic programming.
2489 * It allows the PLL frequency to be changed on-the-fly without first
2490 * execution of a shutdown procedure followed by a bring up procedure.
2491 */
2492 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE,
2493 PLL_UPDATE);
2494
2495 ret = wait_for_pll_update(pll);
2496 if (ret)
2497 return ret;
2498
2499 return wait_for_pll_enable_lock(pll);
2500}
2501
2502const struct clk_ops clk_alpha_pll_stromer_ops = {
2503 .enable = clk_alpha_pll_enable,
2504 .disable = clk_alpha_pll_disable,
2505 .is_enabled = clk_alpha_pll_is_enabled,
2506 .recalc_rate = clk_alpha_pll_recalc_rate,
2507 .determine_rate = clk_alpha_pll_stromer_determine_rate,
2508 .set_rate = clk_alpha_pll_stromer_set_rate,
2509};
2510EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_ops);
2511
2512static int clk_alpha_pll_stromer_plus_set_rate(struct clk_hw *hw,
2513 unsigned long rate,
2514 unsigned long prate)
2515{
2516 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2517 u32 l, alpha_width = pll_alpha_width(pll);
2518 int ret, pll_mode;
2519 u64 a;
2520
2521 rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
2522
2523 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &pll_mode);
2524 if (ret)
2525 return ret;
2526
2527 regmap_write(pll->clkr.regmap, PLL_MODE(pll), 0);
2528
2529 /* Delay of 2 output clock ticks required until output is disabled */
2530 udelay(1);
2531
2532 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
2533
2534 if (alpha_width > ALPHA_BITWIDTH)
2535 a <<= alpha_width - ALPHA_BITWIDTH;
2536
2537 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
2538 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
2539 a >> ALPHA_BITWIDTH);
2540
2541 regmap_write(pll->clkr.regmap, PLL_MODE(pll), PLL_BYPASSNL);
2542
2543 /* Wait five micro seconds or more */
2544 udelay(5);
2545 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N,
2546 PLL_RESET_N);
2547
2548 /* The lock time should be less than 50 micro seconds worst case */
2549 usleep_range(50, 60);
2550
2551 ret = wait_for_pll_enable_lock(pll);
2552 if (ret) {
2553 pr_err("Wait for PLL enable lock failed [%s] %d\n",
2554 clk_hw_get_name(hw), ret);
2555 return ret;
2556 }
2557
2558 if (pll_mode & PLL_OUTCTRL)
2559 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL,
2560 PLL_OUTCTRL);
2561
2562 return 0;
2563}
2564
2565const struct clk_ops clk_alpha_pll_stromer_plus_ops = {
2566 .prepare = clk_alpha_pll_enable,
2567 .unprepare = clk_alpha_pll_disable,
2568 .is_enabled = clk_alpha_pll_is_enabled,
2569 .recalc_rate = clk_alpha_pll_recalc_rate,
2570 .determine_rate = clk_alpha_pll_stromer_determine_rate,
2571 .set_rate = clk_alpha_pll_stromer_plus_set_rate,
2572};
2573EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_plus_ops);