1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
   4 * Copyright (c) 2023, Linaro Ltd.
   5 */
   6
   7#include <linux/clk-provider.h>
   8#include <linux/mod_devicetable.h>
   9#include <linux/module.h>
  10#include <linux/platform_device.h>
  11#include <linux/pm_runtime.h>
  12#include <linux/regmap.h>
  13
  14#include <dt-bindings/clock/qcom,sc8280xp-camcc.h>
  15
  16#include "clk-alpha-pll.h"
  17#include "clk-branch.h"
  18#include "clk-rcg.h"
  19#include "clk-regmap.h"
  20#include "common.h"
  21#include "gdsc.h"
  22#include "reset.h"
  23
  24enum {
  25	DT_IFACE,
  26	DT_BI_TCXO,
  27	DT_BI_TCXO_AO,
  28	DT_SLEEP_CLK,
  29};
  30
  31enum {
  32	P_BI_TCXO,
  33	P_CAMCC_PLL0_OUT_EVEN,
  34	P_CAMCC_PLL0_OUT_MAIN,
  35	P_CAMCC_PLL0_OUT_ODD,
  36	P_CAMCC_PLL1_OUT_EVEN,
  37	P_CAMCC_PLL2_OUT_AUX,
  38	P_CAMCC_PLL2_OUT_EARLY,
  39	P_CAMCC_PLL3_OUT_EVEN,
  40	P_CAMCC_PLL4_OUT_EVEN,
  41	P_CAMCC_PLL5_OUT_EVEN,
  42	P_CAMCC_PLL6_OUT_EVEN,
  43	P_CAMCC_PLL7_OUT_EVEN,
  44	P_CAMCC_PLL7_OUT_ODD,
  45	P_SLEEP_CLK,
  46};
  47
  48static struct pll_vco lucid_vco[] = {
  49	{ 249600000, 1800000000, 0 },
  50};
  51
  52static struct pll_vco zonda_vco[] = {
  53	{ 595200000, 3600000000, 0 },
  54};
  55
  56static struct alpha_pll_config camcc_pll0_config = {
  57	.l = 0x3e,
  58	.alpha = 0x8000,
  59	.config_ctl_val = 0x20485699,
  60	.config_ctl_hi_val = 0x00002261,
  61	.config_ctl_hi1_val = 0x2a9a699c,
  62	.test_ctl_val = 0x00000000,
  63	.test_ctl_hi_val = 0x00000000,
  64	.test_ctl_hi1_val = 0x01800000,
  65	.user_ctl_val = 0x00003100,
  66	.user_ctl_hi_val = 0x00000805,
  67	.user_ctl_hi1_val = 0x00000000,
  68};
  69
  70static struct clk_alpha_pll camcc_pll0 = {
  71	.offset = 0x0,
  72	.vco_table = lucid_vco,
  73	.num_vco = ARRAY_SIZE(lucid_vco),
  74	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
  75	.clkr = {
  76		.hw.init = &(struct clk_init_data){
  77			.name = "camcc_pll0",
  78			.parent_data = &(const struct clk_parent_data){
  79				.index = DT_BI_TCXO,
  80			},
  81			.num_parents = 1,
  82			.ops = &clk_alpha_pll_lucid_5lpe_ops,
  83		},
  84	},
  85};
  86
  87static const struct clk_div_table post_div_table_camcc_pll0_out_even[] = {
  88	{ 0x1, 2 },
  89};
  90
  91static struct clk_alpha_pll_postdiv camcc_pll0_out_even = {
  92	.offset = 0x0,
  93	.post_div_shift = 8,
  94	.post_div_table = post_div_table_camcc_pll0_out_even,
  95	.num_post_div = ARRAY_SIZE(post_div_table_camcc_pll0_out_even),
  96	.width = 4,
  97	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
  98	.clkr.hw.init = &(struct clk_init_data){
  99		.name = "camcc_pll0_out_even",
 100		.parent_hws = (const struct clk_hw*[]){
 101			&camcc_pll0.clkr.hw,
 102		},
 103		.num_parents = 1,
 104		.flags = CLK_SET_RATE_PARENT,
 105		.ops = &clk_alpha_pll_postdiv_lucid_ops,
 106	},
 107};
 108
 109static const struct clk_div_table post_div_table_camcc_pll0_out_odd[] = {
 110	{ 0x3, 3 },
 111};
 112
 113static struct clk_alpha_pll_postdiv camcc_pll0_out_odd = {
 114	.offset = 0x0,
 115	.post_div_shift = 12,
 116	.post_div_table = post_div_table_camcc_pll0_out_odd,
 117	.num_post_div = ARRAY_SIZE(post_div_table_camcc_pll0_out_odd),
 118	.width = 4,
 119	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
 120	.clkr.hw.init = &(struct clk_init_data){
 121		.name = "camcc_pll0_out_odd",
 122		.parent_hws = (const struct clk_hw*[]){
 123			&camcc_pll0.clkr.hw,
 124		},
 125		.num_parents = 1,
 126		.flags = CLK_SET_RATE_PARENT,
 127		.ops = &clk_alpha_pll_postdiv_lucid_ops,
 128	},
 129};
 130
 131static struct alpha_pll_config camcc_pll1_config = {
 132	.l = 0x21,
 133	.alpha = 0x5555,
 134	.config_ctl_val = 0x20485699,
 135	.config_ctl_hi_val = 0x00002261,
 136	.config_ctl_hi1_val = 0x2a9a699c,
 137	.test_ctl_val = 0x00000000,
 138	.test_ctl_hi_val = 0x00000000,
 139	.test_ctl_hi1_val = 0x01800000,
 140	.user_ctl_val = 0x00000100,
 141	.user_ctl_hi_val = 0x00000805,
 142	.user_ctl_hi1_val = 0x00000000,
 143};
 144
 145static struct clk_alpha_pll camcc_pll1 = {
 146	.offset = 0x1000,
 147	.vco_table = lucid_vco,
 148	.num_vco = ARRAY_SIZE(lucid_vco),
 149	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
 150	.clkr = {
 151		.hw.init = &(struct clk_init_data){
 152			.name = "camcc_pll1",
 153			.parent_data = &(const struct clk_parent_data){
 154				.index = DT_BI_TCXO,
 155			},
 156			.num_parents = 1,
 157			.ops = &clk_alpha_pll_lucid_5lpe_ops,
 158		},
 159	},
 160};
 161
 162static const struct clk_div_table post_div_table_camcc_pll1_out_even[] = {
 163	{ 0x1, 2 },
 164};
 165
 166static struct clk_alpha_pll_postdiv camcc_pll1_out_even = {
 167	.offset = 0x1000,
 168	.post_div_shift = 8,
 169	.post_div_table = post_div_table_camcc_pll1_out_even,
 170	.num_post_div = ARRAY_SIZE(post_div_table_camcc_pll1_out_even),
 171	.width = 4,
 172	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
 173	.clkr.hw.init = &(struct clk_init_data){
 174		.name = "camcc_pll1_out_even",
 175		.parent_hws = (const struct clk_hw*[]){
 176			&camcc_pll1.clkr.hw,
 177		},
 178		.num_parents = 1,
 179		.flags = CLK_SET_RATE_PARENT,
 180		.ops = &clk_alpha_pll_postdiv_lucid_ops,
 181	},
 182};
 183
 184static struct alpha_pll_config camcc_pll2_config = {
 185	.l = 0x32,
 186	.alpha = 0x0,
 187	.config_ctl_val = 0x08200800,
 188	.config_ctl_hi_val = 0x05028011,
 189	.config_ctl_hi1_val = 0x08000000,
 190};
 191
 192static struct clk_alpha_pll camcc_pll2 = {
 193	.offset = 0x2000,
 194	.vco_table = zonda_vco,
 195	.num_vco = ARRAY_SIZE(zonda_vco),
 196	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA],
 197	.clkr = {
 198		.hw.init = &(struct clk_init_data){
 199			.name = "camcc_pll2",
 200			.parent_data = &(const struct clk_parent_data){
 201				.index = DT_BI_TCXO,
 202			},
 203			.num_parents = 1,
 204			.ops = &clk_alpha_pll_zonda_ops,
 205		},
 206	},
 207};
 208
 209static struct alpha_pll_config camcc_pll3_config = {
 210	.l = 0x29,
 211	.alpha = 0xaaaa,
 212	.config_ctl_val = 0x20485699,
 213	.config_ctl_hi_val = 0x00002261,
 214	.config_ctl_hi1_val = 0x2a9a699c,
 215	.test_ctl_val = 0x00000000,
 216	.test_ctl_hi_val = 0x00000000,
 217	.test_ctl_hi1_val = 0x01800000,
 218	.user_ctl_val = 0x00000100,
 219	.user_ctl_hi_val = 0x00000805,
 220	.user_ctl_hi1_val = 0x00000000,
 221};
 222
 223static struct clk_alpha_pll camcc_pll3 = {
 224	.offset = 0x3000,
 225	.vco_table = lucid_vco,
 226	.num_vco = ARRAY_SIZE(lucid_vco),
 227	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
 228	.clkr = {
 229		.hw.init = &(struct clk_init_data){
 230			.name = "camcc_pll3",
 231			.parent_data = &(const struct clk_parent_data){
 232				.index = DT_BI_TCXO,
 233			},
 234			.num_parents = 1,
 235			.ops = &clk_alpha_pll_lucid_5lpe_ops,
 236		},
 237	},
 238};
 239
 240static const struct clk_div_table post_div_table_camcc_pll3_out_even[] = {
 241	{ 0x1, 2 },
 242};
 243
 244static struct clk_alpha_pll_postdiv camcc_pll3_out_even = {
 245	.offset = 0x3000,
 246	.post_div_shift = 8,
 247	.post_div_table = post_div_table_camcc_pll3_out_even,
 248	.num_post_div = ARRAY_SIZE(post_div_table_camcc_pll3_out_even),
 249	.width = 4,
 250	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
 251	.clkr.hw.init = &(struct clk_init_data){
 252		.name = "camcc_pll3_out_even",
 253		.parent_hws = (const struct clk_hw*[]){
 254			&camcc_pll3.clkr.hw,
 255		},
 256		.num_parents = 1,
 257		.flags = CLK_SET_RATE_PARENT,
 258		.ops = &clk_alpha_pll_postdiv_lucid_ops,
 259	},
 260};
 261
 262static struct alpha_pll_config camcc_pll4_config = {
 263	.l = 0x29,
 264	.alpha = 0xaaaa,
 265	.config_ctl_val = 0x20485699,
 266	.config_ctl_hi_val = 0x00002261,
 267	.config_ctl_hi1_val = 0x2a9a699c,
 268	.test_ctl_val = 0x00000000,
 269	.test_ctl_hi_val = 0x00000000,
 270	.test_ctl_hi1_val = 0x01800000,
 271	.user_ctl_val = 0x00000100,
 272	.user_ctl_hi_val = 0x00000805,
 273	.user_ctl_hi1_val = 0x00000000,
 274};
 275
 276static struct clk_alpha_pll camcc_pll4 = {
 277	.offset = 0x4000,
 278	.vco_table = lucid_vco,
 279	.num_vco = ARRAY_SIZE(lucid_vco),
 280	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
 281	.clkr = {
 282		.hw.init = &(struct clk_init_data){
 283			.name = "camcc_pll4",
 284			.parent_data = &(const struct clk_parent_data){
 285				.index = DT_BI_TCXO,
 286			},
 287			.num_parents = 1,
 288			.ops = &clk_alpha_pll_lucid_5lpe_ops,
 289		},
 290	},
 291};
 292
 293static const struct clk_div_table post_div_table_camcc_pll4_out_even[] = {
 294	{ 0x1, 2 },
 295};
 296
 297static struct clk_alpha_pll_postdiv camcc_pll4_out_even = {
 298	.offset = 0x4000,
 299	.post_div_shift = 8,
 300	.post_div_table = post_div_table_camcc_pll4_out_even,
 301	.num_post_div = ARRAY_SIZE(post_div_table_camcc_pll4_out_even),
 302	.width = 4,
 303	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
 304	.clkr.hw.init = &(struct clk_init_data){
 305		.name = "camcc_pll4_out_even",
 306		.parent_hws = (const struct clk_hw*[]){
 307			&camcc_pll4.clkr.hw,
 308		},
 309		.num_parents = 1,
 310		.flags = CLK_SET_RATE_PARENT,
 311		.ops = &clk_alpha_pll_postdiv_lucid_ops,
 312	},
 313};
 314
 315static struct alpha_pll_config camcc_pll5_config = {
 316	.l = 0x29,
 317	.alpha = 0xaaaa,
 318	.config_ctl_val = 0x20485699,
 319	.config_ctl_hi_val = 0x00002261,
 320	.config_ctl_hi1_val = 0x2a9a699c,
 321	.test_ctl_val = 0x00000000,
 322	.test_ctl_hi_val = 0x00000000,
 323	.test_ctl_hi1_val = 0x01800000,
 324	.user_ctl_val = 0x00000100,
 325	.user_ctl_hi_val = 0x00000805,
 326	.user_ctl_hi1_val = 0x00000000,
 327};
 328
 329static struct clk_alpha_pll camcc_pll5 = {
 330	.offset = 0x10000,
 331	.vco_table = lucid_vco,
 332	.num_vco = ARRAY_SIZE(lucid_vco),
 333	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
 334	.clkr = {
 335		.hw.init = &(struct clk_init_data){
 336			.name = "camcc_pll5",
 337			.parent_data = &(const struct clk_parent_data){
 338				.index = DT_BI_TCXO,
 339			},
 340			.num_parents = 1,
 341			.ops = &clk_alpha_pll_lucid_5lpe_ops,
 342		},
 343	},
 344};
 345
 346static const struct clk_div_table post_div_table_camcc_pll5_out_even[] = {
 347	{ 0x1, 2 },
 348};
 349
 350static struct clk_alpha_pll_postdiv camcc_pll5_out_even = {
 351	.offset = 0x10000,
 352	.post_div_shift = 8,
 353	.post_div_table = post_div_table_camcc_pll5_out_even,
 354	.num_post_div = ARRAY_SIZE(post_div_table_camcc_pll5_out_even),
 355	.width = 4,
 356	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
 357	.clkr.hw.init = &(struct clk_init_data){
 358		.name = "camcc_pll5_out_even",
 359		.parent_hws = (const struct clk_hw*[]){
 360			&camcc_pll5.clkr.hw,
 361		},
 362		.num_parents = 1,
 363		.flags = CLK_SET_RATE_PARENT,
 364		.ops = &clk_alpha_pll_postdiv_lucid_ops,
 365	},
 366};
 367
 368static struct alpha_pll_config camcc_pll6_config = {
 369	.l = 0x29,
 370	.alpha = 0xaaaa,
 371	.config_ctl_val = 0x20486699,
 372	.config_ctl_hi_val = 0x00002261,
 373	.config_ctl_hi1_val = 0x2a9a699c,
 374	.test_ctl_val = 0x00000000,
 375	.test_ctl_hi_val = 0x00000000,
 376	.test_ctl_hi1_val = 0x01800000,
 377	.user_ctl_val = 0x00000100,
 378	.user_ctl_hi_val = 0x00000805,
 379	.user_ctl_hi1_val = 0x00000000,
 380};
 381
 382static struct clk_alpha_pll camcc_pll6 = {
 383	.offset = 0x11000,
 384	.vco_table = lucid_vco,
 385	.num_vco = ARRAY_SIZE(lucid_vco),
 386	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
 387	.clkr = {
 388		.hw.init = &(struct clk_init_data){
 389			.name = "camcc_pll6",
 390			.parent_data = &(const struct clk_parent_data){
 391				.index = DT_BI_TCXO,
 392			},
 393			.num_parents = 1,
 394			.ops = &clk_alpha_pll_lucid_5lpe_ops,
 395		},
 396	},
 397};
 398
 399static const struct clk_div_table post_div_table_camcc_pll6_out_even[] = {
 400	{ 0x1, 2 },
 401};
 402
 403static struct clk_alpha_pll_postdiv camcc_pll6_out_even = {
 404	.offset = 0x11000,
 405	.post_div_shift = 8,
 406	.post_div_table = post_div_table_camcc_pll6_out_even,
 407	.num_post_div = ARRAY_SIZE(post_div_table_camcc_pll6_out_even),
 408	.width = 4,
 409	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
 410	.clkr.hw.init = &(struct clk_init_data){
 411		.name = "camcc_pll6_out_even",
 412		.parent_hws = (const struct clk_hw*[]){
 413			&camcc_pll6.clkr.hw,
 414		},
 415		.num_parents = 1,
 416		.flags = CLK_SET_RATE_PARENT,
 417		.ops = &clk_alpha_pll_postdiv_lucid_ops,
 418	},
 419};
 420
 421static struct alpha_pll_config camcc_pll7_config = {
 422	.l = 0x32,
 423	.alpha = 0x0,
 424	.config_ctl_val = 0x20485699,
 425	.config_ctl_hi_val = 0x00002261,
 426	.config_ctl_hi1_val = 0x2a9a699c,
 427	.test_ctl_val = 0x00000000,
 428	.test_ctl_hi_val = 0x00000000,
 429	.test_ctl_hi1_val = 0x01800000,
 430	.user_ctl_val = 0x00003100,
 431	.user_ctl_hi_val = 0x00000805,
 432	.user_ctl_hi1_val = 0x00000000,
 433};
 434
 435static struct clk_alpha_pll camcc_pll7 = {
 436	.offset = 0x12000,
 437	.vco_table = lucid_vco,
 438	.num_vco = ARRAY_SIZE(lucid_vco),
 439	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
 440	.clkr = {
 441		.hw.init = &(struct clk_init_data){
 442			.name = "camcc_pll7",
 443			.parent_data = &(const struct clk_parent_data){
 444				.index = DT_BI_TCXO,
 445			},
 446			.num_parents = 1,
 447			.ops = &clk_alpha_pll_lucid_5lpe_ops,
 448		},
 449	},
 450};
 451
 452static const struct clk_div_table post_div_table_camcc_pll7_out_even[] = {
 453	{ 0x1, 2 },
 454};
 455
 456static struct clk_alpha_pll_postdiv camcc_pll7_out_even = {
 457	.offset = 0x12000,
 458	.post_div_shift = 8,
 459	.post_div_table = post_div_table_camcc_pll7_out_even,
 460	.num_post_div = ARRAY_SIZE(post_div_table_camcc_pll7_out_even),
 461	.width = 4,
 462	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
 463	.clkr.hw.init = &(struct clk_init_data){
 464		.name = "camcc_pll7_out_even",
 465		.parent_hws = (const struct clk_hw*[]){
 466			&camcc_pll7.clkr.hw,
 467		},
 468		.num_parents = 1,
 469		.flags = CLK_SET_RATE_PARENT,
 470		.ops = &clk_alpha_pll_postdiv_lucid_ops,
 471	},
 472};
 473
 474static const struct clk_div_table post_div_table_camcc_pll7_out_odd[] = {
 475	{ 0x3, 3 },
 476};
 477
 478static struct clk_alpha_pll_postdiv camcc_pll7_out_odd = {
 479	.offset = 0x12000,
 480	.post_div_shift = 12,
 481	.post_div_table = post_div_table_camcc_pll7_out_odd,
 482	.num_post_div = ARRAY_SIZE(post_div_table_camcc_pll7_out_odd),
 483	.width = 4,
 484	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
 485	.clkr.hw.init = &(struct clk_init_data){
 486		.name = "camcc_pll7_out_odd",
 487		.parent_hws = (const struct clk_hw*[]){
 488			&camcc_pll7.clkr.hw,
 489		},
 490		.num_parents = 1,
 491		.flags = CLK_SET_RATE_PARENT,
 492		.ops = &clk_alpha_pll_postdiv_lucid_ops,
 493	},
 494};
 495
 496static const struct parent_map camcc_parent_map_0[] = {
 497	{ P_BI_TCXO, 0 },
 498	{ P_CAMCC_PLL0_OUT_MAIN, 1 },
 499	{ P_CAMCC_PLL0_OUT_EVEN, 2 },
 500	{ P_CAMCC_PLL0_OUT_ODD, 3 },
 501	{ P_CAMCC_PLL7_OUT_EVEN, 5 },
 502};
 503
 504static const struct clk_parent_data camcc_parent_data_0[] = {
 505	{ .index = DT_BI_TCXO },
 506	{ .hw = &camcc_pll0.clkr.hw },
 507	{ .hw = &camcc_pll0_out_even.clkr.hw },
 508	{ .hw = &camcc_pll0_out_odd.clkr.hw },
 509	{ .hw = &camcc_pll7_out_even.clkr.hw },
 510};
 511
 512static const struct parent_map camcc_parent_map_1[] = {
 513	{ P_BI_TCXO, 0 },
 514	{ P_CAMCC_PLL2_OUT_AUX, 2 },
 515	{ P_CAMCC_PLL2_OUT_EARLY, 5 },
 516};
 517
 518static const struct clk_parent_data camcc_parent_data_1[] = {
 519	{ .index = DT_BI_TCXO },
 520	{ .hw = &camcc_pll2.clkr.hw },
 521	{ .hw = &camcc_pll2.clkr.hw },
 522};
 523
 524static const struct parent_map camcc_parent_map_2[] = {
 525	{ P_BI_TCXO, 0 },
 526	{ P_CAMCC_PLL0_OUT_MAIN, 1 },
 527	{ P_CAMCC_PLL0_OUT_EVEN, 2 },
 528	{ P_CAMCC_PLL0_OUT_ODD, 3 },
 529	{ P_CAMCC_PLL7_OUT_ODD, 4 },
 530	{ P_CAMCC_PLL7_OUT_EVEN, 5 },
 531};
 532
 533static const struct clk_parent_data camcc_parent_data_2[] = {
 534	{ .index = DT_BI_TCXO },
 535	{ .hw = &camcc_pll0.clkr.hw },
 536	{ .hw = &camcc_pll0_out_even.clkr.hw },
 537	{ .hw = &camcc_pll0_out_odd.clkr.hw },
 538	{ .hw = &camcc_pll7_out_odd.clkr.hw },
 539	{ .hw = &camcc_pll7_out_even.clkr.hw },
 540};
 541
 542static const struct parent_map camcc_parent_map_3[] = {
 543	{ P_BI_TCXO, 0 },
 544	{ P_CAMCC_PLL0_OUT_MAIN, 1 },
 545	{ P_CAMCC_PLL0_OUT_EVEN, 2 },
 546	{ P_CAMCC_PLL0_OUT_ODD, 3 },
 547	{ P_CAMCC_PLL7_OUT_EVEN, 5 },
 548	{ P_CAMCC_PLL3_OUT_EVEN, 6 },
 549};
 550
 551static const struct clk_parent_data camcc_parent_data_3[] = {
 552	{ .index = DT_BI_TCXO },
 553	{ .hw = &camcc_pll0.clkr.hw },
 554	{ .hw = &camcc_pll0_out_even.clkr.hw },
 555	{ .hw = &camcc_pll0_out_odd.clkr.hw },
 556	{ .hw = &camcc_pll7_out_even.clkr.hw },
 557	{ .hw = &camcc_pll3_out_even.clkr.hw },
 558};
 559
 560static const struct parent_map camcc_parent_map_4[] = {
 561	{ P_BI_TCXO, 0 },
 562	{ P_CAMCC_PLL3_OUT_EVEN, 6 },
 563};
 564
 565static const struct clk_parent_data camcc_parent_data_4[] = {
 566	{ .index = DT_BI_TCXO },
 567	{ .hw = &camcc_pll3_out_even.clkr.hw },
 568};
 569
 570static const struct parent_map camcc_parent_map_5[] = {
 571	{ P_BI_TCXO, 0 },
 572	{ P_CAMCC_PLL4_OUT_EVEN, 6 },
 573};
 574
 575static const struct clk_parent_data camcc_parent_data_5[] = {
 576	{ .index = DT_BI_TCXO },
 577	{ .hw = &camcc_pll4_out_even.clkr.hw },
 578};
 579
 580static const struct parent_map camcc_parent_map_6[] = {
 581	{ P_BI_TCXO, 0 },
 582	{ P_CAMCC_PLL5_OUT_EVEN, 6 },
 583};
 584
 585static const struct clk_parent_data camcc_parent_data_6[] = {
 586	{ .index = DT_BI_TCXO },
 587	{ .hw = &camcc_pll5_out_even.clkr.hw },
 588};
 589
 590static const struct parent_map camcc_parent_map_7[] = {
 591	{ P_BI_TCXO, 0 },
 592	{ P_CAMCC_PLL6_OUT_EVEN, 6 },
 593};
 594
 595static const struct clk_parent_data camcc_parent_data_7[] = {
 596	{ .index = DT_BI_TCXO },
 597	{ .hw = &camcc_pll6_out_even.clkr.hw },
 598};
 599
 600static const struct parent_map camcc_parent_map_8[] = {
 601	{ P_BI_TCXO, 0 },
 602	{ P_CAMCC_PLL1_OUT_EVEN, 4 },
 603};
 604
 605static const struct clk_parent_data camcc_parent_data_8[] = {
 606	{ .index = DT_BI_TCXO },
 607	{ .hw = &camcc_pll1_out_even.clkr.hw },
 608};
 609
 610static const struct parent_map camcc_parent_map_9[] = {
 611	{ P_SLEEP_CLK, 0 },
 612};
 613
 614static const struct clk_parent_data camcc_parent_data_9[] = {
 615	{ .fw_name = "sleep_clk" },
 616};
 617
 618static const struct parent_map camcc_parent_map_10[] = {
 619	{ P_BI_TCXO, 0 },
 620};
 621
 622static const struct clk_parent_data camcc_parent_data_10_ao[] = {
 623	{ .fw_name = "bi_tcxo_ao" },
 624};
 625
 626static const struct freq_tbl ftbl_camcc_bps_clk_src[] = {
 627	F(19200000, P_BI_TCXO, 1, 0, 0),
 628	F(200000000, P_CAMCC_PLL0_OUT_ODD, 2, 0, 0),
 629	F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
 630	F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0),
 631	F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
 632	F(760000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),
 633};
 634
 635static struct clk_rcg2 camcc_bps_clk_src = {
 636	.cmd_rcgr = 0x7010,
 637	.mnd_width = 0,
 638	.hid_width = 5,
 639	.parent_map = camcc_parent_map_3,
 640	.freq_tbl = ftbl_camcc_bps_clk_src,
 641	.clkr.hw.init = &(struct clk_init_data){
 642		.name = "camcc_bps_clk_src",
 643		.parent_data = camcc_parent_data_3,
 644		.num_parents = ARRAY_SIZE(camcc_parent_data_3),
 645		.flags = CLK_SET_RATE_PARENT,
 646		.ops = &clk_rcg2_shared_ops,
 647	},
 648};
 649
 650static const struct freq_tbl ftbl_camcc_camnoc_axi_clk_src[] = {
 651	F(19200000, P_BI_TCXO, 1, 0, 0),
 652	F(150000000, P_CAMCC_PLL0_OUT_EVEN, 4, 0, 0),
 653	F(266666667, P_CAMCC_PLL0_OUT_ODD, 1.5, 0, 0),
 654	F(320000000, P_CAMCC_PLL7_OUT_ODD, 1, 0, 0),
 655	F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
 656	F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0),
 657};
 658
 659static struct clk_rcg2 camcc_camnoc_axi_clk_src = {
 660	.cmd_rcgr = 0xc170,
 661	.mnd_width = 0,
 662	.hid_width = 5,
 663	.parent_map = camcc_parent_map_2,
 664	.freq_tbl = ftbl_camcc_camnoc_axi_clk_src,
 665	.clkr.hw.init = &(struct clk_init_data){
 666		.name = "camcc_camnoc_axi_clk_src",
 667		.parent_data = camcc_parent_data_2,
 668		.num_parents = ARRAY_SIZE(camcc_parent_data_2),
 669		.ops = &clk_rcg2_ops,
 670	},
 671};
 672
 673static const struct freq_tbl ftbl_camcc_cci_0_clk_src[] = {
 674	F(19200000, P_BI_TCXO, 1, 0, 0),
 675	F(37500000, P_CAMCC_PLL0_OUT_EVEN, 16, 0, 0),
 676};
 677
 678static struct clk_rcg2 camcc_cci_0_clk_src = {
 679	.cmd_rcgr = 0xc108,
 680	.mnd_width = 8,
 681	.hid_width = 5,
 682	.parent_map = camcc_parent_map_0,
 683	.freq_tbl = ftbl_camcc_cci_0_clk_src,
 684	.clkr.hw.init = &(struct clk_init_data){
 685		.name = "camcc_cci_0_clk_src",
 686		.parent_data = camcc_parent_data_0,
 687		.num_parents = ARRAY_SIZE(camcc_parent_data_0),
 688		.ops = &clk_rcg2_ops,
 689	},
 690};
 691
 692static struct clk_rcg2 camcc_cci_1_clk_src = {
 693	.cmd_rcgr = 0xc124,
 694	.mnd_width = 8,
 695	.hid_width = 5,
 696	.parent_map = camcc_parent_map_0,
 697	.freq_tbl = ftbl_camcc_cci_0_clk_src,
 698	.clkr.hw.init = &(struct clk_init_data){
 699		.name = "camcc_cci_1_clk_src",
 700		.parent_data = camcc_parent_data_0,
 701		.num_parents = ARRAY_SIZE(camcc_parent_data_0),
 702		.ops = &clk_rcg2_ops,
 703	},
 704};
 705
 706static struct clk_rcg2 camcc_cci_2_clk_src = {
 707	.cmd_rcgr = 0xc204,
 708	.mnd_width = 8,
 709	.hid_width = 5,
 710	.parent_map = camcc_parent_map_0,
 711	.freq_tbl = ftbl_camcc_cci_0_clk_src,
 712	.clkr.hw.init = &(struct clk_init_data){
 713		.name = "camcc_cci_2_clk_src",
 714		.parent_data = camcc_parent_data_0,
 715		.num_parents = ARRAY_SIZE(camcc_parent_data_0),
 716		.ops = &clk_rcg2_ops,
 717	},
 718};
 719
 720static struct clk_rcg2 camcc_cci_3_clk_src = {
 721	.cmd_rcgr = 0xc220,
 722	.mnd_width = 8,
 723	.hid_width = 5,
 724	.parent_map = camcc_parent_map_0,
 725	.freq_tbl = ftbl_camcc_cci_0_clk_src,
 726	.clkr.hw.init = &(struct clk_init_data){
 727		.name = "camcc_cci_3_clk_src",
 728		.parent_data = camcc_parent_data_0,
 729		.num_parents = ARRAY_SIZE(camcc_parent_data_0),
 730		.ops = &clk_rcg2_ops,
 731	},
 732};
 733
 734static const struct freq_tbl ftbl_camcc_cphy_rx_clk_src[] = {
 735	F(19200000, P_BI_TCXO, 1, 0, 0),
 736	F(240000000, P_CAMCC_PLL0_OUT_EVEN, 2.5, 0, 0),
 737	F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
 738};
 739
 740static struct clk_rcg2 camcc_cphy_rx_clk_src = {
 741	.cmd_rcgr = 0xa064,
 742	.mnd_width = 0,
 743	.hid_width = 5,
 744	.parent_map = camcc_parent_map_0,
 745	.freq_tbl = ftbl_camcc_cphy_rx_clk_src,
 746	.clkr.hw.init = &(struct clk_init_data){
 747		.name = "camcc_cphy_rx_clk_src",
 748		.parent_data = camcc_parent_data_0,
 749		.num_parents = ARRAY_SIZE(camcc_parent_data_0),
 750		.ops = &clk_rcg2_ops,
 751	},
 752};
 753
 754static const struct freq_tbl ftbl_camcc_csi0phytimer_clk_src[] = {
 755	F(19200000, P_BI_TCXO, 1, 0, 0),
 756	F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0),
 757};
 758
 759static struct clk_rcg2 camcc_csi0phytimer_clk_src = {
 760	.cmd_rcgr = 0x6004,
 761	.mnd_width = 0,
 762	.hid_width = 5,
 763	.parent_map = camcc_parent_map_0,
 764	.freq_tbl = ftbl_camcc_csi0phytimer_clk_src,
 765	.clkr.hw.init = &(struct clk_init_data){
 766		.name = "camcc_csi0phytimer_clk_src",
 767		.parent_data = camcc_parent_data_0,
 768		.num_parents = ARRAY_SIZE(camcc_parent_data_0),
 769		.ops = &clk_rcg2_ops,
 770	},
 771};
 772
 773static struct clk_rcg2 camcc_csi1phytimer_clk_src = {
 774	.cmd_rcgr = 0x6028,
 775	.mnd_width = 0,
 776	.hid_width = 5,
 777	.parent_map = camcc_parent_map_0,
 778	.freq_tbl = ftbl_camcc_csi0phytimer_clk_src,
 779	.clkr.hw.init = &(struct clk_init_data){
 780		.name = "camcc_csi1phytimer_clk_src",
 781		.parent_data = camcc_parent_data_0,
 782		.num_parents = ARRAY_SIZE(camcc_parent_data_0),
 783		.ops = &clk_rcg2_ops,
 784	},
 785};
 786
 787static struct clk_rcg2 camcc_csi2phytimer_clk_src = {
 788	.cmd_rcgr = 0x604c,
 789	.mnd_width = 0,
 790	.hid_width = 5,
 791	.parent_map = camcc_parent_map_0,
 792	.freq_tbl = ftbl_camcc_csi0phytimer_clk_src,
 793	.clkr.hw.init = &(struct clk_init_data){
 794		.name = "camcc_csi2phytimer_clk_src",
 795		.parent_data = camcc_parent_data_0,
 796		.num_parents = ARRAY_SIZE(camcc_parent_data_0),
 797		.ops = &clk_rcg2_ops,
 798	},
 799};
 800
 801static struct clk_rcg2 camcc_csi3phytimer_clk_src = {
 802	.cmd_rcgr = 0x6074,
 803	.mnd_width = 0,
 804	.hid_width = 5,
 805	.parent_map = camcc_parent_map_0,
 806	.freq_tbl = ftbl_camcc_csi0phytimer_clk_src,
 807	.clkr.hw.init = &(struct clk_init_data){
 808		.name = "camcc_csi3phytimer_clk_src",
 809		.parent_data = camcc_parent_data_0,
 810		.num_parents = ARRAY_SIZE(camcc_parent_data_0),
 811		.ops = &clk_rcg2_ops,
 812	},
 813};
 814
 815static const struct freq_tbl ftbl_camcc_fast_ahb_clk_src[] = {
 816	F(19200000, P_BI_TCXO, 1, 0, 0),
 817	F(100000000, P_CAMCC_PLL0_OUT_EVEN, 6, 0, 0),
 818	F(200000000, P_CAMCC_PLL0_OUT_EVEN, 3, 0, 0),
 819	F(300000000, P_CAMCC_PLL0_OUT_MAIN, 4, 0, 0),
 820	F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
 821};
 822
 823static struct clk_rcg2 camcc_fast_ahb_clk_src = {
 824	.cmd_rcgr = 0x703c,
 825	.mnd_width = 0,
 826	.hid_width = 5,
 827	.parent_map = camcc_parent_map_0,
 828	.freq_tbl = ftbl_camcc_fast_ahb_clk_src,
 829	.clkr.hw.init = &(struct clk_init_data){
 830		.name = "camcc_fast_ahb_clk_src",
 831		.parent_data = camcc_parent_data_0,
 832		.num_parents = ARRAY_SIZE(camcc_parent_data_0),
 833		.ops = &clk_rcg2_ops,
 834	},
 835};
 836
 837static const struct freq_tbl ftbl_camcc_icp_clk_src[] = {
 838	F(19200000, P_BI_TCXO, 1, 0, 0),
 839	F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
 840	F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
 841};
 842
 843static struct clk_rcg2 camcc_icp_clk_src = {
 844	.cmd_rcgr = 0xc0b8,
 845	.mnd_width = 0,
 846	.hid_width = 5,
 847	.parent_map = camcc_parent_map_0,
 848	.freq_tbl = ftbl_camcc_icp_clk_src,
 849	.clkr.hw.init = &(struct clk_init_data){
 850		.name = "camcc_icp_clk_src",
 851		.parent_data = camcc_parent_data_0,
 852		.num_parents = ARRAY_SIZE(camcc_parent_data_0),
 853		.ops = &clk_rcg2_shared_ops,
 854	},
 855};
 856
 857static const struct freq_tbl ftbl_camcc_ife_0_clk_src[] = {
 858	F(19200000, P_BI_TCXO, 1, 0, 0),
 859	F(400000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),
 860	F(558000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),
 861	F(637000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),
 862	F(760000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),
 863};
 864
 865static struct clk_rcg2 camcc_ife_0_clk_src = {
 866	.cmd_rcgr = 0xa010,
 867	.mnd_width = 0,
 868	.hid_width = 5,
 869	.parent_map = camcc_parent_map_4,
 870	.freq_tbl = ftbl_camcc_ife_0_clk_src,
 871	.clkr.hw.init = &(struct clk_init_data){
 872		.name = "camcc_ife_0_clk_src",
 873		.parent_data = camcc_parent_data_4,
 874		.num_parents = ARRAY_SIZE(camcc_parent_data_4),
 875		.flags = CLK_SET_RATE_PARENT,
 876		.ops = &clk_rcg2_shared_ops,
 877	},
 878};
 879
 880static const struct freq_tbl ftbl_camcc_ife_0_csid_clk_src[] = {
 881	F(19200000, P_BI_TCXO, 1, 0, 0),
 882	F(75000000, P_CAMCC_PLL0_OUT_EVEN, 8, 0, 0),
 883	F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
 884	F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0),
 885	F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
 886};
 887
 888static struct clk_rcg2 camcc_ife_0_csid_clk_src = {
 889	.cmd_rcgr = 0xa03c,
 890	.mnd_width = 0,
 891	.hid_width = 5,
 892	.parent_map = camcc_parent_map_0,
 893	.freq_tbl = ftbl_camcc_ife_0_csid_clk_src,
 894	.clkr.hw.init = &(struct clk_init_data){
 895		.name = "camcc_ife_0_csid_clk_src",
 896		.parent_data = camcc_parent_data_0,
 897		.num_parents = ARRAY_SIZE(camcc_parent_data_0),
 898		.ops = &clk_rcg2_shared_ops,
 899	},
 900};
 901
 902static const struct freq_tbl ftbl_camcc_ife_1_clk_src[] = {
 903	F(19200000, P_BI_TCXO, 1, 0, 0),
 904	F(400000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),
 905	F(558000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),
 906	F(637000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),
 907	F(760000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),
 908};
 909
 910static struct clk_rcg2 camcc_ife_1_clk_src = {
 911	.cmd_rcgr = 0xb010,
 912	.mnd_width = 0,
 913	.hid_width = 5,
 914	.parent_map = camcc_parent_map_5,
 915	.freq_tbl = ftbl_camcc_ife_1_clk_src,
 916	.clkr.hw.init = &(struct clk_init_data){
 917		.name = "camcc_ife_1_clk_src",
 918		.parent_data = camcc_parent_data_5,
 919		.num_parents = ARRAY_SIZE(camcc_parent_data_5),
 920		.flags = CLK_SET_RATE_PARENT,
 921		.ops = &clk_rcg2_shared_ops,
 922	},
 923};
 924
 925static struct clk_rcg2 camcc_ife_1_csid_clk_src = {
 926	.cmd_rcgr = 0xb03c,
 927	.mnd_width = 0,
 928	.hid_width = 5,
 929	.parent_map = camcc_parent_map_0,
 930	.freq_tbl = ftbl_camcc_ife_0_csid_clk_src,
 931	.clkr.hw.init = &(struct clk_init_data){
 932		.name = "camcc_ife_1_csid_clk_src",
 933		.parent_data = camcc_parent_data_0,
 934		.num_parents = ARRAY_SIZE(camcc_parent_data_0),
 935		.ops = &clk_rcg2_shared_ops,
 936	},
 937};
 938
 939static const struct freq_tbl ftbl_camcc_ife_2_clk_src[] = {
 940	F(400000000, P_CAMCC_PLL5_OUT_EVEN, 1, 0, 0),
 941	F(558000000, P_CAMCC_PLL5_OUT_EVEN, 1, 0, 0),
 942	F(637000000, P_CAMCC_PLL5_OUT_EVEN, 1, 0, 0),
 943	F(760000000, P_CAMCC_PLL5_OUT_EVEN, 1, 0, 0),
 944};
 945
 946static struct clk_rcg2 camcc_ife_2_clk_src = {
 947	.cmd_rcgr = 0xf010,
 948	.mnd_width = 0,
 949	.hid_width = 5,
 950	.parent_map = camcc_parent_map_6,
 951	.freq_tbl = ftbl_camcc_ife_2_clk_src,
 952	.clkr.hw.init = &(struct clk_init_data){
 953		.name = "camcc_ife_2_clk_src",
 954		.parent_data = camcc_parent_data_6,
 955		.num_parents = ARRAY_SIZE(camcc_parent_data_6),
 956		.flags = CLK_SET_RATE_PARENT,
 957		.ops = &clk_rcg2_shared_ops,
 958	},
 959};
 960
 961static const struct freq_tbl ftbl_camcc_ife_2_csid_clk_src[] = {
 962	F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
 963	F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0),
 964	F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
 965};
 966
 967static struct clk_rcg2 camcc_ife_2_csid_clk_src = {
 968	.cmd_rcgr = 0xf03c,
 969	.mnd_width = 0,
 970	.hid_width = 5,
 971	.parent_map = camcc_parent_map_0,
 972	.freq_tbl = ftbl_camcc_ife_2_csid_clk_src,
 973	.clkr.hw.init = &(struct clk_init_data){
 974		.name = "camcc_ife_2_csid_clk_src",
 975		.parent_data = camcc_parent_data_0,
 976		.num_parents = ARRAY_SIZE(camcc_parent_data_0),
 977		.ops = &clk_rcg2_shared_ops,
 978	},
 979};
 980
 981static const struct freq_tbl ftbl_camcc_ife_3_clk_src[] = {
 982	F(19200000, P_BI_TCXO, 1, 0, 0),
 983	F(400000000, P_CAMCC_PLL6_OUT_EVEN, 1, 0, 0),
 984	F(558000000, P_CAMCC_PLL6_OUT_EVEN, 1, 0, 0),
 985	F(637000000, P_CAMCC_PLL6_OUT_EVEN, 1, 0, 0),
 986	F(760000000, P_CAMCC_PLL6_OUT_EVEN, 1, 0, 0),
 987};
 988
 989static struct clk_rcg2 camcc_ife_3_clk_src = {
 990	.cmd_rcgr = 0xf07c,
 991	.mnd_width = 0,
 992	.hid_width = 5,
 993	.parent_map = camcc_parent_map_7,
 994	.freq_tbl = ftbl_camcc_ife_3_clk_src,
 995	.clkr.hw.init = &(struct clk_init_data){
 996		.name = "camcc_ife_3_clk_src",
 997		.parent_data = camcc_parent_data_7,
 998		.num_parents = ARRAY_SIZE(camcc_parent_data_7),
 999		.flags = CLK_SET_RATE_PARENT,
1000		.ops = &clk_rcg2_shared_ops,
1001	},
1002};
1003
1004static struct clk_rcg2 camcc_ife_3_csid_clk_src = {
1005	.cmd_rcgr = 0xf0a8,
1006	.mnd_width = 0,
1007	.hid_width = 5,
1008	.parent_map = camcc_parent_map_0,
1009	.freq_tbl = ftbl_camcc_ife_2_csid_clk_src,
1010	.clkr.hw.init = &(struct clk_init_data){
1011		.name = "camcc_ife_3_csid_clk_src",
1012		.parent_data = camcc_parent_data_0,
1013		.num_parents = ARRAY_SIZE(camcc_parent_data_0),
1014		.ops = &clk_rcg2_shared_ops,
1015	},
1016};
1017
1018static const struct freq_tbl ftbl_camcc_ife_lite_0_clk_src[] = {
1019	F(320000000, P_CAMCC_PLL7_OUT_ODD, 1, 0, 0),
1020	F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
1021	F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0),
1022	F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
1023};
1024
1025static struct clk_rcg2 camcc_ife_lite_0_clk_src = {
1026	.cmd_rcgr = 0xc004,
1027	.mnd_width = 0,
1028	.hid_width = 5,
1029	.parent_map = camcc_parent_map_2,
1030	.freq_tbl = ftbl_camcc_ife_lite_0_clk_src,
1031	.clkr.hw.init = &(struct clk_init_data){
1032		.name = "camcc_ife_lite_0_clk_src",
1033		.parent_data = camcc_parent_data_2,
1034		.num_parents = ARRAY_SIZE(camcc_parent_data_2),
1035		.ops = &clk_rcg2_shared_ops,
1036	},
1037};
1038
1039static struct clk_rcg2 camcc_ife_lite_0_csid_clk_src = {
1040	.cmd_rcgr = 0xc020,
1041	.mnd_width = 0,
1042	.hid_width = 5,
1043	.parent_map = camcc_parent_map_0,
1044	.freq_tbl = ftbl_camcc_ife_2_csid_clk_src,
1045	.clkr.hw.init = &(struct clk_init_data){
1046		.name = "camcc_ife_lite_0_csid_clk_src",
1047		.parent_data = camcc_parent_data_0,
1048		.num_parents = ARRAY_SIZE(camcc_parent_data_0),
1049		.ops = &clk_rcg2_shared_ops,
1050	},
1051};
1052
1053static struct clk_rcg2 camcc_ife_lite_1_clk_src = {
1054	.cmd_rcgr = 0xc048,
1055	.mnd_width = 0,
1056	.hid_width = 5,
1057	.parent_map = camcc_parent_map_2,
1058	.freq_tbl = ftbl_camcc_ife_lite_0_clk_src,
1059	.clkr.hw.init = &(struct clk_init_data){
1060		.name = "camcc_ife_lite_1_clk_src",
1061		.parent_data = camcc_parent_data_2,
1062		.num_parents = ARRAY_SIZE(camcc_parent_data_2),
1063		.ops = &clk_rcg2_shared_ops,
1064	},
1065};
1066
1067static struct clk_rcg2 camcc_ife_lite_1_csid_clk_src = {
1068	.cmd_rcgr = 0xc064,
1069	.mnd_width = 0,
1070	.hid_width = 5,
1071	.parent_map = camcc_parent_map_0,
1072	.freq_tbl = ftbl_camcc_ife_2_csid_clk_src,
1073	.clkr.hw.init = &(struct clk_init_data){
1074		.name = "camcc_ife_lite_1_csid_clk_src",
1075		.parent_data = camcc_parent_data_0,
1076		.num_parents = ARRAY_SIZE(camcc_parent_data_0),
1077		.ops = &clk_rcg2_shared_ops,
1078	},
1079};
1080
1081static struct clk_rcg2 camcc_ife_lite_2_clk_src = {
1082	.cmd_rcgr = 0xc240,
1083	.mnd_width = 0,
1084	.hid_width = 5,
1085	.parent_map = camcc_parent_map_2,
1086	.freq_tbl = ftbl_camcc_ife_lite_0_clk_src,
1087	.clkr.hw.init = &(struct clk_init_data){
1088		.name = "camcc_ife_lite_2_clk_src",
1089		.parent_data = camcc_parent_data_2,
1090		.num_parents = ARRAY_SIZE(camcc_parent_data_2),
1091		.ops = &clk_rcg2_shared_ops,
1092	},
1093};
1094
1095static struct clk_rcg2 camcc_ife_lite_2_csid_clk_src = {
1096	.cmd_rcgr = 0xc25c,
1097	.mnd_width = 0,
1098	.hid_width = 5,
1099	.parent_map = camcc_parent_map_0,
1100	.freq_tbl = ftbl_camcc_ife_2_csid_clk_src,
1101	.clkr.hw.init = &(struct clk_init_data){
1102		.name = "camcc_ife_lite_2_csid_clk_src",
1103		.parent_data = camcc_parent_data_0,
1104		.num_parents = ARRAY_SIZE(camcc_parent_data_0),
1105		.ops = &clk_rcg2_shared_ops,
1106	},
1107};
1108
1109static struct clk_rcg2 camcc_ife_lite_3_clk_src = {
1110	.cmd_rcgr = 0xc284,
1111	.mnd_width = 0,
1112	.hid_width = 5,
1113	.parent_map = camcc_parent_map_2,
1114	.freq_tbl = ftbl_camcc_ife_lite_0_clk_src,
1115	.clkr.hw.init = &(struct clk_init_data){
1116		.name = "camcc_ife_lite_3_clk_src",
1117		.parent_data = camcc_parent_data_2,
1118		.num_parents = ARRAY_SIZE(camcc_parent_data_2),
1119		.ops = &clk_rcg2_shared_ops,
1120	},
1121};
1122
1123static struct clk_rcg2 camcc_ife_lite_3_csid_clk_src = {
1124	.cmd_rcgr = 0xc2a0,
1125	.mnd_width = 0,
1126	.hid_width = 5,
1127	.parent_map = camcc_parent_map_0,
1128	.freq_tbl = ftbl_camcc_ife_2_csid_clk_src,
1129	.clkr.hw.init = &(struct clk_init_data){
1130		.name = "camcc_ife_lite_3_csid_clk_src",
1131		.parent_data = camcc_parent_data_0,
1132		.num_parents = ARRAY_SIZE(camcc_parent_data_0),
1133		.ops = &clk_rcg2_shared_ops,
1134	},
1135};
1136
1137static const struct freq_tbl ftbl_camcc_ipe_0_clk_src[] = {
1138	F(19200000, P_BI_TCXO, 1, 0, 0),
1139	F(320000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
1140	F(475000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
1141	F(520000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
1142	F(600000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
1143};
1144
1145static struct clk_rcg2 camcc_ipe_0_clk_src = {
1146	.cmd_rcgr = 0x8010,
1147	.mnd_width = 0,
1148	.hid_width = 5,
1149	.parent_map = camcc_parent_map_8,
1150	.freq_tbl = ftbl_camcc_ipe_0_clk_src,
1151	.clkr.hw.init = &(struct clk_init_data){
1152		.name = "camcc_ipe_0_clk_src",
1153		.parent_data = camcc_parent_data_8,
1154		.num_parents = ARRAY_SIZE(camcc_parent_data_8),
1155		.flags = CLK_SET_RATE_PARENT,
1156		.ops = &clk_rcg2_shared_ops,
1157	},
1158};
1159
1160static const struct freq_tbl ftbl_camcc_jpeg_clk_src[] = {
1161	F(19200000, P_BI_TCXO, 1, 0, 0),
1162	F(200000000, P_CAMCC_PLL0_OUT_ODD, 2, 0, 0),
1163	F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
1164	F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0),
1165	F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
1166};
1167
1168static struct clk_rcg2 camcc_jpeg_clk_src = {
1169	.cmd_rcgr = 0xc08c,
1170	.mnd_width = 0,
1171	.hid_width = 5,
1172	.parent_map = camcc_parent_map_0,
1173	.freq_tbl = ftbl_camcc_jpeg_clk_src,
1174	.clkr.hw.init = &(struct clk_init_data){
1175		.name = "camcc_jpeg_clk_src",
1176		.parent_data = camcc_parent_data_0,
1177		.num_parents = ARRAY_SIZE(camcc_parent_data_0),
1178		.ops = &clk_rcg2_shared_ops,
1179	},
1180};
1181
1182static const struct freq_tbl ftbl_camcc_lrme_clk_src[] = {
1183	F(240000000, P_CAMCC_PLL7_OUT_EVEN, 2, 0, 0),
1184	F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0),
1185	F(320000000, P_CAMCC_PLL7_OUT_ODD, 1, 0, 0),
1186	F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
1187};
1188
1189static struct clk_rcg2 camcc_lrme_clk_src = {
1190	.cmd_rcgr = 0xc144,
1191	.mnd_width = 0,
1192	.hid_width = 5,
1193	.parent_map = camcc_parent_map_2,
1194	.freq_tbl = ftbl_camcc_lrme_clk_src,
1195	.clkr.hw.init = &(struct clk_init_data){
1196		.name = "camcc_lrme_clk_src",
1197		.parent_data = camcc_parent_data_2,
1198		.num_parents = ARRAY_SIZE(camcc_parent_data_2),
1199		.ops = &clk_rcg2_shared_ops,
1200	},
1201};
1202
1203static const struct freq_tbl ftbl_camcc_mclk0_clk_src[] = {
1204	F(19200000, P_BI_TCXO, 1, 0, 0),
1205	F(24000000, P_CAMCC_PLL2_OUT_EARLY, 10, 1, 4),
1206	F(64000000, P_CAMCC_PLL2_OUT_EARLY, 15, 0, 0),
1207};
1208
1209static struct clk_rcg2 camcc_mclk0_clk_src = {
1210	.cmd_rcgr = 0x5004,
1211	.mnd_width = 8,
1212	.hid_width = 5,
1213	.parent_map = camcc_parent_map_1,
1214	.freq_tbl = ftbl_camcc_mclk0_clk_src,
1215	.clkr.hw.init = &(struct clk_init_data){
1216		.name = "camcc_mclk0_clk_src",
1217		.parent_data = camcc_parent_data_1,
1218		.num_parents = ARRAY_SIZE(camcc_parent_data_1),
1219		.ops = &clk_rcg2_ops,
1220	},
1221};
1222
1223static struct clk_rcg2 camcc_mclk1_clk_src = {
1224	.cmd_rcgr = 0x5024,
1225	.mnd_width = 8,
1226	.hid_width = 5,
1227	.parent_map = camcc_parent_map_1,
1228	.freq_tbl = ftbl_camcc_mclk0_clk_src,
1229	.clkr.hw.init = &(struct clk_init_data){
1230		.name = "camcc_mclk1_clk_src",
1231		.parent_data = camcc_parent_data_1,
1232		.num_parents = ARRAY_SIZE(camcc_parent_data_1),
1233		.ops = &clk_rcg2_ops,
1234	},
1235};
1236
1237static struct clk_rcg2 camcc_mclk2_clk_src = {
1238	.cmd_rcgr = 0x5044,
1239	.mnd_width = 8,
1240	.hid_width = 5,
1241	.parent_map = camcc_parent_map_1,
1242	.freq_tbl = ftbl_camcc_mclk0_clk_src,
1243	.clkr.hw.init = &(struct clk_init_data){
1244		.name = "camcc_mclk2_clk_src",
1245		.parent_data = camcc_parent_data_1,
1246		.num_parents = ARRAY_SIZE(camcc_parent_data_1),
1247		.ops = &clk_rcg2_ops,
1248	},
1249};
1250
1251static struct clk_rcg2 camcc_mclk3_clk_src = {
1252	.cmd_rcgr = 0x5064,
1253	.mnd_width = 8,
1254	.hid_width = 5,
1255	.parent_map = camcc_parent_map_1,
1256	.freq_tbl = ftbl_camcc_mclk0_clk_src,
1257	.clkr.hw.init = &(struct clk_init_data){
1258		.name = "camcc_mclk3_clk_src",
1259		.parent_data = camcc_parent_data_1,
1260		.num_parents = ARRAY_SIZE(camcc_parent_data_1),
1261		.ops = &clk_rcg2_ops,
1262	},
1263};
1264
1265static struct clk_rcg2 camcc_mclk4_clk_src = {
1266	.cmd_rcgr = 0x5084,
1267	.mnd_width = 8,
1268	.hid_width = 5,
1269	.parent_map = camcc_parent_map_1,
1270	.freq_tbl = ftbl_camcc_mclk0_clk_src,
1271	.clkr.hw.init = &(struct clk_init_data){
1272		.name = "camcc_mclk4_clk_src",
1273		.parent_data = camcc_parent_data_1,
1274		.num_parents = ARRAY_SIZE(camcc_parent_data_1),
1275		.ops = &clk_rcg2_ops,
1276	},
1277};
1278
1279static struct clk_rcg2 camcc_mclk5_clk_src = {
1280	.cmd_rcgr = 0x50a4,
1281	.mnd_width = 8,
1282	.hid_width = 5,
1283	.parent_map = camcc_parent_map_1,
1284	.freq_tbl = ftbl_camcc_mclk0_clk_src,
1285	.clkr.hw.init = &(struct clk_init_data){
1286		.name = "camcc_mclk5_clk_src",
1287		.parent_data = camcc_parent_data_1,
1288		.num_parents = ARRAY_SIZE(camcc_parent_data_1),
1289		.ops = &clk_rcg2_ops,
1290	},
1291};
1292
1293static struct clk_rcg2 camcc_mclk6_clk_src = {
1294	.cmd_rcgr = 0x50c4,
1295	.mnd_width = 8,
1296	.hid_width = 5,
1297	.parent_map = camcc_parent_map_1,
1298	.freq_tbl = ftbl_camcc_mclk0_clk_src,
1299	.clkr.hw.init = &(struct clk_init_data){
1300		.name = "camcc_mclk6_clk_src",
1301		.parent_data = camcc_parent_data_1,
1302		.num_parents = ARRAY_SIZE(camcc_parent_data_1),
1303		.ops = &clk_rcg2_ops,
1304	},
1305};
1306
1307static struct clk_rcg2 camcc_mclk7_clk_src = {
1308	.cmd_rcgr = 0x50e4,
1309	.mnd_width = 8,
1310	.hid_width = 5,
1311	.parent_map = camcc_parent_map_1,
1312	.freq_tbl = ftbl_camcc_mclk0_clk_src,
1313	.clkr.hw.init = &(struct clk_init_data){
1314		.name = "camcc_mclk7_clk_src",
1315		.parent_data = camcc_parent_data_1,
1316		.num_parents = ARRAY_SIZE(camcc_parent_data_1),
1317		.ops = &clk_rcg2_ops,
1318	},
1319};
1320
1321static const struct freq_tbl ftbl_camcc_sleep_clk_src[] = {
1322	F(32000, P_SLEEP_CLK, 1, 0, 0),
1323};
1324
1325static struct clk_rcg2 camcc_sleep_clk_src = {
1326	.cmd_rcgr = 0xc1e8,
1327	.mnd_width = 0,
1328	.hid_width = 5,
1329	.parent_map = camcc_parent_map_9,
1330	.freq_tbl = ftbl_camcc_sleep_clk_src,
1331	.clkr.hw.init = &(struct clk_init_data){
1332		.name = "camcc_sleep_clk_src",
1333		.parent_data = camcc_parent_data_9,
1334		.num_parents = ARRAY_SIZE(camcc_parent_data_9),
1335		.ops = &clk_rcg2_ops,
1336	},
1337};
1338
1339static const struct freq_tbl ftbl_camcc_slow_ahb_clk_src[] = {
1340	F(19200000, P_BI_TCXO, 1, 0, 0),
1341	F(80000000, P_CAMCC_PLL7_OUT_EVEN, 6, 0, 0),
1342};
1343
1344static struct clk_rcg2 camcc_slow_ahb_clk_src = {
1345	.cmd_rcgr = 0x7058,
1346	.mnd_width = 8,
1347	.hid_width = 5,
1348	.parent_map = camcc_parent_map_0,
1349	.freq_tbl = ftbl_camcc_slow_ahb_clk_src,
1350	.clkr.hw.init = &(struct clk_init_data){
1351		.name = "camcc_slow_ahb_clk_src",
1352		.parent_data = camcc_parent_data_0,
1353		.num_parents = ARRAY_SIZE(camcc_parent_data_0),
1354		.ops = &clk_rcg2_ops,
1355	},
1356};
1357
1358static const struct freq_tbl ftbl_camcc_xo_clk_src[] = {
1359	F(19200000, P_BI_TCXO, 1, 0, 0),
1360};
1361
1362static struct clk_rcg2 camcc_xo_clk_src = {
1363	.cmd_rcgr = 0xc1cc,
1364	.mnd_width = 0,
1365	.hid_width = 5,
1366	.parent_map = camcc_parent_map_10,
1367	.freq_tbl = ftbl_camcc_xo_clk_src,
1368	.clkr.hw.init = &(struct clk_init_data){
1369		.name = "camcc_xo_clk_src",
1370		.parent_data = camcc_parent_data_10_ao,
1371		.num_parents = ARRAY_SIZE(camcc_parent_data_10_ao),
1372		.ops = &clk_rcg2_ops,
1373	},
1374};
1375
1376static struct clk_branch camcc_bps_ahb_clk = {
1377	.halt_reg = 0x7070,
1378	.halt_check = BRANCH_HALT,
1379	.clkr = {
1380		.enable_reg = 0x7070,
1381		.enable_mask = BIT(0),
1382		.hw.init = &(struct clk_init_data){
1383			.name = "camcc_bps_ahb_clk",
1384			.parent_hws = (const struct clk_hw*[]){
1385				&camcc_slow_ahb_clk_src.clkr.hw,
1386			},
1387			.num_parents = 1,
1388			.flags = CLK_SET_RATE_PARENT,
1389			.ops = &clk_branch2_ops,
1390		},
1391	},
1392};
1393
1394static struct clk_branch camcc_bps_areg_clk = {
1395	.halt_reg = 0x7054,
1396	.halt_check = BRANCH_HALT,
1397	.clkr = {
1398		.enable_reg = 0x7054,
1399		.enable_mask = BIT(0),
1400		.hw.init = &(struct clk_init_data){
1401			.name = "camcc_bps_areg_clk",
1402			.parent_hws = (const struct clk_hw*[]){
1403				&camcc_fast_ahb_clk_src.clkr.hw,
1404			},
1405			.num_parents = 1,
1406			.flags = CLK_SET_RATE_PARENT,
1407			.ops = &clk_branch2_ops,
1408		},
1409	},
1410};
1411
1412static struct clk_branch camcc_bps_axi_clk = {
1413	.halt_reg = 0x7038,
1414	.halt_check = BRANCH_HALT,
1415	.clkr = {
1416		.enable_reg = 0x7038,
1417		.enable_mask = BIT(0),
1418		.hw.init = &(struct clk_init_data){
1419			.name = "camcc_bps_axi_clk",
1420			.parent_hws = (const struct clk_hw*[]){
1421				&camcc_camnoc_axi_clk_src.clkr.hw,
1422			},
1423			.num_parents = 1,
1424			.flags = CLK_SET_RATE_PARENT,
1425			.ops = &clk_branch2_ops,
1426		},
1427	},
1428};
1429
1430static struct clk_branch camcc_bps_clk = {
1431	.halt_reg = 0x7028,
1432	.halt_check = BRANCH_HALT,
1433	.clkr = {
1434		.enable_reg = 0x7028,
1435		.enable_mask = BIT(0),
1436		.hw.init = &(struct clk_init_data){
1437			.name = "camcc_bps_clk",
1438			.parent_hws = (const struct clk_hw*[]){
1439				&camcc_bps_clk_src.clkr.hw,
1440			},
1441			.num_parents = 1,
1442			.flags = CLK_SET_RATE_PARENT,
1443			.ops = &clk_branch2_ops,
1444		},
1445	},
1446};
1447
1448static struct clk_branch camcc_camnoc_axi_clk = {
1449	.halt_reg = 0xc18c,
1450	.halt_check = BRANCH_HALT,
1451	.clkr = {
1452		.enable_reg = 0xc18c,
1453		.enable_mask = BIT(0),
1454		.hw.init = &(struct clk_init_data){
1455			.name = "camcc_camnoc_axi_clk",
1456			.parent_hws = (const struct clk_hw*[]){
1457				&camcc_camnoc_axi_clk_src.clkr.hw,
1458			},
1459			.num_parents = 1,
1460			.flags = CLK_SET_RATE_PARENT,
1461			.ops = &clk_branch2_ops,
1462		},
1463	},
1464};
1465
1466static struct clk_branch camcc_camnoc_dcd_xo_clk = {
1467	.halt_reg = 0xc194,
1468	.halt_check = BRANCH_HALT,
1469	.clkr = {
1470		.enable_reg = 0xc194,
1471		.enable_mask = BIT(0),
1472		.hw.init = &(struct clk_init_data){
1473			.name = "camcc_camnoc_dcd_xo_clk",
1474			.parent_hws = (const struct clk_hw*[]){
1475				&camcc_xo_clk_src.clkr.hw,
1476			},
1477			.num_parents = 1,
1478			.flags = CLK_SET_RATE_PARENT,
1479			.ops = &clk_branch2_ops,
1480		},
1481	},
1482};
1483
1484static struct clk_branch camcc_cci_0_clk = {
1485	.halt_reg = 0xc120,
1486	.halt_check = BRANCH_HALT,
1487	.clkr = {
1488		.enable_reg = 0xc120,
1489		.enable_mask = BIT(0),
1490		.hw.init = &(struct clk_init_data){
1491			.name = "camcc_cci_0_clk",
1492			.parent_hws = (const struct clk_hw*[]){
1493				&camcc_cci_0_clk_src.clkr.hw,
1494			},
1495			.num_parents = 1,
1496			.flags = CLK_SET_RATE_PARENT,
1497			.ops = &clk_branch2_ops,
1498		},
1499	},
1500};
1501
1502static struct clk_branch camcc_cci_1_clk = {
1503	.halt_reg = 0xc13c,
1504	.halt_check = BRANCH_HALT,
1505	.clkr = {
1506		.enable_reg = 0xc13c,
1507		.enable_mask = BIT(0),
1508		.hw.init = &(struct clk_init_data){
1509			.name = "camcc_cci_1_clk",
1510			.parent_hws = (const struct clk_hw*[]){
1511				&camcc_cci_1_clk_src.clkr.hw,
1512			},
1513			.num_parents = 1,
1514			.flags = CLK_SET_RATE_PARENT,
1515			.ops = &clk_branch2_ops,
1516		},
1517	},
1518};
1519
1520static struct clk_branch camcc_cci_2_clk = {
1521	.halt_reg = 0xc21c,
1522	.halt_check = BRANCH_HALT,
1523	.clkr = {
1524		.enable_reg = 0xc21c,
1525		.enable_mask = BIT(0),
1526		.hw.init = &(struct clk_init_data){
1527			.name = "camcc_cci_2_clk",
1528			.parent_hws = (const struct clk_hw*[]){
1529				&camcc_cci_2_clk_src.clkr.hw,
1530			},
1531			.num_parents = 1,
1532			.flags = CLK_SET_RATE_PARENT,
1533			.ops = &clk_branch2_ops,
1534		},
1535	},
1536};
1537
1538static struct clk_branch camcc_cci_3_clk = {
1539	.halt_reg = 0xc238,
1540	.halt_check = BRANCH_HALT,
1541	.clkr = {
1542		.enable_reg = 0xc238,
1543		.enable_mask = BIT(0),
1544		.hw.init = &(struct clk_init_data){
1545			.name = "camcc_cci_3_clk",
1546			.parent_hws = (const struct clk_hw*[]){
1547				&camcc_cci_3_clk_src.clkr.hw,
1548			},
1549			.num_parents = 1,
1550			.flags = CLK_SET_RATE_PARENT,
1551			.ops = &clk_branch2_ops,
1552		},
1553	},
1554};
1555
1556static struct clk_branch camcc_core_ahb_clk = {
1557	.halt_reg = 0xc1c8,
1558	.halt_check = BRANCH_HALT_DELAY,
1559	.clkr = {
1560		.enable_reg = 0xc1c8,
1561		.enable_mask = BIT(0),
1562		.hw.init = &(struct clk_init_data){
1563			.name = "camcc_core_ahb_clk",
1564			.parent_hws = (const struct clk_hw*[]){
1565				&camcc_slow_ahb_clk_src.clkr.hw,
1566			},
1567			.num_parents = 1,
1568			.flags = CLK_SET_RATE_PARENT,
1569			.ops = &clk_branch2_ops,
1570		},
1571	},
1572};
1573
1574static struct clk_branch camcc_cpas_ahb_clk = {
1575	.halt_reg = 0xc168,
1576	.halt_check = BRANCH_HALT,
1577	.clkr = {
1578		.enable_reg = 0xc168,
1579		.enable_mask = BIT(0),
1580		.hw.init = &(struct clk_init_data){
1581			.name = "camcc_cpas_ahb_clk",
1582			.parent_hws = (const struct clk_hw*[]){
1583				&camcc_slow_ahb_clk_src.clkr.hw,
1584			},
1585			.num_parents = 1,
1586			.flags = CLK_SET_RATE_PARENT,
1587			.ops = &clk_branch2_ops,
1588		},
1589	},
1590};
1591
1592static struct clk_branch camcc_csi0phytimer_clk = {
1593	.halt_reg = 0x601c,
1594	.halt_check = BRANCH_HALT,
1595	.clkr = {
1596		.enable_reg = 0x601c,
1597		.enable_mask = BIT(0),
1598		.hw.init = &(struct clk_init_data){
1599			.name = "camcc_csi0phytimer_clk",
1600			.parent_hws = (const struct clk_hw*[]){
1601				&camcc_csi0phytimer_clk_src.clkr.hw,
1602			},
1603			.num_parents = 1,
1604			.flags = CLK_SET_RATE_PARENT,
1605			.ops = &clk_branch2_ops,
1606		},
1607	},
1608};
1609
1610static struct clk_branch camcc_csi1phytimer_clk = {
1611	.halt_reg = 0x6040,
1612	.halt_check = BRANCH_HALT,
1613	.clkr = {
1614		.enable_reg = 0x6040,
1615		.enable_mask = BIT(0),
1616		.hw.init = &(struct clk_init_data){
1617			.name = "camcc_csi1phytimer_clk",
1618			.parent_hws = (const struct clk_hw*[]){
1619				&camcc_csi1phytimer_clk_src.clkr.hw,
1620			},
1621			.num_parents = 1,
1622			.flags = CLK_SET_RATE_PARENT,
1623			.ops = &clk_branch2_ops,
1624		},
1625	},
1626};
1627
1628static struct clk_branch camcc_csi2phytimer_clk = {
1629	.halt_reg = 0x6064,
1630	.halt_check = BRANCH_HALT,
1631	.clkr = {
1632		.enable_reg = 0x6064,
1633		.enable_mask = BIT(0),
1634		.hw.init = &(struct clk_init_data){
1635			.name = "camcc_csi2phytimer_clk",
1636			.parent_hws = (const struct clk_hw*[]){
1637				&camcc_csi2phytimer_clk_src.clkr.hw,
1638			},
1639			.num_parents = 1,
1640			.flags = CLK_SET_RATE_PARENT,
1641			.ops = &clk_branch2_ops,
1642		},
1643	},
1644};
1645
1646static struct clk_branch camcc_csi3phytimer_clk = {
1647	.halt_reg = 0x608c,
1648	.halt_check = BRANCH_HALT,
1649	.clkr = {
1650		.enable_reg = 0x608c,
1651		.enable_mask = BIT(0),
1652		.hw.init = &(struct clk_init_data){
1653			.name = "camcc_csi3phytimer_clk",
1654			.parent_hws = (const struct clk_hw*[]){
1655				&camcc_csi3phytimer_clk_src.clkr.hw,
1656			},
1657			.num_parents = 1,
1658			.flags = CLK_SET_RATE_PARENT,
1659			.ops = &clk_branch2_ops,
1660		},
1661	},
1662};
1663
1664static struct clk_branch camcc_csiphy0_clk = {
1665	.halt_reg = 0x6020,
1666	.halt_check = BRANCH_HALT,
1667	.clkr = {
1668		.enable_reg = 0x6020,
1669		.enable_mask = BIT(0),
1670		.hw.init = &(struct clk_init_data){
1671			.name = "camcc_csiphy0_clk",
1672			.parent_hws = (const struct clk_hw*[]){
1673				&camcc_cphy_rx_clk_src.clkr.hw,
1674			},
1675			.num_parents = 1,
1676			.flags = CLK_SET_RATE_PARENT,
1677			.ops = &clk_branch2_ops,
1678		},
1679	},
1680};
1681
1682static struct clk_branch camcc_csiphy1_clk = {
1683	.halt_reg = 0x6044,
1684	.halt_check = BRANCH_HALT,
1685	.clkr = {
1686		.enable_reg = 0x6044,
1687		.enable_mask = BIT(0),
1688		.hw.init = &(struct clk_init_data){
1689			.name = "camcc_csiphy1_clk",
1690			.parent_hws = (const struct clk_hw*[]){
1691				&camcc_cphy_rx_clk_src.clkr.hw,
1692			},
1693			.num_parents = 1,
1694			.flags = CLK_SET_RATE_PARENT,
1695			.ops = &clk_branch2_ops,
1696		},
1697	},
1698};
1699
1700static struct clk_branch camcc_csiphy2_clk = {
1701	.halt_reg = 0x6068,
1702	.halt_check = BRANCH_HALT,
1703	.clkr = {
1704		.enable_reg = 0x6068,
1705		.enable_mask = BIT(0),
1706		.hw.init = &(struct clk_init_data){
1707			.name = "camcc_csiphy2_clk",
1708			.parent_hws = (const struct clk_hw*[]){
1709				&camcc_cphy_rx_clk_src.clkr.hw,
1710			},
1711			.num_parents = 1,
1712			.flags = CLK_SET_RATE_PARENT,
1713			.ops = &clk_branch2_ops,
1714		},
1715	},
1716};
1717
1718static struct clk_branch camcc_csiphy3_clk = {
1719	.halt_reg = 0x6090,
1720	.halt_check = BRANCH_HALT,
1721	.clkr = {
1722		.enable_reg = 0x6090,
1723		.enable_mask = BIT(0),
1724		.hw.init = &(struct clk_init_data){
1725			.name = "camcc_csiphy3_clk",
1726			.parent_hws = (const struct clk_hw*[]){
1727				&camcc_cphy_rx_clk_src.clkr.hw,
1728			},
1729			.num_parents = 1,
1730			.flags = CLK_SET_RATE_PARENT,
1731			.ops = &clk_branch2_ops,
1732		},
1733	},
1734};
1735
1736static struct clk_branch camcc_gdsc_clk = {
1737	.halt_reg = 0xc1e4,
1738	.halt_check = BRANCH_HALT,
1739	.clkr = {
1740		.enable_reg = 0xc1e4,
1741		.enable_mask = BIT(0),
1742		.hw.init = &(struct clk_init_data){
1743			.name = "camcc_gdsc_clk",
1744			.parent_hws = (const struct clk_hw*[]){
1745				&camcc_xo_clk_src.clkr.hw,
1746			},
1747			.num_parents = 1,
1748			.flags = CLK_SET_RATE_PARENT,
1749			.ops = &clk_branch2_ops,
1750		},
1751	},
1752};
1753
1754static struct clk_branch camcc_icp_ahb_clk = {
1755	.halt_reg = 0xc0d8,
1756	.halt_check = BRANCH_HALT,
1757	.clkr = {
1758		.enable_reg = 0xc0d8,
1759		.enable_mask = BIT(0),
1760		.hw.init = &(struct clk_init_data){
1761			.name = "camcc_icp_ahb_clk",
1762			.parent_hws = (const struct clk_hw*[]){
1763				&camcc_slow_ahb_clk_src.clkr.hw,
1764			},
1765			.num_parents = 1,
1766			.flags = CLK_SET_RATE_PARENT,
1767			.ops = &clk_branch2_ops,
1768		},
1769	},
1770};
1771
1772static struct clk_branch camcc_icp_clk = {
1773	.halt_reg = 0xc0d0,
1774	.halt_check = BRANCH_HALT,
1775	.clkr = {
1776		.enable_reg = 0xc0d0,
1777		.enable_mask = BIT(0),
1778		.hw.init = &(struct clk_init_data){
1779			.name = "camcc_icp_clk",
1780			.parent_hws = (const struct clk_hw*[]){
1781				&camcc_icp_clk_src.clkr.hw,
1782			},
1783			.num_parents = 1,
1784			.flags = CLK_SET_RATE_PARENT,
1785			.ops = &clk_branch2_ops,
1786		},
1787	},
1788};
1789
1790static struct clk_branch camcc_ife_0_axi_clk = {
1791	.halt_reg = 0xa080,
1792	.halt_check = BRANCH_HALT,
1793	.clkr = {
1794		.enable_reg = 0xa080,
1795		.enable_mask = BIT(0),
1796		.hw.init = &(struct clk_init_data){
1797			.name = "camcc_ife_0_axi_clk",
1798			.parent_hws = (const struct clk_hw*[]){
1799				&camcc_camnoc_axi_clk_src.clkr.hw,
1800			},
1801			.num_parents = 1,
1802			.flags = CLK_SET_RATE_PARENT,
1803			.ops = &clk_branch2_ops,
1804		},
1805	},
1806};
1807
1808static struct clk_branch camcc_ife_0_clk = {
1809	.halt_reg = 0xa028,
1810	.halt_check = BRANCH_HALT,
1811	.clkr = {
1812		.enable_reg = 0xa028,
1813		.enable_mask = BIT(0),
1814		.hw.init = &(struct clk_init_data){
1815			.name = "camcc_ife_0_clk",
1816			.parent_hws = (const struct clk_hw*[]){
1817				&camcc_ife_0_clk_src.clkr.hw,
1818			},
1819			.num_parents = 1,
1820			.flags = CLK_SET_RATE_PARENT,
1821			.ops = &clk_branch2_ops,
1822		},
1823	},
1824};
1825
1826static struct clk_branch camcc_ife_0_cphy_rx_clk = {
1827	.halt_reg = 0xa07c,
1828	.halt_check = BRANCH_HALT,
1829	.clkr = {
1830		.enable_reg = 0xa07c,
1831		.enable_mask = BIT(0),
1832		.hw.init = &(struct clk_init_data){
1833			.name = "camcc_ife_0_cphy_rx_clk",
1834			.parent_hws = (const struct clk_hw*[]){
1835				&camcc_cphy_rx_clk_src.clkr.hw,
1836			},
1837			.num_parents = 1,
1838			.flags = CLK_SET_RATE_PARENT,
1839			.ops = &clk_branch2_ops,
1840		},
1841	},
1842};
1843
1844static struct clk_branch camcc_ife_0_csid_clk = {
1845	.halt_reg = 0xa054,
1846	.halt_check = BRANCH_HALT,
1847	.clkr = {
1848		.enable_reg = 0xa054,
1849		.enable_mask = BIT(0),
1850		.hw.init = &(struct clk_init_data){
1851			.name = "camcc_ife_0_csid_clk",
1852			.parent_hws = (const struct clk_hw*[]){
1853				&camcc_ife_0_csid_clk_src.clkr.hw,
1854			},
1855			.num_parents = 1,
1856			.flags = CLK_SET_RATE_PARENT,
1857			.ops = &clk_branch2_ops,
1858		},
1859	},
1860};
1861
1862static struct clk_branch camcc_ife_0_dsp_clk = {
1863	.halt_reg = 0xa038,
1864	.halt_check = BRANCH_HALT,
1865	.clkr = {
1866		.enable_reg = 0xa038,
1867		.enable_mask = BIT(0),
1868		.hw.init = &(struct clk_init_data){
1869			.name = "camcc_ife_0_dsp_clk",
1870			.parent_hws = (const struct clk_hw*[]){
1871				&camcc_ife_0_clk_src.clkr.hw,
1872			},
1873			.num_parents = 1,
1874			.flags = CLK_SET_RATE_PARENT,
1875			.ops = &clk_branch2_ops,
1876		},
1877	},
1878};
1879
1880static struct clk_branch camcc_ife_1_axi_clk = {
1881	.halt_reg = 0xb068,
1882	.halt_check = BRANCH_HALT,
1883	.clkr = {
1884		.enable_reg = 0xb068,
1885		.enable_mask = BIT(0),
1886		.hw.init = &(struct clk_init_data){
1887			.name = "camcc_ife_1_axi_clk",
1888			.parent_hws = (const struct clk_hw*[]){
1889				&camcc_camnoc_axi_clk_src.clkr.hw,
1890			},
1891			.num_parents = 1,
1892			.flags = CLK_SET_RATE_PARENT,
1893			.ops = &clk_branch2_ops,
1894		},
1895	},
1896};
1897
1898static struct clk_branch camcc_ife_1_clk = {
1899	.halt_reg = 0xb028,
1900	.halt_check = BRANCH_HALT,
1901	.clkr = {
1902		.enable_reg = 0xb028,
1903		.enable_mask = BIT(0),
1904		.hw.init = &(struct clk_init_data){
1905			.name = "camcc_ife_1_clk",
1906			.parent_hws = (const struct clk_hw*[]){
1907				&camcc_ife_1_clk_src.clkr.hw,
1908			},
1909			.num_parents = 1,
1910			.flags = CLK_SET_RATE_PARENT,
1911			.ops = &clk_branch2_ops,
1912		},
1913	},
1914};
1915
1916static struct clk_branch camcc_ife_1_cphy_rx_clk = {
1917	.halt_reg = 0xb064,
1918	.halt_check = BRANCH_HALT,
1919	.clkr = {
1920		.enable_reg = 0xb064,
1921		.enable_mask = BIT(0),
1922		.hw.init = &(struct clk_init_data){
1923			.name = "camcc_ife_1_cphy_rx_clk",
1924			.parent_hws = (const struct clk_hw*[]){
1925				&camcc_cphy_rx_clk_src.clkr.hw,
1926			},
1927			.num_parents = 1,
1928			.flags = CLK_SET_RATE_PARENT,
1929			.ops = &clk_branch2_ops,
1930		},
1931	},
1932};
1933
1934static struct clk_branch camcc_ife_1_csid_clk = {
1935	.halt_reg = 0xb054,
1936	.halt_check = BRANCH_HALT,
1937	.clkr = {
1938		.enable_reg = 0xb054,
1939		.enable_mask = BIT(0),
1940		.hw.init = &(struct clk_init_data){
1941			.name = "camcc_ife_1_csid_clk",
1942			.parent_hws = (const struct clk_hw*[]){
1943				&camcc_ife_1_csid_clk_src.clkr.hw,
1944			},
1945			.num_parents = 1,
1946			.flags = CLK_SET_RATE_PARENT,
1947			.ops = &clk_branch2_ops,
1948		},
1949	},
1950};
1951
1952static struct clk_branch camcc_ife_1_dsp_clk = {
1953	.halt_reg = 0xb038,
1954	.halt_check = BRANCH_HALT,
1955	.clkr = {
1956		.enable_reg = 0xb038,
1957		.enable_mask = BIT(0),
1958		.hw.init = &(struct clk_init_data){
1959			.name = "camcc_ife_1_dsp_clk",
1960			.parent_hws = (const struct clk_hw*[]){
1961				&camcc_ife_1_clk_src.clkr.hw,
1962			},
1963			.num_parents = 1,
1964			.flags = CLK_SET_RATE_PARENT,
1965			.ops = &clk_branch2_ops,
1966		},
1967	},
1968};
1969
1970static struct clk_branch camcc_ife_2_axi_clk = {
1971	.halt_reg = 0xf068,
1972	.halt_check = BRANCH_HALT,
1973	.clkr = {
1974		.enable_reg = 0xf068,
1975		.enable_mask = BIT(0),
1976		.hw.init = &(struct clk_init_data){
1977			.name = "camcc_ife_2_axi_clk",
1978			.parent_hws = (const struct clk_hw*[]){
1979				&camcc_camnoc_axi_clk_src.clkr.hw,
1980			},
1981			.num_parents = 1,
1982			.flags = CLK_SET_RATE_PARENT,
1983			.ops = &clk_branch2_ops,
1984		},
1985	},
1986};
1987
1988static struct clk_branch camcc_ife_2_clk = {
1989	.halt_reg = 0xf028,
1990	.halt_check = BRANCH_HALT,
1991	.clkr = {
1992		.enable_reg = 0xf028,
1993		.enable_mask = BIT(0),
1994		.hw.init = &(struct clk_init_data){
1995			.name = "camcc_ife_2_clk",
1996			.parent_hws = (const struct clk_hw*[]){
1997				&camcc_ife_2_clk_src.clkr.hw,
1998			},
1999			.num_parents = 1,
2000			.flags = CLK_SET_RATE_PARENT,
2001			.ops = &clk_branch2_ops,
2002		},
2003	},
2004};
2005
2006static struct clk_branch camcc_ife_2_cphy_rx_clk = {
2007	.halt_reg = 0xf064,
2008	.halt_check = BRANCH_HALT,
2009	.clkr = {
2010		.enable_reg = 0xf064,
2011		.enable_mask = BIT(0),
2012		.hw.init = &(struct clk_init_data){
2013			.name = "camcc_ife_2_cphy_rx_clk",
2014			.parent_hws = (const struct clk_hw*[]){
2015				&camcc_cphy_rx_clk_src.clkr.hw,
2016			},
2017			.num_parents = 1,
2018			.flags = CLK_SET_RATE_PARENT,
2019			.ops = &clk_branch2_ops,
2020		},
2021	},
2022};
2023
2024static struct clk_branch camcc_ife_2_csid_clk = {
2025	.halt_reg = 0xf054,
2026	.halt_check = BRANCH_HALT,
2027	.clkr = {
2028		.enable_reg = 0xf054,
2029		.enable_mask = BIT(0),
2030		.hw.init = &(struct clk_init_data){
2031			.name = "camcc_ife_2_csid_clk",
2032			.parent_hws = (const struct clk_hw*[]){
2033				&camcc_ife_2_csid_clk_src.clkr.hw,
2034			},
2035			.num_parents = 1,
2036			.flags = CLK_SET_RATE_PARENT,
2037			.ops = &clk_branch2_ops,
2038		},
2039	},
2040};
2041
2042static struct clk_branch camcc_ife_2_dsp_clk = {
2043	.halt_reg = 0xf038,
2044	.halt_check = BRANCH_HALT,
2045	.clkr = {
2046		.enable_reg = 0xf038,
2047		.enable_mask = BIT(0),
2048		.hw.init = &(struct clk_init_data){
2049			.name = "camcc_ife_2_dsp_clk",
2050			.parent_hws = (const struct clk_hw*[]){
2051				&camcc_ife_2_clk_src.clkr.hw,
2052			},
2053			.num_parents = 1,
2054			.flags = CLK_SET_RATE_PARENT,
2055			.ops = &clk_branch2_ops,
2056		},
2057	},
2058};
2059
2060static struct clk_branch camcc_ife_3_axi_clk = {
2061	.halt_reg = 0xf0d4,
2062	.halt_check = BRANCH_HALT,
2063	.clkr = {
2064		.enable_reg = 0xf0d4,
2065		.enable_mask = BIT(0),
2066		.hw.init = &(struct clk_init_data){
2067			.name = "camcc_ife_3_axi_clk",
2068			.parent_hws = (const struct clk_hw*[]){
2069				&camcc_camnoc_axi_clk_src.clkr.hw,
2070			},
2071			.num_parents = 1,
2072			.flags = CLK_SET_RATE_PARENT,
2073			.ops = &clk_branch2_ops,
2074		},
2075	},
2076};
2077
2078static struct clk_branch camcc_ife_3_clk = {
2079	.halt_reg = 0xf094,
2080	.halt_check = BRANCH_HALT,
2081	.clkr = {
2082		.enable_reg = 0xf094,
2083		.enable_mask = BIT(0),
2084		.hw.init = &(struct clk_init_data){
2085			.name = "camcc_ife_3_clk",
2086			.parent_hws = (const struct clk_hw*[]){
2087				&camcc_ife_3_clk_src.clkr.hw,
2088			},
2089			.num_parents = 1,
2090			.flags = CLK_SET_RATE_PARENT,
2091			.ops = &clk_branch2_ops,
2092		},
2093	},
2094};
2095
2096static struct clk_branch camcc_ife_3_cphy_rx_clk = {
2097	.halt_reg = 0xf0d0,
2098	.halt_check = BRANCH_HALT,
2099	.clkr = {
2100		.enable_reg = 0xf0d0,
2101		.enable_mask = BIT(0),
2102		.hw.init = &(struct clk_init_data){
2103			.name = "camcc_ife_3_cphy_rx_clk",
2104			.parent_hws = (const struct clk_hw*[]){
2105				&camcc_cphy_rx_clk_src.clkr.hw,
2106			},
2107			.num_parents = 1,
2108			.flags = CLK_SET_RATE_PARENT,
2109			.ops = &clk_branch2_ops,
2110		},
2111	},
2112};
2113
2114static struct clk_branch camcc_ife_3_csid_clk = {
2115	.halt_reg = 0xf0c0,
2116	.halt_check = BRANCH_HALT,
2117	.clkr = {
2118		.enable_reg = 0xf0c0,
2119		.enable_mask = BIT(0),
2120		.hw.init = &(struct clk_init_data){
2121			.name = "camcc_ife_3_csid_clk",
2122			.parent_hws = (const struct clk_hw*[]){
2123				&camcc_ife_3_csid_clk_src.clkr.hw,
2124			},
2125			.num_parents = 1,
2126			.flags = CLK_SET_RATE_PARENT,
2127			.ops = &clk_branch2_ops,
2128		},
2129	},
2130};
2131
2132static struct clk_branch camcc_ife_3_dsp_clk = {
2133	.halt_reg = 0xf0a4,
2134	.halt_check = BRANCH_HALT,
2135	.clkr = {
2136		.enable_reg = 0xf0a4,
2137		.enable_mask = BIT(0),
2138		.hw.init = &(struct clk_init_data){
2139			.name = "camcc_ife_3_dsp_clk",
2140			.parent_hws = (const struct clk_hw*[]){
2141				&camcc_ife_3_clk_src.clkr.hw,
2142			},
2143			.num_parents = 1,
2144			.flags = CLK_SET_RATE_PARENT,
2145			.ops = &clk_branch2_ops,
2146		},
2147	},
2148};
2149
2150static struct clk_branch camcc_ife_lite_0_clk = {
2151	.halt_reg = 0xc01c,
2152	.halt_check = BRANCH_HALT,
2153	.clkr = {
2154		.enable_reg = 0xc01c,
2155		.enable_mask = BIT(0),
2156		.hw.init = &(struct clk_init_data){
2157			.name = "camcc_ife_lite_0_clk",
2158			.parent_hws = (const struct clk_hw*[]){
2159				&camcc_ife_lite_0_clk_src.clkr.hw,
2160			},
2161			.num_parents = 1,
2162			.flags = CLK_SET_RATE_PARENT,
2163			.ops = &clk_branch2_ops,
2164		},
2165	},
2166};
2167
2168static struct clk_branch camcc_ife_lite_0_cphy_rx_clk = {
2169	.halt_reg = 0xc040,
2170	.halt_check = BRANCH_HALT,
2171	.clkr = {
2172		.enable_reg = 0xc040,
2173		.enable_mask = BIT(0),
2174		.hw.init = &(struct clk_init_data){
2175			.name = "camcc_ife_lite_0_cphy_rx_clk",
2176			.parent_hws = (const struct clk_hw*[]){
2177				&camcc_cphy_rx_clk_src.clkr.hw,
2178			},
2179			.num_parents = 1,
2180			.flags = CLK_SET_RATE_PARENT,
2181			.ops = &clk_branch2_ops,
2182		},
2183	},
2184};
2185
2186static struct clk_branch camcc_ife_lite_0_csid_clk = {
2187	.halt_reg = 0xc038,
2188	.halt_check = BRANCH_HALT,
2189	.clkr = {
2190		.enable_reg = 0xc038,
2191		.enable_mask = BIT(0),
2192		.hw.init = &(struct clk_init_data){
2193			.name = "camcc_ife_lite_0_csid_clk",
2194			.parent_hws = (const struct clk_hw*[]){
2195				&camcc_ife_lite_0_csid_clk_src.clkr.hw,
2196			},
2197			.num_parents = 1,
2198			.flags = CLK_SET_RATE_PARENT,
2199			.ops = &clk_branch2_ops,
2200		},
2201	},
2202};
2203
2204static struct clk_branch camcc_ife_lite_1_clk = {
2205	.halt_reg = 0xc060,
2206	.halt_check = BRANCH_HALT,
2207	.clkr = {
2208		.enable_reg = 0xc060,
2209		.enable_mask = BIT(0),
2210		.hw.init = &(struct clk_init_data){
2211			.name = "camcc_ife_lite_1_clk",
2212			.parent_hws = (const struct clk_hw*[]){
2213				&camcc_ife_lite_1_clk_src.clkr.hw,
2214			},
2215			.num_parents = 1,
2216			.flags = CLK_SET_RATE_PARENT,
2217			.ops = &clk_branch2_ops,
2218		},
2219	},
2220};
2221
2222static struct clk_branch camcc_ife_lite_1_cphy_rx_clk = {
2223	.halt_reg = 0xc084,
2224	.halt_check = BRANCH_HALT,
2225	.clkr = {
2226		.enable_reg = 0xc084,
2227		.enable_mask = BIT(0),
2228		.hw.init = &(struct clk_init_data){
2229			.name = "camcc_ife_lite_1_cphy_rx_clk",
2230			.parent_hws = (const struct clk_hw*[]){
2231				&camcc_cphy_rx_clk_src.clkr.hw,
2232			},
2233			.num_parents = 1,
2234			.flags = CLK_SET_RATE_PARENT,
2235			.ops = &clk_branch2_ops,
2236		},
2237	},
2238};
2239
2240static struct clk_branch camcc_ife_lite_1_csid_clk = {
2241	.halt_reg = 0xc07c,
2242	.halt_check = BRANCH_HALT,
2243	.clkr = {
2244		.enable_reg = 0xc07c,
2245		.enable_mask = BIT(0),
2246		.hw.init = &(struct clk_init_data){
2247			.name = "camcc_ife_lite_1_csid_clk",
2248			.parent_hws = (const struct clk_hw*[]){
2249				&camcc_ife_lite_1_csid_clk_src.clkr.hw,
2250			},
2251			.num_parents = 1,
2252			.flags = CLK_SET_RATE_PARENT,
2253			.ops = &clk_branch2_ops,
2254		},
2255	},
2256};
2257
2258static struct clk_branch camcc_ife_lite_2_clk = {
2259	.halt_reg = 0xc258,
2260	.halt_check = BRANCH_HALT,
2261	.clkr = {
2262		.enable_reg = 0xc258,
2263		.enable_mask = BIT(0),
2264		.hw.init = &(struct clk_init_data){
2265			.name = "camcc_ife_lite_2_clk",
2266			.parent_hws = (const struct clk_hw*[]){
2267				&camcc_ife_lite_2_clk_src.clkr.hw,
2268			},
2269			.num_parents = 1,
2270			.flags = CLK_SET_RATE_PARENT,
2271			.ops = &clk_branch2_ops,
2272		},
2273	},
2274};
2275
2276static struct clk_branch camcc_ife_lite_2_cphy_rx_clk = {
2277	.halt_reg = 0xc27c,
2278	.halt_check = BRANCH_HALT,
2279	.clkr = {
2280		.enable_reg = 0xc27c,
2281		.enable_mask = BIT(0),
2282		.hw.init = &(struct clk_init_data){
2283			.name = "camcc_ife_lite_2_cphy_rx_clk",
2284			.parent_hws = (const struct clk_hw*[]){
2285				&camcc_cphy_rx_clk_src.clkr.hw,
2286			},
2287			.num_parents = 1,
2288			.flags = CLK_SET_RATE_PARENT,
2289			.ops = &clk_branch2_ops,
2290		},
2291	},
2292};
2293
2294static struct clk_branch camcc_ife_lite_2_csid_clk = {
2295	.halt_reg = 0xc274,
2296	.halt_check = BRANCH_HALT,
2297	.clkr = {
2298		.enable_reg = 0xc274,
2299		.enable_mask = BIT(0),
2300		.hw.init = &(struct clk_init_data){
2301			.name = "camcc_ife_lite_2_csid_clk",
2302			.parent_hws = (const struct clk_hw*[]){
2303				&camcc_ife_lite_2_csid_clk_src.clkr.hw,
2304			},
2305			.num_parents = 1,
2306			.flags = CLK_SET_RATE_PARENT,
2307			.ops = &clk_branch2_ops,
2308		},
2309	},
2310};
2311
2312static struct clk_branch camcc_ife_lite_3_clk = {
2313	.halt_reg = 0xc29c,
2314	.halt_check = BRANCH_HALT,
2315	.clkr = {
2316		.enable_reg = 0xc29c,
2317		.enable_mask = BIT(0),
2318		.hw.init = &(struct clk_init_data){
2319			.name = "camcc_ife_lite_3_clk",
2320			.parent_hws = (const struct clk_hw*[]){
2321				&camcc_ife_lite_3_clk_src.clkr.hw,
2322			},
2323			.num_parents = 1,
2324			.flags = CLK_SET_RATE_PARENT,
2325			.ops = &clk_branch2_ops,
2326		},
2327	},
2328};
2329
2330static struct clk_branch camcc_ife_lite_3_cphy_rx_clk = {
2331	.halt_reg = 0xc2c0,
2332	.halt_check = BRANCH_HALT,
2333	.clkr = {
2334		.enable_reg = 0xc2c0,
2335		.enable_mask = BIT(0),
2336		.hw.init = &(struct clk_init_data){
2337			.name = "camcc_ife_lite_3_cphy_rx_clk",
2338			.parent_hws = (const struct clk_hw*[]){
2339				&camcc_cphy_rx_clk_src.clkr.hw,
2340			},
2341			.num_parents = 1,
2342			.flags = CLK_SET_RATE_PARENT,
2343			.ops = &clk_branch2_ops,
2344		},
2345	},
2346};
2347
2348static struct clk_branch camcc_ife_lite_3_csid_clk = {
2349	.halt_reg = 0xc2b8,
2350	.halt_check = BRANCH_HALT,
2351	.clkr = {
2352		.enable_reg = 0xc2b8,
2353		.enable_mask = BIT(0),
2354		.hw.init = &(struct clk_init_data){
2355			.name = "camcc_ife_lite_3_csid_clk",
2356			.parent_hws = (const struct clk_hw*[]){
2357				&camcc_ife_lite_3_csid_clk_src.clkr.hw,
2358			},
2359			.num_parents = 1,
2360			.flags = CLK_SET_RATE_PARENT,
2361			.ops = &clk_branch2_ops,
2362		},
2363	},
2364};
2365
2366static struct clk_branch camcc_ipe_0_ahb_clk = {
2367	.halt_reg = 0x8040,
2368	.halt_check = BRANCH_HALT,
2369	.clkr = {
2370		.enable_reg = 0x8040,
2371		.enable_mask = BIT(0),
2372		.hw.init = &(struct clk_init_data){
2373			.name = "camcc_ipe_0_ahb_clk",
2374			.parent_hws = (const struct clk_hw*[]){
2375				&camcc_slow_ahb_clk_src.clkr.hw,
2376			},
2377			.num_parents = 1,
2378			.flags = CLK_SET_RATE_PARENT,
2379			.ops = &clk_branch2_ops,
2380		},
2381	},
2382};
2383
2384static struct clk_branch camcc_ipe_0_areg_clk = {
2385	.halt_reg = 0x803c,
2386	.halt_check = BRANCH_HALT,
2387	.clkr = {
2388		.enable_reg = 0x803c,
2389		.enable_mask = BIT(0),
2390		.hw.init = &(struct clk_init_data){
2391			.name = "camcc_ipe_0_areg_clk",
2392			.parent_hws = (const struct clk_hw*[]){
2393				&camcc_fast_ahb_clk_src.clkr.hw,
2394			},
2395			.num_parents = 1,
2396			.flags = CLK_SET_RATE_PARENT,
2397			.ops = &clk_branch2_ops,
2398		},
2399	},
2400};
2401
2402static struct clk_branch camcc_ipe_0_axi_clk = {
2403	.halt_reg = 0x8038,
2404	.halt_check = BRANCH_HALT,
2405	.clkr = {
2406		.enable_reg = 0x8038,
2407		.enable_mask = BIT(0),
2408		.hw.init = &(struct clk_init_data){
2409			.name = "camcc_ipe_0_axi_clk",
2410			.parent_hws = (const struct clk_hw*[]){
2411				&camcc_camnoc_axi_clk_src.clkr.hw,
2412			},
2413			.num_parents = 1,
2414			.flags = CLK_SET_RATE_PARENT,
2415			.ops = &clk_branch2_ops,
2416		},
2417	},
2418};
2419
2420static struct clk_branch camcc_ipe_0_clk = {
2421	.halt_reg = 0x8028,
2422	.halt_check = BRANCH_HALT,
2423	.clkr = {
2424		.enable_reg = 0x8028,
2425		.enable_mask = BIT(0),
2426		.hw.init = &(struct clk_init_data){
2427			.name = "camcc_ipe_0_clk",
2428			.parent_hws = (const struct clk_hw*[]){
2429				&camcc_ipe_0_clk_src.clkr.hw,
2430			},
2431			.num_parents = 1,
2432			.flags = CLK_SET_RATE_PARENT,
2433			.ops = &clk_branch2_ops,
2434		},
2435	},
2436};
2437
2438static struct clk_branch camcc_ipe_1_ahb_clk = {
2439	.halt_reg = 0x9028,
2440	.halt_check = BRANCH_HALT,
2441	.clkr = {
2442		.enable_reg = 0x9028,
2443		.enable_mask = BIT(0),
2444		.hw.init = &(struct clk_init_data){
2445			.name = "camcc_ipe_1_ahb_clk",
2446			.parent_hws = (const struct clk_hw*[]){
2447				&camcc_slow_ahb_clk_src.clkr.hw,
2448			},
2449			.num_parents = 1,
2450			.flags = CLK_SET_RATE_PARENT,
2451			.ops = &clk_branch2_ops,
2452		},
2453	},
2454};
2455
2456static struct clk_branch camcc_ipe_1_areg_clk = {
2457	.halt_reg = 0x9024,
2458	.halt_check = BRANCH_HALT,
2459	.clkr = {
2460		.enable_reg = 0x9024,
2461		.enable_mask = BIT(0),
2462		.hw.init = &(struct clk_init_data){
2463			.name = "camcc_ipe_1_areg_clk",
2464			.parent_hws = (const struct clk_hw*[]){
2465				&camcc_fast_ahb_clk_src.clkr.hw,
2466			},
2467			.num_parents = 1,
2468			.flags = CLK_SET_RATE_PARENT,
2469			.ops = &clk_branch2_ops,
2470		},
2471	},
2472};
2473
2474static struct clk_branch camcc_ipe_1_axi_clk = {
2475	.halt_reg = 0x9020,
2476	.halt_check = BRANCH_HALT,
2477	.clkr = {
2478		.enable_reg = 0x9020,
2479		.enable_mask = BIT(0),
2480		.hw.init = &(struct clk_init_data){
2481			.name = "camcc_ipe_1_axi_clk",
2482			.parent_hws = (const struct clk_hw*[]){
2483				&camcc_camnoc_axi_clk_src.clkr.hw,
2484			},
2485			.num_parents = 1,
2486			.flags = CLK_SET_RATE_PARENT,
2487			.ops = &clk_branch2_ops,
2488		},
2489	},
2490};
2491
2492static struct clk_branch camcc_ipe_1_clk = {
2493	.halt_reg = 0x9010,
2494	.halt_check = BRANCH_HALT,
2495	.clkr = {
2496		.enable_reg = 0x9010,
2497		.enable_mask = BIT(0),
2498		.hw.init = &(struct clk_init_data){
2499			.name = "camcc_ipe_1_clk",
2500			.parent_hws = (const struct clk_hw*[]){
2501				&camcc_ipe_0_clk_src.clkr.hw,
2502			},
2503			.num_parents = 1,
2504			.flags = CLK_SET_RATE_PARENT,
2505			.ops = &clk_branch2_ops,
2506		},
2507	},
2508};
2509
2510static struct clk_branch camcc_jpeg_clk = {
2511	.halt_reg = 0xc0a4,
2512	.halt_check = BRANCH_HALT,
2513	.clkr = {
2514		.enable_reg = 0xc0a4,
2515		.enable_mask = BIT(0),
2516		.hw.init = &(struct clk_init_data){
2517			.name = "camcc_jpeg_clk",
2518			.parent_hws = (const struct clk_hw*[]){
2519				&camcc_jpeg_clk_src.clkr.hw,
2520			},
2521			.num_parents = 1,
2522			.flags = CLK_SET_RATE_PARENT,
2523			.ops = &clk_branch2_ops,
2524		},
2525	},
2526};
2527
2528static struct clk_branch camcc_lrme_clk = {
2529	.halt_reg = 0xc15c,
2530	.halt_check = BRANCH_HALT,
2531	.clkr = {
2532		.enable_reg = 0xc15c,
2533		.enable_mask = BIT(0),
2534		.hw.init = &(struct clk_init_data){
2535			.name = "camcc_lrme_clk",
2536			.parent_hws = (const struct clk_hw*[]){
2537				&camcc_lrme_clk_src.clkr.hw,
2538			},
2539			.num_parents = 1,
2540			.flags = CLK_SET_RATE_PARENT,
2541			.ops = &clk_branch2_ops,
2542		},
2543	},
2544};
2545
2546static struct clk_branch camcc_mclk0_clk = {
2547	.halt_reg = 0x501c,
2548	.halt_check = BRANCH_HALT,
2549	.clkr = {
2550		.enable_reg = 0x501c,
2551		.enable_mask = BIT(0),
2552		.hw.init = &(struct clk_init_data){
2553			.name = "camcc_mclk0_clk",
2554			.parent_hws = (const struct clk_hw*[]){
2555				&camcc_mclk0_clk_src.clkr.hw,
2556			},
2557			.num_parents = 1,
2558			.flags = CLK_SET_RATE_PARENT,
2559			.ops = &clk_branch2_ops,
2560		},
2561	},
2562};
2563
2564static struct clk_branch camcc_mclk1_clk = {
2565	.halt_reg = 0x503c,
2566	.halt_check = BRANCH_HALT,
2567	.clkr = {
2568		.enable_reg = 0x503c,
2569		.enable_mask = BIT(0),
2570		.hw.init = &(struct clk_init_data){
2571			.name = "camcc_mclk1_clk",
2572			.parent_hws = (const struct clk_hw*[]){
2573				&camcc_mclk1_clk_src.clkr.hw,
2574			},
2575			.num_parents = 1,
2576			.flags = CLK_SET_RATE_PARENT,
2577			.ops = &clk_branch2_ops,
2578		},
2579	},
2580};
2581
2582static struct clk_branch camcc_mclk2_clk = {
2583	.halt_reg = 0x505c,
2584	.halt_check = BRANCH_HALT,
2585	.clkr = {
2586		.enable_reg = 0x505c,
2587		.enable_mask = BIT(0),
2588		.hw.init = &(struct clk_init_data){
2589			.name = "camcc_mclk2_clk",
2590			.parent_hws = (const struct clk_hw*[]){
2591				&camcc_mclk2_clk_src.clkr.hw,
2592			},
2593			.num_parents = 1,
2594			.flags = CLK_SET_RATE_PARENT,
2595			.ops = &clk_branch2_ops,
2596		},
2597	},
2598};
2599
2600static struct clk_branch camcc_mclk3_clk = {
2601	.halt_reg = 0x507c,
2602	.halt_check = BRANCH_HALT,
2603	.clkr = {
2604		.enable_reg = 0x507c,
2605		.enable_mask = BIT(0),
2606		.hw.init = &(struct clk_init_data){
2607			.name = "camcc_mclk3_clk",
2608			.parent_hws = (const struct clk_hw*[]){
2609				&camcc_mclk3_clk_src.clkr.hw,
2610			},
2611			.num_parents = 1,
2612			.flags = CLK_SET_RATE_PARENT,
2613			.ops = &clk_branch2_ops,
2614		},
2615	},
2616};
2617
2618static struct clk_branch camcc_mclk4_clk = {
2619	.halt_reg = 0x509c,
2620	.halt_check = BRANCH_HALT,
2621	.clkr = {
2622		.enable_reg = 0x509c,
2623		.enable_mask = BIT(0),
2624		.hw.init = &(struct clk_init_data){
2625			.name = "camcc_mclk4_clk",
2626			.parent_hws = (const struct clk_hw*[]){
2627				&camcc_mclk4_clk_src.clkr.hw,
2628			},
2629			.num_parents = 1,
2630			.flags = CLK_SET_RATE_PARENT,
2631			.ops = &clk_branch2_ops,
2632		},
2633	},
2634};
2635
2636static struct clk_branch camcc_mclk5_clk = {
2637	.halt_reg = 0x50bc,
2638	.halt_check = BRANCH_HALT,
2639	.clkr = {
2640		.enable_reg = 0x50bc,
2641		.enable_mask = BIT(0),
2642		.hw.init = &(struct clk_init_data){
2643			.name = "camcc_mclk5_clk",
2644			.parent_hws = (const struct clk_hw*[]){
2645				&camcc_mclk5_clk_src.clkr.hw,
2646			},
2647			.num_parents = 1,
2648			.flags = CLK_SET_RATE_PARENT,
2649			.ops = &clk_branch2_ops,
2650		},
2651	},
2652};
2653
2654static struct clk_branch camcc_mclk6_clk = {
2655	.halt_reg = 0x50dc,
2656	.halt_check = BRANCH_HALT,
2657	.clkr = {
2658		.enable_reg = 0x50dc,
2659		.enable_mask = BIT(0),
2660		.hw.init = &(struct clk_init_data){
2661			.name = "camcc_mclk6_clk",
2662			.parent_hws = (const struct clk_hw*[]){
2663				&camcc_mclk6_clk_src.clkr.hw,
2664			},
2665			.num_parents = 1,
2666			.flags = CLK_SET_RATE_PARENT,
2667			.ops = &clk_branch2_ops,
2668		},
2669	},
2670};
2671
2672static struct clk_branch camcc_mclk7_clk = {
2673	.halt_reg = 0x50fc,
2674	.halt_check = BRANCH_HALT,
2675	.clkr = {
2676		.enable_reg = 0x50fc,
2677		.enable_mask = BIT(0),
2678		.hw.init = &(struct clk_init_data){
2679			.name = "camcc_mclk7_clk",
2680			.parent_hws = (const struct clk_hw*[]){
2681				&camcc_mclk7_clk_src.clkr.hw,
2682			},
2683			.num_parents = 1,
2684			.flags = CLK_SET_RATE_PARENT,
2685			.ops = &clk_branch2_ops,
2686		},
2687	},
2688};
2689
2690static struct clk_branch camcc_sleep_clk = {
2691	.halt_reg = 0xc200,
2692	.halt_check = BRANCH_HALT,
2693	.clkr = {
2694		.enable_reg = 0xc200,
2695		.enable_mask = BIT(0),
2696		.hw.init = &(struct clk_init_data){
2697			.name = "camcc_sleep_clk",
2698			.parent_hws = (const struct clk_hw*[]){
2699				&camcc_sleep_clk_src.clkr.hw,
2700			},
2701			.num_parents = 1,
2702			.flags = CLK_SET_RATE_PARENT,
2703			.ops = &clk_branch2_ops,
2704		},
2705	},
2706};
2707
2708static struct gdsc titan_top_gdsc;
2709
2710static struct gdsc bps_gdsc = {
2711	.gdscr = 0x7004,
2712	.pd = {
2713		.name = "bps_gdsc",
2714	},
2715	.flags = HW_CTRL | RETAIN_FF_ENABLE,
2716	.parent = &titan_top_gdsc.pd,
2717	.pwrsts = PWRSTS_OFF_ON,
2718};
2719
2720static struct gdsc ife_0_gdsc = {
2721	.gdscr = 0xa004,
2722	.pd = {
2723		.name = "ife_0_gdsc",
2724	},
2725	.flags = RETAIN_FF_ENABLE,
2726	.parent = &titan_top_gdsc.pd,
2727	.pwrsts = PWRSTS_OFF_ON,
2728};
2729
2730static struct gdsc ife_1_gdsc = {
2731	.gdscr = 0xb004,
2732	.pd = {
2733		.name = "ife_1_gdsc",
2734	},
2735	.flags = RETAIN_FF_ENABLE,
2736	.parent = &titan_top_gdsc.pd,
2737	.pwrsts = PWRSTS_OFF_ON,
2738};
2739
2740static struct gdsc ife_2_gdsc = {
2741	.gdscr = 0xf004,
2742	.pd = {
2743		.name = "ife_2_gdsc",
2744	},
2745	.flags = RETAIN_FF_ENABLE,
2746	.parent = &titan_top_gdsc.pd,
2747	.pwrsts = PWRSTS_OFF_ON,
2748};
2749
2750static struct gdsc ife_3_gdsc = {
2751	.gdscr = 0xf070,
2752	.pd = {
2753		.name = "ife_3_gdsc",
2754	},
2755	.flags = RETAIN_FF_ENABLE,
2756	.parent = &titan_top_gdsc.pd,
2757	.pwrsts = PWRSTS_OFF_ON,
2758};
2759
2760static struct gdsc ipe_0_gdsc = {
2761	.gdscr = 0x8004,
2762	.pd = {
2763		.name = "ipe_0_gdsc",
2764	},
2765	.flags = HW_CTRL | RETAIN_FF_ENABLE,
2766	.parent = &titan_top_gdsc.pd,
2767	.pwrsts = PWRSTS_OFF_ON,
2768};
2769
2770static struct gdsc ipe_1_gdsc = {
2771	.gdscr = 0x9004,
2772	.pd = {
2773		.name = "ipe_1_gdsc",
2774	},
2775	.flags = HW_CTRL | RETAIN_FF_ENABLE,
2776	.parent = &titan_top_gdsc.pd,
2777	.pwrsts = PWRSTS_OFF_ON,
2778};
2779
2780static struct gdsc titan_top_gdsc = {
2781	.gdscr = 0xc1bc,
2782	.pd = {
2783		.name = "titan_top_gdsc",
2784	},
2785	.flags = RETAIN_FF_ENABLE,
2786	.pwrsts = PWRSTS_OFF_ON,
2787};
2788
2789static struct clk_regmap *camcc_sc8280xp_clocks[] = {
2790	[CAMCC_BPS_AHB_CLK] = &camcc_bps_ahb_clk.clkr,
2791	[CAMCC_BPS_AREG_CLK] = &camcc_bps_areg_clk.clkr,
2792	[CAMCC_BPS_AXI_CLK] = &camcc_bps_axi_clk.clkr,
2793	[CAMCC_BPS_CLK] = &camcc_bps_clk.clkr,
2794	[CAMCC_BPS_CLK_SRC] = &camcc_bps_clk_src.clkr,
2795	[CAMCC_CAMNOC_AXI_CLK] = &camcc_camnoc_axi_clk.clkr,
2796	[CAMCC_CAMNOC_AXI_CLK_SRC] = &camcc_camnoc_axi_clk_src.clkr,
2797	[CAMCC_CAMNOC_DCD_XO_CLK] = &camcc_camnoc_dcd_xo_clk.clkr,
2798	[CAMCC_CCI_0_CLK] = &camcc_cci_0_clk.clkr,
2799	[CAMCC_CCI_0_CLK_SRC] = &camcc_cci_0_clk_src.clkr,
2800	[CAMCC_CCI_1_CLK] = &camcc_cci_1_clk.clkr,
2801	[CAMCC_CCI_1_CLK_SRC] = &camcc_cci_1_clk_src.clkr,
2802	[CAMCC_CCI_2_CLK] = &camcc_cci_2_clk.clkr,
2803	[CAMCC_CCI_2_CLK_SRC] = &camcc_cci_2_clk_src.clkr,
2804	[CAMCC_CCI_3_CLK] = &camcc_cci_3_clk.clkr,
2805	[CAMCC_CCI_3_CLK_SRC] = &camcc_cci_3_clk_src.clkr,
2806	[CAMCC_CORE_AHB_CLK] = &camcc_core_ahb_clk.clkr,
2807	[CAMCC_CPAS_AHB_CLK] = &camcc_cpas_ahb_clk.clkr,
2808	[CAMCC_CPHY_RX_CLK_SRC] = &camcc_cphy_rx_clk_src.clkr,
2809	[CAMCC_CSI0PHYTIMER_CLK] = &camcc_csi0phytimer_clk.clkr,
2810	[CAMCC_CSI0PHYTIMER_CLK_SRC] = &camcc_csi0phytimer_clk_src.clkr,
2811	[CAMCC_CSI1PHYTIMER_CLK] = &camcc_csi1phytimer_clk.clkr,
2812	[CAMCC_CSI1PHYTIMER_CLK_SRC] = &camcc_csi1phytimer_clk_src.clkr,
2813	[CAMCC_CSI2PHYTIMER_CLK] = &camcc_csi2phytimer_clk.clkr,
2814	[CAMCC_CSI2PHYTIMER_CLK_SRC] = &camcc_csi2phytimer_clk_src.clkr,
2815	[CAMCC_CSI3PHYTIMER_CLK] = &camcc_csi3phytimer_clk.clkr,
2816	[CAMCC_CSI3PHYTIMER_CLK_SRC] = &camcc_csi3phytimer_clk_src.clkr,
2817	[CAMCC_CSIPHY0_CLK] = &camcc_csiphy0_clk.clkr,
2818	[CAMCC_CSIPHY1_CLK] = &camcc_csiphy1_clk.clkr,
2819	[CAMCC_CSIPHY2_CLK] = &camcc_csiphy2_clk.clkr,
2820	[CAMCC_CSIPHY3_CLK] = &camcc_csiphy3_clk.clkr,
2821	[CAMCC_FAST_AHB_CLK_SRC] = &camcc_fast_ahb_clk_src.clkr,
2822	[CAMCC_GDSC_CLK] = &camcc_gdsc_clk.clkr,
2823	[CAMCC_ICP_AHB_CLK] = &camcc_icp_ahb_clk.clkr,
2824	[CAMCC_ICP_CLK] = &camcc_icp_clk.clkr,
2825	[CAMCC_ICP_CLK_SRC] = &camcc_icp_clk_src.clkr,
2826	[CAMCC_IFE_0_AXI_CLK] = &camcc_ife_0_axi_clk.clkr,
2827	[CAMCC_IFE_0_CLK] = &camcc_ife_0_clk.clkr,
2828	[CAMCC_IFE_0_CLK_SRC] = &camcc_ife_0_clk_src.clkr,
2829	[CAMCC_IFE_0_CPHY_RX_CLK] = &camcc_ife_0_cphy_rx_clk.clkr,
2830	[CAMCC_IFE_0_CSID_CLK] = &camcc_ife_0_csid_clk.clkr,
2831	[CAMCC_IFE_0_CSID_CLK_SRC] = &camcc_ife_0_csid_clk_src.clkr,
2832	[CAMCC_IFE_0_DSP_CLK] = &camcc_ife_0_dsp_clk.clkr,
2833	[CAMCC_IFE_1_AXI_CLK] = &camcc_ife_1_axi_clk.clkr,
2834	[CAMCC_IFE_1_CLK] = &camcc_ife_1_clk.clkr,
2835	[CAMCC_IFE_1_CLK_SRC] = &camcc_ife_1_clk_src.clkr,
2836	[CAMCC_IFE_1_CPHY_RX_CLK] = &camcc_ife_1_cphy_rx_clk.clkr,
2837	[CAMCC_IFE_1_CSID_CLK] = &camcc_ife_1_csid_clk.clkr,
2838	[CAMCC_IFE_1_CSID_CLK_SRC] = &camcc_ife_1_csid_clk_src.clkr,
2839	[CAMCC_IFE_1_DSP_CLK] = &camcc_ife_1_dsp_clk.clkr,
2840	[CAMCC_IFE_2_AXI_CLK] = &camcc_ife_2_axi_clk.clkr,
2841	[CAMCC_IFE_2_CLK] = &camcc_ife_2_clk.clkr,
2842	[CAMCC_IFE_2_CLK_SRC] = &camcc_ife_2_clk_src.clkr,
2843	[CAMCC_IFE_2_CPHY_RX_CLK] = &camcc_ife_2_cphy_rx_clk.clkr,
2844	[CAMCC_IFE_2_CSID_CLK] = &camcc_ife_2_csid_clk.clkr,
2845	[CAMCC_IFE_2_CSID_CLK_SRC] = &camcc_ife_2_csid_clk_src.clkr,
2846	[CAMCC_IFE_2_DSP_CLK] = &camcc_ife_2_dsp_clk.clkr,
2847	[CAMCC_IFE_3_AXI_CLK] = &camcc_ife_3_axi_clk.clkr,
2848	[CAMCC_IFE_3_CLK] = &camcc_ife_3_clk.clkr,
2849	[CAMCC_IFE_3_CLK_SRC] = &camcc_ife_3_clk_src.clkr,
2850	[CAMCC_IFE_3_CPHY_RX_CLK] = &camcc_ife_3_cphy_rx_clk.clkr,
2851	[CAMCC_IFE_3_CSID_CLK] = &camcc_ife_3_csid_clk.clkr,
2852	[CAMCC_IFE_3_CSID_CLK_SRC] = &camcc_ife_3_csid_clk_src.clkr,
2853	[CAMCC_IFE_3_DSP_CLK] = &camcc_ife_3_dsp_clk.clkr,
2854	[CAMCC_IFE_LITE_0_CLK] = &camcc_ife_lite_0_clk.clkr,
2855	[CAMCC_IFE_LITE_0_CLK_SRC] = &camcc_ife_lite_0_clk_src.clkr,
2856	[CAMCC_IFE_LITE_0_CPHY_RX_CLK] = &camcc_ife_lite_0_cphy_rx_clk.clkr,
2857	[CAMCC_IFE_LITE_0_CSID_CLK] = &camcc_ife_lite_0_csid_clk.clkr,
2858	[CAMCC_IFE_LITE_0_CSID_CLK_SRC] = &camcc_ife_lite_0_csid_clk_src.clkr,
2859	[CAMCC_IFE_LITE_1_CLK] = &camcc_ife_lite_1_clk.clkr,
2860	[CAMCC_IFE_LITE_1_CLK_SRC] = &camcc_ife_lite_1_clk_src.clkr,
2861	[CAMCC_IFE_LITE_1_CPHY_RX_CLK] = &camcc_ife_lite_1_cphy_rx_clk.clkr,
2862	[CAMCC_IFE_LITE_1_CSID_CLK] = &camcc_ife_lite_1_csid_clk.clkr,
2863	[CAMCC_IFE_LITE_1_CSID_CLK_SRC] = &camcc_ife_lite_1_csid_clk_src.clkr,
2864	[CAMCC_IFE_LITE_2_CLK] = &camcc_ife_lite_2_clk.clkr,
2865	[CAMCC_IFE_LITE_2_CLK_SRC] = &camcc_ife_lite_2_clk_src.clkr,
2866	[CAMCC_IFE_LITE_2_CPHY_RX_CLK] = &camcc_ife_lite_2_cphy_rx_clk.clkr,
2867	[CAMCC_IFE_LITE_2_CSID_CLK] = &camcc_ife_lite_2_csid_clk.clkr,
2868	[CAMCC_IFE_LITE_2_CSID_CLK_SRC] = &camcc_ife_lite_2_csid_clk_src.clkr,
2869	[CAMCC_IFE_LITE_3_CLK] = &camcc_ife_lite_3_clk.clkr,
2870	[CAMCC_IFE_LITE_3_CLK_SRC] = &camcc_ife_lite_3_clk_src.clkr,
2871	[CAMCC_IFE_LITE_3_CPHY_RX_CLK] = &camcc_ife_lite_3_cphy_rx_clk.clkr,
2872	[CAMCC_IFE_LITE_3_CSID_CLK] = &camcc_ife_lite_3_csid_clk.clkr,
2873	[CAMCC_IFE_LITE_3_CSID_CLK_SRC] = &camcc_ife_lite_3_csid_clk_src.clkr,
2874	[CAMCC_IPE_0_AHB_CLK] = &camcc_ipe_0_ahb_clk.clkr,
2875	[CAMCC_IPE_0_AREG_CLK] = &camcc_ipe_0_areg_clk.clkr,
2876	[CAMCC_IPE_0_AXI_CLK] = &camcc_ipe_0_axi_clk.clkr,
2877	[CAMCC_IPE_0_CLK] = &camcc_ipe_0_clk.clkr,
2878	[CAMCC_IPE_0_CLK_SRC] = &camcc_ipe_0_clk_src.clkr,
2879	[CAMCC_IPE_1_AHB_CLK] = &camcc_ipe_1_ahb_clk.clkr,
2880	[CAMCC_IPE_1_AREG_CLK] = &camcc_ipe_1_areg_clk.clkr,
2881	[CAMCC_IPE_1_AXI_CLK] = &camcc_ipe_1_axi_clk.clkr,
2882	[CAMCC_IPE_1_CLK] = &camcc_ipe_1_clk.clkr,
2883	[CAMCC_JPEG_CLK] = &camcc_jpeg_clk.clkr,
2884	[CAMCC_JPEG_CLK_SRC] = &camcc_jpeg_clk_src.clkr,
2885	[CAMCC_LRME_CLK] = &camcc_lrme_clk.clkr,
2886	[CAMCC_LRME_CLK_SRC] = &camcc_lrme_clk_src.clkr,
2887	[CAMCC_MCLK0_CLK] = &camcc_mclk0_clk.clkr,
2888	[CAMCC_MCLK0_CLK_SRC] = &camcc_mclk0_clk_src.clkr,
2889	[CAMCC_MCLK1_CLK] = &camcc_mclk1_clk.clkr,
2890	[CAMCC_MCLK1_CLK_SRC] = &camcc_mclk1_clk_src.clkr,
2891	[CAMCC_MCLK2_CLK] = &camcc_mclk2_clk.clkr,
2892	[CAMCC_MCLK2_CLK_SRC] = &camcc_mclk2_clk_src.clkr,
2893	[CAMCC_MCLK3_CLK] = &camcc_mclk3_clk.clkr,
2894	[CAMCC_MCLK3_CLK_SRC] = &camcc_mclk3_clk_src.clkr,
2895	[CAMCC_MCLK4_CLK] = &camcc_mclk4_clk.clkr,
2896	[CAMCC_MCLK4_CLK_SRC] = &camcc_mclk4_clk_src.clkr,
2897	[CAMCC_MCLK5_CLK] = &camcc_mclk5_clk.clkr,
2898	[CAMCC_MCLK5_CLK_SRC] = &camcc_mclk5_clk_src.clkr,
2899	[CAMCC_MCLK6_CLK] = &camcc_mclk6_clk.clkr,
2900	[CAMCC_MCLK6_CLK_SRC] = &camcc_mclk6_clk_src.clkr,
2901	[CAMCC_MCLK7_CLK] = &camcc_mclk7_clk.clkr,
2902	[CAMCC_MCLK7_CLK_SRC] = &camcc_mclk7_clk_src.clkr,
2903	[CAMCC_PLL0] = &camcc_pll0.clkr,
2904	[CAMCC_PLL0_OUT_EVEN] = &camcc_pll0_out_even.clkr,
2905	[CAMCC_PLL0_OUT_ODD] = &camcc_pll0_out_odd.clkr,
2906	[CAMCC_PLL1] = &camcc_pll1.clkr,
2907	[CAMCC_PLL1_OUT_EVEN] = &camcc_pll1_out_even.clkr,
2908	[CAMCC_PLL2] = &camcc_pll2.clkr,
2909	[CAMCC_PLL3] = &camcc_pll3.clkr,
2910	[CAMCC_PLL3_OUT_EVEN] = &camcc_pll3_out_even.clkr,
2911	[CAMCC_PLL4] = &camcc_pll4.clkr,
2912	[CAMCC_PLL4_OUT_EVEN] = &camcc_pll4_out_even.clkr,
2913	[CAMCC_PLL5] = &camcc_pll5.clkr,
2914	[CAMCC_PLL5_OUT_EVEN] = &camcc_pll5_out_even.clkr,
2915	[CAMCC_PLL6] = &camcc_pll6.clkr,
2916	[CAMCC_PLL6_OUT_EVEN] = &camcc_pll6_out_even.clkr,
2917	[CAMCC_PLL7] = &camcc_pll7.clkr,
2918	[CAMCC_PLL7_OUT_EVEN] = &camcc_pll7_out_even.clkr,
2919	[CAMCC_PLL7_OUT_ODD] = &camcc_pll7_out_odd.clkr,
2920	[CAMCC_SLEEP_CLK] = &camcc_sleep_clk.clkr,
2921	[CAMCC_SLEEP_CLK_SRC] = &camcc_sleep_clk_src.clkr,
2922	[CAMCC_SLOW_AHB_CLK_SRC] = &camcc_slow_ahb_clk_src.clkr,
2923	[CAMCC_XO_CLK_SRC] = &camcc_xo_clk_src.clkr,
2924};
2925
2926static struct gdsc *camcc_sc8280xp_gdscs[] = {
2927	[BPS_GDSC] = &bps_gdsc,
2928	[IFE_0_GDSC] = &ife_0_gdsc,
2929	[IFE_1_GDSC] = &ife_1_gdsc,
2930	[IFE_2_GDSC] = &ife_2_gdsc,
2931	[IFE_3_GDSC] = &ife_3_gdsc,
2932	[IPE_0_GDSC] = &ipe_0_gdsc,
2933	[IPE_1_GDSC] = &ipe_1_gdsc,
2934	[TITAN_TOP_GDSC] = &titan_top_gdsc,
2935};
2936
2937static const struct qcom_reset_map camcc_sc8280xp_resets[] = {
2938	[CAMCC_BPS_BCR] = { 0x7000 },
2939	[CAMCC_CAMNOC_BCR] = { 0xc16c },
2940	[CAMCC_CCI_BCR] = { 0xc104 },
2941	[CAMCC_CPAS_BCR] = { 0xc164 },
2942	[CAMCC_CSI0PHY_BCR] = { 0x6000 },
2943	[CAMCC_CSI1PHY_BCR] = { 0x6024 },
2944	[CAMCC_CSI2PHY_BCR] = { 0x6048 },
2945	[CAMCC_CSI3PHY_BCR] = { 0x6070 },
2946	[CAMCC_ICP_BCR] = { 0xc0b4 },
2947	[CAMCC_IFE_0_BCR] = { 0xa000 },
2948	[CAMCC_IFE_1_BCR] = { 0xb000 },
2949	[CAMCC_IFE_2_BCR] = { 0xf000 },
2950	[CAMCC_IFE_3_BCR] = { 0xf06c },
2951	[CAMCC_IFE_LITE_0_BCR] = { 0xc000 },
2952	[CAMCC_IFE_LITE_1_BCR] = { 0xc044 },
2953	[CAMCC_IFE_LITE_2_BCR] = { 0xc23c },
2954	[CAMCC_IFE_LITE_3_BCR] = { 0xc280 },
2955	[CAMCC_IPE_0_BCR] = { 0x8000 },
2956	[CAMCC_IPE_1_BCR] = { 0x9000 },
2957	[CAMCC_JPEG_BCR] = { 0xc088 },
2958	[CAMCC_LRME_BCR] = { 0xc140 },
2959};
2960
2961static const struct regmap_config camcc_sc8280xp_regmap_config = {
2962	.reg_bits = 32,
2963	.reg_stride = 4,
2964	.val_bits = 32,
2965	.max_register = 0x13020,
2966	.fast_io = true,
2967};
2968
2969static struct qcom_cc_desc camcc_sc8280xp_desc = {
2970	.config = &camcc_sc8280xp_regmap_config,
2971	.clks = camcc_sc8280xp_clocks,
2972	.num_clks = ARRAY_SIZE(camcc_sc8280xp_clocks),
2973	.resets = camcc_sc8280xp_resets,
2974	.num_resets = ARRAY_SIZE(camcc_sc8280xp_resets),
2975	.gdscs = camcc_sc8280xp_gdscs,
2976	.num_gdscs = ARRAY_SIZE(camcc_sc8280xp_gdscs),
2977};
2978
2979static const struct of_device_id camcc_sc8280xp_match_table[] = {
2980	{ .compatible = "qcom,sc8280xp-camcc" },
2981	{ }
2982};
2983MODULE_DEVICE_TABLE(of, camcc_sc8280xp_match_table);
2984
2985static int camcc_sc8280xp_probe(struct platform_device *pdev)
2986{
2987	struct regmap *regmap;
2988	int ret;
2989
2990	ret = devm_pm_runtime_enable(&pdev->dev);
2991	if (ret)
2992		return ret;
2993
2994	ret = pm_runtime_resume_and_get(&pdev->dev);
2995	if (ret)
2996		return ret;
2997
2998	regmap = qcom_cc_map(pdev, &camcc_sc8280xp_desc);
2999	if (IS_ERR(regmap)) {
3000		ret = PTR_ERR(regmap);
3001		goto err_put_rpm;
3002	}
3003
3004	clk_lucid_pll_configure(&camcc_pll0, regmap, &camcc_pll0_config);
3005	clk_lucid_pll_configure(&camcc_pll1, regmap, &camcc_pll1_config);
3006	clk_zonda_pll_configure(&camcc_pll2, regmap, &camcc_pll2_config);
3007	clk_lucid_pll_configure(&camcc_pll3, regmap, &camcc_pll3_config);
3008	clk_lucid_pll_configure(&camcc_pll4, regmap, &camcc_pll4_config);
3009	clk_lucid_pll_configure(&camcc_pll5, regmap, &camcc_pll5_config);
3010	clk_lucid_pll_configure(&camcc_pll6, regmap, &camcc_pll6_config);
3011	clk_lucid_pll_configure(&camcc_pll7, regmap, &camcc_pll7_config);
3012
3013	/*
3014	 * Keep camcc_gdsc_clk always enabled:
3015	 */
3016	regmap_update_bits(regmap, 0xc1e4, BIT(0), 1);
3017
3018	ret = qcom_cc_really_probe(pdev, &camcc_sc8280xp_desc, regmap);
3019	if (ret)
3020		goto err_disable;
3021
3022	pm_runtime_put(&pdev->dev);
3023
3024	return 0;
3025
3026err_disable:
3027	regmap_update_bits(regmap, 0xc1e4, BIT(0), 0);
3028err_put_rpm:
3029	pm_runtime_put_sync(&pdev->dev);
3030
3031	return ret;
3032}
3033
3034static struct platform_driver camcc_sc8280xp_driver = {
3035	.probe = camcc_sc8280xp_probe,
3036	.driver = {
3037		.name = "camcc-sc8280xp",
3038		.of_match_table = camcc_sc8280xp_match_table,
3039	},
3040};
3041
3042module_platform_driver(camcc_sc8280xp_driver);
3043
3044MODULE_DESCRIPTION("QCOM CAMCC SC8280XP Driver");
3045MODULE_LICENSE("GPL");