1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * Copyright 2012 Freescale Semiconductor, Inc.
  4 * Copyright 2012 Linaro Ltd.
  5 */
  6
  7#include <linux/clk-provider.h>
  8#include <linux/export.h>
  9#include <linux/io.h>
 10#include <linux/slab.h>
 11#include <linux/err.h>
 12#include "clk.h"
 13
 14/**
 15 * struct clk_pfd - IMX PFD clock
 16 * @hw:		clock source
 17 * @reg:	PFD register address
 18 * @idx:	the index of PFD encoded in the register
 19 *
 20 * PFD clock found on i.MX6 series.  Each register for PFD has 4 clk_pfd
 21 * data encoded, and member idx is used to specify the one.  And each
 22 * register has SET, CLR and TOG registers at offset 0x4 0x8 and 0xc.
 23 */
 24struct clk_pfd {
 25	struct clk_hw	hw;
 26	void __iomem	*reg;
 27	u8		idx;
 28};
 29
 30#define to_clk_pfd(_hw) container_of(_hw, struct clk_pfd, hw)
 31
 32#define SET	0x4
 33#define CLR	0x8
 34#define OTG	0xc
 35
 36static int clk_pfd_enable(struct clk_hw *hw)
 37{
 38	struct clk_pfd *pfd = to_clk_pfd(hw);
 39
 40	writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + CLR);
 41
 42	return 0;
 43}
 44
 45static void clk_pfd_disable(struct clk_hw *hw)
 46{
 47	struct clk_pfd *pfd = to_clk_pfd(hw);
 48
 49	writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + SET);
 50}
 51
 52static unsigned long clk_pfd_recalc_rate(struct clk_hw *hw,
 53					 unsigned long parent_rate)
 54{
 55	struct clk_pfd *pfd = to_clk_pfd(hw);
 56	u64 tmp = parent_rate;
 57	u8 frac = (readl_relaxed(pfd->reg) >> (pfd->idx * 8)) & 0x3f;
 58
 59	tmp *= 18;
 60	do_div(tmp, frac);
 61
 62	return tmp;
 63}
 64
 65static long clk_pfd_round_rate(struct clk_hw *hw, unsigned long rate,
 66			       unsigned long *prate)
 67{
 68	u64 tmp = *prate;
 69	u8 frac;
 70
 71	tmp = tmp * 18 + rate / 2;
 72	do_div(tmp, rate);
 73	frac = tmp;
 74	if (frac < 12)
 75		frac = 12;
 76	else if (frac > 35)
 77		frac = 35;
 78	tmp = *prate;
 79	tmp *= 18;
 80	do_div(tmp, frac);
 81
 82	return tmp;
 83}
 84
 85static int clk_pfd_set_rate(struct clk_hw *hw, unsigned long rate,
 86		unsigned long parent_rate)
 87{
 88	struct clk_pfd *pfd = to_clk_pfd(hw);
 89	u64 tmp = parent_rate;
 90	u8 frac;
 91
 92	tmp = tmp * 18 + rate / 2;
 93	do_div(tmp, rate);
 94	frac = tmp;
 95	if (frac < 12)
 96		frac = 12;
 97	else if (frac > 35)
 98		frac = 35;
 99
100	writel_relaxed(0x3f << (pfd->idx * 8), pfd->reg + CLR);
101	writel_relaxed(frac << (pfd->idx * 8), pfd->reg + SET);
102
103	return 0;
104}
105
106static int clk_pfd_is_enabled(struct clk_hw *hw)
107{
108	struct clk_pfd *pfd = to_clk_pfd(hw);
109
110	if (readl_relaxed(pfd->reg) & (1 << ((pfd->idx + 1) * 8 - 1)))
111		return 0;
112
113	return 1;
114}
115
116static const struct clk_ops clk_pfd_ops = {
117	.enable		= clk_pfd_enable,
118	.disable	= clk_pfd_disable,
119	.recalc_rate	= clk_pfd_recalc_rate,
120	.round_rate	= clk_pfd_round_rate,
121	.set_rate	= clk_pfd_set_rate,
122	.is_enabled     = clk_pfd_is_enabled,
123};
124
125struct clk_hw *imx_clk_hw_pfd(const char *name, const char *parent_name,
126			void __iomem *reg, u8 idx)
127{
128	struct clk_pfd *pfd;
129	struct clk_hw *hw;
130	struct clk_init_data init;
131	int ret;
132
133	pfd = kzalloc(sizeof(*pfd), GFP_KERNEL);
134	if (!pfd)
135		return ERR_PTR(-ENOMEM);
136
137	pfd->reg = reg;
138	pfd->idx = idx;
139
140	init.name = name;
141	init.ops = &clk_pfd_ops;
142	init.flags = 0;
143	init.parent_names = &parent_name;
144	init.num_parents = 1;
145
146	pfd->hw.init = &init;
147	hw = &pfd->hw;
148
149	ret = clk_hw_register(NULL, hw);
150	if (ret) {
151		kfree(pfd);
152		return ERR_PTR(ret);
153	}
154
155	return hw;
156}
157EXPORT_SYMBOL_GPL(imx_clk_hw_pfd);