1#include <linux/kernel.h>
   2#include <linux/sched.h>
 
   3#include <linux/init.h>
   4#include <linux/module.h>
   5#include <linux/timer.h>
   6#include <linux/acpi_pmtmr.h>
   7#include <linux/cpufreq.h>
   8#include <linux/delay.h>
   9#include <linux/clocksource.h>
  10#include <linux/percpu.h>
  11#include <linux/timex.h>
 
 
  12
  13#include <asm/hpet.h>
  14#include <asm/timer.h>
  15#include <asm/vgtod.h>
  16#include <asm/time.h>
  17#include <asm/delay.h>
  18#include <asm/hypervisor.h>
  19#include <asm/nmi.h>
  20#include <asm/x86_init.h>
 
 
 
 
 
  21
  22unsigned int __read_mostly cpu_khz;	/* TSC clocks / usec, not used here */
  23EXPORT_SYMBOL(cpu_khz);
  24
  25unsigned int __read_mostly tsc_khz;
  26EXPORT_SYMBOL(tsc_khz);
  27
 
 
  28/*
  29 * TSC can be unstable due to cpufreq or due to unsynced TSCs
  30 */
  31static int __read_mostly tsc_unstable;
 
  32
  33/* native_sched_clock() is called before tsc_init(), so
  34   we must start with the TSC soft disabled to prevent
  35   erroneous rdtsc usage on !cpu_has_tsc processors */
  36static int __read_mostly tsc_disabled = -1;
  37
  38int tsc_clocksource_reliable;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  39/*
  40 * Scheduler clock - returns current time in nanosec units.
  41 */
  42u64 native_sched_clock(void)
  43{
  44	u64 this_offset;
 
 
 
 
 
  45
  46	/*
  47	 * Fall back to jiffies if there's no TSC available:
  48	 * ( But note that we still use it if the TSC is marked
  49	 *   unstable. We do this because unlike Time Of Day,
  50	 *   the scheduler clock tolerates small errors and it's
  51	 *   very important for it to be as fast as the platform
  52	 *   can achieve it. )
  53	 */
  54	if (unlikely(tsc_disabled)) {
  55		/* No locking but a rare wrong value is not a big deal: */
  56		return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
  57	}
  58
  59	/* read the Time Stamp Counter: */
  60	rdtscll(this_offset);
 
  61
  62	/* return the value in ns */
  63	return __cycles_2_ns(this_offset);
 
 
 
 
  64}
  65
  66/* We need to define a real function for sched_clock, to override the
  67   weak default version */
  68#ifdef CONFIG_PARAVIRT
  69unsigned long long sched_clock(void)
  70{
  71	return paravirt_sched_clock();
  72}
 
 
 
 
 
  73#else
  74unsigned long long
  75sched_clock(void) __attribute__((alias("native_sched_clock")));
 
  76#endif
  77
 
 
 
 
 
 
 
 
 
  78int check_tsc_unstable(void)
  79{
  80	return tsc_unstable;
  81}
  82EXPORT_SYMBOL_GPL(check_tsc_unstable);
  83
  84#ifdef CONFIG_X86_TSC
  85int __init notsc_setup(char *str)
  86{
  87	printk(KERN_WARNING "notsc: Kernel compiled with CONFIG_X86_TSC, "
  88			"cannot disable TSC completely.\n");
  89	tsc_disabled = 1;
  90	return 1;
  91}
  92#else
  93/*
  94 * disable flag for tsc. Takes effect by clearing the TSC cpu flag
  95 * in cpu/common.c
  96 */
  97int __init notsc_setup(char *str)
  98{
  99	setup_clear_cpu_cap(X86_FEATURE_TSC);
 100	return 1;
 101}
 102#endif
 103
 104__setup("notsc", notsc_setup);
 105
 106static int no_sched_irq_time;
 
 
 107
 108static int __init tsc_setup(char *str)
 109{
 110	if (!strcmp(str, "reliable"))
 111		tsc_clocksource_reliable = 1;
 112	if (!strncmp(str, "noirqtime", 9))
 113		no_sched_irq_time = 1;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 114	return 1;
 115}
 116
 117__setup("tsc=", tsc_setup);
 118
 119#define MAX_RETRIES     5
 120#define SMI_TRESHOLD    50000
 121
 122/*
 123 * Read TSC and the reference counters. Take care of SMI disturbance
 124 */
 125static u64 tsc_read_refs(u64 *p, int hpet)
 126{
 127	u64 t1, t2;
 
 128	int i;
 129
 130	for (i = 0; i < MAX_RETRIES; i++) {
 131		t1 = get_cycles();
 132		if (hpet)
 133			*p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
 134		else
 135			*p = acpi_pm_read_early();
 136		t2 = get_cycles();
 137		if ((t2 - t1) < SMI_TRESHOLD)
 138			return t2;
 139	}
 140	return ULLONG_MAX;
 141}
 142
 143/*
 144 * Calculate the TSC frequency from HPET reference
 145 */
 146static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2)
 147{
 148	u64 tmp;
 149
 150	if (hpet2 < hpet1)
 151		hpet2 += 0x100000000ULL;
 152	hpet2 -= hpet1;
 153	tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD));
 154	do_div(tmp, 1000000);
 155	do_div(deltatsc, tmp);
 156
 157	return (unsigned long) deltatsc;
 158}
 159
 160/*
 161 * Calculate the TSC frequency from PMTimer reference
 162 */
 163static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2)
 164{
 165	u64 tmp;
 166
 167	if (!pm1 && !pm2)
 168		return ULONG_MAX;
 169
 170	if (pm2 < pm1)
 171		pm2 += (u64)ACPI_PM_OVRRUN;
 172	pm2 -= pm1;
 173	tmp = pm2 * 1000000000LL;
 174	do_div(tmp, PMTMR_TICKS_PER_SEC);
 175	do_div(deltatsc, tmp);
 176
 177	return (unsigned long) deltatsc;
 178}
 179
 180#define CAL_MS		10
 181#define CAL_LATCH	(PIT_TICK_RATE / (1000 / CAL_MS))
 182#define CAL_PIT_LOOPS	1000
 183
 184#define CAL2_MS		50
 185#define CAL2_LATCH	(PIT_TICK_RATE / (1000 / CAL2_MS))
 186#define CAL2_PIT_LOOPS	5000
 187
 188
 189/*
 190 * Try to calibrate the TSC against the Programmable
 191 * Interrupt Timer and return the frequency of the TSC
 192 * in kHz.
 193 *
 194 * Return ULONG_MAX on failure to calibrate.
 195 */
 196static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin)
 197{
 198	u64 tsc, t1, t2, delta;
 199	unsigned long tscmin, tscmax;
 200	int pitcnt;
 201
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 202	/* Set the Gate high, disable speaker */
 203	outb((inb(0x61) & ~0x02) | 0x01, 0x61);
 204
 205	/*
 206	 * Setup CTC channel 2* for mode 0, (interrupt on terminal
 207	 * count mode), binary count. Set the latch register to 50ms
 208	 * (LSB then MSB) to begin countdown.
 209	 */
 210	outb(0xb0, 0x43);
 211	outb(latch & 0xff, 0x42);
 212	outb(latch >> 8, 0x42);
 213
 214	tsc = t1 = t2 = get_cycles();
 215
 216	pitcnt = 0;
 217	tscmax = 0;
 218	tscmin = ULONG_MAX;
 219	while ((inb(0x61) & 0x20) == 0) {
 220		t2 = get_cycles();
 221		delta = t2 - tsc;
 222		tsc = t2;
 223		if ((unsigned long) delta < tscmin)
 224			tscmin = (unsigned int) delta;
 225		if ((unsigned long) delta > tscmax)
 226			tscmax = (unsigned int) delta;
 227		pitcnt++;
 228	}
 229
 230	/*
 231	 * Sanity checks:
 232	 *
 233	 * If we were not able to read the PIT more than loopmin
 234	 * times, then we have been hit by a massive SMI
 235	 *
 236	 * If the maximum is 10 times larger than the minimum,
 237	 * then we got hit by an SMI as well.
 238	 */
 239	if (pitcnt < loopmin || tscmax > 10 * tscmin)
 240		return ULONG_MAX;
 241
 242	/* Calculate the PIT value */
 243	delta = t2 - t1;
 244	do_div(delta, ms);
 245	return delta;
 246}
 247
 248/*
 249 * This reads the current MSB of the PIT counter, and
 250 * checks if we are running on sufficiently fast and
 251 * non-virtualized hardware.
 252 *
 253 * Our expectations are:
 254 *
 255 *  - the PIT is running at roughly 1.19MHz
 256 *
 257 *  - each IO is going to take about 1us on real hardware,
 258 *    but we allow it to be much faster (by a factor of 10) or
 259 *    _slightly_ slower (ie we allow up to a 2us read+counter
 260 *    update - anything else implies a unacceptably slow CPU
 261 *    or PIT for the fast calibration to work.
 262 *
 263 *  - with 256 PIT ticks to read the value, we have 214us to
 264 *    see the same MSB (and overhead like doing a single TSC
 265 *    read per MSB value etc).
 266 *
 267 *  - We're doing 2 reads per loop (LSB, MSB), and we expect
 268 *    them each to take about a microsecond on real hardware.
 269 *    So we expect a count value of around 100. But we'll be
 270 *    generous, and accept anything over 50.
 271 *
 272 *  - if the PIT is stuck, and we see *many* more reads, we
 273 *    return early (and the next caller of pit_expect_msb()
 274 *    then consider it a failure when they don't see the
 275 *    next expected value).
 276 *
 277 * These expectations mean that we know that we have seen the
 278 * transition from one expected value to another with a fairly
 279 * high accuracy, and we didn't miss any events. We can thus
 280 * use the TSC value at the transitions to calculate a pretty
 281 * good value for the TSC frequencty.
 282 */
 283static inline int pit_verify_msb(unsigned char val)
 284{
 285	/* Ignore LSB */
 286	inb(0x42);
 287	return inb(0x42) == val;
 288}
 289
 290static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap)
 291{
 292	int count;
 293	u64 tsc = 0, prev_tsc = 0;
 294
 295	for (count = 0; count < 50000; count++) {
 296		if (!pit_verify_msb(val))
 297			break;
 298		prev_tsc = tsc;
 299		tsc = get_cycles();
 300	}
 301	*deltap = get_cycles() - prev_tsc;
 302	*tscp = tsc;
 303
 304	/*
 305	 * We require _some_ success, but the quality control
 306	 * will be based on the error terms on the TSC values.
 307	 */
 308	return count > 5;
 309}
 310
 311/*
 312 * How many MSB values do we want to see? We aim for
 313 * a maximum error rate of 500ppm (in practice the
 314 * real error is much smaller), but refuse to spend
 315 * more than 50ms on it.
 316 */
 317#define MAX_QUICK_PIT_MS 50
 318#define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
 319
 320static unsigned long quick_pit_calibrate(void)
 321{
 322	int i;
 323	u64 tsc, delta;
 324	unsigned long d1, d2;
 325
 
 
 
 326	/* Set the Gate high, disable speaker */
 327	outb((inb(0x61) & ~0x02) | 0x01, 0x61);
 328
 329	/*
 330	 * Counter 2, mode 0 (one-shot), binary count
 331	 *
 332	 * NOTE! Mode 2 decrements by two (and then the
 333	 * output is flipped each time, giving the same
 334	 * final output frequency as a decrement-by-one),
 335	 * so mode 0 is much better when looking at the
 336	 * individual counts.
 337	 */
 338	outb(0xb0, 0x43);
 339
 340	/* Start at 0xffff */
 341	outb(0xff, 0x42);
 342	outb(0xff, 0x42);
 343
 344	/*
 345	 * The PIT starts counting at the next edge, so we
 346	 * need to delay for a microsecond. The easiest way
 347	 * to do that is to just read back the 16-bit counter
 348	 * once from the PIT.
 349	 */
 350	pit_verify_msb(0);
 351
 352	if (pit_expect_msb(0xff, &tsc, &d1)) {
 353		for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
 354			if (!pit_expect_msb(0xff-i, &delta, &d2))
 355				break;
 356
 
 
 
 
 
 
 
 
 
 
 357			/*
 358			 * Iterate until the error is less than 500 ppm
 359			 */
 360			delta -= tsc;
 361			if (d1+d2 >= delta >> 11)
 362				continue;
 363
 364			/*
 365			 * Check the PIT one more time to verify that
 366			 * all TSC reads were stable wrt the PIT.
 367			 *
 368			 * This also guarantees serialization of the
 369			 * last cycle read ('d2') in pit_expect_msb.
 370			 */
 371			if (!pit_verify_msb(0xfe - i))
 372				break;
 373			goto success;
 374		}
 375	}
 376	printk("Fast TSC calibration failed\n");
 377	return 0;
 378
 379success:
 380	/*
 381	 * Ok, if we get here, then we've seen the
 382	 * MSB of the PIT decrement 'i' times, and the
 383	 * error has shrunk to less than 500 ppm.
 384	 *
 385	 * As a result, we can depend on there not being
 386	 * any odd delays anywhere, and the TSC reads are
 387	 * reliable (within the error).
 388	 *
 389	 * kHz = ticks / time-in-seconds / 1000;
 390	 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
 391	 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
 392	 */
 393	delta *= PIT_TICK_RATE;
 394	do_div(delta, i*256*1000);
 395	printk("Fast TSC calibration using PIT\n");
 396	return delta;
 397}
 398
 399/**
 400 * native_calibrate_tsc - calibrate the tsc on boot
 
 401 */
 402unsigned long native_calibrate_tsc(void)
 403{
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 404	u64 tsc1, tsc2, delta, ref1, ref2;
 405	unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX;
 406	unsigned long flags, latch, ms, fast_calibrate;
 407	int hpet = is_hpet_enabled(), i, loopmin;
 408
 409	local_irq_save(flags);
 410	fast_calibrate = quick_pit_calibrate();
 411	local_irq_restore(flags);
 412	if (fast_calibrate)
 413		return fast_calibrate;
 414
 415	/*
 416	 * Run 5 calibration loops to get the lowest frequency value
 417	 * (the best estimate). We use two different calibration modes
 418	 * here:
 419	 *
 420	 * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and
 421	 * load a timeout of 50ms. We read the time right after we
 422	 * started the timer and wait until the PIT count down reaches
 423	 * zero. In each wait loop iteration we read the TSC and check
 424	 * the delta to the previous read. We keep track of the min
 425	 * and max values of that delta. The delta is mostly defined
 426	 * by the IO time of the PIT access, so we can detect when a
 427	 * SMI/SMM disturbance happened between the two reads. If the
 428	 * maximum time is significantly larger than the minimum time,
 429	 * then we discard the result and have another try.
 430	 *
 431	 * 2) Reference counter. If available we use the HPET or the
 432	 * PMTIMER as a reference to check the sanity of that value.
 433	 * We use separate TSC readouts and check inside of the
 434	 * reference read for a SMI/SMM disturbance. We dicard
 435	 * disturbed values here as well. We do that around the PIT
 436	 * calibration delay loop as we have to wait for a certain
 437	 * amount of time anyway.
 438	 */
 439
 440	/* Preset PIT loop values */
 441	latch = CAL_LATCH;
 442	ms = CAL_MS;
 443	loopmin = CAL_PIT_LOOPS;
 444
 445	for (i = 0; i < 3; i++) {
 446		unsigned long tsc_pit_khz;
 447
 448		/*
 449		 * Read the start value and the reference count of
 450		 * hpet/pmtimer when available. Then do the PIT
 451		 * calibration, which will take at least 50ms, and
 452		 * read the end value.
 453		 */
 454		local_irq_save(flags);
 455		tsc1 = tsc_read_refs(&ref1, hpet);
 456		tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin);
 457		tsc2 = tsc_read_refs(&ref2, hpet);
 458		local_irq_restore(flags);
 459
 460		/* Pick the lowest PIT TSC calibration so far */
 461		tsc_pit_min = min(tsc_pit_min, tsc_pit_khz);
 462
 463		/* hpet or pmtimer available ? */
 464		if (ref1 == ref2)
 465			continue;
 466
 467		/* Check, whether the sampling was disturbed by an SMI */
 468		if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX)
 469			continue;
 470
 471		tsc2 = (tsc2 - tsc1) * 1000000LL;
 472		if (hpet)
 473			tsc2 = calc_hpet_ref(tsc2, ref1, ref2);
 474		else
 475			tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2);
 476
 477		tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2);
 478
 479		/* Check the reference deviation */
 480		delta = ((u64) tsc_pit_min) * 100;
 481		do_div(delta, tsc_ref_min);
 482
 483		/*
 484		 * If both calibration results are inside a 10% window
 485		 * then we can be sure, that the calibration
 486		 * succeeded. We break out of the loop right away. We
 487		 * use the reference value, as it is more precise.
 488		 */
 489		if (delta >= 90 && delta <= 110) {
 490			printk(KERN_INFO
 491			       "TSC: PIT calibration matches %s. %d loops\n",
 492			       hpet ? "HPET" : "PMTIMER", i + 1);
 493			return tsc_ref_min;
 494		}
 495
 496		/*
 497		 * Check whether PIT failed more than once. This
 498		 * happens in virtualized environments. We need to
 499		 * give the virtual PC a slightly longer timeframe for
 500		 * the HPET/PMTIMER to make the result precise.
 501		 */
 502		if (i == 1 && tsc_pit_min == ULONG_MAX) {
 503			latch = CAL2_LATCH;
 504			ms = CAL2_MS;
 505			loopmin = CAL2_PIT_LOOPS;
 506		}
 507	}
 508
 509	/*
 510	 * Now check the results.
 511	 */
 512	if (tsc_pit_min == ULONG_MAX) {
 513		/* PIT gave no useful value */
 514		printk(KERN_WARNING "TSC: Unable to calibrate against PIT\n");
 515
 516		/* We don't have an alternative source, disable TSC */
 517		if (!hpet && !ref1 && !ref2) {
 518			printk("TSC: No reference (HPET/PMTIMER) available\n");
 519			return 0;
 520		}
 521
 522		/* The alternative source failed as well, disable TSC */
 523		if (tsc_ref_min == ULONG_MAX) {
 524			printk(KERN_WARNING "TSC: HPET/PMTIMER calibration "
 525			       "failed.\n");
 526			return 0;
 527		}
 528
 529		/* Use the alternative source */
 530		printk(KERN_INFO "TSC: using %s reference calibration\n",
 531		       hpet ? "HPET" : "PMTIMER");
 532
 533		return tsc_ref_min;
 534	}
 535
 536	/* We don't have an alternative source, use the PIT calibration value */
 537	if (!hpet && !ref1 && !ref2) {
 538		printk(KERN_INFO "TSC: Using PIT calibration value\n");
 539		return tsc_pit_min;
 540	}
 541
 542	/* The alternative source failed, use the PIT calibration value */
 543	if (tsc_ref_min == ULONG_MAX) {
 544		printk(KERN_WARNING "TSC: HPET/PMTIMER calibration failed. "
 545		       "Using PIT calibration\n");
 546		return tsc_pit_min;
 547	}
 548
 549	/*
 550	 * The calibration values differ too much. In doubt, we use
 551	 * the PIT value as we know that there are PMTIMERs around
 552	 * running at double speed. At least we let the user know:
 553	 */
 554	printk(KERN_WARNING "TSC: PIT calibration deviates from %s: %lu %lu.\n",
 555	       hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min);
 556	printk(KERN_INFO "TSC: Using PIT calibration value\n");
 557	return tsc_pit_min;
 558}
 559
 560int recalibrate_cpu_khz(void)
 
 
 
 561{
 562#ifndef CONFIG_SMP
 563	unsigned long cpu_khz_old = cpu_khz;
 564
 565	if (cpu_has_tsc) {
 566		tsc_khz = x86_platform.calibrate_tsc();
 567		cpu_khz = tsc_khz;
 568		cpu_data(0).loops_per_jiffy =
 569			cpufreq_scale(cpu_data(0).loops_per_jiffy,
 570					cpu_khz_old, cpu_khz);
 571		return 0;
 572	} else
 573		return -ENODEV;
 574#else
 575	return -ENODEV;
 576#endif
 577}
 578
 579EXPORT_SYMBOL(recalibrate_cpu_khz);
 580
 581
 582/* Accelerators for sched_clock()
 583 * convert from cycles(64bits) => nanoseconds (64bits)
 584 *  basic equation:
 585 *              ns = cycles / (freq / ns_per_sec)
 586 *              ns = cycles * (ns_per_sec / freq)
 587 *              ns = cycles * (10^9 / (cpu_khz * 10^3))
 588 *              ns = cycles * (10^6 / cpu_khz)
 589 *
 590 *      Then we use scaling math (suggested by george@mvista.com) to get:
 591 *              ns = cycles * (10^6 * SC / cpu_khz) / SC
 592 *              ns = cycles * cyc2ns_scale / SC
 593 *
 594 *      And since SC is a constant power of two, we can convert the div
 595 *  into a shift.
 596 *
 597 *  We can use khz divisor instead of mhz to keep a better precision, since
 598 *  cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
 599 *  (mathieu.desnoyers@polymtl.ca)
 600 *
 601 *                      -johnstul@us.ibm.com "math is hard, lets go shopping!"
 602 */
 603
 604DEFINE_PER_CPU(unsigned long, cyc2ns);
 605DEFINE_PER_CPU(unsigned long long, cyc2ns_offset);
 606
 607static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu)
 608{
 609	unsigned long long tsc_now, ns_now, *offset;
 610	unsigned long flags, *scale;
 611
 612	local_irq_save(flags);
 613	sched_clock_idle_sleep_event();
 614
 615	scale = &per_cpu(cyc2ns, cpu);
 616	offset = &per_cpu(cyc2ns_offset, cpu);
 617
 618	rdtscll(tsc_now);
 619	ns_now = __cycles_2_ns(tsc_now);
 
 
 620
 621	if (cpu_khz) {
 622		*scale = (NSEC_PER_MSEC << CYC2NS_SCALE_FACTOR)/cpu_khz;
 623		*offset = ns_now - mult_frac(tsc_now, *scale,
 624					     (1UL << CYC2NS_SCALE_FACTOR));
 625	}
 626
 627	sched_clock_idle_wakeup_event(0);
 628	local_irq_restore(flags);
 
 
 
 
 
 
 
 629}
 
 
 630
 631static unsigned long long cyc2ns_suspend;
 632
 633void tsc_save_sched_clock_state(void)
 634{
 635	if (!sched_clock_stable)
 636		return;
 637
 638	cyc2ns_suspend = sched_clock();
 639}
 640
 641/*
 642 * Even on processors with invariant TSC, TSC gets reset in some the
 643 * ACPI system sleep states. And in some systems BIOS seem to reinit TSC to
 644 * arbitrary value (still sync'd across cpu's) during resume from such sleep
 645 * states. To cope up with this, recompute the cyc2ns_offset for each cpu so
 646 * that sched_clock() continues from the point where it was left off during
 647 * suspend.
 648 */
 649void tsc_restore_sched_clock_state(void)
 650{
 651	unsigned long long offset;
 652	unsigned long flags;
 653	int cpu;
 654
 655	if (!sched_clock_stable)
 656		return;
 657
 658	local_irq_save(flags);
 659
 660	__this_cpu_write(cyc2ns_offset, 0);
 
 
 
 
 
 
 
 
 661	offset = cyc2ns_suspend - sched_clock();
 662
 663	for_each_possible_cpu(cpu)
 664		per_cpu(cyc2ns_offset, cpu) = offset;
 
 
 665
 666	local_irq_restore(flags);
 667}
 668
 669#ifdef CONFIG_CPU_FREQ
 670
 671/* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
 672 * changes.
 673 *
 674 * RED-PEN: On SMP we assume all CPUs run with the same frequency.  It's
 675 * not that important because current Opteron setups do not support
 676 * scaling on SMP anyroads.
 677 *
 678 * Should fix up last_tsc too. Currently gettimeofday in the
 679 * first tick after the change will be slightly wrong.
 680 */
 681
 682static unsigned int  ref_freq;
 683static unsigned long loops_per_jiffy_ref;
 684static unsigned long tsc_khz_ref;
 685
 686static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
 687				void *data)
 688{
 689	struct cpufreq_freqs *freq = data;
 690	unsigned long *lpj;
 691
 692	if (cpu_has(&cpu_data(freq->cpu), X86_FEATURE_CONSTANT_TSC))
 
 693		return 0;
 694
 695	lpj = &boot_cpu_data.loops_per_jiffy;
 696#ifdef CONFIG_SMP
 697	if (!(freq->flags & CPUFREQ_CONST_LOOPS))
 698		lpj = &cpu_data(freq->cpu).loops_per_jiffy;
 699#endif
 700
 701	if (!ref_freq) {
 702		ref_freq = freq->old;
 703		loops_per_jiffy_ref = *lpj;
 704		tsc_khz_ref = tsc_khz;
 705	}
 
 706	if ((val == CPUFREQ_PRECHANGE  && freq->old < freq->new) ||
 707			(val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
 708			(val == CPUFREQ_RESUMECHANGE)) {
 709		*lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
 710
 711		tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
 712		if (!(freq->flags & CPUFREQ_CONST_LOOPS))
 713			mark_tsc_unstable("cpufreq changes");
 714	}
 715
 716	set_cyc2ns_scale(tsc_khz, freq->cpu);
 
 717
 718	return 0;
 719}
 720
 721static struct notifier_block time_cpufreq_notifier_block = {
 722	.notifier_call  = time_cpufreq_notifier
 723};
 724
 725static int __init cpufreq_tsc(void)
 726{
 727	if (!cpu_has_tsc)
 728		return 0;
 729	if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
 730		return 0;
 731	cpufreq_register_notifier(&time_cpufreq_notifier_block,
 732				CPUFREQ_TRANSITION_NOTIFIER);
 733	return 0;
 734}
 735
 736core_initcall(cpufreq_tsc);
 737
 738#endif /* CONFIG_CPU_FREQ */
 739
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 740/* clocksource code */
 741
 742static struct clocksource clocksource_tsc;
 
 
 
 743
 744/*
 745 * We compare the TSC to the cycle_last value in the clocksource
 746 * structure to avoid a nasty time-warp. This can be observed in a
 747 * very small window right after one CPU updated cycle_last under
 748 * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
 749 * is smaller than the cycle_last reference value due to a TSC which
 750 * is slighty behind. This delta is nowhere else observable, but in
 751 * that case it results in a forward time jump in the range of hours
 752 * due to the unsigned delta calculation of the time keeping core
 753 * code, which is necessary to support wrapping clocksources like pm
 754 * timer.
 
 
 
 
 755 */
 756static cycle_t read_tsc(struct clocksource *cs)
 757{
 758	cycle_t ret = (cycle_t)get_cycles();
 
 
 
 
 
 
 
 
 
 
 
 
 
 759
 760	return ret >= clocksource_tsc.cycle_last ?
 761		ret : clocksource_tsc.cycle_last;
 
 
 
 
 
 762}
 763
 764static void resume_tsc(struct clocksource *cs)
 765{
 766	clocksource_tsc.cycle_last = 0;
 
 767}
 768
 769static struct clocksource clocksource_tsc = {
 770	.name                   = "tsc",
 771	.rating                 = 300,
 772	.read                   = read_tsc,
 773	.resume			= resume_tsc,
 774	.mask                   = CLOCKSOURCE_MASK(64),
 775	.flags                  = CLOCK_SOURCE_IS_CONTINUOUS |
 
 
 
 776				  CLOCK_SOURCE_MUST_VERIFY,
 777#ifdef CONFIG_X86_64
 778	.archdata               = { .vclock_mode = VCLOCK_TSC },
 779#endif
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 780};
 781
 782void mark_tsc_unstable(char *reason)
 783{
 784	if (!tsc_unstable) {
 785		tsc_unstable = 1;
 786		sched_clock_stable = 0;
 787		disable_sched_clock_irqtime();
 788		printk(KERN_INFO "Marking TSC unstable due to %s\n", reason);
 789		/* Change only the rating, when not registered */
 790		if (clocksource_tsc.mult)
 791			clocksource_mark_unstable(&clocksource_tsc);
 792		else {
 793			clocksource_tsc.flags |= CLOCK_SOURCE_UNSTABLE;
 794			clocksource_tsc.rating = 0;
 795		}
 796	}
 797}
 798
 799EXPORT_SYMBOL_GPL(mark_tsc_unstable);
 800
 
 
 
 
 
 
 
 
 
 
 
 
 801static void __init check_system_tsc_reliable(void)
 802{
 803#ifdef CONFIG_MGEODE_LX
 804	/* RTSC counts during suspend */
 
 805#define RTSC_SUSP 0x100
 806	unsigned long res_low, res_high;
 807
 808	rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
 809	/* Geode_LX - the OLPC CPU has a very reliable TSC */
 810	if (res_low & RTSC_SUSP)
 811		tsc_clocksource_reliable = 1;
 
 812#endif
 813	if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE))
 814		tsc_clocksource_reliable = 1;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 815}
 816
 817/*
 818 * Make an educated guess if the TSC is trustworthy and synchronized
 819 * over all CPUs.
 820 */
 821__cpuinit int unsynchronized_tsc(void)
 822{
 823	if (!cpu_has_tsc || tsc_unstable)
 824		return 1;
 825
 826#ifdef CONFIG_SMP
 827	if (apic_is_clustered_box())
 828		return 1;
 829#endif
 830
 831	if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
 832		return 0;
 833
 834	if (tsc_clocksource_reliable)
 835		return 0;
 836	/*
 837	 * Intel systems are normally all synchronized.
 838	 * Exceptions must mark TSC as unstable:
 839	 */
 840	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
 841		/* assume multi socket systems are not synchronized: */
 842		if (num_possible_cpus() > 1)
 843			return 1;
 844	}
 845
 846	return 0;
 847}
 848
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 849
 850static void tsc_refine_calibration_work(struct work_struct *work);
 851static DECLARE_DELAYED_WORK(tsc_irqwork, tsc_refine_calibration_work);
 852/**
 853 * tsc_refine_calibration_work - Further refine tsc freq calibration
 854 * @work - ignored.
 855 *
 856 * This functions uses delayed work over a period of a
 857 * second to further refine the TSC freq value. Since this is
 858 * timer based, instead of loop based, we don't block the boot
 859 * process while this longer calibration is done.
 860 *
 861 * If there are any calibration anomalies (too many SMIs, etc),
 862 * or the refined calibration is off by 1% of the fast early
 863 * calibration, we throw out the new calibration and use the
 864 * early calibration.
 865 */
 866static void tsc_refine_calibration_work(struct work_struct *work)
 867{
 868	static u64 tsc_start = -1, ref_start;
 869	static int hpet;
 870	u64 tsc_stop, ref_stop, delta;
 871	unsigned long freq;
 
 872
 873	/* Don't bother refining TSC on unstable systems */
 874	if (check_tsc_unstable())
 875		goto out;
 876
 877	/*
 878	 * Since the work is started early in boot, we may be
 879	 * delayed the first time we expire. So set the workqueue
 880	 * again once we know timers are working.
 881	 */
 882	if (tsc_start == -1) {
 
 883		/*
 884		 * Only set hpet once, to avoid mixing hardware
 885		 * if the hpet becomes enabled later.
 886		 */
 887		hpet = is_hpet_enabled();
 888		schedule_delayed_work(&tsc_irqwork, HZ);
 889		tsc_start = tsc_read_refs(&ref_start, hpet);
 
 890		return;
 891	}
 892
 893	tsc_stop = tsc_read_refs(&ref_stop, hpet);
 894
 895	/* hpet or pmtimer available ? */
 896	if (ref_start == ref_stop)
 897		goto out;
 898
 899	/* Check, whether the sampling was disturbed by an SMI */
 900	if (tsc_start == ULLONG_MAX || tsc_stop == ULLONG_MAX)
 901		goto out;
 902
 903	delta = tsc_stop - tsc_start;
 904	delta *= 1000000LL;
 905	if (hpet)
 906		freq = calc_hpet_ref(delta, ref_start, ref_stop);
 907	else
 908		freq = calc_pmtimer_ref(delta, ref_start, ref_stop);
 909
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 910	/* Make sure we're within 1% */
 911	if (abs(tsc_khz - freq) > tsc_khz/100)
 912		goto out;
 913
 914	tsc_khz = freq;
 915	printk(KERN_INFO "Refined TSC clocksource calibration: "
 916		"%lu.%03lu MHz.\n", (unsigned long)tsc_khz / 1000,
 917					(unsigned long)tsc_khz % 1000);
 
 
 
 
 
 
 
 918
 919out:
 
 
 
 
 
 920	clocksource_register_khz(&clocksource_tsc, tsc_khz);
 
 
 921}
 922
 923
 924static int __init init_tsc_clocksource(void)
 925{
 926	if (!cpu_has_tsc || tsc_disabled > 0 || !tsc_khz)
 927		return 0;
 928
 929	if (tsc_clocksource_reliable)
 930		clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
 931	/* lower the rating if we already know its unstable: */
 932	if (check_tsc_unstable()) {
 933		clocksource_tsc.rating = 0;
 934		clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS;
 935	}
 936
 
 
 
 937	/*
 938	 * Trust the results of the earlier calibration on systems
 939	 * exporting a reliable TSC.
 940	 */
 941	if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE)) {
 
 
 942		clocksource_register_khz(&clocksource_tsc, tsc_khz);
 943		return 0;
 
 
 
 944	}
 945
 946	schedule_delayed_work(&tsc_irqwork, 0);
 947	return 0;
 948}
 949/*
 950 * We use device_initcall here, to ensure we run after the hpet
 951 * is fully initialized, which may occur at fs_initcall time.
 952 */
 953device_initcall(init_tsc_clocksource);
 954
 955void __init tsc_init(void)
 956{
 957	u64 lpj;
 958	int cpu;
 
 
 
 
 
 
 
 
 
 
 
 
 959
 960	x86_init.timers.tsc_pre_init();
 
 
 
 
 
 
 
 
 961
 962	if (!cpu_has_tsc)
 963		return;
 964
 965	tsc_khz = x86_platform.calibrate_tsc();
 966	cpu_khz = tsc_khz;
 
 
 
 
 
 
 
 
 
 967
 968	if (!tsc_khz) {
 969		mark_tsc_unstable("could not calculate TSC khz");
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 970		return;
 971	}
 
 
 
 
 
 
 972
 973	printk("Detected %lu.%03lu MHz processor.\n",
 974			(unsigned long)cpu_khz / 1000,
 975			(unsigned long)cpu_khz % 1000);
 
 
 
 976
 977	/*
 978	 * Secondary CPUs do not run through tsc_init(), so set up
 979	 * all the scale factors for all CPUs, assuming the same
 980	 * speed as the bootup CPU. (cpufreq notifiers will fix this
 981	 * up if their speed diverges)
 982	 */
 983	for_each_possible_cpu(cpu)
 984		set_cyc2ns_scale(cpu_khz, cpu);
 985
 986	if (tsc_disabled > 0)
 987		return;
 
 
 
 
 
 
 
 988
 989	/* now allow native_sched_clock() to use rdtsc */
 990	tsc_disabled = 0;
 991
 992	if (!no_sched_irq_time)
 993		enable_sched_clock_irqtime();
 994
 995	lpj = ((u64)tsc_khz * 1000);
 996	do_div(lpj, HZ);
 997	lpj_fine = lpj;
 998
 999	use_tsc_delay();
1000
1001	if (unsynchronized_tsc())
1002		mark_tsc_unstable("TSCs unsynchronized");
 
 
1003
1004	check_system_tsc_reliable();
 
 
 
 
1005}
1006
1007#ifdef CONFIG_SMP
1008/*
1009 * If we have a constant TSC and are using the TSC for the delay loop,
1010 * we can skip clock calibration if another cpu in the same socket has already
1011 * been calibrated. This assumes that CONSTANT_TSC applies to all
1012 * cpus in the socket - this should be a safe assumption.
1013 */
1014unsigned long __cpuinit calibrate_delay_is_known(void)
1015{
1016	int i, cpu = smp_processor_id();
 
 
1017
1018	if (!tsc_disabled && !cpu_has(&cpu_data(cpu), X86_FEATURE_CONSTANT_TSC))
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1019		return 0;
1020
1021	for_each_online_cpu(i)
1022		if (cpu_data(i).phys_proc_id == cpu_data(cpu).phys_proc_id)
1023			return cpu_data(i).loops_per_jiffy;
1024	return 0;
1025}
1026#endif