1/*
  2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  3 *		http://www.samsung.com
  4 *
  5 * Copyright 2009 Samsung Electronics Co.
  6 *	Byungho Min <bhmin@samsung.com>
  7 *
  8 * Common Codes for S5PC100
  9 *
 10 * This program is free software; you can redistribute it and/or modify
 11 * it under the terms of the GNU General Public License version 2 as
 12 * published by the Free Software Foundation.
 13 */
 14
 15#include <linux/kernel.h>
 16#include <linux/types.h>
 17#include <linux/interrupt.h>
 18#include <linux/list.h>
 19#include <linux/timer.h>
 20#include <linux/init.h>
 21#include <linux/clk.h>
 22#include <linux/io.h>
 23#include <linux/device.h>
 24#include <linux/serial_core.h>
 25#include <linux/platform_device.h>
 26#include <linux/sched.h>
 27
 28#include <asm/irq.h>
 29#include <asm/proc-fns.h>
 30#include <asm/system_misc.h>
 31#include <asm/mach/arch.h>
 32#include <asm/mach/map.h>
 33#include <asm/mach/irq.h>
 34
 35#include <mach/map.h>
 36#include <mach/hardware.h>
 37#include <mach/regs-clock.h>
 38
 39#include <plat/cpu.h>
 40#include <plat/devs.h>
 41#include <plat/clock.h>
 42#include <plat/sdhci.h>
 43#include <plat/adc-core.h>
 44#include <plat/ata-core.h>
 45#include <plat/fb-core.h>
 46#include <plat/iic-core.h>
 47#include <plat/onenand-core.h>
 48#include <plat/regs-serial.h>
 49#include <plat/watchdog-reset.h>
 50
 51#include "common.h"
 52
 53static const char name_s5pc100[] = "S5PC100";
 54
 55static struct cpu_table cpu_ids[] __initdata = {
 56	{
 57		.idcode		= S5PC100_CPU_ID,
 58		.idmask		= S5PC100_CPU_MASK,
 59		.map_io		= s5pc100_map_io,
 60		.init_clocks	= s5pc100_init_clocks,
 61		.init_uarts	= s5pc100_init_uarts,
 62		.init		= s5pc100_init,
 63		.name		= name_s5pc100,
 64	},
 65};
 66
 67/* Initial IO mappings */
 68
 69static struct map_desc s5pc100_iodesc[] __initdata = {
 70	{
 71		.virtual	= (unsigned long)S5P_VA_CHIPID,
 72		.pfn		= __phys_to_pfn(S5PC100_PA_CHIPID),
 73		.length		= SZ_4K,
 74		.type		= MT_DEVICE,
 75	}, {
 76		.virtual	= (unsigned long)S3C_VA_SYS,
 77		.pfn		= __phys_to_pfn(S5PC100_PA_SYSCON),
 78		.length		= SZ_64K,
 79		.type		= MT_DEVICE,
 80	}, {
 81		.virtual	= (unsigned long)S3C_VA_TIMER,
 82		.pfn		= __phys_to_pfn(S5PC100_PA_TIMER),
 83		.length		= SZ_16K,
 84		.type		= MT_DEVICE,
 85	}, {
 86		.virtual	= (unsigned long)S3C_VA_WATCHDOG,
 87		.pfn		= __phys_to_pfn(S5PC100_PA_WATCHDOG),
 88		.length		= SZ_4K,
 89		.type		= MT_DEVICE,
 90	}, {
 91		.virtual	= (unsigned long)S5P_VA_SROMC,
 92		.pfn		= __phys_to_pfn(S5PC100_PA_SROMC),
 93		.length		= SZ_4K,
 94		.type		= MT_DEVICE,
 95	}, {
 96		.virtual	= (unsigned long)S5P_VA_SYSTIMER,
 97		.pfn		= __phys_to_pfn(S5PC100_PA_SYSTIMER),
 98		.length		= SZ_16K,
 99		.type		= MT_DEVICE,
100	}, {
101		.virtual	= (unsigned long)S5P_VA_GPIO,
102		.pfn		= __phys_to_pfn(S5PC100_PA_GPIO),
103		.length		= SZ_4K,
104		.type		= MT_DEVICE,
105	}, {
106		.virtual	= (unsigned long)VA_VIC0,
107		.pfn		= __phys_to_pfn(S5PC100_PA_VIC0),
108		.length		= SZ_16K,
109		.type		= MT_DEVICE,
110	}, {
111		.virtual	= (unsigned long)VA_VIC1,
112		.pfn		= __phys_to_pfn(S5PC100_PA_VIC1),
113		.length		= SZ_16K,
114		.type		= MT_DEVICE,
115	}, {
116		.virtual	= (unsigned long)VA_VIC2,
117		.pfn		= __phys_to_pfn(S5PC100_PA_VIC2),
118		.length		= SZ_16K,
119		.type		= MT_DEVICE,
120	}, {
121		.virtual	= (unsigned long)S3C_VA_UART,
122		.pfn		= __phys_to_pfn(S3C_PA_UART),
123		.length		= SZ_512K,
124		.type		= MT_DEVICE,
125	}, {
126		.virtual	= (unsigned long)S5PC100_VA_OTHERS,
127		.pfn		= __phys_to_pfn(S5PC100_PA_OTHERS),
128		.length		= SZ_4K,
129		.type		= MT_DEVICE,
130	}
131};
132
133/*
134 * s5pc100_map_io
135 *
136 * register the standard CPU IO areas
137 */
138
139void __init s5pc100_init_io(struct map_desc *mach_desc, int size)
140{
141	/* initialize the io descriptors we need for initialization */
142	iotable_init(s5pc100_iodesc, ARRAY_SIZE(s5pc100_iodesc));
143	if (mach_desc)
144		iotable_init(mach_desc, size);
145
146	/* detect cpu id and rev. */
147	s5p_init_cpu(S5P_VA_CHIPID);
148
149	s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
150}
151
152void __init s5pc100_map_io(void)
153{
154	/* initialise device information early */
155	s5pc100_default_sdhci0();
156	s5pc100_default_sdhci1();
157	s5pc100_default_sdhci2();
158
159	s3c_adc_setname("s3c64xx-adc");
160
161	/* the i2c devices are directly compatible with s3c2440 */
162	s3c_i2c0_setname("s3c2440-i2c");
163	s3c_i2c1_setname("s3c2440-i2c");
164
165	s3c_onenand_setname("s5pc100-onenand");
166	s3c_fb_setname("s5pc100-fb");
167	s3c_cfcon_setname("s5pc100-pata");
168}
169
170void __init s5pc100_init_clocks(int xtal)
171{
172	printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
173
174	s3c24xx_register_baseclocks(xtal);
175	s5p_register_clocks(xtal);
176	s5pc100_register_clocks();
177	s5pc100_setup_clocks();
178}
179
180void __init s5pc100_init_irq(void)
181{
182	u32 vic[] = {~0, ~0, ~0};
183
184	/* VIC0, VIC1, and VIC2 are fully populated. */
185	s5p_init_irq(vic, ARRAY_SIZE(vic));
186}
187
188static struct bus_type s5pc100_subsys = {
189	.name		= "s5pc100-core",
190	.dev_name	= "s5pc100-core",
191};
192
193static struct device s5pc100_dev = {
194	.bus	= &s5pc100_subsys,
195};
196
197static int __init s5pc100_core_init(void)
198{
199	return subsys_system_register(&s5pc100_subsys, NULL);
200}
201core_initcall(s5pc100_core_init);
202
203int __init s5pc100_init(void)
204{
205	printk(KERN_INFO "S5PC100: Initializing architecture\n");
206	return device_register(&s5pc100_dev);
207}
208
209/* uart registration process */
210
211void __init s5pc100_init_uarts(struct s3c2410_uartcfg *cfg, int no)
212{
213	s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
214}
215
216void s5pc100_restart(char mode, const char *cmd)
217{
218	if (mode != 's')
219		arch_wdt_reset();
220
221	soft_restart(0);
222}