1/*
   2 * Hardware modules present on the OMAP44xx chips
   3 *
   4 * Copyright (C) 2009-2012 Texas Instruments, Inc.
   5 * Copyright (C) 2009-2010 Nokia Corporation
   6 *
   7 * Paul Walmsley
   8 * Benoit Cousson
   9 *
  10 * This file is automatically generated from the OMAP hardware databases.
  11 * We respectfully ask that any modifications to this file be coordinated
  12 * with the public linux-omap@vger.kernel.org mailing list and the
  13 * authors above to ensure that the autogeneration scripts are kept
  14 * up-to-date with the file contents.
  15 *
  16 * This program is free software; you can redistribute it and/or modify
  17 * it under the terms of the GNU General Public License version 2 as
  18 * published by the Free Software Foundation.
  19 */
  20
  21#include <linux/io.h>
  22
  23#include <plat/omap_hwmod.h>
  24#include <plat/cpu.h>
  25#include <plat/i2c.h>
  26#include <plat/gpio.h>
  27#include <plat/dma.h>
  28#include <plat/mcspi.h>
  29#include <plat/mcbsp.h>
  30#include <plat/mmc.h>
  31#include <plat/dmtimer.h>
  32#include <plat/common.h>
  33
  34#include "omap_hwmod_common_data.h"
  35
  36#include "smartreflex.h"
  37#include "cm1_44xx.h"
  38#include "cm2_44xx.h"
  39#include "prm44xx.h"
  40#include "prm-regbits-44xx.h"
  41#include "wd_timer.h"
  42
  43/* Base offset for all OMAP4 interrupts external to MPUSS */
  44#define OMAP44XX_IRQ_GIC_START	32
  45
  46/* Base offset for all OMAP4 dma requests */
  47#define OMAP44XX_DMA_REQ_START	1
  48
  49/*
  50 * IP blocks
  51 */
  52
  53/*
  54 * 'c2c_target_fw' class
  55 * instance(s): c2c_target_fw
  56 */
  57static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
  58	.name	= "c2c_target_fw",
  59};
  60
  61/* c2c_target_fw */
  62static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
  63	.name		= "c2c_target_fw",
  64	.class		= &omap44xx_c2c_target_fw_hwmod_class,
  65	.clkdm_name	= "d2d_clkdm",
  66	.prcm = {
  67		.omap4 = {
  68			.clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
  69			.context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
  70		},
  71	},
  72};
  73
  74/*
  75 * 'dmm' class
  76 * instance(s): dmm
  77 */
  78static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  79	.name	= "dmm",
  80};
  81
  82/* dmm */
  83static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  84	{ .irq = 113 + OMAP44XX_IRQ_GIC_START },
  85	{ .irq = -1 }
  86};
  87
  88static struct omap_hwmod omap44xx_dmm_hwmod = {
  89	.name		= "dmm",
  90	.class		= &omap44xx_dmm_hwmod_class,
  91	.clkdm_name	= "l3_emif_clkdm",
  92	.mpu_irqs	= omap44xx_dmm_irqs,
  93	.prcm = {
  94		.omap4 = {
  95			.clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  96			.context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
  97		},
  98	},
  99};
 100
 101/*
 102 * 'emif_fw' class
 103 * instance(s): emif_fw
 104 */
 105static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 106	.name	= "emif_fw",
 107};
 108
 109/* emif_fw */
 110static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 111	.name		= "emif_fw",
 112	.class		= &omap44xx_emif_fw_hwmod_class,
 113	.clkdm_name	= "l3_emif_clkdm",
 114	.prcm = {
 115		.omap4 = {
 116			.clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
 117			.context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
 118		},
 119	},
 120};
 121
 122/*
 123 * 'l3' class
 124 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 125 */
 126static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 127	.name	= "l3",
 128};
 129
 130/* l3_instr */
 131static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 132	.name		= "l3_instr",
 133	.class		= &omap44xx_l3_hwmod_class,
 134	.clkdm_name	= "l3_instr_clkdm",
 135	.prcm = {
 136		.omap4 = {
 137			.clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
 138			.context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
 139			.modulemode   = MODULEMODE_HWCTRL,
 140		},
 141	},
 142};
 143
 144/* l3_main_1 */
 145static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
 146	{ .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
 147	{ .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
 148	{ .irq = -1 }
 149};
 150
 151static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 152	.name		= "l3_main_1",
 153	.class		= &omap44xx_l3_hwmod_class,
 154	.clkdm_name	= "l3_1_clkdm",
 155	.mpu_irqs	= omap44xx_l3_main_1_irqs,
 156	.prcm = {
 157		.omap4 = {
 158			.clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
 159			.context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
 160		},
 161	},
 162};
 163
 164/* l3_main_2 */
 165static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 166	.name		= "l3_main_2",
 167	.class		= &omap44xx_l3_hwmod_class,
 168	.clkdm_name	= "l3_2_clkdm",
 169	.prcm = {
 170		.omap4 = {
 171			.clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 172			.context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 173		},
 174	},
 175};
 176
 177/* l3_main_3 */
 178static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 179	.name		= "l3_main_3",
 180	.class		= &omap44xx_l3_hwmod_class,
 181	.clkdm_name	= "l3_instr_clkdm",
 182	.prcm = {
 183		.omap4 = {
 184			.clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 185			.context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 186			.modulemode   = MODULEMODE_HWCTRL,
 187		},
 188	},
 189};
 190
 191/*
 192 * 'l4' class
 193 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 194 */
 195static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 196	.name	= "l4",
 197};
 198
 199/* l4_abe */
 200static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 201	.name		= "l4_abe",
 202	.class		= &omap44xx_l4_hwmod_class,
 203	.clkdm_name	= "abe_clkdm",
 204	.prcm = {
 205		.omap4 = {
 206			.clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 207		},
 208	},
 209};
 210
 211/* l4_cfg */
 212static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 213	.name		= "l4_cfg",
 214	.class		= &omap44xx_l4_hwmod_class,
 215	.clkdm_name	= "l4_cfg_clkdm",
 216	.prcm = {
 217		.omap4 = {
 218			.clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 219			.context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 220		},
 221	},
 222};
 223
 224/* l4_per */
 225static struct omap_hwmod omap44xx_l4_per_hwmod = {
 226	.name		= "l4_per",
 227	.class		= &omap44xx_l4_hwmod_class,
 228	.clkdm_name	= "l4_per_clkdm",
 229	.prcm = {
 230		.omap4 = {
 231			.clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 232			.context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 233		},
 234	},
 235};
 236
 237/* l4_wkup */
 238static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 239	.name		= "l4_wkup",
 240	.class		= &omap44xx_l4_hwmod_class,
 241	.clkdm_name	= "l4_wkup_clkdm",
 242	.prcm = {
 243		.omap4 = {
 244			.clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 245			.context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 246		},
 247	},
 248};
 249
 250/*
 251 * 'mpu_bus' class
 252 * instance(s): mpu_private
 253 */
 254static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 255	.name	= "mpu_bus",
 256};
 257
 258/* mpu_private */
 259static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 260	.name		= "mpu_private",
 261	.class		= &omap44xx_mpu_bus_hwmod_class,
 262	.clkdm_name	= "mpuss_clkdm",
 263};
 264
 265/*
 266 * 'ocp_wp_noc' class
 267 * instance(s): ocp_wp_noc
 268 */
 269static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
 270	.name	= "ocp_wp_noc",
 271};
 272
 273/* ocp_wp_noc */
 274static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
 275	.name		= "ocp_wp_noc",
 276	.class		= &omap44xx_ocp_wp_noc_hwmod_class,
 277	.clkdm_name	= "l3_instr_clkdm",
 278	.prcm = {
 279		.omap4 = {
 280			.clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
 281			.context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
 282			.modulemode   = MODULEMODE_HWCTRL,
 283		},
 284	},
 285};
 286
 287/*
 288 * Modules omap_hwmod structures
 289 *
 290 * The following IPs are excluded for the moment because:
 291 * - They do not need an explicit SW control using omap_hwmod API.
 292 * - They still need to be validated with the driver
 293 *   properly adapted to omap_hwmod / omap_device
 294 *
 295 * usim
 296 */
 297
 298/*
 299 * 'aess' class
 300 * audio engine sub system
 301 */
 302
 303static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 304	.rev_offs	= 0x0000,
 305	.sysc_offs	= 0x0010,
 306	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 307	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 308			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 309			   MSTANDBY_SMART_WKUP),
 310	.sysc_fields	= &omap_hwmod_sysc_type2,
 311};
 312
 313static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 314	.name	= "aess",
 315	.sysc	= &omap44xx_aess_sysc,
 316};
 317
 318/* aess */
 319static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 320	{ .irq = 99 + OMAP44XX_IRQ_GIC_START },
 321	{ .irq = -1 }
 322};
 323
 324static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 325	{ .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 326	{ .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 327	{ .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 328	{ .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 329	{ .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 330	{ .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 331	{ .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 332	{ .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 333	{ .dma_req = -1 }
 334};
 335
 336static struct omap_hwmod omap44xx_aess_hwmod = {
 337	.name		= "aess",
 338	.class		= &omap44xx_aess_hwmod_class,
 339	.clkdm_name	= "abe_clkdm",
 340	.mpu_irqs	= omap44xx_aess_irqs,
 341	.sdma_reqs	= omap44xx_aess_sdma_reqs,
 342	.main_clk	= "aess_fck",
 343	.prcm = {
 344		.omap4 = {
 345			.clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 346			.context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 347			.modulemode   = MODULEMODE_SWCTRL,
 348		},
 349	},
 350};
 351
 352/*
 353 * 'c2c' class
 354 * chip 2 chip interface used to plug the ape soc (omap) with an external modem
 355 * soc
 356 */
 357
 358static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
 359	.name	= "c2c",
 360};
 361
 362/* c2c */
 363static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
 364	{ .irq = 88 + OMAP44XX_IRQ_GIC_START },
 365	{ .irq = -1 }
 366};
 367
 368static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
 369	{ .dma_req = 68 + OMAP44XX_DMA_REQ_START },
 370	{ .dma_req = -1 }
 371};
 372
 373static struct omap_hwmod omap44xx_c2c_hwmod = {
 374	.name		= "c2c",
 375	.class		= &omap44xx_c2c_hwmod_class,
 376	.clkdm_name	= "d2d_clkdm",
 377	.mpu_irqs	= omap44xx_c2c_irqs,
 378	.sdma_reqs	= omap44xx_c2c_sdma_reqs,
 379	.prcm = {
 380		.omap4 = {
 381			.clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
 382			.context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
 383		},
 384	},
 385};
 386
 387/*
 388 * 'counter' class
 389 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 390 */
 391
 392static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 393	.rev_offs	= 0x0000,
 394	.sysc_offs	= 0x0004,
 395	.sysc_flags	= SYSC_HAS_SIDLEMODE,
 396	.idlemodes	= (SIDLE_FORCE | SIDLE_NO),
 397	.sysc_fields	= &omap_hwmod_sysc_type1,
 398};
 399
 400static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 401	.name	= "counter",
 402	.sysc	= &omap44xx_counter_sysc,
 403};
 404
 405/* counter_32k */
 406static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 407	.name		= "counter_32k",
 408	.class		= &omap44xx_counter_hwmod_class,
 409	.clkdm_name	= "l4_wkup_clkdm",
 410	.flags		= HWMOD_SWSUP_SIDLE,
 411	.main_clk	= "sys_32k_ck",
 412	.prcm = {
 413		.omap4 = {
 414			.clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 415			.context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 416		},
 417	},
 418};
 419
 420/*
 421 * 'ctrl_module' class
 422 * attila core control module + core pad control module + wkup pad control
 423 * module + attila wkup control module
 424 */
 425
 426static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
 427	.rev_offs	= 0x0000,
 428	.sysc_offs	= 0x0010,
 429	.sysc_flags	= SYSC_HAS_SIDLEMODE,
 430	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 431			   SIDLE_SMART_WKUP),
 432	.sysc_fields	= &omap_hwmod_sysc_type2,
 433};
 434
 435static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 436	.name	= "ctrl_module",
 437	.sysc	= &omap44xx_ctrl_module_sysc,
 438};
 439
 440/* ctrl_module_core */
 441static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
 442	{ .irq = 8 + OMAP44XX_IRQ_GIC_START },
 443	{ .irq = -1 }
 444};
 445
 446static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
 447	.name		= "ctrl_module_core",
 448	.class		= &omap44xx_ctrl_module_hwmod_class,
 449	.clkdm_name	= "l4_cfg_clkdm",
 450	.mpu_irqs	= omap44xx_ctrl_module_core_irqs,
 451};
 452
 453/* ctrl_module_pad_core */
 454static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
 455	.name		= "ctrl_module_pad_core",
 456	.class		= &omap44xx_ctrl_module_hwmod_class,
 457	.clkdm_name	= "l4_cfg_clkdm",
 458};
 459
 460/* ctrl_module_wkup */
 461static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
 462	.name		= "ctrl_module_wkup",
 463	.class		= &omap44xx_ctrl_module_hwmod_class,
 464	.clkdm_name	= "l4_wkup_clkdm",
 465};
 466
 467/* ctrl_module_pad_wkup */
 468static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
 469	.name		= "ctrl_module_pad_wkup",
 470	.class		= &omap44xx_ctrl_module_hwmod_class,
 471	.clkdm_name	= "l4_wkup_clkdm",
 472};
 473
 474/*
 475 * 'debugss' class
 476 * debug and emulation sub system
 477 */
 478
 479static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
 480	.name	= "debugss",
 481};
 482
 483/* debugss */
 484static struct omap_hwmod omap44xx_debugss_hwmod = {
 485	.name		= "debugss",
 486	.class		= &omap44xx_debugss_hwmod_class,
 487	.clkdm_name	= "emu_sys_clkdm",
 488	.main_clk	= "trace_clk_div_ck",
 489	.prcm = {
 490		.omap4 = {
 491			.clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
 492			.context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
 493		},
 494	},
 495};
 496
 497/*
 498 * 'dma' class
 499 * dma controller for data exchange between memory to memory (i.e. internal or
 500 * external memory) and gp peripherals to memory or memory to gp peripherals
 501 */
 502
 503static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 504	.rev_offs	= 0x0000,
 505	.sysc_offs	= 0x002c,
 506	.syss_offs	= 0x0028,
 507	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 508			   SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 509			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 510			   SYSS_HAS_RESET_STATUS),
 511	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 512			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 513	.sysc_fields	= &omap_hwmod_sysc_type1,
 514};
 515
 516static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 517	.name	= "dma",
 518	.sysc	= &omap44xx_dma_sysc,
 519};
 520
 521/* dma dev_attr */
 522static struct omap_dma_dev_attr dma_dev_attr = {
 523	.dev_caps	= RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 524			  IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 525	.lch_count	= 32,
 526};
 527
 528/* dma_system */
 529static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 530	{ .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 531	{ .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 532	{ .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 533	{ .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 534	{ .irq = -1 }
 535};
 536
 537static struct omap_hwmod omap44xx_dma_system_hwmod = {
 538	.name		= "dma_system",
 539	.class		= &omap44xx_dma_hwmod_class,
 540	.clkdm_name	= "l3_dma_clkdm",
 541	.mpu_irqs	= omap44xx_dma_system_irqs,
 542	.main_clk	= "l3_div_ck",
 543	.prcm = {
 544		.omap4 = {
 545			.clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 546			.context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 547		},
 548	},
 549	.dev_attr	= &dma_dev_attr,
 550};
 551
 552/*
 553 * 'dmic' class
 554 * digital microphone controller
 555 */
 556
 557static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 558	.rev_offs	= 0x0000,
 559	.sysc_offs	= 0x0010,
 560	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 561			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 562	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 563			   SIDLE_SMART_WKUP),
 564	.sysc_fields	= &omap_hwmod_sysc_type2,
 565};
 566
 567static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 568	.name	= "dmic",
 569	.sysc	= &omap44xx_dmic_sysc,
 570};
 571
 572/* dmic */
 573static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
 574	{ .irq = 114 + OMAP44XX_IRQ_GIC_START },
 575	{ .irq = -1 }
 576};
 577
 578static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
 579	{ .dma_req = 66 + OMAP44XX_DMA_REQ_START },
 580	{ .dma_req = -1 }
 581};
 582
 583static struct omap_hwmod omap44xx_dmic_hwmod = {
 584	.name		= "dmic",
 585	.class		= &omap44xx_dmic_hwmod_class,
 586	.clkdm_name	= "abe_clkdm",
 587	.mpu_irqs	= omap44xx_dmic_irqs,
 588	.sdma_reqs	= omap44xx_dmic_sdma_reqs,
 589	.main_clk	= "dmic_fck",
 590	.prcm = {
 591		.omap4 = {
 592			.clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
 593			.context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
 594			.modulemode   = MODULEMODE_SWCTRL,
 595		},
 596	},
 597};
 598
 599/*
 600 * 'dsp' class
 601 * dsp sub-system
 602 */
 603
 604static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 605	.name	= "dsp",
 606};
 607
 608/* dsp */
 609static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
 610	{ .irq = 28 + OMAP44XX_IRQ_GIC_START },
 611	{ .irq = -1 }
 612};
 613
 614static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 615	{ .name = "dsp", .rst_shift = 0 },
 616	{ .name = "mmu_cache", .rst_shift = 1 },
 617};
 618
 619static struct omap_hwmod omap44xx_dsp_hwmod = {
 620	.name		= "dsp",
 621	.class		= &omap44xx_dsp_hwmod_class,
 622	.clkdm_name	= "tesla_clkdm",
 623	.mpu_irqs	= omap44xx_dsp_irqs,
 624	.rst_lines	= omap44xx_dsp_resets,
 625	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_dsp_resets),
 626	.main_clk	= "dsp_fck",
 627	.prcm = {
 628		.omap4 = {
 629			.clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
 630			.rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
 631			.context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
 632			.modulemode   = MODULEMODE_HWCTRL,
 633		},
 634	},
 635};
 636
 637/*
 638 * 'dss' class
 639 * display sub-system
 640 */
 641
 642static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
 643	.rev_offs	= 0x0000,
 644	.syss_offs	= 0x0014,
 645	.sysc_flags	= SYSS_HAS_RESET_STATUS,
 646};
 647
 648static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 649	.name	= "dss",
 650	.sysc	= &omap44xx_dss_sysc,
 651	.reset	= omap_dss_reset,
 652};
 653
 654/* dss */
 655static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 656	{ .role = "sys_clk", .clk = "dss_sys_clk" },
 657	{ .role = "tv_clk", .clk = "dss_tv_clk" },
 658	{ .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 659};
 660
 661static struct omap_hwmod omap44xx_dss_hwmod = {
 662	.name		= "dss_core",
 663	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 664	.class		= &omap44xx_dss_hwmod_class,
 665	.clkdm_name	= "l3_dss_clkdm",
 666	.main_clk	= "dss_dss_clk",
 667	.prcm = {
 668		.omap4 = {
 669			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 670			.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 671		},
 672	},
 673	.opt_clks	= dss_opt_clks,
 674	.opt_clks_cnt	= ARRAY_SIZE(dss_opt_clks),
 675};
 676
 677/*
 678 * 'dispc' class
 679 * display controller
 680 */
 681
 682static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
 683	.rev_offs	= 0x0000,
 684	.sysc_offs	= 0x0010,
 685	.syss_offs	= 0x0014,
 686	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 687			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 688			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 689			   SYSS_HAS_RESET_STATUS),
 690	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 691			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 692	.sysc_fields	= &omap_hwmod_sysc_type1,
 693};
 694
 695static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 696	.name	= "dispc",
 697	.sysc	= &omap44xx_dispc_sysc,
 698};
 699
 700/* dss_dispc */
 701static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
 702	{ .irq = 25 + OMAP44XX_IRQ_GIC_START },
 703	{ .irq = -1 }
 704};
 705
 706static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
 707	{ .dma_req = 5 + OMAP44XX_DMA_REQ_START },
 708	{ .dma_req = -1 }
 709};
 710
 711static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
 712	.manager_count		= 3,
 713	.has_framedonetv_irq	= 1
 714};
 715
 716static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 717	.name		= "dss_dispc",
 718	.class		= &omap44xx_dispc_hwmod_class,
 719	.clkdm_name	= "l3_dss_clkdm",
 720	.mpu_irqs	= omap44xx_dss_dispc_irqs,
 721	.sdma_reqs	= omap44xx_dss_dispc_sdma_reqs,
 722	.main_clk	= "dss_dss_clk",
 723	.prcm = {
 724		.omap4 = {
 725			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 726			.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 727		},
 728	},
 729	.dev_attr	= &omap44xx_dss_dispc_dev_attr
 730};
 731
 732/*
 733 * 'dsi' class
 734 * display serial interface controller
 735 */
 736
 737static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
 738	.rev_offs	= 0x0000,
 739	.sysc_offs	= 0x0010,
 740	.syss_offs	= 0x0014,
 741	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 742			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 743			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 744	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 745	.sysc_fields	= &omap_hwmod_sysc_type1,
 746};
 747
 748static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
 749	.name	= "dsi",
 750	.sysc	= &omap44xx_dsi_sysc,
 751};
 752
 753/* dss_dsi1 */
 754static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
 755	{ .irq = 53 + OMAP44XX_IRQ_GIC_START },
 756	{ .irq = -1 }
 757};
 758
 759static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
 760	{ .dma_req = 74 + OMAP44XX_DMA_REQ_START },
 761	{ .dma_req = -1 }
 762};
 763
 764static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 765	{ .role = "sys_clk", .clk = "dss_sys_clk" },
 766};
 767
 768static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
 769	.name		= "dss_dsi1",
 770	.class		= &omap44xx_dsi_hwmod_class,
 771	.clkdm_name	= "l3_dss_clkdm",
 772	.mpu_irqs	= omap44xx_dss_dsi1_irqs,
 773	.sdma_reqs	= omap44xx_dss_dsi1_sdma_reqs,
 774	.main_clk	= "dss_dss_clk",
 775	.prcm = {
 776		.omap4 = {
 777			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 778			.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 779		},
 780	},
 781	.opt_clks	= dss_dsi1_opt_clks,
 782	.opt_clks_cnt	= ARRAY_SIZE(dss_dsi1_opt_clks),
 783};
 784
 785/* dss_dsi2 */
 786static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
 787	{ .irq = 84 + OMAP44XX_IRQ_GIC_START },
 788	{ .irq = -1 }
 789};
 790
 791static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
 792	{ .dma_req = 83 + OMAP44XX_DMA_REQ_START },
 793	{ .dma_req = -1 }
 794};
 795
 796static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
 797	{ .role = "sys_clk", .clk = "dss_sys_clk" },
 798};
 799
 800static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
 801	.name		= "dss_dsi2",
 802	.class		= &omap44xx_dsi_hwmod_class,
 803	.clkdm_name	= "l3_dss_clkdm",
 804	.mpu_irqs	= omap44xx_dss_dsi2_irqs,
 805	.sdma_reqs	= omap44xx_dss_dsi2_sdma_reqs,
 806	.main_clk	= "dss_dss_clk",
 807	.prcm = {
 808		.omap4 = {
 809			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 810			.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 811		},
 812	},
 813	.opt_clks	= dss_dsi2_opt_clks,
 814	.opt_clks_cnt	= ARRAY_SIZE(dss_dsi2_opt_clks),
 815};
 816
 817/*
 818 * 'hdmi' class
 819 * hdmi controller
 820 */
 821
 822static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
 823	.rev_offs	= 0x0000,
 824	.sysc_offs	= 0x0010,
 825	.sysc_flags	= (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 826			   SYSC_HAS_SOFTRESET),
 827	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 828			   SIDLE_SMART_WKUP),
 829	.sysc_fields	= &omap_hwmod_sysc_type2,
 830};
 831
 832static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
 833	.name	= "hdmi",
 834	.sysc	= &omap44xx_hdmi_sysc,
 835};
 836
 837/* dss_hdmi */
 838static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
 839	{ .irq = 101 + OMAP44XX_IRQ_GIC_START },
 840	{ .irq = -1 }
 841};
 842
 843static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
 844	{ .dma_req = 75 + OMAP44XX_DMA_REQ_START },
 845	{ .dma_req = -1 }
 846};
 847
 848static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 849	{ .role = "sys_clk", .clk = "dss_sys_clk" },
 850};
 851
 852static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
 853	.name		= "dss_hdmi",
 854	.class		= &omap44xx_hdmi_hwmod_class,
 855	.clkdm_name	= "l3_dss_clkdm",
 856	/*
 857	 * HDMI audio requires to use no-idle mode. Hence,
 858	 * set idle mode by software.
 859	 */
 860	.flags		= HWMOD_SWSUP_SIDLE,
 861	.mpu_irqs	= omap44xx_dss_hdmi_irqs,
 862	.sdma_reqs	= omap44xx_dss_hdmi_sdma_reqs,
 863	.main_clk	= "dss_48mhz_clk",
 864	.prcm = {
 865		.omap4 = {
 866			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 867			.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 868		},
 869	},
 870	.opt_clks	= dss_hdmi_opt_clks,
 871	.opt_clks_cnt	= ARRAY_SIZE(dss_hdmi_opt_clks),
 872};
 873
 874/*
 875 * 'rfbi' class
 876 * remote frame buffer interface
 877 */
 878
 879static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
 880	.rev_offs	= 0x0000,
 881	.sysc_offs	= 0x0010,
 882	.syss_offs	= 0x0014,
 883	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 884			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 885	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 886	.sysc_fields	= &omap_hwmod_sysc_type1,
 887};
 888
 889static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
 890	.name	= "rfbi",
 891	.sysc	= &omap44xx_rfbi_sysc,
 892};
 893
 894/* dss_rfbi */
 895static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
 896	{ .dma_req = 13 + OMAP44XX_DMA_REQ_START },
 897	{ .dma_req = -1 }
 898};
 899
 900static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 901	{ .role = "ick", .clk = "dss_fck" },
 902};
 903
 904static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
 905	.name		= "dss_rfbi",
 906	.class		= &omap44xx_rfbi_hwmod_class,
 907	.clkdm_name	= "l3_dss_clkdm",
 908	.sdma_reqs	= omap44xx_dss_rfbi_sdma_reqs,
 909	.main_clk	= "dss_dss_clk",
 910	.prcm = {
 911		.omap4 = {
 912			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 913			.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 914		},
 915	},
 916	.opt_clks	= dss_rfbi_opt_clks,
 917	.opt_clks_cnt	= ARRAY_SIZE(dss_rfbi_opt_clks),
 918};
 919
 920/*
 921 * 'venc' class
 922 * video encoder
 923 */
 924
 925static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
 926	.name	= "venc",
 927};
 928
 929/* dss_venc */
 930static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 931	.name		= "dss_venc",
 932	.class		= &omap44xx_venc_hwmod_class,
 933	.clkdm_name	= "l3_dss_clkdm",
 934	.main_clk	= "dss_tv_clk",
 935	.prcm = {
 936		.omap4 = {
 937			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 938			.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 939		},
 940	},
 941};
 942
 943/*
 944 * 'elm' class
 945 * bch error location module
 946 */
 947
 948static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
 949	.rev_offs	= 0x0000,
 950	.sysc_offs	= 0x0010,
 951	.syss_offs	= 0x0014,
 952	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 953			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 954			   SYSS_HAS_RESET_STATUS),
 955	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 956	.sysc_fields	= &omap_hwmod_sysc_type1,
 957};
 958
 959static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
 960	.name	= "elm",
 961	.sysc	= &omap44xx_elm_sysc,
 962};
 963
 964/* elm */
 965static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
 966	{ .irq = 4 + OMAP44XX_IRQ_GIC_START },
 967	{ .irq = -1 }
 968};
 969
 970static struct omap_hwmod omap44xx_elm_hwmod = {
 971	.name		= "elm",
 972	.class		= &omap44xx_elm_hwmod_class,
 973	.clkdm_name	= "l4_per_clkdm",
 974	.mpu_irqs	= omap44xx_elm_irqs,
 975	.prcm = {
 976		.omap4 = {
 977			.clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
 978			.context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
 979		},
 980	},
 981};
 982
 983/*
 984 * 'emif' class
 985 * external memory interface no1
 986 */
 987
 988static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
 989	.rev_offs	= 0x0000,
 990};
 991
 992static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
 993	.name	= "emif",
 994	.sysc	= &omap44xx_emif_sysc,
 995};
 996
 997/* emif1 */
 998static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
 999	{ .irq = 110 + OMAP44XX_IRQ_GIC_START },
1000	{ .irq = -1 }
1001};
1002
1003static struct omap_hwmod omap44xx_emif1_hwmod = {
1004	.name		= "emif1",
1005	.class		= &omap44xx_emif_hwmod_class,
1006	.clkdm_name	= "l3_emif_clkdm",
1007	.flags		= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1008	.mpu_irqs	= omap44xx_emif1_irqs,
1009	.main_clk	= "ddrphy_ck",
1010	.prcm = {
1011		.omap4 = {
1012			.clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
1013			.context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
1014			.modulemode   = MODULEMODE_HWCTRL,
1015		},
1016	},
1017};
1018
1019/* emif2 */
1020static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
1021	{ .irq = 111 + OMAP44XX_IRQ_GIC_START },
1022	{ .irq = -1 }
1023};
1024
1025static struct omap_hwmod omap44xx_emif2_hwmod = {
1026	.name		= "emif2",
1027	.class		= &omap44xx_emif_hwmod_class,
1028	.clkdm_name	= "l3_emif_clkdm",
1029	.flags		= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1030	.mpu_irqs	= omap44xx_emif2_irqs,
1031	.main_clk	= "ddrphy_ck",
1032	.prcm = {
1033		.omap4 = {
1034			.clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
1035			.context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
1036			.modulemode   = MODULEMODE_HWCTRL,
1037		},
1038	},
1039};
1040
1041/*
1042 * 'fdif' class
1043 * face detection hw accelerator module
1044 */
1045
1046static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1047	.rev_offs	= 0x0000,
1048	.sysc_offs	= 0x0010,
1049	/*
1050	 * FDIF needs 100 OCP clk cycles delay after a softreset before
1051	 * accessing sysconfig again.
1052	 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1053	 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1054	 *
1055	 * TODO: Indicate errata when available.
1056	 */
1057	.srst_udelay	= 2,
1058	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1059			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1060	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1061			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1062	.sysc_fields	= &omap_hwmod_sysc_type2,
1063};
1064
1065static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1066	.name	= "fdif",
1067	.sysc	= &omap44xx_fdif_sysc,
1068};
1069
1070/* fdif */
1071static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
1072	{ .irq = 69 + OMAP44XX_IRQ_GIC_START },
1073	{ .irq = -1 }
1074};
1075
1076static struct omap_hwmod omap44xx_fdif_hwmod = {
1077	.name		= "fdif",
1078	.class		= &omap44xx_fdif_hwmod_class,
1079	.clkdm_name	= "iss_clkdm",
1080	.mpu_irqs	= omap44xx_fdif_irqs,
1081	.main_clk	= "fdif_fck",
1082	.prcm = {
1083		.omap4 = {
1084			.clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1085			.context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1086			.modulemode   = MODULEMODE_SWCTRL,
1087		},
1088	},
1089};
1090
1091/*
1092 * 'gpio' class
1093 * general purpose io module
1094 */
1095
1096static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1097	.rev_offs	= 0x0000,
1098	.sysc_offs	= 0x0010,
1099	.syss_offs	= 0x0114,
1100	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1101			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1102			   SYSS_HAS_RESET_STATUS),
1103	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1104			   SIDLE_SMART_WKUP),
1105	.sysc_fields	= &omap_hwmod_sysc_type1,
1106};
1107
1108static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1109	.name	= "gpio",
1110	.sysc	= &omap44xx_gpio_sysc,
1111	.rev	= 2,
1112};
1113
1114/* gpio dev_attr */
1115static struct omap_gpio_dev_attr gpio_dev_attr = {
1116	.bank_width	= 32,
1117	.dbck_flag	= true,
1118};
1119
1120/* gpio1 */
1121static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1122	{ .irq = 29 + OMAP44XX_IRQ_GIC_START },
1123	{ .irq = -1 }
1124};
1125
1126static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1127	{ .role = "dbclk", .clk = "gpio1_dbclk" },
1128};
1129
1130static struct omap_hwmod omap44xx_gpio1_hwmod = {
1131	.name		= "gpio1",
1132	.class		= &omap44xx_gpio_hwmod_class,
1133	.clkdm_name	= "l4_wkup_clkdm",
1134	.mpu_irqs	= omap44xx_gpio1_irqs,
1135	.main_clk	= "gpio1_ick",
1136	.prcm = {
1137		.omap4 = {
1138			.clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1139			.context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1140			.modulemode   = MODULEMODE_HWCTRL,
1141		},
1142	},
1143	.opt_clks	= gpio1_opt_clks,
1144	.opt_clks_cnt	= ARRAY_SIZE(gpio1_opt_clks),
1145	.dev_attr	= &gpio_dev_attr,
1146};
1147
1148/* gpio2 */
1149static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1150	{ .irq = 30 + OMAP44XX_IRQ_GIC_START },
1151	{ .irq = -1 }
1152};
1153
1154static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1155	{ .role = "dbclk", .clk = "gpio2_dbclk" },
1156};
1157
1158static struct omap_hwmod omap44xx_gpio2_hwmod = {
1159	.name		= "gpio2",
1160	.class		= &omap44xx_gpio_hwmod_class,
1161	.clkdm_name	= "l4_per_clkdm",
1162	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1163	.mpu_irqs	= omap44xx_gpio2_irqs,
1164	.main_clk	= "gpio2_ick",
1165	.prcm = {
1166		.omap4 = {
1167			.clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1168			.context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1169			.modulemode   = MODULEMODE_HWCTRL,
1170		},
1171	},
1172	.opt_clks	= gpio2_opt_clks,
1173	.opt_clks_cnt	= ARRAY_SIZE(gpio2_opt_clks),
1174	.dev_attr	= &gpio_dev_attr,
1175};
1176
1177/* gpio3 */
1178static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1179	{ .irq = 31 + OMAP44XX_IRQ_GIC_START },
1180	{ .irq = -1 }
1181};
1182
1183static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1184	{ .role = "dbclk", .clk = "gpio3_dbclk" },
1185};
1186
1187static struct omap_hwmod omap44xx_gpio3_hwmod = {
1188	.name		= "gpio3",
1189	.class		= &omap44xx_gpio_hwmod_class,
1190	.clkdm_name	= "l4_per_clkdm",
1191	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1192	.mpu_irqs	= omap44xx_gpio3_irqs,
1193	.main_clk	= "gpio3_ick",
1194	.prcm = {
1195		.omap4 = {
1196			.clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1197			.context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1198			.modulemode   = MODULEMODE_HWCTRL,
1199		},
1200	},
1201	.opt_clks	= gpio3_opt_clks,
1202	.opt_clks_cnt	= ARRAY_SIZE(gpio3_opt_clks),
1203	.dev_attr	= &gpio_dev_attr,
1204};
1205
1206/* gpio4 */
1207static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1208	{ .irq = 32 + OMAP44XX_IRQ_GIC_START },
1209	{ .irq = -1 }
1210};
1211
1212static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1213	{ .role = "dbclk", .clk = "gpio4_dbclk" },
1214};
1215
1216static struct omap_hwmod omap44xx_gpio4_hwmod = {
1217	.name		= "gpio4",
1218	.class		= &omap44xx_gpio_hwmod_class,
1219	.clkdm_name	= "l4_per_clkdm",
1220	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1221	.mpu_irqs	= omap44xx_gpio4_irqs,
1222	.main_clk	= "gpio4_ick",
1223	.prcm = {
1224		.omap4 = {
1225			.clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1226			.context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1227			.modulemode   = MODULEMODE_HWCTRL,
1228		},
1229	},
1230	.opt_clks	= gpio4_opt_clks,
1231	.opt_clks_cnt	= ARRAY_SIZE(gpio4_opt_clks),
1232	.dev_attr	= &gpio_dev_attr,
1233};
1234
1235/* gpio5 */
1236static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1237	{ .irq = 33 + OMAP44XX_IRQ_GIC_START },
1238	{ .irq = -1 }
1239};
1240
1241static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1242	{ .role = "dbclk", .clk = "gpio5_dbclk" },
1243};
1244
1245static struct omap_hwmod omap44xx_gpio5_hwmod = {
1246	.name		= "gpio5",
1247	.class		= &omap44xx_gpio_hwmod_class,
1248	.clkdm_name	= "l4_per_clkdm",
1249	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1250	.mpu_irqs	= omap44xx_gpio5_irqs,
1251	.main_clk	= "gpio5_ick",
1252	.prcm = {
1253		.omap4 = {
1254			.clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1255			.context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1256			.modulemode   = MODULEMODE_HWCTRL,
1257		},
1258	},
1259	.opt_clks	= gpio5_opt_clks,
1260	.opt_clks_cnt	= ARRAY_SIZE(gpio5_opt_clks),
1261	.dev_attr	= &gpio_dev_attr,
1262};
1263
1264/* gpio6 */
1265static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1266	{ .irq = 34 + OMAP44XX_IRQ_GIC_START },
1267	{ .irq = -1 }
1268};
1269
1270static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1271	{ .role = "dbclk", .clk = "gpio6_dbclk" },
1272};
1273
1274static struct omap_hwmod omap44xx_gpio6_hwmod = {
1275	.name		= "gpio6",
1276	.class		= &omap44xx_gpio_hwmod_class,
1277	.clkdm_name	= "l4_per_clkdm",
1278	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1279	.mpu_irqs	= omap44xx_gpio6_irqs,
1280	.main_clk	= "gpio6_ick",
1281	.prcm = {
1282		.omap4 = {
1283			.clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1284			.context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1285			.modulemode   = MODULEMODE_HWCTRL,
1286		},
1287	},
1288	.opt_clks	= gpio6_opt_clks,
1289	.opt_clks_cnt	= ARRAY_SIZE(gpio6_opt_clks),
1290	.dev_attr	= &gpio_dev_attr,
1291};
1292
1293/*
1294 * 'gpmc' class
1295 * general purpose memory controller
1296 */
1297
1298static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1299	.rev_offs	= 0x0000,
1300	.sysc_offs	= 0x0010,
1301	.syss_offs	= 0x0014,
1302	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1303			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1304	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1305	.sysc_fields	= &omap_hwmod_sysc_type1,
1306};
1307
1308static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1309	.name	= "gpmc",
1310	.sysc	= &omap44xx_gpmc_sysc,
1311};
1312
1313/* gpmc */
1314static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
1315	{ .irq = 20 + OMAP44XX_IRQ_GIC_START },
1316	{ .irq = -1 }
1317};
1318
1319static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
1320	{ .dma_req = 3 + OMAP44XX_DMA_REQ_START },
1321	{ .dma_req = -1 }
1322};
1323
1324static struct omap_hwmod omap44xx_gpmc_hwmod = {
1325	.name		= "gpmc",
1326	.class		= &omap44xx_gpmc_hwmod_class,
1327	.clkdm_name	= "l3_2_clkdm",
1328	.flags		= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1329	.mpu_irqs	= omap44xx_gpmc_irqs,
1330	.sdma_reqs	= omap44xx_gpmc_sdma_reqs,
1331	.prcm = {
1332		.omap4 = {
1333			.clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1334			.context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1335			.modulemode   = MODULEMODE_HWCTRL,
1336		},
1337	},
1338};
1339
1340/*
1341 * 'gpu' class
1342 * 2d/3d graphics accelerator
1343 */
1344
1345static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1346	.rev_offs	= 0x1fc00,
1347	.sysc_offs	= 0x1fc10,
1348	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1349	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1350			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1351			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1352	.sysc_fields	= &omap_hwmod_sysc_type2,
1353};
1354
1355static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1356	.name	= "gpu",
1357	.sysc	= &omap44xx_gpu_sysc,
1358};
1359
1360/* gpu */
1361static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
1362	{ .irq = 21 + OMAP44XX_IRQ_GIC_START },
1363	{ .irq = -1 }
1364};
1365
1366static struct omap_hwmod omap44xx_gpu_hwmod = {
1367	.name		= "gpu",
1368	.class		= &omap44xx_gpu_hwmod_class,
1369	.clkdm_name	= "l3_gfx_clkdm",
1370	.mpu_irqs	= omap44xx_gpu_irqs,
1371	.main_clk	= "gpu_fck",
1372	.prcm = {
1373		.omap4 = {
1374			.clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1375			.context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1376			.modulemode   = MODULEMODE_SWCTRL,
1377		},
1378	},
1379};
1380
1381/*
1382 * 'hdq1w' class
1383 * hdq / 1-wire serial interface controller
1384 */
1385
1386static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1387	.rev_offs	= 0x0000,
1388	.sysc_offs	= 0x0014,
1389	.syss_offs	= 0x0018,
1390	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1391			   SYSS_HAS_RESET_STATUS),
1392	.sysc_fields	= &omap_hwmod_sysc_type1,
1393};
1394
1395static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1396	.name	= "hdq1w",
1397	.sysc	= &omap44xx_hdq1w_sysc,
1398};
1399
1400/* hdq1w */
1401static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
1402	{ .irq = 58 + OMAP44XX_IRQ_GIC_START },
1403	{ .irq = -1 }
1404};
1405
1406static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1407	.name		= "hdq1w",
1408	.class		= &omap44xx_hdq1w_hwmod_class,
1409	.clkdm_name	= "l4_per_clkdm",
1410	.flags		= HWMOD_INIT_NO_RESET, /* XXX temporary */
1411	.mpu_irqs	= omap44xx_hdq1w_irqs,
1412	.main_clk	= "hdq1w_fck",
1413	.prcm = {
1414		.omap4 = {
1415			.clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1416			.context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1417			.modulemode   = MODULEMODE_SWCTRL,
1418		},
1419	},
1420};
1421
1422/*
1423 * 'hsi' class
1424 * mipi high-speed synchronous serial interface (multichannel and full-duplex
1425 * serial if)
1426 */
1427
1428static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1429	.rev_offs	= 0x0000,
1430	.sysc_offs	= 0x0010,
1431	.syss_offs	= 0x0014,
1432	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1433			   SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1434			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1435	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1436			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1437			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1438	.sysc_fields	= &omap_hwmod_sysc_type1,
1439};
1440
1441static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1442	.name	= "hsi",
1443	.sysc	= &omap44xx_hsi_sysc,
1444};
1445
1446/* hsi */
1447static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
1448	{ .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
1449	{ .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
1450	{ .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
1451	{ .irq = -1 }
1452};
1453
1454static struct omap_hwmod omap44xx_hsi_hwmod = {
1455	.name		= "hsi",
1456	.class		= &omap44xx_hsi_hwmod_class,
1457	.clkdm_name	= "l3_init_clkdm",
1458	.mpu_irqs	= omap44xx_hsi_irqs,
1459	.main_clk	= "hsi_fck",
1460	.prcm = {
1461		.omap4 = {
1462			.clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1463			.context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1464			.modulemode   = MODULEMODE_HWCTRL,
1465		},
1466	},
1467};
1468
1469/*
1470 * 'i2c' class
1471 * multimaster high-speed i2c controller
1472 */
1473
1474static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1475	.sysc_offs	= 0x0010,
1476	.syss_offs	= 0x0090,
1477	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1478			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1479			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1480	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1481			   SIDLE_SMART_WKUP),
1482	.clockact	= CLOCKACT_TEST_ICLK,
1483	.sysc_fields	= &omap_hwmod_sysc_type1,
1484};
1485
1486static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1487	.name	= "i2c",
1488	.sysc	= &omap44xx_i2c_sysc,
1489	.rev	= OMAP_I2C_IP_VERSION_2,
1490	.reset	= &omap_i2c_reset,
1491};
1492
1493static struct omap_i2c_dev_attr i2c_dev_attr = {
1494	.flags	= OMAP_I2C_FLAG_BUS_SHIFT_NONE |
1495			OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
1496};
1497
1498/* i2c1 */
1499static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1500	{ .irq = 56 + OMAP44XX_IRQ_GIC_START },
1501	{ .irq = -1 }
1502};
1503
1504static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1505	{ .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1506	{ .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1507	{ .dma_req = -1 }
1508};
1509
1510static struct omap_hwmod omap44xx_i2c1_hwmod = {
1511	.name		= "i2c1",
1512	.class		= &omap44xx_i2c_hwmod_class,
1513	.clkdm_name	= "l4_per_clkdm",
1514	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1515	.mpu_irqs	= omap44xx_i2c1_irqs,
1516	.sdma_reqs	= omap44xx_i2c1_sdma_reqs,
1517	.main_clk	= "i2c1_fck",
1518	.prcm = {
1519		.omap4 = {
1520			.clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1521			.context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1522			.modulemode   = MODULEMODE_SWCTRL,
1523		},
1524	},
1525	.dev_attr	= &i2c_dev_attr,
1526};
1527
1528/* i2c2 */
1529static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1530	{ .irq = 57 + OMAP44XX_IRQ_GIC_START },
1531	{ .irq = -1 }
1532};
1533
1534static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1535	{ .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1536	{ .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1537	{ .dma_req = -1 }
1538};
1539
1540static struct omap_hwmod omap44xx_i2c2_hwmod = {
1541	.name		= "i2c2",
1542	.class		= &omap44xx_i2c_hwmod_class,
1543	.clkdm_name	= "l4_per_clkdm",
1544	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1545	.mpu_irqs	= omap44xx_i2c2_irqs,
1546	.sdma_reqs	= omap44xx_i2c2_sdma_reqs,
1547	.main_clk	= "i2c2_fck",
1548	.prcm = {
1549		.omap4 = {
1550			.clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1551			.context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1552			.modulemode   = MODULEMODE_SWCTRL,
1553		},
1554	},
1555	.dev_attr	= &i2c_dev_attr,
1556};
1557
1558/* i2c3 */
1559static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1560	{ .irq = 61 + OMAP44XX_IRQ_GIC_START },
1561	{ .irq = -1 }
1562};
1563
1564static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1565	{ .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1566	{ .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1567	{ .dma_req = -1 }
1568};
1569
1570static struct omap_hwmod omap44xx_i2c3_hwmod = {
1571	.name		= "i2c3",
1572	.class		= &omap44xx_i2c_hwmod_class,
1573	.clkdm_name	= "l4_per_clkdm",
1574	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1575	.mpu_irqs	= omap44xx_i2c3_irqs,
1576	.sdma_reqs	= omap44xx_i2c3_sdma_reqs,
1577	.main_clk	= "i2c3_fck",
1578	.prcm = {
1579		.omap4 = {
1580			.clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1581			.context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1582			.modulemode   = MODULEMODE_SWCTRL,
1583		},
1584	},
1585	.dev_attr	= &i2c_dev_attr,
1586};
1587
1588/* i2c4 */
1589static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1590	{ .irq = 62 + OMAP44XX_IRQ_GIC_START },
1591	{ .irq = -1 }
1592};
1593
1594static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1595	{ .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1596	{ .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
1597	{ .dma_req = -1 }
1598};
1599
1600static struct omap_hwmod omap44xx_i2c4_hwmod = {
1601	.name		= "i2c4",
1602	.class		= &omap44xx_i2c_hwmod_class,
1603	.clkdm_name	= "l4_per_clkdm",
1604	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1605	.mpu_irqs	= omap44xx_i2c4_irqs,
1606	.sdma_reqs	= omap44xx_i2c4_sdma_reqs,
1607	.main_clk	= "i2c4_fck",
1608	.prcm = {
1609		.omap4 = {
1610			.clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1611			.context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1612			.modulemode   = MODULEMODE_SWCTRL,
1613		},
1614	},
1615	.dev_attr	= &i2c_dev_attr,
1616};
1617
1618/*
1619 * 'ipu' class
1620 * imaging processor unit
1621 */
1622
1623static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1624	.name	= "ipu",
1625};
1626
1627/* ipu */
1628static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
1629	{ .irq = 100 + OMAP44XX_IRQ_GIC_START },
1630	{ .irq = -1 }
1631};
1632
1633static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1634	{ .name = "cpu0", .rst_shift = 0 },
1635	{ .name = "cpu1", .rst_shift = 1 },
1636	{ .name = "mmu_cache", .rst_shift = 2 },
1637};
1638
1639static struct omap_hwmod omap44xx_ipu_hwmod = {
1640	.name		= "ipu",
1641	.class		= &omap44xx_ipu_hwmod_class,
1642	.clkdm_name	= "ducati_clkdm",
1643	.mpu_irqs	= omap44xx_ipu_irqs,
1644	.rst_lines	= omap44xx_ipu_resets,
1645	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_ipu_resets),
1646	.main_clk	= "ipu_fck",
1647	.prcm = {
1648		.omap4 = {
1649			.clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1650			.rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1651			.context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1652			.modulemode   = MODULEMODE_HWCTRL,
1653		},
1654	},
1655};
1656
1657/*
1658 * 'iss' class
1659 * external images sensor pixel data processor
1660 */
1661
1662static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1663	.rev_offs	= 0x0000,
1664	.sysc_offs	= 0x0010,
1665	/*
1666	 * ISS needs 100 OCP clk cycles delay after a softreset before
1667	 * accessing sysconfig again.
1668	 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1669	 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1670	 *
1671	 * TODO: Indicate errata when available.
1672	 */
1673	.srst_udelay	= 2,
1674	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1675			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1676	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1677			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1678			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1679	.sysc_fields	= &omap_hwmod_sysc_type2,
1680};
1681
1682static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1683	.name	= "iss",
1684	.sysc	= &omap44xx_iss_sysc,
1685};
1686
1687/* iss */
1688static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
1689	{ .irq = 24 + OMAP44XX_IRQ_GIC_START },
1690	{ .irq = -1 }
1691};
1692
1693static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
1694	{ .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
1695	{ .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
1696	{ .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
1697	{ .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
1698	{ .dma_req = -1 }
1699};
1700
1701static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1702	{ .role = "ctrlclk", .clk = "iss_ctrlclk" },
1703};
1704
1705static struct omap_hwmod omap44xx_iss_hwmod = {
1706	.name		= "iss",
1707	.class		= &omap44xx_iss_hwmod_class,
1708	.clkdm_name	= "iss_clkdm",
1709	.mpu_irqs	= omap44xx_iss_irqs,
1710	.sdma_reqs	= omap44xx_iss_sdma_reqs,
1711	.main_clk	= "iss_fck",
1712	.prcm = {
1713		.omap4 = {
1714			.clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1715			.context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1716			.modulemode   = MODULEMODE_SWCTRL,
1717		},
1718	},
1719	.opt_clks	= iss_opt_clks,
1720	.opt_clks_cnt	= ARRAY_SIZE(iss_opt_clks),
1721};
1722
1723/*
1724 * 'iva' class
1725 * multi-standard video encoder/decoder hardware accelerator
1726 */
1727
1728static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1729	.name	= "iva",
1730};
1731
1732/* iva */
1733static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1734	{ .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1735	{ .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1736	{ .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1737	{ .irq = -1 }
1738};
1739
1740static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1741	{ .name = "seq0", .rst_shift = 0 },
1742	{ .name = "seq1", .rst_shift = 1 },
1743	{ .name = "logic", .rst_shift = 2 },
1744};
1745
1746static struct omap_hwmod omap44xx_iva_hwmod = {
1747	.name		= "iva",
1748	.class		= &omap44xx_iva_hwmod_class,
1749	.clkdm_name	= "ivahd_clkdm",
1750	.mpu_irqs	= omap44xx_iva_irqs,
1751	.rst_lines	= omap44xx_iva_resets,
1752	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_iva_resets),
1753	.main_clk	= "iva_fck",
1754	.prcm = {
1755		.omap4 = {
1756			.clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1757			.rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1758			.context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1759			.modulemode   = MODULEMODE_HWCTRL,
1760		},
1761	},
1762};
1763
1764/*
1765 * 'kbd' class
1766 * keyboard controller
1767 */
1768
1769static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1770	.rev_offs	= 0x0000,
1771	.sysc_offs	= 0x0010,
1772	.syss_offs	= 0x0014,
1773	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1774			   SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1775			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1776			   SYSS_HAS_RESET_STATUS),
1777	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1778	.sysc_fields	= &omap_hwmod_sysc_type1,
1779};
1780
1781static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1782	.name	= "kbd",
1783	.sysc	= &omap44xx_kbd_sysc,
1784};
1785
1786/* kbd */
1787static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
1788	{ .irq = 120 + OMAP44XX_IRQ_GIC_START },
1789	{ .irq = -1 }
1790};
1791
1792static struct omap_hwmod omap44xx_kbd_hwmod = {
1793	.name		= "kbd",
1794	.class		= &omap44xx_kbd_hwmod_class,
1795	.clkdm_name	= "l4_wkup_clkdm",
1796	.mpu_irqs	= omap44xx_kbd_irqs,
1797	.main_clk	= "kbd_fck",
1798	.prcm = {
1799		.omap4 = {
1800			.clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1801			.context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1802			.modulemode   = MODULEMODE_SWCTRL,
1803		},
1804	},
1805};
1806
1807/*
1808 * 'mailbox' class
1809 * mailbox module allowing communication between the on-chip processors using a
1810 * queued mailbox-interrupt mechanism.
1811 */
1812
1813static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1814	.rev_offs	= 0x0000,
1815	.sysc_offs	= 0x0010,
1816	.sysc_flags	= (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1817			   SYSC_HAS_SOFTRESET),
1818	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1819	.sysc_fields	= &omap_hwmod_sysc_type2,
1820};
1821
1822static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1823	.name	= "mailbox",
1824	.sysc	= &omap44xx_mailbox_sysc,
1825};
1826
1827/* mailbox */
1828static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
1829	{ .irq = 26 + OMAP44XX_IRQ_GIC_START },
1830	{ .irq = -1 }
1831};
1832
1833static struct omap_hwmod omap44xx_mailbox_hwmod = {
1834	.name		= "mailbox",
1835	.class		= &omap44xx_mailbox_hwmod_class,
1836	.clkdm_name	= "l4_cfg_clkdm",
1837	.mpu_irqs	= omap44xx_mailbox_irqs,
1838	.prcm = {
1839		.omap4 = {
1840			.clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1841			.context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1842		},
1843	},
1844};
1845
1846/*
1847 * 'mcasp' class
1848 * multi-channel audio serial port controller
1849 */
1850
1851/* The IP is not compliant to type1 / type2 scheme */
1852static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1853	.sidle_shift	= 0,
1854};
1855
1856static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1857	.sysc_offs	= 0x0004,
1858	.sysc_flags	= SYSC_HAS_SIDLEMODE,
1859	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1860			   SIDLE_SMART_WKUP),
1861	.sysc_fields	= &omap_hwmod_sysc_type_mcasp,
1862};
1863
1864static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1865	.name	= "mcasp",
1866	.sysc	= &omap44xx_mcasp_sysc,
1867};
1868
1869/* mcasp */
1870static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
1871	{ .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
1872	{ .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
1873	{ .irq = -1 }
1874};
1875
1876static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
1877	{ .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
1878	{ .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
1879	{ .dma_req = -1 }
1880};
1881
1882static struct omap_hwmod omap44xx_mcasp_hwmod = {
1883	.name		= "mcasp",
1884	.class		= &omap44xx_mcasp_hwmod_class,
1885	.clkdm_name	= "abe_clkdm",
1886	.mpu_irqs	= omap44xx_mcasp_irqs,
1887	.sdma_reqs	= omap44xx_mcasp_sdma_reqs,
1888	.main_clk	= "mcasp_fck",
1889	.prcm = {
1890		.omap4 = {
1891			.clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1892			.context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1893			.modulemode   = MODULEMODE_SWCTRL,
1894		},
1895	},
1896};
1897
1898/*
1899 * 'mcbsp' class
1900 * multi channel buffered serial port controller
1901 */
1902
1903static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1904	.sysc_offs	= 0x008c,
1905	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1906			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1907	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1908	.sysc_fields	= &omap_hwmod_sysc_type1,
1909};
1910
1911static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1912	.name	= "mcbsp",
1913	.sysc	= &omap44xx_mcbsp_sysc,
1914	.rev	= MCBSP_CONFIG_TYPE4,
1915};
1916
1917/* mcbsp1 */
1918static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
1919	{ .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
1920	{ .irq = -1 }
1921};
1922
1923static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
1924	{ .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
1925	{ .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
1926	{ .dma_req = -1 }
1927};
1928
1929static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1930	{ .role = "pad_fck", .clk = "pad_clks_ck" },
1931	{ .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1932};
1933
1934static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1935	.name		= "mcbsp1",
1936	.class		= &omap44xx_mcbsp_hwmod_class,
1937	.clkdm_name	= "abe_clkdm",
1938	.mpu_irqs	= omap44xx_mcbsp1_irqs,
1939	.sdma_reqs	= omap44xx_mcbsp1_sdma_reqs,
1940	.main_clk	= "mcbsp1_fck",
1941	.prcm = {
1942		.omap4 = {
1943			.clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1944			.context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1945			.modulemode   = MODULEMODE_SWCTRL,
1946		},
1947	},
1948	.opt_clks	= mcbsp1_opt_clks,
1949	.opt_clks_cnt	= ARRAY_SIZE(mcbsp1_opt_clks),
1950};
1951
1952/* mcbsp2 */
1953static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
1954	{ .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
1955	{ .irq = -1 }
1956};
1957
1958static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
1959	{ .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
1960	{ .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
1961	{ .dma_req = -1 }
1962};
1963
1964static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1965	{ .role = "pad_fck", .clk = "pad_clks_ck" },
1966	{ .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
1967};
1968
1969static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
1970	.name		= "mcbsp2",
1971	.class		= &omap44xx_mcbsp_hwmod_class,
1972	.clkdm_name	= "abe_clkdm",
1973	.mpu_irqs	= omap44xx_mcbsp2_irqs,
1974	.sdma_reqs	= omap44xx_mcbsp2_sdma_reqs,
1975	.main_clk	= "mcbsp2_fck",
1976	.prcm = {
1977		.omap4 = {
1978			.clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
1979			.context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
1980			.modulemode   = MODULEMODE_SWCTRL,
1981		},
1982	},
1983	.opt_clks	= mcbsp2_opt_clks,
1984	.opt_clks_cnt	= ARRAY_SIZE(mcbsp2_opt_clks),
1985};
1986
1987/* mcbsp3 */
1988static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
1989	{ .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
1990	{ .irq = -1 }
1991};
1992
1993static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
1994	{ .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
1995	{ .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
1996	{ .dma_req = -1 }
1997};
1998
1999static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
2000	{ .role = "pad_fck", .clk = "pad_clks_ck" },
2001	{ .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
2002};
2003
2004static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2005	.name		= "mcbsp3",
2006	.class		= &omap44xx_mcbsp_hwmod_class,
2007	.clkdm_name	= "abe_clkdm",
2008	.mpu_irqs	= omap44xx_mcbsp3_irqs,
2009	.sdma_reqs	= omap44xx_mcbsp3_sdma_reqs,
2010	.main_clk	= "mcbsp3_fck",
2011	.prcm = {
2012		.omap4 = {
2013			.clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
2014			.context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
2015			.modulemode   = MODULEMODE_SWCTRL,
2016		},
2017	},
2018	.opt_clks	= mcbsp3_opt_clks,
2019	.opt_clks_cnt	= ARRAY_SIZE(mcbsp3_opt_clks),
2020};
2021
2022/* mcbsp4 */
2023static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2024	{ .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
2025	{ .irq = -1 }
2026};
2027
2028static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2029	{ .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2030	{ .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2031	{ .dma_req = -1 }
2032};
2033
2034static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
2035	{ .role = "pad_fck", .clk = "pad_clks_ck" },
2036	{ .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
2037};
2038
2039static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2040	.name		= "mcbsp4",
2041	.class		= &omap44xx_mcbsp_hwmod_class,
2042	.clkdm_name	= "l4_per_clkdm",
2043	.mpu_irqs	= omap44xx_mcbsp4_irqs,
2044	.sdma_reqs	= omap44xx_mcbsp4_sdma_reqs,
2045	.main_clk	= "mcbsp4_fck",
2046	.prcm = {
2047		.omap4 = {
2048			.clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
2049			.context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
2050			.modulemode   = MODULEMODE_SWCTRL,
2051		},
2052	},
2053	.opt_clks	= mcbsp4_opt_clks,
2054	.opt_clks_cnt	= ARRAY_SIZE(mcbsp4_opt_clks),
2055};
2056
2057/*
2058 * 'mcpdm' class
2059 * multi channel pdm controller (proprietary interface with phoenix power
2060 * ic)
2061 */
2062
2063static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
2064	.rev_offs	= 0x0000,
2065	.sysc_offs	= 0x0010,
2066	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2067			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2068	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2069			   SIDLE_SMART_WKUP),
2070	.sysc_fields	= &omap_hwmod_sysc_type2,
2071};
2072
2073static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
2074	.name	= "mcpdm",
2075	.sysc	= &omap44xx_mcpdm_sysc,
2076};
2077
2078/* mcpdm */
2079static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
2080	{ .irq = 112 + OMAP44XX_IRQ_GIC_START },
2081	{ .irq = -1 }
2082};
2083
2084static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
2085	{ .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
2086	{ .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
2087	{ .dma_req = -1 }
2088};
2089
2090static struct omap_hwmod omap44xx_mcpdm_hwmod = {
2091	.name		= "mcpdm",
2092	.class		= &omap44xx_mcpdm_hwmod_class,
2093	.clkdm_name	= "abe_clkdm",
2094	.mpu_irqs	= omap44xx_mcpdm_irqs,
2095	.sdma_reqs	= omap44xx_mcpdm_sdma_reqs,
2096	.main_clk	= "mcpdm_fck",
2097	.prcm = {
2098		.omap4 = {
2099			.clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
2100			.context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
2101			.modulemode   = MODULEMODE_SWCTRL,
2102		},
2103	},
2104};
2105
2106/*
2107 * 'mcspi' class
2108 * multichannel serial port interface (mcspi) / master/slave synchronous serial
2109 * bus
2110 */
2111
2112static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
2113	.rev_offs	= 0x0000,
2114	.sysc_offs	= 0x0010,
2115	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2116			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2117	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2118			   SIDLE_SMART_WKUP),
2119	.sysc_fields	= &omap_hwmod_sysc_type2,
2120};
2121
2122static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
2123	.name	= "mcspi",
2124	.sysc	= &omap44xx_mcspi_sysc,
2125	.rev	= OMAP4_MCSPI_REV,
2126};
2127
2128/* mcspi1 */
2129static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
2130	{ .irq = 65 + OMAP44XX_IRQ_GIC_START },
2131	{ .irq = -1 }
2132};
2133
2134static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
2135	{ .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
2136	{ .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
2137	{ .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
2138	{ .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
2139	{ .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
2140	{ .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
2141	{ .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
2142	{ .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
2143	{ .dma_req = -1 }
2144};
2145
2146/* mcspi1 dev_attr */
2147static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
2148	.num_chipselect	= 4,
2149};
2150
2151static struct omap_hwmod omap44xx_mcspi1_hwmod = {
2152	.name		= "mcspi1",
2153	.class		= &omap44xx_mcspi_hwmod_class,
2154	.clkdm_name	= "l4_per_clkdm",
2155	.mpu_irqs	= omap44xx_mcspi1_irqs,
2156	.sdma_reqs	= omap44xx_mcspi1_sdma_reqs,
2157	.main_clk	= "mcspi1_fck",
2158	.prcm = {
2159		.omap4 = {
2160			.clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
2161			.context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
2162			.modulemode   = MODULEMODE_SWCTRL,
2163		},
2164	},
2165	.dev_attr	= &mcspi1_dev_attr,
2166};
2167
2168/* mcspi2 */
2169static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
2170	{ .irq = 66 + OMAP44XX_IRQ_GIC_START },
2171	{ .irq = -1 }
2172};
2173
2174static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
2175	{ .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
2176	{ .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
2177	{ .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
2178	{ .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
2179	{ .dma_req = -1 }
2180};
2181
2182/* mcspi2 dev_attr */
2183static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
2184	.num_chipselect	= 2,
2185};
2186
2187static struct omap_hwmod omap44xx_mcspi2_hwmod = {
2188	.name		= "mcspi2",
2189	.class		= &omap44xx_mcspi_hwmod_class,
2190	.clkdm_name	= "l4_per_clkdm",
2191	.mpu_irqs	= omap44xx_mcspi2_irqs,
2192	.sdma_reqs	= omap44xx_mcspi2_sdma_reqs,
2193	.main_clk	= "mcspi2_fck",
2194	.prcm = {
2195		.omap4 = {
2196			.clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
2197			.context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
2198			.modulemode   = MODULEMODE_SWCTRL,
2199		},
2200	},
2201	.dev_attr	= &mcspi2_dev_attr,
2202};
2203
2204/* mcspi3 */
2205static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
2206	{ .irq = 91 + OMAP44XX_IRQ_GIC_START },
2207	{ .irq = -1 }
2208};
2209
2210static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
2211	{ .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
2212	{ .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
2213	{ .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
2214	{ .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
2215	{ .dma_req = -1 }
2216};
2217
2218/* mcspi3 dev_attr */
2219static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
2220	.num_chipselect	= 2,
2221};
2222
2223static struct omap_hwmod omap44xx_mcspi3_hwmod = {
2224	.name		= "mcspi3",
2225	.class		= &omap44xx_mcspi_hwmod_class,
2226	.clkdm_name	= "l4_per_clkdm",
2227	.mpu_irqs	= omap44xx_mcspi3_irqs,
2228	.sdma_reqs	= omap44xx_mcspi3_sdma_reqs,
2229	.main_clk	= "mcspi3_fck",
2230	.prcm = {
2231		.omap4 = {
2232			.clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
2233			.context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
2234			.modulemode   = MODULEMODE_SWCTRL,
2235		},
2236	},
2237	.dev_attr	= &mcspi3_dev_attr,
2238};
2239
2240/* mcspi4 */
2241static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
2242	{ .irq = 48 + OMAP44XX_IRQ_GIC_START },
2243	{ .irq = -1 }
2244};
2245
2246static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
2247	{ .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
2248	{ .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
2249	{ .dma_req = -1 }
2250};
2251
2252/* mcspi4 dev_attr */
2253static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
2254	.num_chipselect	= 1,
2255};
2256
2257static struct omap_hwmod omap44xx_mcspi4_hwmod = {
2258	.name		= "mcspi4",
2259	.class		= &omap44xx_mcspi_hwmod_class,
2260	.clkdm_name	= "l4_per_clkdm",
2261	.mpu_irqs	= omap44xx_mcspi4_irqs,
2262	.sdma_reqs	= omap44xx_mcspi4_sdma_reqs,
2263	.main_clk	= "mcspi4_fck",
2264	.prcm = {
2265		.omap4 = {
2266			.clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
2267			.context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
2268			.modulemode   = MODULEMODE_SWCTRL,
2269		},
2270	},
2271	.dev_attr	= &mcspi4_dev_attr,
2272};
2273
2274/*
2275 * 'mmc' class
2276 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2277 */
2278
2279static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
2280	.rev_offs	= 0x0000,
2281	.sysc_offs	= 0x0010,
2282	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
2283			   SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2284			   SYSC_HAS_SOFTRESET),
2285	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2286			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2287			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2288	.sysc_fields	= &omap_hwmod_sysc_type2,
2289};
2290
2291static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
2292	.name	= "mmc",
2293	.sysc	= &omap44xx_mmc_sysc,
2294};
2295
2296/* mmc1 */
2297static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
2298	{ .irq = 83 + OMAP44XX_IRQ_GIC_START },
2299	{ .irq = -1 }
2300};
2301
2302static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
2303	{ .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
2304	{ .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
2305	{ .dma_req = -1 }
2306};
2307
2308/* mmc1 dev_attr */
2309static struct omap_mmc_dev_attr mmc1_dev_attr = {
2310	.flags	= OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2311};
2312
2313static struct omap_hwmod omap44xx_mmc1_hwmod = {
2314	.name		= "mmc1",
2315	.class		= &omap44xx_mmc_hwmod_class,
2316	.clkdm_name	= "l3_init_clkdm",
2317	.mpu_irqs	= omap44xx_mmc1_irqs,
2318	.sdma_reqs	= omap44xx_mmc1_sdma_reqs,
2319	.main_clk	= "mmc1_fck",
2320	.prcm = {
2321		.omap4 = {
2322			.clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
2323			.context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
2324			.modulemode   = MODULEMODE_SWCTRL,
2325		},
2326	},
2327	.dev_attr	= &mmc1_dev_attr,
2328};
2329
2330/* mmc2 */
2331static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
2332	{ .irq = 86 + OMAP44XX_IRQ_GIC_START },
2333	{ .irq = -1 }
2334};
2335
2336static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
2337	{ .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
2338	{ .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
2339	{ .dma_req = -1 }
2340};
2341
2342static struct omap_hwmod omap44xx_mmc2_hwmod = {
2343	.name		= "mmc2",
2344	.class		= &omap44xx_mmc_hwmod_class,
2345	.clkdm_name	= "l3_init_clkdm",
2346	.mpu_irqs	= omap44xx_mmc2_irqs,
2347	.sdma_reqs	= omap44xx_mmc2_sdma_reqs,
2348	.main_clk	= "mmc2_fck",
2349	.prcm = {
2350		.omap4 = {
2351			.clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2352			.context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2353			.modulemode   = MODULEMODE_SWCTRL,
2354		},
2355	},
2356};
2357
2358/* mmc3 */
2359static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
2360	{ .irq = 94 + OMAP44XX_IRQ_GIC_START },
2361	{ .irq = -1 }
2362};
2363
2364static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2365	{ .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2366	{ .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2367	{ .dma_req = -1 }
2368};
2369
2370static struct omap_hwmod omap44xx_mmc3_hwmod = {
2371	.name		= "mmc3",
2372	.class		= &omap44xx_mmc_hwmod_class,
2373	.clkdm_name	= "l4_per_clkdm",
2374	.mpu_irqs	= omap44xx_mmc3_irqs,
2375	.sdma_reqs	= omap44xx_mmc3_sdma_reqs,
2376	.main_clk	= "mmc3_fck",
2377	.prcm = {
2378		.omap4 = {
2379			.clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2380			.context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2381			.modulemode   = MODULEMODE_SWCTRL,
2382		},
2383	},
2384};
2385
2386/* mmc4 */
2387static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
2388	{ .irq = 96 + OMAP44XX_IRQ_GIC_START },
2389	{ .irq = -1 }
2390};
2391
2392static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2393	{ .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2394	{ .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2395	{ .dma_req = -1 }
2396};
2397
2398static struct omap_hwmod omap44xx_mmc4_hwmod = {
2399	.name		= "mmc4",
2400	.class		= &omap44xx_mmc_hwmod_class,
2401	.clkdm_name	= "l4_per_clkdm",
2402	.mpu_irqs	= omap44xx_mmc4_irqs,
2403	.sdma_reqs	= omap44xx_mmc4_sdma_reqs,
2404	.main_clk	= "mmc4_fck",
2405	.prcm = {
2406		.omap4 = {
2407			.clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2408			.context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2409			.modulemode   = MODULEMODE_SWCTRL,
2410		},
2411	},
2412};
2413
2414/* mmc5 */
2415static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
2416	{ .irq = 59 + OMAP44XX_IRQ_GIC_START },
2417	{ .irq = -1 }
2418};
2419
2420static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2421	{ .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2422	{ .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2423	{ .dma_req = -1 }
2424};
2425
2426static struct omap_hwmod omap44xx_mmc5_hwmod = {
2427	.name		= "mmc5",
2428	.class		= &omap44xx_mmc_hwmod_class,
2429	.clkdm_name	= "l4_per_clkdm",
2430	.mpu_irqs	= omap44xx_mmc5_irqs,
2431	.sdma_reqs	= omap44xx_mmc5_sdma_reqs,
2432	.main_clk	= "mmc5_fck",
2433	.prcm = {
2434		.omap4 = {
2435			.clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2436			.context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2437			.modulemode   = MODULEMODE_SWCTRL,
2438		},
2439	},
2440};
2441
2442/*
2443 * 'mpu' class
2444 * mpu sub-system
2445 */
2446
2447static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2448	.name	= "mpu",
2449};
2450
2451/* mpu */
2452static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
2453	{ .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
2454	{ .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
2455	{ .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
2456	{ .irq = -1 }
2457};
2458
2459static struct omap_hwmod omap44xx_mpu_hwmod = {
2460	.name		= "mpu",
2461	.class		= &omap44xx_mpu_hwmod_class,
2462	.clkdm_name	= "mpuss_clkdm",
2463	.flags		= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2464	.mpu_irqs	= omap44xx_mpu_irqs,
2465	.main_clk	= "dpll_mpu_m2_ck",
2466	.prcm = {
2467		.omap4 = {
2468			.clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2469			.context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2470		},
2471	},
2472};
2473
2474/*
2475 * 'ocmc_ram' class
2476 * top-level core on-chip ram
2477 */
2478
2479static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2480	.name	= "ocmc_ram",
2481};
2482
2483/* ocmc_ram */
2484static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2485	.name		= "ocmc_ram",
2486	.class		= &omap44xx_ocmc_ram_hwmod_class,
2487	.clkdm_name	= "l3_2_clkdm",
2488	.prcm = {
2489		.omap4 = {
2490			.clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2491			.context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2492		},
2493	},
2494};
2495
2496/*
2497 * 'ocp2scp' class
2498 * bridge to transform ocp interface protocol to scp (serial control port)
2499 * protocol
2500 */
2501
2502static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2503	.name	= "ocp2scp",
2504};
2505
2506/* ocp2scp_usb_phy */
2507static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = {
2508	{ .role = "phy_48m", .clk = "ocp2scp_usb_phy_phy_48m" },
2509};
2510
2511static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2512	.name		= "ocp2scp_usb_phy",
2513	.class		= &omap44xx_ocp2scp_hwmod_class,
2514	.clkdm_name	= "l3_init_clkdm",
2515	.prcm = {
2516		.omap4 = {
2517			.clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2518			.context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2519			.modulemode   = MODULEMODE_HWCTRL,
2520		},
2521	},
2522	.opt_clks	= ocp2scp_usb_phy_opt_clks,
2523	.opt_clks_cnt	= ARRAY_SIZE(ocp2scp_usb_phy_opt_clks),
2524};
2525
2526/*
2527 * 'prcm' class
2528 * power and reset manager (part of the prcm infrastructure) + clock manager 2
2529 * + clock manager 1 (in always on power domain) + local prm in mpu
2530 */
2531
2532static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2533	.name	= "prcm",
2534};
2535
2536/* prcm_mpu */
2537static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2538	.name		= "prcm_mpu",
2539	.class		= &omap44xx_prcm_hwmod_class,
2540	.clkdm_name	= "l4_wkup_clkdm",
2541};
2542
2543/* cm_core_aon */
2544static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2545	.name		= "cm_core_aon",
2546	.class		= &omap44xx_prcm_hwmod_class,
2547	.clkdm_name	= "cm_clkdm",
2548};
2549
2550/* cm_core */
2551static struct omap_hwmod omap44xx_cm_core_hwmod = {
2552	.name		= "cm_core",
2553	.class		= &omap44xx_prcm_hwmod_class,
2554	.clkdm_name	= "cm_clkdm",
2555};
2556
2557/* prm */
2558static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
2559	{ .irq = 11 + OMAP44XX_IRQ_GIC_START },
2560	{ .irq = -1 }
2561};
2562
2563static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2564	{ .name = "rst_global_warm_sw", .rst_shift = 0 },
2565	{ .name = "rst_global_cold_sw", .rst_shift = 1 },
2566};
2567
2568static struct omap_hwmod omap44xx_prm_hwmod = {
2569	.name		= "prm",
2570	.class		= &omap44xx_prcm_hwmod_class,
2571	.clkdm_name	= "prm_clkdm",
2572	.mpu_irqs	= omap44xx_prm_irqs,
2573	.rst_lines	= omap44xx_prm_resets,
2574	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_prm_resets),
2575};
2576
2577/*
2578 * 'scrm' class
2579 * system clock and reset manager
2580 */
2581
2582static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2583	.name	= "scrm",
2584};
2585
2586/* scrm */
2587static struct omap_hwmod omap44xx_scrm_hwmod = {
2588	.name		= "scrm",
2589	.class		= &omap44xx_scrm_hwmod_class,
2590	.clkdm_name	= "l4_wkup_clkdm",
2591};
2592
2593/*
2594 * 'sl2if' class
2595 * shared level 2 memory interface
2596 */
2597
2598static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2599	.name	= "sl2if",
2600};
2601
2602/* sl2if */
2603static struct omap_hwmod omap44xx_sl2if_hwmod = {
2604	.name		= "sl2if",
2605	.class		= &omap44xx_sl2if_hwmod_class,
2606	.clkdm_name	= "ivahd_clkdm",
2607	.prcm = {
2608		.omap4 = {
2609			.clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2610			.context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2611			.modulemode   = MODULEMODE_HWCTRL,
2612		},
2613	},
2614};
2615
2616/*
2617 * 'slimbus' class
2618 * bidirectional, multi-drop, multi-channel two-line serial interface between
2619 * the device and external components
2620 */
2621
2622static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2623	.rev_offs	= 0x0000,
2624	.sysc_offs	= 0x0010,
2625	.sysc_flags	= (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2626			   SYSC_HAS_SOFTRESET),
2627	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2628			   SIDLE_SMART_WKUP),
2629	.sysc_fields	= &omap_hwmod_sysc_type2,
2630};
2631
2632static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2633	.name	= "slimbus",
2634	.sysc	= &omap44xx_slimbus_sysc,
2635};
2636
2637/* slimbus1 */
2638static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
2639	{ .irq = 97 + OMAP44XX_IRQ_GIC_START },
2640	{ .irq = -1 }
2641};
2642
2643static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
2644	{ .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
2645	{ .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
2646	{ .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
2647	{ .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
2648	{ .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
2649	{ .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
2650	{ .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
2651	{ .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
2652	{ .dma_req = -1 }
2653};
2654
2655static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2656	{ .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2657	{ .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2658	{ .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2659	{ .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2660};
2661
2662static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2663	.name		= "slimbus1",
2664	.class		= &omap44xx_slimbus_hwmod_class,
2665	.clkdm_name	= "abe_clkdm",
2666	.mpu_irqs	= omap44xx_slimbus1_irqs,
2667	.sdma_reqs	= omap44xx_slimbus1_sdma_reqs,
2668	.prcm = {
2669		.omap4 = {
2670			.clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2671			.context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2672			.modulemode   = MODULEMODE_SWCTRL,
2673		},
2674	},
2675	.opt_clks	= slimbus1_opt_clks,
2676	.opt_clks_cnt	= ARRAY_SIZE(slimbus1_opt_clks),
2677};
2678
2679/* slimbus2 */
2680static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
2681	{ .irq = 98 + OMAP44XX_IRQ_GIC_START },
2682	{ .irq = -1 }
2683};
2684
2685static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
2686	{ .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
2687	{ .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
2688	{ .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
2689	{ .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
2690	{ .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
2691	{ .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
2692	{ .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
2693	{ .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
2694	{ .dma_req = -1 }
2695};
2696
2697static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2698	{ .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2699	{ .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2700	{ .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2701};
2702
2703static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2704	.name		= "slimbus2",
2705	.class		= &omap44xx_slimbus_hwmod_class,
2706	.clkdm_name	= "l4_per_clkdm",
2707	.mpu_irqs	= omap44xx_slimbus2_irqs,
2708	.sdma_reqs	= omap44xx_slimbus2_sdma_reqs,
2709	.prcm = {
2710		.omap4 = {
2711			.clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2712			.context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2713			.modulemode   = MODULEMODE_SWCTRL,
2714		},
2715	},
2716	.opt_clks	= slimbus2_opt_clks,
2717	.opt_clks_cnt	= ARRAY_SIZE(slimbus2_opt_clks),
2718};
2719
2720/*
2721 * 'smartreflex' class
2722 * smartreflex module (monitor silicon performance and outputs a measure of
2723 * performance error)
2724 */
2725
2726/* The IP is not compliant to type1 / type2 scheme */
2727static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2728	.sidle_shift	= 24,
2729	.enwkup_shift	= 26,
2730};
2731
2732static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2733	.sysc_offs	= 0x0038,
2734	.sysc_flags	= (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2735	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2736			   SIDLE_SMART_WKUP),
2737	.sysc_fields	= &omap_hwmod_sysc_type_smartreflex,
2738};
2739
2740static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2741	.name	= "smartreflex",
2742	.sysc	= &omap44xx_smartreflex_sysc,
2743	.rev	= 2,
2744};
2745
2746/* smartreflex_core */
2747static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2748	.sensor_voltdm_name   = "core",
2749};
2750
2751static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
2752	{ .irq = 19 + OMAP44XX_IRQ_GIC_START },
2753	{ .irq = -1 }
2754};
2755
2756static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2757	.name		= "smartreflex_core",
2758	.class		= &omap44xx_smartreflex_hwmod_class,
2759	.clkdm_name	= "l4_ao_clkdm",
2760	.mpu_irqs	= omap44xx_smartreflex_core_irqs,
2761
2762	.main_clk	= "smartreflex_core_fck",
2763	.prcm = {
2764		.omap4 = {
2765			.clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2766			.context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2767			.modulemode   = MODULEMODE_SWCTRL,
2768		},
2769	},
2770	.dev_attr	= &smartreflex_core_dev_attr,
2771};
2772
2773/* smartreflex_iva */
2774static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
2775	.sensor_voltdm_name	= "iva",
2776};
2777
2778static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
2779	{ .irq = 102 + OMAP44XX_IRQ_GIC_START },
2780	{ .irq = -1 }
2781};
2782
2783static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
2784	.name		= "smartreflex_iva",
2785	.class		= &omap44xx_smartreflex_hwmod_class,
2786	.clkdm_name	= "l4_ao_clkdm",
2787	.mpu_irqs	= omap44xx_smartreflex_iva_irqs,
2788	.main_clk	= "smartreflex_iva_fck",
2789	.prcm = {
2790		.omap4 = {
2791			.clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
2792			.context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
2793			.modulemode   = MODULEMODE_SWCTRL,
2794		},
2795	},
2796	.dev_attr	= &smartreflex_iva_dev_attr,
2797};
2798
2799/* smartreflex_mpu */
2800static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2801	.sensor_voltdm_name	= "mpu",
2802};
2803
2804static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
2805	{ .irq = 18 + OMAP44XX_IRQ_GIC_START },
2806	{ .irq = -1 }
2807};
2808
2809static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
2810	.name		= "smartreflex_mpu",
2811	.class		= &omap44xx_smartreflex_hwmod_class,
2812	.clkdm_name	= "l4_ao_clkdm",
2813	.mpu_irqs	= omap44xx_smartreflex_mpu_irqs,
2814	.main_clk	= "smartreflex_mpu_fck",
2815	.prcm = {
2816		.omap4 = {
2817			.clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
2818			.context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
2819			.modulemode   = MODULEMODE_SWCTRL,
2820		},
2821	},
2822	.dev_attr	= &smartreflex_mpu_dev_attr,
2823};
2824
2825/*
2826 * 'spinlock' class
2827 * spinlock provides hardware assistance for synchronizing the processes
2828 * running on multiple processors
2829 */
2830
2831static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
2832	.rev_offs	= 0x0000,
2833	.sysc_offs	= 0x0010,
2834	.syss_offs	= 0x0014,
2835	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2836			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2837			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2838	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2839			   SIDLE_SMART_WKUP),
2840	.sysc_fields	= &omap_hwmod_sysc_type1,
2841};
2842
2843static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
2844	.name	= "spinlock",
2845	.sysc	= &omap44xx_spinlock_sysc,
2846};
2847
2848/* spinlock */
2849static struct omap_hwmod omap44xx_spinlock_hwmod = {
2850	.name		= "spinlock",
2851	.class		= &omap44xx_spinlock_hwmod_class,
2852	.clkdm_name	= "l4_cfg_clkdm",
2853	.prcm = {
2854		.omap4 = {
2855			.clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
2856			.context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
2857		},
2858	},
2859};
2860
2861/*
2862 * 'timer' class
2863 * general purpose timer module with accurate 1ms tick
2864 * This class contains several variants: ['timer_1ms', 'timer']
2865 */
2866
2867static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
2868	.rev_offs	= 0x0000,
2869	.sysc_offs	= 0x0010,
2870	.syss_offs	= 0x0014,
2871	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2872			   SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2873			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2874			   SYSS_HAS_RESET_STATUS),
2875	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2876	.sysc_fields	= &omap_hwmod_sysc_type1,
2877};
2878
2879static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
2880	.name	= "timer",
2881	.sysc	= &omap44xx_timer_1ms_sysc,
2882};
2883
2884static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
2885	.rev_offs	= 0x0000,
2886	.sysc_offs	= 0x0010,
2887	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2888			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2889	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2890			   SIDLE_SMART_WKUP),
2891	.sysc_fields	= &omap_hwmod_sysc_type2,
2892};
2893
2894static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
2895	.name	= "timer",
2896	.sysc	= &omap44xx_timer_sysc,
2897};
2898
2899/* always-on timers dev attribute */
2900static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
2901	.timer_capability	= OMAP_TIMER_ALWON,
2902};
2903
2904/* pwm timers dev attribute */
2905static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
2906	.timer_capability	= OMAP_TIMER_HAS_PWM,
2907};
2908
2909/* timer1 */
2910static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
2911	{ .irq = 37 + OMAP44XX_IRQ_GIC_START },
2912	{ .irq = -1 }
2913};
2914
2915static struct omap_hwmod omap44xx_timer1_hwmod = {
2916	.name		= "timer1",
2917	.class		= &omap44xx_timer_1ms_hwmod_class,
2918	.clkdm_name	= "l4_wkup_clkdm",
2919	.mpu_irqs	= omap44xx_timer1_irqs,
2920	.main_clk	= "timer1_fck",
2921	.prcm = {
2922		.omap4 = {
2923			.clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
2924			.context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
2925			.modulemode   = MODULEMODE_SWCTRL,
2926		},
2927	},
2928	.dev_attr	= &capability_alwon_dev_attr,
2929};
2930
2931/* timer2 */
2932static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
2933	{ .irq = 38 + OMAP44XX_IRQ_GIC_START },
2934	{ .irq = -1 }
2935};
2936
2937static struct omap_hwmod omap44xx_timer2_hwmod = {
2938	.name		= "timer2",
2939	.class		= &omap44xx_timer_1ms_hwmod_class,
2940	.clkdm_name	= "l4_per_clkdm",
2941	.mpu_irqs	= omap44xx_timer2_irqs,
2942	.main_clk	= "timer2_fck",
2943	.prcm = {
2944		.omap4 = {
2945			.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
2946			.context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
2947			.modulemode   = MODULEMODE_SWCTRL,
2948		},
2949	},
2950	.dev_attr	= &capability_alwon_dev_attr,
2951};
2952
2953/* timer3 */
2954static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
2955	{ .irq = 39 + OMAP44XX_IRQ_GIC_START },
2956	{ .irq = -1 }
2957};
2958
2959static struct omap_hwmod omap44xx_timer3_hwmod = {
2960	.name		= "timer3",
2961	.class		= &omap44xx_timer_hwmod_class,
2962	.clkdm_name	= "l4_per_clkdm",
2963	.mpu_irqs	= omap44xx_timer3_irqs,
2964	.main_clk	= "timer3_fck",
2965	.prcm = {
2966		.omap4 = {
2967			.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
2968			.context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
2969			.modulemode   = MODULEMODE_SWCTRL,
2970		},
2971	},
2972	.dev_attr	= &capability_alwon_dev_attr,
2973};
2974
2975/* timer4 */
2976static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
2977	{ .irq = 40 + OMAP44XX_IRQ_GIC_START },
2978	{ .irq = -1 }
2979};
2980
2981static struct omap_hwmod omap44xx_timer4_hwmod = {
2982	.name		= "timer4",
2983	.class		= &omap44xx_timer_hwmod_class,
2984	.clkdm_name	= "l4_per_clkdm",
2985	.mpu_irqs	= omap44xx_timer4_irqs,
2986	.main_clk	= "timer4_fck",
2987	.prcm = {
2988		.omap4 = {
2989			.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
2990			.context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
2991			.modulemode   = MODULEMODE_SWCTRL,
2992		},
2993	},
2994	.dev_attr	= &capability_alwon_dev_attr,
2995};
2996
2997/* timer5 */
2998static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
2999	{ .irq = 41 + OMAP44XX_IRQ_GIC_START },
3000	{ .irq = -1 }
3001};
3002
3003static struct omap_hwmod omap44xx_timer5_hwmod = {
3004	.name		= "timer5",
3005	.class		= &omap44xx_timer_hwmod_class,
3006	.clkdm_name	= "abe_clkdm",
3007	.mpu_irqs	= omap44xx_timer5_irqs,
3008	.main_clk	= "timer5_fck",
3009	.prcm = {
3010		.omap4 = {
3011			.clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
3012			.context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
3013			.modulemode   = MODULEMODE_SWCTRL,
3014		},
3015	},
3016	.dev_attr	= &capability_alwon_dev_attr,
3017};
3018
3019/* timer6 */
3020static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
3021	{ .irq = 42 + OMAP44XX_IRQ_GIC_START },
3022	{ .irq = -1 }
3023};
3024
3025static struct omap_hwmod omap44xx_timer6_hwmod = {
3026	.name		= "timer6",
3027	.class		= &omap44xx_timer_hwmod_class,
3028	.clkdm_name	= "abe_clkdm",
3029	.mpu_irqs	= omap44xx_timer6_irqs,
3030
3031	.main_clk	= "timer6_fck",
3032	.prcm = {
3033		.omap4 = {
3034			.clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
3035			.context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
3036			.modulemode   = MODULEMODE_SWCTRL,
3037		},
3038	},
3039	.dev_attr	= &capability_alwon_dev_attr,
3040};
3041
3042/* timer7 */
3043static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
3044	{ .irq = 43 + OMAP44XX_IRQ_GIC_START },
3045	{ .irq = -1 }
3046};
3047
3048static struct omap_hwmod omap44xx_timer7_hwmod = {
3049	.name		= "timer7",
3050	.class		= &omap44xx_timer_hwmod_class,
3051	.clkdm_name	= "abe_clkdm",
3052	.mpu_irqs	= omap44xx_timer7_irqs,
3053	.main_clk	= "timer7_fck",
3054	.prcm = {
3055		.omap4 = {
3056			.clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
3057			.context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
3058			.modulemode   = MODULEMODE_SWCTRL,
3059		},
3060	},
3061	.dev_attr	= &capability_alwon_dev_attr,
3062};
3063
3064/* timer8 */
3065static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
3066	{ .irq = 44 + OMAP44XX_IRQ_GIC_START },
3067	{ .irq = -1 }
3068};
3069
3070static struct omap_hwmod omap44xx_timer8_hwmod = {
3071	.name		= "timer8",
3072	.class		= &omap44xx_timer_hwmod_class,
3073	.clkdm_name	= "abe_clkdm",
3074	.mpu_irqs	= omap44xx_timer8_irqs,
3075	.main_clk	= "timer8_fck",
3076	.prcm = {
3077		.omap4 = {
3078			.clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
3079			.context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
3080			.modulemode   = MODULEMODE_SWCTRL,
3081		},
3082	},
3083	.dev_attr	= &capability_pwm_dev_attr,
3084};
3085
3086/* timer9 */
3087static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
3088	{ .irq = 45 + OMAP44XX_IRQ_GIC_START },
3089	{ .irq = -1 }
3090};
3091
3092static struct omap_hwmod omap44xx_timer9_hwmod = {
3093	.name		= "timer9",
3094	.class		= &omap44xx_timer_hwmod_class,
3095	.clkdm_name	= "l4_per_clkdm",
3096	.mpu_irqs	= omap44xx_timer9_irqs,
3097	.main_clk	= "timer9_fck",
3098	.prcm = {
3099		.omap4 = {
3100			.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
3101			.context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
3102			.modulemode   = MODULEMODE_SWCTRL,
3103		},
3104	},
3105	.dev_attr	= &capability_pwm_dev_attr,
3106};
3107
3108/* timer10 */
3109static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
3110	{ .irq = 46 + OMAP44XX_IRQ_GIC_START },
3111	{ .irq = -1 }
3112};
3113
3114static struct omap_hwmod omap44xx_timer10_hwmod = {
3115	.name		= "timer10",
3116	.class		= &omap44xx_timer_1ms_hwmod_class,
3117	.clkdm_name	= "l4_per_clkdm",
3118	.mpu_irqs	= omap44xx_timer10_irqs,
3119	.main_clk	= "timer10_fck",
3120	.prcm = {
3121		.omap4 = {
3122			.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
3123			.context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
3124			.modulemode   = MODULEMODE_SWCTRL,
3125		},
3126	},
3127	.dev_attr	= &capability_pwm_dev_attr,
3128};
3129
3130/* timer11 */
3131static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
3132	{ .irq = 47 + OMAP44XX_IRQ_GIC_START },
3133	{ .irq = -1 }
3134};
3135
3136static struct omap_hwmod omap44xx_timer11_hwmod = {
3137	.name		= "timer11",
3138	.class		= &omap44xx_timer_hwmod_class,
3139	.clkdm_name	= "l4_per_clkdm",
3140	.mpu_irqs	= omap44xx_timer11_irqs,
3141	.main_clk	= "timer11_fck",
3142	.prcm = {
3143		.omap4 = {
3144			.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
3145			.context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
3146			.modulemode   = MODULEMODE_SWCTRL,
3147		},
3148	},
3149	.dev_attr	= &capability_pwm_dev_attr,
3150};
3151
3152/*
3153 * 'uart' class
3154 * universal asynchronous receiver/transmitter (uart)
3155 */
3156
3157static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
3158	.rev_offs	= 0x0050,
3159	.sysc_offs	= 0x0054,
3160	.syss_offs	= 0x0058,
3161	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3162			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3163			   SYSS_HAS_RESET_STATUS),
3164	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3165			   SIDLE_SMART_WKUP),
3166	.sysc_fields	= &omap_hwmod_sysc_type1,
3167};
3168
3169static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
3170	.name	= "uart",
3171	.sysc	= &omap44xx_uart_sysc,
3172};
3173
3174/* uart1 */
3175static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
3176	{ .irq = 72 + OMAP44XX_IRQ_GIC_START },
3177	{ .irq = -1 }
3178};
3179
3180static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
3181	{ .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
3182	{ .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
3183	{ .dma_req = -1 }
3184};
3185
3186static struct omap_hwmod omap44xx_uart1_hwmod = {
3187	.name		= "uart1",
3188	.class		= &omap44xx_uart_hwmod_class,
3189	.clkdm_name	= "l4_per_clkdm",
3190	.mpu_irqs	= omap44xx_uart1_irqs,
3191	.sdma_reqs	= omap44xx_uart1_sdma_reqs,
3192	.main_clk	= "uart1_fck",
3193	.prcm = {
3194		.omap4 = {
3195			.clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
3196			.context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
3197			.modulemode   = MODULEMODE_SWCTRL,
3198		},
3199	},
3200};
3201
3202/* uart2 */
3203static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
3204	{ .irq = 73 + OMAP44XX_IRQ_GIC_START },
3205	{ .irq = -1 }
3206};
3207
3208static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
3209	{ .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
3210	{ .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
3211	{ .dma_req = -1 }
3212};
3213
3214static struct omap_hwmod omap44xx_uart2_hwmod = {
3215	.name		= "uart2",
3216	.class		= &omap44xx_uart_hwmod_class,
3217	.clkdm_name	= "l4_per_clkdm",
3218	.mpu_irqs	= omap44xx_uart2_irqs,
3219	.sdma_reqs	= omap44xx_uart2_sdma_reqs,
3220	.main_clk	= "uart2_fck",
3221	.prcm = {
3222		.omap4 = {
3223			.clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
3224			.context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
3225			.modulemode   = MODULEMODE_SWCTRL,
3226		},
3227	},
3228};
3229
3230/* uart3 */
3231static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
3232	{ .irq = 74 + OMAP44XX_IRQ_GIC_START },
3233	{ .irq = -1 }
3234};
3235
3236static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
3237	{ .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
3238	{ .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
3239	{ .dma_req = -1 }
3240};
3241
3242static struct omap_hwmod omap44xx_uart3_hwmod = {
3243	.name		= "uart3",
3244	.class		= &omap44xx_uart_hwmod_class,
3245	.clkdm_name	= "l4_per_clkdm",
3246	.flags		= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3247	.mpu_irqs	= omap44xx_uart3_irqs,
3248	.sdma_reqs	= omap44xx_uart3_sdma_reqs,
3249	.main_clk	= "uart3_fck",
3250	.prcm = {
3251		.omap4 = {
3252			.clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
3253			.context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
3254			.modulemode   = MODULEMODE_SWCTRL,
3255		},
3256	},
3257};
3258
3259/* uart4 */
3260static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
3261	{ .irq = 70 + OMAP44XX_IRQ_GIC_START },
3262	{ .irq = -1 }
3263};
3264
3265static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
3266	{ .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
3267	{ .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
3268	{ .dma_req = -1 }
3269};
3270
3271static struct omap_hwmod omap44xx_uart4_hwmod = {
3272	.name		= "uart4",
3273	.class		= &omap44xx_uart_hwmod_class,
3274	.clkdm_name	= "l4_per_clkdm",
3275	.mpu_irqs	= omap44xx_uart4_irqs,
3276	.sdma_reqs	= omap44xx_uart4_sdma_reqs,
3277	.main_clk	= "uart4_fck",
3278	.prcm = {
3279		.omap4 = {
3280			.clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
3281			.context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
3282			.modulemode   = MODULEMODE_SWCTRL,
3283		},
3284	},
3285};
3286
3287/*
3288 * 'usb_host_fs' class
3289 * full-speed usb host controller
3290 */
3291
3292/* The IP is not compliant to type1 / type2 scheme */
3293static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
3294	.midle_shift	= 4,
3295	.sidle_shift	= 2,
3296	.srst_shift	= 1,
3297};
3298
3299static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
3300	.rev_offs	= 0x0000,
3301	.sysc_offs	= 0x0210,
3302	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3303			   SYSC_HAS_SOFTRESET),
3304	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3305			   SIDLE_SMART_WKUP),
3306	.sysc_fields	= &omap_hwmod_sysc_type_usb_host_fs,
3307};
3308
3309static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
3310	.name	= "usb_host_fs",
3311	.sysc	= &omap44xx_usb_host_fs_sysc,
3312};
3313
3314/* usb_host_fs */
3315static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
3316	{ .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
3317	{ .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
3318	{ .irq = -1 }
3319};
3320
3321static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
3322	.name		= "usb_host_fs",
3323	.class		= &omap44xx_usb_host_fs_hwmod_class,
3324	.clkdm_name	= "l3_init_clkdm",
3325	.mpu_irqs	= omap44xx_usb_host_fs_irqs,
3326	.main_clk	= "usb_host_fs_fck",
3327	.prcm = {
3328		.omap4 = {
3329			.clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
3330			.context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
3331			.modulemode   = MODULEMODE_SWCTRL,
3332		},
3333	},
3334};
3335
3336/*
3337 * 'usb_host_hs' class
3338 * high-speed multi-port usb host controller
3339 */
3340
3341static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
3342	.rev_offs	= 0x0000,
3343	.sysc_offs	= 0x0010,
3344	.syss_offs	= 0x0014,
3345	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3346			   SYSC_HAS_SOFTRESET),
3347	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3348			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3349			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3350	.sysc_fields	= &omap_hwmod_sysc_type2,
3351};
3352
3353static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
3354	.name	= "usb_host_hs",
3355	.sysc	= &omap44xx_usb_host_hs_sysc,
3356};
3357
3358/* usb_host_hs */
3359static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
3360	{ .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
3361	{ .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
3362	{ .irq = -1 }
3363};
3364
3365static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
3366	.name		= "usb_host_hs",
3367	.class		= &omap44xx_usb_host_hs_hwmod_class,
3368	.clkdm_name	= "l3_init_clkdm",
3369	.main_clk	= "usb_host_hs_fck",
3370	.prcm = {
3371		.omap4 = {
3372			.clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
3373			.context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
3374			.modulemode   = MODULEMODE_SWCTRL,
3375		},
3376	},
3377	.mpu_irqs	= omap44xx_usb_host_hs_irqs,
3378
3379	/*
3380	 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3381	 * id: i660
3382	 *
3383	 * Description:
3384	 * In the following configuration :
3385	 * - USBHOST module is set to smart-idle mode
3386	 * - PRCM asserts idle_req to the USBHOST module ( This typically
3387	 *   happens when the system is going to a low power mode : all ports
3388	 *   have been suspended, the master part of the USBHOST module has
3389	 *   entered the standby state, and SW has cut the functional clocks)
3390	 * - an USBHOST interrupt occurs before the module is able to answer
3391	 *   idle_ack, typically a remote wakeup IRQ.
3392	 * Then the USB HOST module will enter a deadlock situation where it
3393	 * is no more accessible nor functional.
3394	 *
3395	 * Workaround:
3396	 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3397	 */
3398
3399	/*
3400	 * Errata: USB host EHCI may stall when entering smart-standby mode
3401	 * Id: i571
3402	 *
3403	 * Description:
3404	 * When the USBHOST module is set to smart-standby mode, and when it is
3405	 * ready to enter the standby state (i.e. all ports are suspended and
3406	 * all attached devices are in suspend mode), then it can wrongly assert
3407	 * the Mstandby signal too early while there are still some residual OCP
3408	 * transactions ongoing. If this condition occurs, the internal state
3409	 * machine may go to an undefined state and the USB link may be stuck
3410	 * upon the next resume.
3411	 *
3412	 * Workaround:
3413	 * Don't use smart standby; use only force standby,
3414	 * hence HWMOD_SWSUP_MSTANDBY
3415	 */
3416
3417	/*
3418	 * During system boot; If the hwmod framework resets the module
3419	 * the module will have smart idle settings; which can lead to deadlock
3420	 * (above Errata Id:i660); so, dont reset the module during boot;
3421	 * Use HWMOD_INIT_NO_RESET.
3422	 */
3423
3424	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
3425			  HWMOD_INIT_NO_RESET,
3426};
3427
3428/*
3429 * 'usb_otg_hs' class
3430 * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3431 */
3432
3433static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
3434	.rev_offs	= 0x0400,
3435	.sysc_offs	= 0x0404,
3436	.syss_offs	= 0x0408,
3437	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3438			   SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3439			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3440	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3441			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3442			   MSTANDBY_SMART),
3443	.sysc_fields	= &omap_hwmod_sysc_type1,
3444};
3445
3446static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
3447	.name	= "usb_otg_hs",
3448	.sysc	= &omap44xx_usb_otg_hs_sysc,
3449};
3450
3451/* usb_otg_hs */
3452static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
3453	{ .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
3454	{ .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
3455	{ .irq = -1 }
3456};
3457
3458static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3459	{ .role = "xclk", .clk = "usb_otg_hs_xclk" },
3460};
3461
3462static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3463	.name		= "usb_otg_hs",
3464	.class		= &omap44xx_usb_otg_hs_hwmod_class,
3465	.clkdm_name	= "l3_init_clkdm",
3466	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3467	.mpu_irqs	= omap44xx_usb_otg_hs_irqs,
3468	.main_clk	= "usb_otg_hs_ick",
3469	.prcm = {
3470		.omap4 = {
3471			.clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3472			.context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3473			.modulemode   = MODULEMODE_HWCTRL,
3474		},
3475	},
3476	.opt_clks	= usb_otg_hs_opt_clks,
3477	.opt_clks_cnt	= ARRAY_SIZE(usb_otg_hs_opt_clks),
3478};
3479
3480/*
3481 * 'usb_tll_hs' class
3482 * usb_tll_hs module is the adapter on the usb_host_hs ports
3483 */
3484
3485static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3486	.rev_offs	= 0x0000,
3487	.sysc_offs	= 0x0010,
3488	.syss_offs	= 0x0014,
3489	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3490			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3491			   SYSC_HAS_AUTOIDLE),
3492	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3493	.sysc_fields	= &omap_hwmod_sysc_type1,
3494};
3495
3496static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3497	.name	= "usb_tll_hs",
3498	.sysc	= &omap44xx_usb_tll_hs_sysc,
3499};
3500
3501static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
3502	{ .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
3503	{ .irq = -1 }
3504};
3505
3506static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3507	.name		= "usb_tll_hs",
3508	.class		= &omap44xx_usb_tll_hs_hwmod_class,
3509	.clkdm_name	= "l3_init_clkdm",
3510	.mpu_irqs	= omap44xx_usb_tll_hs_irqs,
3511	.main_clk	= "usb_tll_hs_ick",
3512	.prcm = {
3513		.omap4 = {
3514			.clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3515			.context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3516			.modulemode   = MODULEMODE_HWCTRL,
3517		},
3518	},
3519};
3520
3521/*
3522 * 'wd_timer' class
3523 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3524 * overflow condition
3525 */
3526
3527static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3528	.rev_offs	= 0x0000,
3529	.sysc_offs	= 0x0010,
3530	.syss_offs	= 0x0014,
3531	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3532			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3533	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3534			   SIDLE_SMART_WKUP),
3535	.sysc_fields	= &omap_hwmod_sysc_type1,
3536};
3537
3538static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3539	.name		= "wd_timer",
3540	.sysc		= &omap44xx_wd_timer_sysc,
3541	.pre_shutdown	= &omap2_wd_timer_disable,
3542	.reset		= &omap2_wd_timer_reset,
3543};
3544
3545/* wd_timer2 */
3546static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
3547	{ .irq = 80 + OMAP44XX_IRQ_GIC_START },
3548	{ .irq = -1 }
3549};
3550
3551static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3552	.name		= "wd_timer2",
3553	.class		= &omap44xx_wd_timer_hwmod_class,
3554	.clkdm_name	= "l4_wkup_clkdm",
3555	.mpu_irqs	= omap44xx_wd_timer2_irqs,
3556	.main_clk	= "wd_timer2_fck",
3557	.prcm = {
3558		.omap4 = {
3559			.clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3560			.context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3561			.modulemode   = MODULEMODE_SWCTRL,
3562		},
3563	},
3564};
3565
3566/* wd_timer3 */
3567static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
3568	{ .irq = 36 + OMAP44XX_IRQ_GIC_START },
3569	{ .irq = -1 }
3570};
3571
3572static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3573	.name		= "wd_timer3",
3574	.class		= &omap44xx_wd_timer_hwmod_class,
3575	.clkdm_name	= "abe_clkdm",
3576	.mpu_irqs	= omap44xx_wd_timer3_irqs,
3577	.main_clk	= "wd_timer3_fck",
3578	.prcm = {
3579		.omap4 = {
3580			.clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3581			.context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3582			.modulemode   = MODULEMODE_SWCTRL,
3583		},
3584	},
3585};
3586
3587
3588/*
3589 * interfaces
3590 */
3591
3592static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
3593	{
3594		.pa_start	= 0x4a204000,
3595		.pa_end		= 0x4a2040ff,
3596		.flags		= ADDR_TYPE_RT
3597	},
3598	{ }
3599};
3600
3601/* c2c -> c2c_target_fw */
3602static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
3603	.master		= &omap44xx_c2c_hwmod,
3604	.slave		= &omap44xx_c2c_target_fw_hwmod,
3605	.clk		= "div_core_ck",
3606	.addr		= omap44xx_c2c_target_fw_addrs,
3607	.user		= OCP_USER_MPU,
3608};
3609
3610/* l4_cfg -> c2c_target_fw */
3611static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
3612	.master		= &omap44xx_l4_cfg_hwmod,
3613	.slave		= &omap44xx_c2c_target_fw_hwmod,
3614	.clk		= "l4_div_ck",
3615	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3616};
3617
3618/* l3_main_1 -> dmm */
3619static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3620	.master		= &omap44xx_l3_main_1_hwmod,
3621	.slave		= &omap44xx_dmm_hwmod,
3622	.clk		= "l3_div_ck",
3623	.user		= OCP_USER_SDMA,
3624};
3625
3626static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
3627	{
3628		.pa_start	= 0x4e000000,
3629		.pa_end		= 0x4e0007ff,
3630		.flags		= ADDR_TYPE_RT
3631	},
3632	{ }
3633};
3634
3635/* mpu -> dmm */
3636static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3637	.master		= &omap44xx_mpu_hwmod,
3638	.slave		= &omap44xx_dmm_hwmod,
3639	.clk		= "l3_div_ck",
3640	.addr		= omap44xx_dmm_addrs,
3641	.user		= OCP_USER_MPU,
3642};
3643
3644/* c2c -> emif_fw */
3645static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
3646	.master		= &omap44xx_c2c_hwmod,
3647	.slave		= &omap44xx_emif_fw_hwmod,
3648	.clk		= "div_core_ck",
3649	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3650};
3651
3652/* dmm -> emif_fw */
3653static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
3654	.master		= &omap44xx_dmm_hwmod,
3655	.slave		= &omap44xx_emif_fw_hwmod,
3656	.clk		= "l3_div_ck",
3657	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3658};
3659
3660static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
3661	{
3662		.pa_start	= 0x4a20c000,
3663		.pa_end		= 0x4a20c0ff,
3664		.flags		= ADDR_TYPE_RT
3665	},
3666	{ }
3667};
3668
3669/* l4_cfg -> emif_fw */
3670static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
3671	.master		= &omap44xx_l4_cfg_hwmod,
3672	.slave		= &omap44xx_emif_fw_hwmod,
3673	.clk		= "l4_div_ck",
3674	.addr		= omap44xx_emif_fw_addrs,
3675	.user		= OCP_USER_MPU,
3676};
3677
3678/* iva -> l3_instr */
3679static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3680	.master		= &omap44xx_iva_hwmod,
3681	.slave		= &omap44xx_l3_instr_hwmod,
3682	.clk		= "l3_div_ck",
3683	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3684};
3685
3686/* l3_main_3 -> l3_instr */
3687static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3688	.master		= &omap44xx_l3_main_3_hwmod,
3689	.slave		= &omap44xx_l3_instr_hwmod,
3690	.clk		= "l3_div_ck",
3691	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3692};
3693
3694/* ocp_wp_noc -> l3_instr */
3695static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3696	.master		= &omap44xx_ocp_wp_noc_hwmod,
3697	.slave		= &omap44xx_l3_instr_hwmod,
3698	.clk		= "l3_div_ck",
3699	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3700};
3701
3702/* dsp -> l3_main_1 */
3703static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3704	.master		= &omap44xx_dsp_hwmod,
3705	.slave		= &omap44xx_l3_main_1_hwmod,
3706	.clk		= "l3_div_ck",
3707	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3708};
3709
3710/* dss -> l3_main_1 */
3711static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3712	.master		= &omap44xx_dss_hwmod,
3713	.slave		= &omap44xx_l3_main_1_hwmod,
3714	.clk		= "l3_div_ck",
3715	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3716};
3717
3718/* l3_main_2 -> l3_main_1 */
3719static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3720	.master		= &omap44xx_l3_main_2_hwmod,
3721	.slave		= &omap44xx_l3_main_1_hwmod,
3722	.clk		= "l3_div_ck",
3723	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3724};
3725
3726/* l4_cfg -> l3_main_1 */
3727static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3728	.master		= &omap44xx_l4_cfg_hwmod,
3729	.slave		= &omap44xx_l3_main_1_hwmod,
3730	.clk		= "l4_div_ck",
3731	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3732};
3733
3734/* mmc1 -> l3_main_1 */
3735static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3736	.master		= &omap44xx_mmc1_hwmod,
3737	.slave		= &omap44xx_l3_main_1_hwmod,
3738	.clk		= "l3_div_ck",
3739	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3740};
3741
3742/* mmc2 -> l3_main_1 */
3743static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3744	.master		= &omap44xx_mmc2_hwmod,
3745	.slave		= &omap44xx_l3_main_1_hwmod,
3746	.clk		= "l3_div_ck",
3747	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3748};
3749
3750static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
3751	{
3752		.pa_start	= 0x44000000,
3753		.pa_end		= 0x44000fff,
3754		.flags		= ADDR_TYPE_RT
3755	},
3756	{ }
3757};
3758
3759/* mpu -> l3_main_1 */
3760static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
3761	.master		= &omap44xx_mpu_hwmod,
3762	.slave		= &omap44xx_l3_main_1_hwmod,
3763	.clk		= "l3_div_ck",
3764	.addr		= omap44xx_l3_main_1_addrs,
3765	.user		= OCP_USER_MPU,
3766};
3767
3768/* c2c_target_fw -> l3_main_2 */
3769static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
3770	.master		= &omap44xx_c2c_target_fw_hwmod,
3771	.slave		= &omap44xx_l3_main_2_hwmod,
3772	.clk		= "l3_div_ck",
3773	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3774};
3775
3776/* debugss -> l3_main_2 */
3777static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
3778	.master		= &omap44xx_debugss_hwmod,
3779	.slave		= &omap44xx_l3_main_2_hwmod,
3780	.clk		= "dbgclk_mux_ck",
3781	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3782};
3783
3784/* dma_system -> l3_main_2 */
3785static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
3786	.master		= &omap44xx_dma_system_hwmod,
3787	.slave		= &omap44xx_l3_main_2_hwmod,
3788	.clk		= "l3_div_ck",
3789	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3790};
3791
3792/* fdif -> l3_main_2 */
3793static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
3794	.master		= &omap44xx_fdif_hwmod,
3795	.slave		= &omap44xx_l3_main_2_hwmod,
3796	.clk		= "l3_div_ck",
3797	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3798};
3799
3800/* gpu -> l3_main_2 */
3801static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
3802	.master		= &omap44xx_gpu_hwmod,
3803	.slave		= &omap44xx_l3_main_2_hwmod,
3804	.clk		= "l3_div_ck",
3805	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3806};
3807
3808/* hsi -> l3_main_2 */
3809static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
3810	.master		= &omap44xx_hsi_hwmod,
3811	.slave		= &omap44xx_l3_main_2_hwmod,
3812	.clk		= "l3_div_ck",
3813	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3814};
3815
3816/* ipu -> l3_main_2 */
3817static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
3818	.master		= &omap44xx_ipu_hwmod,
3819	.slave		= &omap44xx_l3_main_2_hwmod,
3820	.clk		= "l3_div_ck",
3821	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3822};
3823
3824/* iss -> l3_main_2 */
3825static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
3826	.master		= &omap44xx_iss_hwmod,
3827	.slave		= &omap44xx_l3_main_2_hwmod,
3828	.clk		= "l3_div_ck",
3829	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3830};
3831
3832/* iva -> l3_main_2 */
3833static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
3834	.master		= &omap44xx_iva_hwmod,
3835	.slave		= &omap44xx_l3_main_2_hwmod,
3836	.clk		= "l3_div_ck",
3837	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3838};
3839
3840static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
3841	{
3842		.pa_start	= 0x44800000,
3843		.pa_end		= 0x44801fff,
3844		.flags		= ADDR_TYPE_RT
3845	},
3846	{ }
3847};
3848
3849/* l3_main_1 -> l3_main_2 */
3850static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
3851	.master		= &omap44xx_l3_main_1_hwmod,
3852	.slave		= &omap44xx_l3_main_2_hwmod,
3853	.clk		= "l3_div_ck",
3854	.addr		= omap44xx_l3_main_2_addrs,
3855	.user		= OCP_USER_MPU,
3856};
3857
3858/* l4_cfg -> l3_main_2 */
3859static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
3860	.master		= &omap44xx_l4_cfg_hwmod,
3861	.slave		= &omap44xx_l3_main_2_hwmod,
3862	.clk		= "l4_div_ck",
3863	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3864};
3865
3866/* usb_host_fs -> l3_main_2 */
3867static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
3868	.master		= &omap44xx_usb_host_fs_hwmod,
3869	.slave		= &omap44xx_l3_main_2_hwmod,
3870	.clk		= "l3_div_ck",
3871	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3872};
3873
3874/* usb_host_hs -> l3_main_2 */
3875static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
3876	.master		= &omap44xx_usb_host_hs_hwmod,
3877	.slave		= &omap44xx_l3_main_2_hwmod,
3878	.clk		= "l3_div_ck",
3879	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3880};
3881
3882/* usb_otg_hs -> l3_main_2 */
3883static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
3884	.master		= &omap44xx_usb_otg_hs_hwmod,
3885	.slave		= &omap44xx_l3_main_2_hwmod,
3886	.clk		= "l3_div_ck",
3887	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3888};
3889
3890static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
3891	{
3892		.pa_start	= 0x45000000,
3893		.pa_end		= 0x45000fff,
3894		.flags		= ADDR_TYPE_RT
3895	},
3896	{ }
3897};
3898
3899/* l3_main_1 -> l3_main_3 */
3900static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
3901	.master		= &omap44xx_l3_main_1_hwmod,
3902	.slave		= &omap44xx_l3_main_3_hwmod,
3903	.clk		= "l3_div_ck",
3904	.addr		= omap44xx_l3_main_3_addrs,
3905	.user		= OCP_USER_MPU,
3906};
3907
3908/* l3_main_2 -> l3_main_3 */
3909static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
3910	.master		= &omap44xx_l3_main_2_hwmod,
3911	.slave		= &omap44xx_l3_main_3_hwmod,
3912	.clk		= "l3_div_ck",
3913	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3914};
3915
3916/* l4_cfg -> l3_main_3 */
3917static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
3918	.master		= &omap44xx_l4_cfg_hwmod,
3919	.slave		= &omap44xx_l3_main_3_hwmod,
3920	.clk		= "l4_div_ck",
3921	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3922};
3923
3924/* aess -> l4_abe */
3925static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
3926	.master		= &omap44xx_aess_hwmod,
3927	.slave		= &omap44xx_l4_abe_hwmod,
3928	.clk		= "ocp_abe_iclk",
3929	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3930};
3931
3932/* dsp -> l4_abe */
3933static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
3934	.master		= &omap44xx_dsp_hwmod,
3935	.slave		= &omap44xx_l4_abe_hwmod,
3936	.clk		= "ocp_abe_iclk",
3937	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3938};
3939
3940/* l3_main_1 -> l4_abe */
3941static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
3942	.master		= &omap44xx_l3_main_1_hwmod,
3943	.slave		= &omap44xx_l4_abe_hwmod,
3944	.clk		= "l3_div_ck",
3945	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3946};
3947
3948/* mpu -> l4_abe */
3949static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
3950	.master		= &omap44xx_mpu_hwmod,
3951	.slave		= &omap44xx_l4_abe_hwmod,
3952	.clk		= "ocp_abe_iclk",
3953	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3954};
3955
3956/* l3_main_1 -> l4_cfg */
3957static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
3958	.master		= &omap44xx_l3_main_1_hwmod,
3959	.slave		= &omap44xx_l4_cfg_hwmod,
3960	.clk		= "l3_div_ck",
3961	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3962};
3963
3964/* l3_main_2 -> l4_per */
3965static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
3966	.master		= &omap44xx_l3_main_2_hwmod,
3967	.slave		= &omap44xx_l4_per_hwmod,
3968	.clk		= "l3_div_ck",
3969	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3970};
3971
3972/* l4_cfg -> l4_wkup */
3973static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
3974	.master		= &omap44xx_l4_cfg_hwmod,
3975	.slave		= &omap44xx_l4_wkup_hwmod,
3976	.clk		= "l4_div_ck",
3977	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3978};
3979
3980/* mpu -> mpu_private */
3981static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
3982	.master		= &omap44xx_mpu_hwmod,
3983	.slave		= &omap44xx_mpu_private_hwmod,
3984	.clk		= "l3_div_ck",
3985	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3986};
3987
3988static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
3989	{
3990		.pa_start	= 0x4a102000,
3991		.pa_end		= 0x4a10207f,
3992		.flags		= ADDR_TYPE_RT
3993	},
3994	{ }
3995};
3996
3997/* l4_cfg -> ocp_wp_noc */
3998static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
3999	.master		= &omap44xx_l4_cfg_hwmod,
4000	.slave		= &omap44xx_ocp_wp_noc_hwmod,
4001	.clk		= "l4_div_ck",
4002	.addr		= omap44xx_ocp_wp_noc_addrs,
4003	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4004};
4005
4006static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
4007	{
4008		.pa_start	= 0x401f1000,
4009		.pa_end		= 0x401f13ff,
4010		.flags		= ADDR_TYPE_RT
4011	},
4012	{ }
4013};
4014
4015/* l4_abe -> aess */
4016static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
4017	.master		= &omap44xx_l4_abe_hwmod,
4018	.slave		= &omap44xx_aess_hwmod,
4019	.clk		= "ocp_abe_iclk",
4020	.addr		= omap44xx_aess_addrs,
4021	.user		= OCP_USER_MPU,
4022};
4023
4024static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
4025	{
4026		.pa_start	= 0x490f1000,
4027		.pa_end		= 0x490f13ff,
4028		.flags		= ADDR_TYPE_RT
4029	},
4030	{ }
4031};
4032
4033/* l4_abe -> aess (dma) */
4034static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
4035	.master		= &omap44xx_l4_abe_hwmod,
4036	.slave		= &omap44xx_aess_hwmod,
4037	.clk		= "ocp_abe_iclk",
4038	.addr		= omap44xx_aess_dma_addrs,
4039	.user		= OCP_USER_SDMA,
4040};
4041
4042/* l3_main_2 -> c2c */
4043static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
4044	.master		= &omap44xx_l3_main_2_hwmod,
4045	.slave		= &omap44xx_c2c_hwmod,
4046	.clk		= "l3_div_ck",
4047	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4048};
4049
4050static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
4051	{
4052		.pa_start	= 0x4a304000,
4053		.pa_end		= 0x4a30401f,
4054		.flags		= ADDR_TYPE_RT
4055	},
4056	{ }
4057};
4058
4059/* l4_wkup -> counter_32k */
4060static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
4061	.master		= &omap44xx_l4_wkup_hwmod,
4062	.slave		= &omap44xx_counter_32k_hwmod,
4063	.clk		= "l4_wkup_clk_mux_ck",
4064	.addr		= omap44xx_counter_32k_addrs,
4065	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4066};
4067
4068static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
4069	{
4070		.pa_start	= 0x4a002000,
4071		.pa_end		= 0x4a0027ff,
4072		.flags		= ADDR_TYPE_RT
4073	},
4074	{ }
4075};
4076
4077/* l4_cfg -> ctrl_module_core */
4078static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
4079	.master		= &omap44xx_l4_cfg_hwmod,
4080	.slave		= &omap44xx_ctrl_module_core_hwmod,
4081	.clk		= "l4_div_ck",
4082	.addr		= omap44xx_ctrl_module_core_addrs,
4083	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4084};
4085
4086static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
4087	{
4088		.pa_start	= 0x4a100000,
4089		.pa_end		= 0x4a1007ff,
4090		.flags		= ADDR_TYPE_RT
4091	},
4092	{ }
4093};
4094
4095/* l4_cfg -> ctrl_module_pad_core */
4096static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
4097	.master		= &omap44xx_l4_cfg_hwmod,
4098	.slave		= &omap44xx_ctrl_module_pad_core_hwmod,
4099	.clk		= "l4_div_ck",
4100	.addr		= omap44xx_ctrl_module_pad_core_addrs,
4101	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4102};
4103
4104static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
4105	{
4106		.pa_start	= 0x4a30c000,
4107		.pa_end		= 0x4a30c7ff,
4108		.flags		= ADDR_TYPE_RT
4109	},
4110	{ }
4111};
4112
4113/* l4_wkup -> ctrl_module_wkup */
4114static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
4115	.master		= &omap44xx_l4_wkup_hwmod,
4116	.slave		= &omap44xx_ctrl_module_wkup_hwmod,
4117	.clk		= "l4_wkup_clk_mux_ck",
4118	.addr		= omap44xx_ctrl_module_wkup_addrs,
4119	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4120};
4121
4122static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
4123	{
4124		.pa_start	= 0x4a31e000,
4125		.pa_end		= 0x4a31e7ff,
4126		.flags		= ADDR_TYPE_RT
4127	},
4128	{ }
4129};
4130
4131/* l4_wkup -> ctrl_module_pad_wkup */
4132static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
4133	.master		= &omap44xx_l4_wkup_hwmod,
4134	.slave		= &omap44xx_ctrl_module_pad_wkup_hwmod,
4135	.clk		= "l4_wkup_clk_mux_ck",
4136	.addr		= omap44xx_ctrl_module_pad_wkup_addrs,
4137	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4138};
4139
4140static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
4141	{
4142		.pa_start	= 0x54160000,
4143		.pa_end		= 0x54167fff,
4144		.flags		= ADDR_TYPE_RT
4145	},
4146	{ }
4147};
4148
4149/* l3_instr -> debugss */
4150static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
4151	.master		= &omap44xx_l3_instr_hwmod,
4152	.slave		= &omap44xx_debugss_hwmod,
4153	.clk		= "l3_div_ck",
4154	.addr		= omap44xx_debugss_addrs,
4155	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4156};
4157
4158static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
4159	{
4160		.pa_start	= 0x4a056000,
4161		.pa_end		= 0x4a056fff,
4162		.flags		= ADDR_TYPE_RT
4163	},
4164	{ }
4165};
4166
4167/* l4_cfg -> dma_system */
4168static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
4169	.master		= &omap44xx_l4_cfg_hwmod,
4170	.slave		= &omap44xx_dma_system_hwmod,
4171	.clk		= "l4_div_ck",
4172	.addr		= omap44xx_dma_system_addrs,
4173	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4174};
4175
4176static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
4177	{
4178		.name		= "mpu",
4179		.pa_start	= 0x4012e000,
4180		.pa_end		= 0x4012e07f,
4181		.flags		= ADDR_TYPE_RT
4182	},
4183	{ }
4184};
4185
4186/* l4_abe -> dmic */
4187static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
4188	.master		= &omap44xx_l4_abe_hwmod,
4189	.slave		= &omap44xx_dmic_hwmod,
4190	.clk		= "ocp_abe_iclk",
4191	.addr		= omap44xx_dmic_addrs,
4192	.user		= OCP_USER_MPU,
4193};
4194
4195static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
4196	{
4197		.name		= "dma",
4198		.pa_start	= 0x4902e000,
4199		.pa_end		= 0x4902e07f,
4200		.flags		= ADDR_TYPE_RT
4201	},
4202	{ }
4203};
4204
4205/* l4_abe -> dmic (dma) */
4206static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
4207	.master		= &omap44xx_l4_abe_hwmod,
4208	.slave		= &omap44xx_dmic_hwmod,
4209	.clk		= "ocp_abe_iclk",
4210	.addr		= omap44xx_dmic_dma_addrs,
4211	.user		= OCP_USER_SDMA,
4212};
4213
4214/* dsp -> iva */
4215static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
4216	.master		= &omap44xx_dsp_hwmod,
4217	.slave		= &omap44xx_iva_hwmod,
4218	.clk		= "dpll_iva_m5x2_ck",
4219	.user		= OCP_USER_DSP,
4220};
4221
4222/* dsp -> sl2if */
4223static struct omap_hwmod_ocp_if omap44xx_dsp__sl2if = {
4224	.master		= &omap44xx_dsp_hwmod,
4225	.slave		= &omap44xx_sl2if_hwmod,
4226	.clk		= "dpll_iva_m5x2_ck",
4227	.user		= OCP_USER_DSP,
4228};
4229
4230/* l4_cfg -> dsp */
4231static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
4232	.master		= &omap44xx_l4_cfg_hwmod,
4233	.slave		= &omap44xx_dsp_hwmod,
4234	.clk		= "l4_div_ck",
4235	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4236};
4237
4238static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
4239	{
4240		.pa_start	= 0x58000000,
4241		.pa_end		= 0x5800007f,
4242		.flags		= ADDR_TYPE_RT
4243	},
4244	{ }
4245};
4246
4247/* l3_main_2 -> dss */
4248static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
4249	.master		= &omap44xx_l3_main_2_hwmod,
4250	.slave		= &omap44xx_dss_hwmod,
4251	.clk		= "dss_fck",
4252	.addr		= omap44xx_dss_dma_addrs,
4253	.user		= OCP_USER_SDMA,
4254};
4255
4256static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
4257	{
4258		.pa_start	= 0x48040000,
4259		.pa_end		= 0x4804007f,
4260		.flags		= ADDR_TYPE_RT
4261	},
4262	{ }
4263};
4264
4265/* l4_per -> dss */
4266static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
4267	.master		= &omap44xx_l4_per_hwmod,
4268	.slave		= &omap44xx_dss_hwmod,
4269	.clk		= "l4_div_ck",
4270	.addr		= omap44xx_dss_addrs,
4271	.user		= OCP_USER_MPU,
4272};
4273
4274static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
4275	{
4276		.pa_start	= 0x58001000,
4277		.pa_end		= 0x58001fff,
4278		.flags		= ADDR_TYPE_RT
4279	},
4280	{ }
4281};
4282
4283/* l3_main_2 -> dss_dispc */
4284static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
4285	.master		= &omap44xx_l3_main_2_hwmod,
4286	.slave		= &omap44xx_dss_dispc_hwmod,
4287	.clk		= "dss_fck",
4288	.addr		= omap44xx_dss_dispc_dma_addrs,
4289	.user		= OCP_USER_SDMA,
4290};
4291
4292static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
4293	{
4294		.pa_start	= 0x48041000,
4295		.pa_end		= 0x48041fff,
4296		.flags		= ADDR_TYPE_RT
4297	},
4298	{ }
4299};
4300
4301/* l4_per -> dss_dispc */
4302static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
4303	.master		= &omap44xx_l4_per_hwmod,
4304	.slave		= &omap44xx_dss_dispc_hwmod,
4305	.clk		= "l4_div_ck",
4306	.addr		= omap44xx_dss_dispc_addrs,
4307	.user		= OCP_USER_MPU,
4308};
4309
4310static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
4311	{
4312		.pa_start	= 0x58004000,
4313		.pa_end		= 0x580041ff,
4314		.flags		= ADDR_TYPE_RT
4315	},
4316	{ }
4317};
4318
4319/* l3_main_2 -> dss_dsi1 */
4320static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
4321	.master		= &omap44xx_l3_main_2_hwmod,
4322	.slave		= &omap44xx_dss_dsi1_hwmod,
4323	.clk		= "dss_fck",
4324	.addr		= omap44xx_dss_dsi1_dma_addrs,
4325	.user		= OCP_USER_SDMA,
4326};
4327
4328static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
4329	{
4330		.pa_start	= 0x48044000,
4331		.pa_end		= 0x480441ff,
4332		.flags		= ADDR_TYPE_RT
4333	},
4334	{ }
4335};
4336
4337/* l4_per -> dss_dsi1 */
4338static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
4339	.master		= &omap44xx_l4_per_hwmod,
4340	.slave		= &omap44xx_dss_dsi1_hwmod,
4341	.clk		= "l4_div_ck",
4342	.addr		= omap44xx_dss_dsi1_addrs,
4343	.user		= OCP_USER_MPU,
4344};
4345
4346static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
4347	{
4348		.pa_start	= 0x58005000,
4349		.pa_end		= 0x580051ff,
4350		.flags		= ADDR_TYPE_RT
4351	},
4352	{ }
4353};
4354
4355/* l3_main_2 -> dss_dsi2 */
4356static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
4357	.master		= &omap44xx_l3_main_2_hwmod,
4358	.slave		= &omap44xx_dss_dsi2_hwmod,
4359	.clk		= "dss_fck",
4360	.addr		= omap44xx_dss_dsi2_dma_addrs,
4361	.user		= OCP_USER_SDMA,
4362};
4363
4364static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
4365	{
4366		.pa_start	= 0x48045000,
4367		.pa_end		= 0x480451ff,
4368		.flags		= ADDR_TYPE_RT
4369	},
4370	{ }
4371};
4372
4373/* l4_per -> dss_dsi2 */
4374static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
4375	.master		= &omap44xx_l4_per_hwmod,
4376	.slave		= &omap44xx_dss_dsi2_hwmod,
4377	.clk		= "l4_div_ck",
4378	.addr		= omap44xx_dss_dsi2_addrs,
4379	.user		= OCP_USER_MPU,
4380};
4381
4382static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
4383	{
4384		.pa_start	= 0x58006000,
4385		.pa_end		= 0x58006fff,
4386		.flags		= ADDR_TYPE_RT
4387	},
4388	{ }
4389};
4390
4391/* l3_main_2 -> dss_hdmi */
4392static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
4393	.master		= &omap44xx_l3_main_2_hwmod,
4394	.slave		= &omap44xx_dss_hdmi_hwmod,
4395	.clk		= "dss_fck",
4396	.addr		= omap44xx_dss_hdmi_dma_addrs,
4397	.user		= OCP_USER_SDMA,
4398};
4399
4400static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
4401	{
4402		.pa_start	= 0x48046000,
4403		.pa_end		= 0x48046fff,
4404		.flags		= ADDR_TYPE_RT
4405	},
4406	{ }
4407};
4408
4409/* l4_per -> dss_hdmi */
4410static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
4411	.master		= &omap44xx_l4_per_hwmod,
4412	.slave		= &omap44xx_dss_hdmi_hwmod,
4413	.clk		= "l4_div_ck",
4414	.addr		= omap44xx_dss_hdmi_addrs,
4415	.user		= OCP_USER_MPU,
4416};
4417
4418static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
4419	{
4420		.pa_start	= 0x58002000,
4421		.pa_end		= 0x580020ff,
4422		.flags		= ADDR_TYPE_RT
4423	},
4424	{ }
4425};
4426
4427/* l3_main_2 -> dss_rfbi */
4428static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
4429	.master		= &omap44xx_l3_main_2_hwmod,
4430	.slave		= &omap44xx_dss_rfbi_hwmod,
4431	.clk		= "dss_fck",
4432	.addr		= omap44xx_dss_rfbi_dma_addrs,
4433	.user		= OCP_USER_SDMA,
4434};
4435
4436static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
4437	{
4438		.pa_start	= 0x48042000,
4439		.pa_end		= 0x480420ff,
4440		.flags		= ADDR_TYPE_RT
4441	},
4442	{ }
4443};
4444
4445/* l4_per -> dss_rfbi */
4446static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
4447	.master		= &omap44xx_l4_per_hwmod,
4448	.slave		= &omap44xx_dss_rfbi_hwmod,
4449	.clk		= "l4_div_ck",
4450	.addr		= omap44xx_dss_rfbi_addrs,
4451	.user		= OCP_USER_MPU,
4452};
4453
4454static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
4455	{
4456		.pa_start	= 0x58003000,
4457		.pa_end		= 0x580030ff,
4458		.flags		= ADDR_TYPE_RT
4459	},
4460	{ }
4461};
4462
4463/* l3_main_2 -> dss_venc */
4464static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
4465	.master		= &omap44xx_l3_main_2_hwmod,
4466	.slave		= &omap44xx_dss_venc_hwmod,
4467	.clk		= "dss_fck",
4468	.addr		= omap44xx_dss_venc_dma_addrs,
4469	.user		= OCP_USER_SDMA,
4470};
4471
4472static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
4473	{
4474		.pa_start	= 0x48043000,
4475		.pa_end		= 0x480430ff,
4476		.flags		= ADDR_TYPE_RT
4477	},
4478	{ }
4479};
4480
4481/* l4_per -> dss_venc */
4482static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
4483	.master		= &omap44xx_l4_per_hwmod,
4484	.slave		= &omap44xx_dss_venc_hwmod,
4485	.clk		= "l4_div_ck",
4486	.addr		= omap44xx_dss_venc_addrs,
4487	.user		= OCP_USER_MPU,
4488};
4489
4490static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
4491	{
4492		.pa_start	= 0x48078000,
4493		.pa_end		= 0x48078fff,
4494		.flags		= ADDR_TYPE_RT
4495	},
4496	{ }
4497};
4498
4499/* l4_per -> elm */
4500static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
4501	.master		= &omap44xx_l4_per_hwmod,
4502	.slave		= &omap44xx_elm_hwmod,
4503	.clk		= "l4_div_ck",
4504	.addr		= omap44xx_elm_addrs,
4505	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4506};
4507
4508static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
4509	{
4510		.pa_start	= 0x4c000000,
4511		.pa_end		= 0x4c0000ff,
4512		.flags		= ADDR_TYPE_RT
4513	},
4514	{ }
4515};
4516
4517/* emif_fw -> emif1 */
4518static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
4519	.master		= &omap44xx_emif_fw_hwmod,
4520	.slave		= &omap44xx_emif1_hwmod,
4521	.clk		= "l3_div_ck",
4522	.addr		= omap44xx_emif1_addrs,
4523	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4524};
4525
4526static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
4527	{
4528		.pa_start	= 0x4d000000,
4529		.pa_end		= 0x4d0000ff,
4530		.flags		= ADDR_TYPE_RT
4531	},
4532	{ }
4533};
4534
4535/* emif_fw -> emif2 */
4536static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
4537	.master		= &omap44xx_emif_fw_hwmod,
4538	.slave		= &omap44xx_emif2_hwmod,
4539	.clk		= "l3_div_ck",
4540	.addr		= omap44xx_emif2_addrs,
4541	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4542};
4543
4544static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
4545	{
4546		.pa_start	= 0x4a10a000,
4547		.pa_end		= 0x4a10a1ff,
4548		.flags		= ADDR_TYPE_RT
4549	},
4550	{ }
4551};
4552
4553/* l4_cfg -> fdif */
4554static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
4555	.master		= &omap44xx_l4_cfg_hwmod,
4556	.slave		= &omap44xx_fdif_hwmod,
4557	.clk		= "l4_div_ck",
4558	.addr		= omap44xx_fdif_addrs,
4559	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4560};
4561
4562static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
4563	{
4564		.pa_start	= 0x4a310000,
4565		.pa_end		= 0x4a3101ff,
4566		.flags		= ADDR_TYPE_RT
4567	},
4568	{ }
4569};
4570
4571/* l4_wkup -> gpio1 */
4572static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
4573	.master		= &omap44xx_l4_wkup_hwmod,
4574	.slave		= &omap44xx_gpio1_hwmod,
4575	.clk		= "l4_wkup_clk_mux_ck",
4576	.addr		= omap44xx_gpio1_addrs,
4577	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4578};
4579
4580static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
4581	{
4582		.pa_start	= 0x48055000,
4583		.pa_end		= 0x480551ff,
4584		.flags		= ADDR_TYPE_RT
4585	},
4586	{ }
4587};
4588
4589/* l4_per -> gpio2 */
4590static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
4591	.master		= &omap44xx_l4_per_hwmod,
4592	.slave		= &omap44xx_gpio2_hwmod,
4593	.clk		= "l4_div_ck",
4594	.addr		= omap44xx_gpio2_addrs,
4595	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4596};
4597
4598static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
4599	{
4600		.pa_start	= 0x48057000,
4601		.pa_end		= 0x480571ff,
4602		.flags		= ADDR_TYPE_RT
4603	},
4604	{ }
4605};
4606
4607/* l4_per -> gpio3 */
4608static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
4609	.master		= &omap44xx_l4_per_hwmod,
4610	.slave		= &omap44xx_gpio3_hwmod,
4611	.clk		= "l4_div_ck",
4612	.addr		= omap44xx_gpio3_addrs,
4613	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4614};
4615
4616static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
4617	{
4618		.pa_start	= 0x48059000,
4619		.pa_end		= 0x480591ff,
4620		.flags		= ADDR_TYPE_RT
4621	},
4622	{ }
4623};
4624
4625/* l4_per -> gpio4 */
4626static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
4627	.master		= &omap44xx_l4_per_hwmod,
4628	.slave		= &omap44xx_gpio4_hwmod,
4629	.clk		= "l4_div_ck",
4630	.addr		= omap44xx_gpio4_addrs,
4631	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4632};
4633
4634static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
4635	{
4636		.pa_start	= 0x4805b000,
4637		.pa_end		= 0x4805b1ff,
4638		.flags		= ADDR_TYPE_RT
4639	},
4640	{ }
4641};
4642
4643/* l4_per -> gpio5 */
4644static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
4645	.master		= &omap44xx_l4_per_hwmod,
4646	.slave		= &omap44xx_gpio5_hwmod,
4647	.clk		= "l4_div_ck",
4648	.addr		= omap44xx_gpio5_addrs,
4649	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4650};
4651
4652static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
4653	{
4654		.pa_start	= 0x4805d000,
4655		.pa_end		= 0x4805d1ff,
4656		.flags		= ADDR_TYPE_RT
4657	},
4658	{ }
4659};
4660
4661/* l4_per -> gpio6 */
4662static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
4663	.master		= &omap44xx_l4_per_hwmod,
4664	.slave		= &omap44xx_gpio6_hwmod,
4665	.clk		= "l4_div_ck",
4666	.addr		= omap44xx_gpio6_addrs,
4667	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4668};
4669
4670static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
4671	{
4672		.pa_start	= 0x50000000,
4673		.pa_end		= 0x500003ff,
4674		.flags		= ADDR_TYPE_RT
4675	},
4676	{ }
4677};
4678
4679/* l3_main_2 -> gpmc */
4680static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4681	.master		= &omap44xx_l3_main_2_hwmod,
4682	.slave		= &omap44xx_gpmc_hwmod,
4683	.clk		= "l3_div_ck",
4684	.addr		= omap44xx_gpmc_addrs,
4685	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4686};
4687
4688static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4689	{
4690		.pa_start	= 0x56000000,
4691		.pa_end		= 0x5600ffff,
4692		.flags		= ADDR_TYPE_RT
4693	},
4694	{ }
4695};
4696
4697/* l3_main_2 -> gpu */
4698static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4699	.master		= &omap44xx_l3_main_2_hwmod,
4700	.slave		= &omap44xx_gpu_hwmod,
4701	.clk		= "l3_div_ck",
4702	.addr		= omap44xx_gpu_addrs,
4703	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4704};
4705
4706static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
4707	{
4708		.pa_start	= 0x480b2000,
4709		.pa_end		= 0x480b201f,
4710		.flags		= ADDR_TYPE_RT
4711	},
4712	{ }
4713};
4714
4715/* l4_per -> hdq1w */
4716static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
4717	.master		= &omap44xx_l4_per_hwmod,
4718	.slave		= &omap44xx_hdq1w_hwmod,
4719	.clk		= "l4_div_ck",
4720	.addr		= omap44xx_hdq1w_addrs,
4721	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4722};
4723
4724static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
4725	{
4726		.pa_start	= 0x4a058000,
4727		.pa_end		= 0x4a05bfff,
4728		.flags		= ADDR_TYPE_RT
4729	},
4730	{ }
4731};
4732
4733/* l4_cfg -> hsi */
4734static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
4735	.master		= &omap44xx_l4_cfg_hwmod,
4736	.slave		= &omap44xx_hsi_hwmod,
4737	.clk		= "l4_div_ck",
4738	.addr		= omap44xx_hsi_addrs,
4739	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4740};
4741
4742static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
4743	{
4744		.pa_start	= 0x48070000,
4745		.pa_end		= 0x480700ff,
4746		.flags		= ADDR_TYPE_RT
4747	},
4748	{ }
4749};
4750
4751/* l4_per -> i2c1 */
4752static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
4753	.master		= &omap44xx_l4_per_hwmod,
4754	.slave		= &omap44xx_i2c1_hwmod,
4755	.clk		= "l4_div_ck",
4756	.addr		= omap44xx_i2c1_addrs,
4757	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4758};
4759
4760static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
4761	{
4762		.pa_start	= 0x48072000,
4763		.pa_end		= 0x480720ff,
4764		.flags		= ADDR_TYPE_RT
4765	},
4766	{ }
4767};
4768
4769/* l4_per -> i2c2 */
4770static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
4771	.master		= &omap44xx_l4_per_hwmod,
4772	.slave		= &omap44xx_i2c2_hwmod,
4773	.clk		= "l4_div_ck",
4774	.addr		= omap44xx_i2c2_addrs,
4775	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4776};
4777
4778static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
4779	{
4780		.pa_start	= 0x48060000,
4781		.pa_end		= 0x480600ff,
4782		.flags		= ADDR_TYPE_RT
4783	},
4784	{ }
4785};
4786
4787/* l4_per -> i2c3 */
4788static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
4789	.master		= &omap44xx_l4_per_hwmod,
4790	.slave		= &omap44xx_i2c3_hwmod,
4791	.clk		= "l4_div_ck",
4792	.addr		= omap44xx_i2c3_addrs,
4793	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4794};
4795
4796static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
4797	{
4798		.pa_start	= 0x48350000,
4799		.pa_end		= 0x483500ff,
4800		.flags		= ADDR_TYPE_RT
4801	},
4802	{ }
4803};
4804
4805/* l4_per -> i2c4 */
4806static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
4807	.master		= &omap44xx_l4_per_hwmod,
4808	.slave		= &omap44xx_i2c4_hwmod,
4809	.clk		= "l4_div_ck",
4810	.addr		= omap44xx_i2c4_addrs,
4811	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4812};
4813
4814/* l3_main_2 -> ipu */
4815static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
4816	.master		= &omap44xx_l3_main_2_hwmod,
4817	.slave		= &omap44xx_ipu_hwmod,
4818	.clk		= "l3_div_ck",
4819	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4820};
4821
4822static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
4823	{
4824		.pa_start	= 0x52000000,
4825		.pa_end		= 0x520000ff,
4826		.flags		= ADDR_TYPE_RT
4827	},
4828	{ }
4829};
4830
4831/* l3_main_2 -> iss */
4832static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
4833	.master		= &omap44xx_l3_main_2_hwmod,
4834	.slave		= &omap44xx_iss_hwmod,
4835	.clk		= "l3_div_ck",
4836	.addr		= omap44xx_iss_addrs,
4837	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4838};
4839
4840/* iva -> sl2if */
4841static struct omap_hwmod_ocp_if omap44xx_iva__sl2if = {
4842	.master		= &omap44xx_iva_hwmod,
4843	.slave		= &omap44xx_sl2if_hwmod,
4844	.clk		= "dpll_iva_m5x2_ck",
4845	.user		= OCP_USER_IVA,
4846};
4847
4848static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
4849	{
4850		.pa_start	= 0x5a000000,
4851		.pa_end		= 0x5a07ffff,
4852		.flags		= ADDR_TYPE_RT
4853	},
4854	{ }
4855};
4856
4857/* l3_main_2 -> iva */
4858static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
4859	.master		= &omap44xx_l3_main_2_hwmod,
4860	.slave		= &omap44xx_iva_hwmod,
4861	.clk		= "l3_div_ck",
4862	.addr		= omap44xx_iva_addrs,
4863	.user		= OCP_USER_MPU,
4864};
4865
4866static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
4867	{
4868		.pa_start	= 0x4a31c000,
4869		.pa_end		= 0x4a31c07f,
4870		.flags		= ADDR_TYPE_RT
4871	},
4872	{ }
4873};
4874
4875/* l4_wkup -> kbd */
4876static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
4877	.master		= &omap44xx_l4_wkup_hwmod,
4878	.slave		= &omap44xx_kbd_hwmod,
4879	.clk		= "l4_wkup_clk_mux_ck",
4880	.addr		= omap44xx_kbd_addrs,
4881	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4882};
4883
4884static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
4885	{
4886		.pa_start	= 0x4a0f4000,
4887		.pa_end		= 0x4a0f41ff,
4888		.flags		= ADDR_TYPE_RT
4889	},
4890	{ }
4891};
4892
4893/* l4_cfg -> mailbox */
4894static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
4895	.master		= &omap44xx_l4_cfg_hwmod,
4896	.slave		= &omap44xx_mailbox_hwmod,
4897	.clk		= "l4_div_ck",
4898	.addr		= omap44xx_mailbox_addrs,
4899	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4900};
4901
4902static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
4903	{
4904		.pa_start	= 0x40128000,
4905		.pa_end		= 0x401283ff,
4906		.flags		= ADDR_TYPE_RT
4907	},
4908	{ }
4909};
4910
4911/* l4_abe -> mcasp */
4912static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
4913	.master		= &omap44xx_l4_abe_hwmod,
4914	.slave		= &omap44xx_mcasp_hwmod,
4915	.clk		= "ocp_abe_iclk",
4916	.addr		= omap44xx_mcasp_addrs,
4917	.user		= OCP_USER_MPU,
4918};
4919
4920static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
4921	{
4922		.pa_start	= 0x49028000,
4923		.pa_end		= 0x490283ff,
4924		.flags		= ADDR_TYPE_RT
4925	},
4926	{ }
4927};
4928
4929/* l4_abe -> mcasp (dma) */
4930static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
4931	.master		= &omap44xx_l4_abe_hwmod,
4932	.slave		= &omap44xx_mcasp_hwmod,
4933	.clk		= "ocp_abe_iclk",
4934	.addr		= omap44xx_mcasp_dma_addrs,
4935	.user		= OCP_USER_SDMA,
4936};
4937
4938static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
4939	{
4940		.name		= "mpu",
4941		.pa_start	= 0x40122000,
4942		.pa_end		= 0x401220ff,
4943		.flags		= ADDR_TYPE_RT
4944	},
4945	{ }
4946};
4947
4948/* l4_abe -> mcbsp1 */
4949static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
4950	.master		= &omap44xx_l4_abe_hwmod,
4951	.slave		= &omap44xx_mcbsp1_hwmod,
4952	.clk		= "ocp_abe_iclk",
4953	.addr		= omap44xx_mcbsp1_addrs,
4954	.user		= OCP_USER_MPU,
4955};
4956
4957static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
4958	{
4959		.name		= "dma",
4960		.pa_start	= 0x49022000,
4961		.pa_end		= 0x490220ff,
4962		.flags		= ADDR_TYPE_RT
4963	},
4964	{ }
4965};
4966
4967/* l4_abe -> mcbsp1 (dma) */
4968static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
4969	.master		= &omap44xx_l4_abe_hwmod,
4970	.slave		= &omap44xx_mcbsp1_hwmod,
4971	.clk		= "ocp_abe_iclk",
4972	.addr		= omap44xx_mcbsp1_dma_addrs,
4973	.user		= OCP_USER_SDMA,
4974};
4975
4976static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
4977	{
4978		.name		= "mpu",
4979		.pa_start	= 0x40124000,
4980		.pa_end		= 0x401240ff,
4981		.flags		= ADDR_TYPE_RT
4982	},
4983	{ }
4984};
4985
4986/* l4_abe -> mcbsp2 */
4987static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
4988	.master		= &omap44xx_l4_abe_hwmod,
4989	.slave		= &omap44xx_mcbsp2_hwmod,
4990	.clk		= "ocp_abe_iclk",
4991	.addr		= omap44xx_mcbsp2_addrs,
4992	.user		= OCP_USER_MPU,
4993};
4994
4995static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
4996	{
4997		.name		= "dma",
4998		.pa_start	= 0x49024000,
4999		.pa_end		= 0x490240ff,
5000		.flags		= ADDR_TYPE_RT
5001	},
5002	{ }
5003};
5004
5005/* l4_abe -> mcbsp2 (dma) */
5006static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
5007	.master		= &omap44xx_l4_abe_hwmod,
5008	.slave		= &omap44xx_mcbsp2_hwmod,
5009	.clk		= "ocp_abe_iclk",
5010	.addr		= omap44xx_mcbsp2_dma_addrs,
5011	.user		= OCP_USER_SDMA,
5012};
5013
5014static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
5015	{
5016		.name		= "mpu",
5017		.pa_start	= 0x40126000,
5018		.pa_end		= 0x401260ff,
5019		.flags		= ADDR_TYPE_RT
5020	},
5021	{ }
5022};
5023
5024/* l4_abe -> mcbsp3 */
5025static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
5026	.master		= &omap44xx_l4_abe_hwmod,
5027	.slave		= &omap44xx_mcbsp3_hwmod,
5028	.clk		= "ocp_abe_iclk",
5029	.addr		= omap44xx_mcbsp3_addrs,
5030	.user		= OCP_USER_MPU,
5031};
5032
5033static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
5034	{
5035		.name		= "dma",
5036		.pa_start	= 0x49026000,
5037		.pa_end		= 0x490260ff,
5038		.flags		= ADDR_TYPE_RT
5039	},
5040	{ }
5041};
5042
5043/* l4_abe -> mcbsp3 (dma) */
5044static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
5045	.master		= &omap44xx_l4_abe_hwmod,
5046	.slave		= &omap44xx_mcbsp3_hwmod,
5047	.clk		= "ocp_abe_iclk",
5048	.addr		= omap44xx_mcbsp3_dma_addrs,
5049	.user		= OCP_USER_SDMA,
5050};
5051
5052static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
5053	{
5054		.pa_start	= 0x48096000,
5055		.pa_end		= 0x480960ff,
5056		.flags		= ADDR_TYPE_RT
5057	},
5058	{ }
5059};
5060
5061/* l4_per -> mcbsp4 */
5062static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
5063	.master		= &omap44xx_l4_per_hwmod,
5064	.slave		= &omap44xx_mcbsp4_hwmod,
5065	.clk		= "l4_div_ck",
5066	.addr		= omap44xx_mcbsp4_addrs,
5067	.user		= OCP_USER_MPU | OCP_USER_SDMA,
5068};
5069
5070static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
5071	{
5072		.pa_start	= 0x40132000,
5073		.pa_end		= 0x4013207f,
5074		.flags		= ADDR_TYPE_RT
5075	},
5076	{ }
5077};
5078
5079/* l4_abe -> mcpdm */
5080static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
5081	.master		= &omap44xx_l4_abe_hwmod,
5082	.slave		= &omap44xx_mcpdm_hwmod,
5083	.clk		= "ocp_abe_iclk",
5084	.addr		= omap44xx_mcpdm_addrs,
5085	.user		= OCP_USER_MPU,
5086};
5087
5088static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
5089	{
5090		.pa_start	= 0x49032000,
5091		.pa_end		= 0x4903207f,
5092		.flags		= ADDR_TYPE_RT
5093	},
5094	{ }
5095};
5096
5097/* l4_abe -> mcpdm (dma) */
5098static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
5099	.master		= &omap44xx_l4_abe_hwmod,
5100	.slave		= &omap44xx_mcpdm_hwmod,
5101	.clk		= "ocp_abe_iclk",
5102	.addr		= omap44xx_mcpdm_dma_addrs,
5103	.user		= OCP_USER_SDMA,
5104};
5105
5106static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
5107	{
5108		.pa_start	= 0x48098000,
5109		.pa_end		= 0x480981ff,
5110		.flags		= ADDR_TYPE_RT
5111	},
5112	{ }
5113};
5114
5115/* l4_per -> mcspi1 */
5116static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
5117	.master		= &omap44xx_l4_per_hwmod,
5118	.slave		= &omap44xx_mcspi1_hwmod,
5119	.clk		= "l4_div_ck",
5120	.addr		= omap44xx_mcspi1_addrs,
5121	.user		= OCP_USER_MPU | OCP_USER_SDMA,
5122};
5123
5124static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
5125	{
5126		.pa_start	= 0x4809a000,
5127		.pa_end		= 0x4809a1ff,
5128		.flags		= ADDR_TYPE_RT
5129	},
5130	{ }
5131};
5132
5133/* l4_per -> mcspi2 */
5134static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
5135	.master		= &omap44xx_l4_per_hwmod,
5136	.slave		= &omap44xx_mcspi2_hwmod,
5137	.clk		= "l4_div_ck",
5138	.addr		= omap44xx_mcspi2_addrs,
5139	.user		= OCP_USER_MPU | OCP_USER_SDMA,
5140};
5141
5142static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
5143	{
5144		.pa_start	= 0x480b8000,
5145		.pa_end		= 0x480b81ff,
5146		.flags		= ADDR_TYPE_RT
5147	},
5148	{ }
5149};
5150
5151/* l4_per -> mcspi3 */
5152static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
5153	.master		= &omap44xx_l4_per_hwmod,
5154	.slave		= &omap44xx_mcspi3_hwmod,
5155	.clk		= "l4_div_ck",
5156	.addr		= omap44xx_mcspi3_addrs,
5157	.user		= OCP_USER_MPU | OCP_USER_SDMA,
5158};
5159
5160static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
5161	{
5162		.pa_start	= 0x480ba000,
5163		.pa_end		= 0x480ba1ff,
5164		.flags		= ADDR_TYPE_RT
5165	},
5166	{ }
5167};
5168
5169/* l4_per -> mcspi4 */
5170static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
5171	.master		= &omap44xx_l4_per_hwmod,
5172	.slave		= &omap44xx_mcspi4_hwmod,
5173	.clk		= "l4_div_ck",
5174	.addr		= omap44xx_mcspi4_addrs,
5175	.user		= OCP_USER_MPU | OCP_USER_SDMA,
5176};
5177
5178static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
5179	{
5180		.pa_start	= 0x4809c000,
5181		.pa_end		= 0x4809c3ff,
5182		.flags		= ADDR_TYPE_RT
5183	},
5184	{ }
5185};
5186
5187/* l4_per -> mmc1 */
5188static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
5189	.master		= &omap44xx_l4_per_hwmod,
5190	.slave		= &omap44xx_mmc1_hwmod,
5191	.clk		= "l4_div_ck",
5192	.addr		= omap44xx_mmc1_addrs,
5193	.user		= OCP_USER_MPU | OCP_USER_SDMA,
5194};
5195
5196static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
5197	{
5198		.pa_start	= 0x480b4000,
5199		.pa_end		= 0x480b43ff,
5200		.flags		= ADDR_TYPE_RT
5201	},
5202	{ }
5203};
5204
5205/* l4_per -> mmc2 */
5206static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
5207	.master		= &omap44xx_l4_per_hwmod,
5208	.slave		= &omap44xx_mmc2_hwmod,
5209	.clk		= "l4_div_ck",
5210	.addr		= omap44xx_mmc2_addrs,
5211	.user		= OCP_USER_MPU | OCP_USER_SDMA,
5212};
5213
5214static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
5215	{
5216		.pa_start	= 0x480ad000,
5217		.pa_end		= 0x480ad3ff,
5218		.flags		= ADDR_TYPE_RT
5219	},
5220	{ }
5221};
5222
5223/* l4_per -> mmc3 */
5224static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
5225	.master		= &omap44xx_l4_per_hwmod,
5226	.slave		= &omap44xx_mmc3_hwmod,
5227	.clk		= "l4_div_ck",
5228	.addr		= omap44xx_mmc3_addrs,
5229	.user		= OCP_USER_MPU | OCP_USER_SDMA,
5230};
5231
5232static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
5233	{
5234		.pa_start	= 0x480d1000,
5235		.pa_end		= 0x480d13ff,
5236		.flags		= ADDR_TYPE_RT
5237	},
5238	{ }
5239};
5240
5241/* l4_per -> mmc4 */
5242static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
5243	.master		= &omap44xx_l4_per_hwmod,
5244	.slave		= &omap44xx_mmc4_hwmod,
5245	.clk		= "l4_div_ck",
5246	.addr		= omap44xx_mmc4_addrs,
5247	.user		= OCP_USER_MPU | OCP_USER_SDMA,
5248};
5249
5250static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
5251	{
5252		.pa_start	= 0x480d5000,
5253		.pa_end		= 0x480d53ff,
5254		.flags		= ADDR_TYPE_RT
5255	},
5256	{ }
5257};
5258
5259/* l4_per -> mmc5 */
5260static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
5261	.master		= &omap44xx_l4_per_hwmod,
5262	.slave		= &omap44xx_mmc5_hwmod,
5263	.clk		= "l4_div_ck",
5264	.addr		= omap44xx_mmc5_addrs,
5265	.user		= OCP_USER_MPU | OCP_USER_SDMA,
5266};
5267
5268/* l3_main_2 -> ocmc_ram */
5269static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
5270	.master		= &omap44xx_l3_main_2_hwmod,
5271	.slave		= &omap44xx_ocmc_ram_hwmod,
5272	.clk		= "l3_div_ck",
5273	.user		= OCP_USER_MPU | OCP_USER_SDMA,
5274};
5275
5276/* l4_cfg -> ocp2scp_usb_phy */
5277static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
5278	.master		= &omap44xx_l4_cfg_hwmod,
5279	.slave		= &omap44xx_ocp2scp_usb_phy_hwmod,
5280	.clk		= "l4_div_ck",
5281	.user		= OCP_USER_MPU | OCP_USER_SDMA,
5282};
5283
5284static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
5285	{
5286		.pa_start	= 0x48243000,
5287		.pa_end		= 0x48243fff,
5288		.flags		= ADDR_TYPE_RT
5289	},
5290	{ }
5291};
5292
5293/* mpu_private -> prcm_mpu */
5294static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
5295	.master		= &omap44xx_mpu_private_hwmod,
5296	.slave		= &omap44xx_prcm_mpu_hwmod,
5297	.clk		= "l3_div_ck",
5298	.addr		= omap44xx_prcm_mpu_addrs,
5299	.user		= OCP_USER_MPU | OCP_USER_SDMA,
5300};
5301
5302static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
5303	{
5304		.pa_start	= 0x4a004000,
5305		.pa_end		= 0x4a004fff,
5306		.flags		= ADDR_TYPE_RT
5307	},
5308	{ }
5309};
5310
5311/* l4_wkup -> cm_core_aon */
5312static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
5313	.master		= &omap44xx_l4_wkup_hwmod,
5314	.slave		= &omap44xx_cm_core_aon_hwmod,
5315	.clk		= "l4_wkup_clk_mux_ck",
5316	.addr		= omap44xx_cm_core_aon_addrs,
5317	.user		= OCP_USER_MPU | OCP_USER_SDMA,
5318};
5319
5320static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
5321	{
5322		.pa_start	= 0x4a008000,
5323		.pa_end		= 0x4a009fff,
5324		.flags		= ADDR_TYPE_RT
5325	},
5326	{ }
5327};
5328
5329/* l4_cfg -> cm_core */
5330static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
5331	.master		= &omap44xx_l4_cfg_hwmod,
5332	.slave		= &omap44xx_cm_core_hwmod,
5333	.clk		= "l4_div_ck",
5334	.addr		= omap44xx_cm_core_addrs,
5335	.user		= OCP_USER_MPU | OCP_USER_SDMA,
5336};
5337
5338static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
5339	{
5340		.pa_start	= 0x4a306000,
5341		.pa_end		= 0x4a307fff,
5342		.flags		= ADDR_TYPE_RT
5343	},
5344	{ }
5345};
5346
5347/* l4_wkup -> prm */
5348static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
5349	.master		= &omap44xx_l4_wkup_hwmod,
5350	.slave		= &omap44xx_prm_hwmod,
5351	.clk		= "l4_wkup_clk_mux_ck",
5352	.addr		= omap44xx_prm_addrs,
5353	.user		= OCP_USER_MPU | OCP_USER_SDMA,
5354};
5355
5356static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
5357	{
5358		.pa_start	= 0x4a30a000,
5359		.pa_end		= 0x4a30a7ff,
5360		.flags		= ADDR_TYPE_RT
5361	},
5362	{ }
5363};
5364
5365/* l4_wkup -> scrm */
5366static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
5367	.master		= &omap44xx_l4_wkup_hwmod,
5368	.slave		= &omap44xx_scrm_hwmod,
5369	.clk		= "l4_wkup_clk_mux_ck",
5370	.addr		= omap44xx_scrm_addrs,
5371	.user		= OCP_USER_MPU | OCP_USER_SDMA,
5372};
5373
5374/* l3_main_2 -> sl2if */
5375static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sl2if = {
5376	.master		= &omap44xx_l3_main_2_hwmod,
5377	.slave		= &omap44xx_sl2if_hwmod,
5378	.clk		= "l3_div_ck",
5379	.user		= OCP_USER_MPU | OCP_USER_SDMA,
5380};
5381
5382static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
5383	{
5384		.pa_start	= 0x4012c000,
5385		.pa_end		= 0x4012c3ff,
5386		.flags		= ADDR_TYPE_RT
5387	},
5388	{ }
5389};
5390
5391/* l4_abe -> slimbus1 */
5392static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
5393	.master		= &omap44xx_l4_abe_hwmod,
5394	.slave		= &omap44xx_slimbus1_hwmod,
5395	.clk		= "ocp_abe_iclk",
5396	.addr		= omap44xx_slimbus1_addrs,
5397	.user		= OCP_USER_MPU,
5398};
5399
5400static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
5401	{
5402		.pa_start	= 0x4902c000,
5403		.pa_end		= 0x4902c3ff,
5404		.flags		= ADDR_TYPE_RT
5405	},
5406	{ }
5407};
5408
5409/* l4_abe -> slimbus1 (dma) */
5410static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
5411	.master		= &omap44xx_l4_abe_hwmod,
5412	.slave		= &omap44xx_slimbus1_hwmod,
5413	.clk		= "ocp_abe_iclk",
5414	.addr		= omap44xx_slimbus1_dma_addrs,
5415	.user		= OCP_USER_SDMA,
5416};
5417
5418static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
5419	{
5420		.pa_start	= 0x48076000,
5421		.pa_end		= 0x480763ff,
5422		.flags		= ADDR_TYPE_RT
5423	},
5424	{ }
5425};
5426
5427/* l4_per -> slimbus2 */
5428static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
5429	.master		= &omap44xx_l4_per_hwmod,
5430	.slave		= &omap44xx_slimbus2_hwmod,
5431	.clk		= "l4_div_ck",
5432	.addr		= omap44xx_slimbus2_addrs,
5433	.user		= OCP_USER_MPU | OCP_USER_SDMA,
5434};
5435
5436static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
5437	{
5438		.pa_start	= 0x4a0dd000,
5439		.pa_end		= 0x4a0dd03f,
5440		.flags		= ADDR_TYPE_RT
5441	},
5442	{ }
5443};
5444
5445/* l4_cfg -> smartreflex_core */
5446static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
5447	.master		= &omap44xx_l4_cfg_hwmod,
5448	.slave		= &omap44xx_smartreflex_core_hwmod,
5449	.clk		= "l4_div_ck",
5450	.addr		= omap44xx_smartreflex_core_addrs,
5451	.user		= OCP_USER_MPU | OCP_USER_SDMA,
5452};
5453
5454static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
5455	{
5456		.pa_start	= 0x4a0db000,
5457		.pa_end		= 0x4a0db03f,
5458		.flags		= ADDR_TYPE_RT
5459	},
5460	{ }
5461};
5462
5463/* l4_cfg -> smartreflex_iva */
5464static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
5465	.master		= &omap44xx_l4_cfg_hwmod,
5466	.slave		= &omap44xx_smartreflex_iva_hwmod,
5467	.clk		= "l4_div_ck",
5468	.addr		= omap44xx_smartreflex_iva_addrs,
5469	.user		= OCP_USER_MPU | OCP_USER_SDMA,
5470};
5471
5472static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
5473	{
5474		.pa_start	= 0x4a0d9000,
5475		.pa_end		= 0x4a0d903f,
5476		.flags		= ADDR_TYPE_RT
5477	},
5478	{ }
5479};
5480
5481/* l4_cfg -> smartreflex_mpu */
5482static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
5483	.master		= &omap44xx_l4_cfg_hwmod,
5484	.slave		= &omap44xx_smartreflex_mpu_hwmod,
5485	.clk		= "l4_div_ck",
5486	.addr		= omap44xx_smartreflex_mpu_addrs,
5487	.user		= OCP_USER_MPU | OCP_USER_SDMA,
5488};
5489
5490static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
5491	{
5492		.pa_start	= 0x4a0f6000,
5493		.pa_end		= 0x4a0f6fff,
5494		.flags		= ADDR_TYPE_RT
5495	},
5496	{ }
5497};
5498
5499/* l4_cfg -> spinlock */
5500static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
5501	.master		= &omap44xx_l4_cfg_hwmod,
5502	.slave		= &omap44xx_spinlock_hwmod,
5503	.clk		= "l4_div_ck",
5504	.addr		= omap44xx_spinlock_addrs,
5505	.user		= OCP_USER_MPU | OCP_USER_SDMA,
5506};
5507
5508static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
5509	{
5510		.pa_start	= 0x4a318000,
5511		.pa_end		= 0x4a31807f,
5512		.flags		= ADDR_TYPE_RT
5513	},
5514	{ }
5515};
5516
5517/* l4_wkup -> timer1 */
5518static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
5519	.master		= &omap44xx_l4_wkup_hwmod,
5520	.slave		= &omap44xx_timer1_hwmod,
5521	.clk		= "l4_wkup_clk_mux_ck",
5522	.addr		= omap44xx_timer1_addrs,
5523	.user		= OCP_USER_MPU | OCP_USER_SDMA,
5524};
5525
5526static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
5527	{
5528		.pa_start	= 0x48032000,
5529		.pa_end		= 0x4803207f,
5530		.flags		= ADDR_TYPE_RT
5531	},
5532	{ }
5533};
5534
5535/* l4_per -> timer2 */
5536static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
5537	.master		= &omap44xx_l4_per_hwmod,
5538	.slave		= &omap44xx_timer2_hwmod,
5539	.clk		= "l4_div_ck",
5540	.addr		= omap44xx_timer2_addrs,
5541	.user		= OCP_USER_MPU | OCP_USER_SDMA,
5542};
5543
5544static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
5545	{
5546		.pa_start	= 0x48034000,
5547		.pa_end		= 0x4803407f,
5548		.flags		= ADDR_TYPE_RT
5549	},
5550	{ }
5551};
5552
5553/* l4_per -> timer3 */
5554static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
5555	.master		= &omap44xx_l4_per_hwmod,
5556	.slave		= &omap44xx_timer3_hwmod,
5557	.clk		= "l4_div_ck",
5558	.addr		= omap44xx_timer3_addrs,
5559	.user		= OCP_USER_MPU | OCP_USER_SDMA,
5560};
5561
5562static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
5563	{
5564		.pa_start	= 0x48036000,
5565		.pa_end		= 0x4803607f,
5566		.flags		= ADDR_TYPE_RT
5567	},
5568	{ }
5569};
5570
5571/* l4_per -> timer4 */
5572static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
5573	.master		= &omap44xx_l4_per_hwmod,
5574	.slave		= &omap44xx_timer4_hwmod,
5575	.clk		= "l4_div_ck",
5576	.addr		= omap44xx_timer4_addrs,
5577	.user		= OCP_USER_MPU | OCP_USER_SDMA,
5578};
5579
5580static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
5581	{
5582		.pa_start	= 0x40138000,
5583		.pa_end		= 0x4013807f,
5584		.flags		= ADDR_TYPE_RT
5585	},
5586	{ }
5587};
5588
5589/* l4_abe -> timer5 */
5590static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
5591	.master		= &omap44xx_l4_abe_hwmod,
5592	.slave		= &omap44xx_timer5_hwmod,
5593	.clk		= "ocp_abe_iclk",
5594	.addr		= omap44xx_timer5_addrs,
5595	.user		= OCP_USER_MPU,
5596};
5597
5598static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
5599	{
5600		.pa_start	= 0x49038000,
5601		.pa_end		= 0x4903807f,
5602		.flags		= ADDR_TYPE_RT
5603	},
5604	{ }
5605};
5606
5607/* l4_abe -> timer5 (dma) */
5608static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
5609	.master		= &omap44xx_l4_abe_hwmod,
5610	.slave		= &omap44xx_timer5_hwmod,
5611	.clk		= "ocp_abe_iclk",
5612	.addr		= omap44xx_timer5_dma_addrs,
5613	.user		= OCP_USER_SDMA,
5614};
5615
5616static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
5617	{
5618		.pa_start	= 0x4013a000,
5619		.pa_end		= 0x4013a07f,
5620		.flags		= ADDR_TYPE_RT
5621	},
5622	{ }
5623};
5624
5625/* l4_abe -> timer6 */
5626static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
5627	.master		= &omap44xx_l4_abe_hwmod,
5628	.slave		= &omap44xx_timer6_hwmod,
5629	.clk		= "ocp_abe_iclk",
5630	.addr		= omap44xx_timer6_addrs,
5631	.user		= OCP_USER_MPU,
5632};
5633
5634static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
5635	{
5636		.pa_start	= 0x4903a000,
5637		.pa_end		= 0x4903a07f,
5638		.flags		= ADDR_TYPE_RT
5639	},
5640	{ }
5641};
5642
5643/* l4_abe -> timer6 (dma) */
5644static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
5645	.master		= &omap44xx_l4_abe_hwmod,
5646	.slave		= &omap44xx_timer6_hwmod,
5647	.clk		= "ocp_abe_iclk",
5648	.addr		= omap44xx_timer6_dma_addrs,
5649	.user		= OCP_USER_SDMA,
5650};
5651
5652static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
5653	{
5654		.pa_start	= 0x4013c000,
5655		.pa_end		= 0x4013c07f,
5656		.flags		= ADDR_TYPE_RT
5657	},
5658	{ }
5659};
5660
5661/* l4_abe -> timer7 */
5662static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
5663	.master		= &omap44xx_l4_abe_hwmod,
5664	.slave		= &omap44xx_timer7_hwmod,
5665	.clk		= "ocp_abe_iclk",
5666	.addr		= omap44xx_timer7_addrs,
5667	.user		= OCP_USER_MPU,
5668};
5669
5670static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
5671	{
5672		.pa_start	= 0x4903c000,
5673		.pa_end		= 0x4903c07f,
5674		.flags		= ADDR_TYPE_RT
5675	},
5676	{ }
5677};
5678
5679/* l4_abe -> timer7 (dma) */
5680static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
5681	.master		= &omap44xx_l4_abe_hwmod,
5682	.slave		= &omap44xx_timer7_hwmod,
5683	.clk		= "ocp_abe_iclk",
5684	.addr		= omap44xx_timer7_dma_addrs,
5685	.user		= OCP_USER_SDMA,
5686};
5687
5688static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
5689	{
5690		.pa_start	= 0x4013e000,
5691		.pa_end		= 0x4013e07f,
5692		.flags		= ADDR_TYPE_RT
5693	},
5694	{ }
5695};
5696
5697/* l4_abe -> timer8 */
5698static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
5699	.master		= &omap44xx_l4_abe_hwmod,
5700	.slave		= &omap44xx_timer8_hwmod,
5701	.clk		= "ocp_abe_iclk",
5702	.addr		= omap44xx_timer8_addrs,
5703	.user		= OCP_USER_MPU,
5704};
5705
5706static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
5707	{
5708		.pa_start	= 0x4903e000,
5709		.pa_end		= 0x4903e07f,
5710		.flags		= ADDR_TYPE_RT
5711	},
5712	{ }
5713};
5714
5715/* l4_abe -> timer8 (dma) */
5716static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
5717	.master		= &omap44xx_l4_abe_hwmod,
5718	.slave		= &omap44xx_timer8_hwmod,
5719	.clk		= "ocp_abe_iclk",
5720	.addr		= omap44xx_timer8_dma_addrs,
5721	.user		= OCP_USER_SDMA,
5722};
5723
5724static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
5725	{
5726		.pa_start	= 0x4803e000,
5727		.pa_end		= 0x4803e07f,
5728		.flags		= ADDR_TYPE_RT
5729	},
5730	{ }
5731};
5732
5733/* l4_per -> timer9 */
5734static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
5735	.master		= &omap44xx_l4_per_hwmod,
5736	.slave		= &omap44xx_timer9_hwmod,
5737	.clk		= "l4_div_ck",
5738	.addr		= omap44xx_timer9_addrs,
5739	.user		= OCP_USER_MPU | OCP_USER_SDMA,
5740};
5741
5742static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
5743	{
5744		.pa_start	= 0x48086000,
5745		.pa_end		= 0x4808607f,
5746		.flags		= ADDR_TYPE_RT
5747	},
5748	{ }
5749};
5750
5751/* l4_per -> timer10 */
5752static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
5753	.master		= &omap44xx_l4_per_hwmod,
5754	.slave		= &omap44xx_timer10_hwmod,
5755	.clk		= "l4_div_ck",
5756	.addr		= omap44xx_timer10_addrs,
5757	.user		= OCP_USER_MPU | OCP_USER_SDMA,
5758};
5759
5760static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
5761	{
5762		.pa_start	= 0x48088000,
5763		.pa_end		= 0x4808807f,
5764		.flags		= ADDR_TYPE_RT
5765	},
5766	{ }
5767};
5768
5769/* l4_per -> timer11 */
5770static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
5771	.master		= &omap44xx_l4_per_hwmod,
5772	.slave		= &omap44xx_timer11_hwmod,
5773	.clk		= "l4_div_ck",
5774	.addr		= omap44xx_timer11_addrs,
5775	.user		= OCP_USER_MPU | OCP_USER_SDMA,
5776};
5777
5778static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
5779	{
5780		.pa_start	= 0x4806a000,
5781		.pa_end		= 0x4806a0ff,
5782		.flags		= ADDR_TYPE_RT
5783	},
5784	{ }
5785};
5786
5787/* l4_per -> uart1 */
5788static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
5789	.master		= &omap44xx_l4_per_hwmod,
5790	.slave		= &omap44xx_uart1_hwmod,
5791	.clk		= "l4_div_ck",
5792	.addr		= omap44xx_uart1_addrs,
5793	.user		= OCP_USER_MPU | OCP_USER_SDMA,
5794};
5795
5796static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
5797	{
5798		.pa_start	= 0x4806c000,
5799		.pa_end		= 0x4806c0ff,
5800		.flags		= ADDR_TYPE_RT
5801	},
5802	{ }
5803};
5804
5805/* l4_per -> uart2 */
5806static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
5807	.master		= &omap44xx_l4_per_hwmod,
5808	.slave		= &omap44xx_uart2_hwmod,
5809	.clk		= "l4_div_ck",
5810	.addr		= omap44xx_uart2_addrs,
5811	.user		= OCP_USER_MPU | OCP_USER_SDMA,
5812};
5813
5814static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
5815	{
5816		.pa_start	= 0x48020000,
5817		.pa_end		= 0x480200ff,
5818		.flags		= ADDR_TYPE_RT
5819	},
5820	{ }
5821};
5822
5823/* l4_per -> uart3 */
5824static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
5825	.master		= &omap44xx_l4_per_hwmod,
5826	.slave		= &omap44xx_uart3_hwmod,
5827	.clk		= "l4_div_ck",
5828	.addr		= omap44xx_uart3_addrs,
5829	.user		= OCP_USER_MPU | OCP_USER_SDMA,
5830};
5831
5832static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
5833	{
5834		.pa_start	= 0x4806e000,
5835		.pa_end		= 0x4806e0ff,
5836		.flags		= ADDR_TYPE_RT
5837	},
5838	{ }
5839};
5840
5841/* l4_per -> uart4 */
5842static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
5843	.master		= &omap44xx_l4_per_hwmod,
5844	.slave		= &omap44xx_uart4_hwmod,
5845	.clk		= "l4_div_ck",
5846	.addr		= omap44xx_uart4_addrs,
5847	.user		= OCP_USER_MPU | OCP_USER_SDMA,
5848};
5849
5850static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
5851	{
5852		.pa_start	= 0x4a0a9000,
5853		.pa_end		= 0x4a0a93ff,
5854		.flags		= ADDR_TYPE_RT
5855	},
5856	{ }
5857};
5858
5859/* l4_cfg -> usb_host_fs */
5860static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
5861	.master		= &omap44xx_l4_cfg_hwmod,
5862	.slave		= &omap44xx_usb_host_fs_hwmod,
5863	.clk		= "l4_div_ck",
5864	.addr		= omap44xx_usb_host_fs_addrs,
5865	.user		= OCP_USER_MPU | OCP_USER_SDMA,
5866};
5867
5868static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
5869	{
5870		.name		= "uhh",
5871		.pa_start	= 0x4a064000,
5872		.pa_end		= 0x4a0647ff,
5873		.flags		= ADDR_TYPE_RT
5874	},
5875	{
5876		.name		= "ohci",
5877		.pa_start	= 0x4a064800,
5878		.pa_end		= 0x4a064bff,
5879	},
5880	{
5881		.name		= "ehci",
5882		.pa_start	= 0x4a064c00,
5883		.pa_end		= 0x4a064fff,
5884	},
5885	{}
5886};
5887
5888/* l4_cfg -> usb_host_hs */
5889static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
5890	.master		= &omap44xx_l4_cfg_hwmod,
5891	.slave		= &omap44xx_usb_host_hs_hwmod,
5892	.clk		= "l4_div_ck",
5893	.addr		= omap44xx_usb_host_hs_addrs,
5894	.user		= OCP_USER_MPU | OCP_USER_SDMA,
5895};
5896
5897static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
5898	{
5899		.pa_start	= 0x4a0ab000,
5900		.pa_end		= 0x4a0ab003,
5901		.flags		= ADDR_TYPE_RT
5902	},
5903	{ }
5904};
5905
5906/* l4_cfg -> usb_otg_hs */
5907static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
5908	.master		= &omap44xx_l4_cfg_hwmod,
5909	.slave		= &omap44xx_usb_otg_hs_hwmod,
5910	.clk		= "l4_div_ck",
5911	.addr		= omap44xx_usb_otg_hs_addrs,
5912	.user		= OCP_USER_MPU | OCP_USER_SDMA,
5913};
5914
5915static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
5916	{
5917		.name		= "tll",
5918		.pa_start	= 0x4a062000,
5919		.pa_end		= 0x4a063fff,
5920		.flags		= ADDR_TYPE_RT
5921	},
5922	{}
5923};
5924
5925/* l4_cfg -> usb_tll_hs */
5926static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
5927	.master		= &omap44xx_l4_cfg_hwmod,
5928	.slave		= &omap44xx_usb_tll_hs_hwmod,
5929	.clk		= "l4_div_ck",
5930	.addr		= omap44xx_usb_tll_hs_addrs,
5931	.user		= OCP_USER_MPU | OCP_USER_SDMA,
5932};
5933
5934static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
5935	{
5936		.pa_start	= 0x4a314000,
5937		.pa_end		= 0x4a31407f,
5938		.flags		= ADDR_TYPE_RT
5939	},
5940	{ }
5941};
5942
5943/* l4_wkup -> wd_timer2 */
5944static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
5945	.master		= &omap44xx_l4_wkup_hwmod,
5946	.slave		= &omap44xx_wd_timer2_hwmod,
5947	.clk		= "l4_wkup_clk_mux_ck",
5948	.addr		= omap44xx_wd_timer2_addrs,
5949	.user		= OCP_USER_MPU | OCP_USER_SDMA,
5950};
5951
5952static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
5953	{
5954		.pa_start	= 0x40130000,
5955		.pa_end		= 0x4013007f,
5956		.flags		= ADDR_TYPE_RT
5957	},
5958	{ }
5959};
5960
5961/* l4_abe -> wd_timer3 */
5962static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
5963	.master		= &omap44xx_l4_abe_hwmod,
5964	.slave		= &omap44xx_wd_timer3_hwmod,
5965	.clk		= "ocp_abe_iclk",
5966	.addr		= omap44xx_wd_timer3_addrs,
5967	.user		= OCP_USER_MPU,
5968};
5969
5970static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
5971	{
5972		.pa_start	= 0x49030000,
5973		.pa_end		= 0x4903007f,
5974		.flags		= ADDR_TYPE_RT
5975	},
5976	{ }
5977};
5978
5979/* l4_abe -> wd_timer3 (dma) */
5980static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
5981	.master		= &omap44xx_l4_abe_hwmod,
5982	.slave		= &omap44xx_wd_timer3_hwmod,
5983	.clk		= "ocp_abe_iclk",
5984	.addr		= omap44xx_wd_timer3_dma_addrs,
5985	.user		= OCP_USER_SDMA,
5986};
5987
5988static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
5989	&omap44xx_c2c__c2c_target_fw,
5990	&omap44xx_l4_cfg__c2c_target_fw,
5991	&omap44xx_l3_main_1__dmm,
5992	&omap44xx_mpu__dmm,
5993	&omap44xx_c2c__emif_fw,
5994	&omap44xx_dmm__emif_fw,
5995	&omap44xx_l4_cfg__emif_fw,
5996	&omap44xx_iva__l3_instr,
5997	&omap44xx_l3_main_3__l3_instr,
5998	&omap44xx_ocp_wp_noc__l3_instr,
5999	&omap44xx_dsp__l3_main_1,
6000	&omap44xx_dss__l3_main_1,
6001	&omap44xx_l3_main_2__l3_main_1,
6002	&omap44xx_l4_cfg__l3_main_1,
6003	&omap44xx_mmc1__l3_main_1,
6004	&omap44xx_mmc2__l3_main_1,
6005	&omap44xx_mpu__l3_main_1,
6006	&omap44xx_c2c_target_fw__l3_main_2,
6007	&omap44xx_debugss__l3_main_2,
6008	&omap44xx_dma_system__l3_main_2,
6009	&omap44xx_fdif__l3_main_2,
6010	&omap44xx_gpu__l3_main_2,
6011	&omap44xx_hsi__l3_main_2,
6012	&omap44xx_ipu__l3_main_2,
6013	&omap44xx_iss__l3_main_2,
6014	&omap44xx_iva__l3_main_2,
6015	&omap44xx_l3_main_1__l3_main_2,
6016	&omap44xx_l4_cfg__l3_main_2,
6017	/* &omap44xx_usb_host_fs__l3_main_2, */
6018	&omap44xx_usb_host_hs__l3_main_2,
6019	&omap44xx_usb_otg_hs__l3_main_2,
6020	&omap44xx_l3_main_1__l3_main_3,
6021	&omap44xx_l3_main_2__l3_main_3,
6022	&omap44xx_l4_cfg__l3_main_3,
6023	/* &omap44xx_aess__l4_abe, */
6024	&omap44xx_dsp__l4_abe,
6025	&omap44xx_l3_main_1__l4_abe,
6026	&omap44xx_mpu__l4_abe,
6027	&omap44xx_l3_main_1__l4_cfg,
6028	&omap44xx_l3_main_2__l4_per,
6029	&omap44xx_l4_cfg__l4_wkup,
6030	&omap44xx_mpu__mpu_private,
6031	&omap44xx_l4_cfg__ocp_wp_noc,
6032	/* &omap44xx_l4_abe__aess, */
6033	/* &omap44xx_l4_abe__aess_dma, */
6034	&omap44xx_l3_main_2__c2c,
6035	&omap44xx_l4_wkup__counter_32k,
6036	&omap44xx_l4_cfg__ctrl_module_core,
6037	&omap44xx_l4_cfg__ctrl_module_pad_core,
6038	&omap44xx_l4_wkup__ctrl_module_wkup,
6039	&omap44xx_l4_wkup__ctrl_module_pad_wkup,
6040	&omap44xx_l3_instr__debugss,
6041	&omap44xx_l4_cfg__dma_system,
6042	&omap44xx_l4_abe__dmic,
6043	&omap44xx_l4_abe__dmic_dma,
6044	&omap44xx_dsp__iva,
6045	&omap44xx_dsp__sl2if,
6046	&omap44xx_l4_cfg__dsp,
6047	&omap44xx_l3_main_2__dss,
6048	&omap44xx_l4_per__dss,
6049	&omap44xx_l3_main_2__dss_dispc,
6050	&omap44xx_l4_per__dss_dispc,
6051	&omap44xx_l3_main_2__dss_dsi1,
6052	&omap44xx_l4_per__dss_dsi1,
6053	&omap44xx_l3_main_2__dss_dsi2,
6054	&omap44xx_l4_per__dss_dsi2,
6055	&omap44xx_l3_main_2__dss_hdmi,
6056	&omap44xx_l4_per__dss_hdmi,
6057	&omap44xx_l3_main_2__dss_rfbi,
6058	&omap44xx_l4_per__dss_rfbi,
6059	&omap44xx_l3_main_2__dss_venc,
6060	&omap44xx_l4_per__dss_venc,
6061	&omap44xx_l4_per__elm,
6062	&omap44xx_emif_fw__emif1,
6063	&omap44xx_emif_fw__emif2,
6064	&omap44xx_l4_cfg__fdif,
6065	&omap44xx_l4_wkup__gpio1,
6066	&omap44xx_l4_per__gpio2,
6067	&omap44xx_l4_per__gpio3,
6068	&omap44xx_l4_per__gpio4,
6069	&omap44xx_l4_per__gpio5,
6070	&omap44xx_l4_per__gpio6,
6071	&omap44xx_l3_main_2__gpmc,
6072	&omap44xx_l3_main_2__gpu,
6073	&omap44xx_l4_per__hdq1w,
6074	&omap44xx_l4_cfg__hsi,
6075	&omap44xx_l4_per__i2c1,
6076	&omap44xx_l4_per__i2c2,
6077	&omap44xx_l4_per__i2c3,
6078	&omap44xx_l4_per__i2c4,
6079	&omap44xx_l3_main_2__ipu,
6080	&omap44xx_l3_main_2__iss,
6081	&omap44xx_iva__sl2if,
6082	&omap44xx_l3_main_2__iva,
6083	&omap44xx_l4_wkup__kbd,
6084	&omap44xx_l4_cfg__mailbox,
6085	&omap44xx_l4_abe__mcasp,
6086	&omap44xx_l4_abe__mcasp_dma,
6087	&omap44xx_l4_abe__mcbsp1,
6088	&omap44xx_l4_abe__mcbsp1_dma,
6089	&omap44xx_l4_abe__mcbsp2,
6090	&omap44xx_l4_abe__mcbsp2_dma,
6091	&omap44xx_l4_abe__mcbsp3,
6092	&omap44xx_l4_abe__mcbsp3_dma,
6093	&omap44xx_l4_per__mcbsp4,
6094	&omap44xx_l4_abe__mcpdm,
6095	&omap44xx_l4_abe__mcpdm_dma,
6096	&omap44xx_l4_per__mcspi1,
6097	&omap44xx_l4_per__mcspi2,
6098	&omap44xx_l4_per__mcspi3,
6099	&omap44xx_l4_per__mcspi4,
6100	&omap44xx_l4_per__mmc1,
6101	&omap44xx_l4_per__mmc2,
6102	&omap44xx_l4_per__mmc3,
6103	&omap44xx_l4_per__mmc4,
6104	&omap44xx_l4_per__mmc5,
6105	&omap44xx_l3_main_2__ocmc_ram,
6106	&omap44xx_l4_cfg__ocp2scp_usb_phy,
6107	&omap44xx_mpu_private__prcm_mpu,
6108	&omap44xx_l4_wkup__cm_core_aon,
6109	&omap44xx_l4_cfg__cm_core,
6110	&omap44xx_l4_wkup__prm,
6111	&omap44xx_l4_wkup__scrm,
6112	&omap44xx_l3_main_2__sl2if,
6113	&omap44xx_l4_abe__slimbus1,
6114	&omap44xx_l4_abe__slimbus1_dma,
6115	&omap44xx_l4_per__slimbus2,
6116	&omap44xx_l4_cfg__smartreflex_core,
6117	&omap44xx_l4_cfg__smartreflex_iva,
6118	&omap44xx_l4_cfg__smartreflex_mpu,
6119	&omap44xx_l4_cfg__spinlock,
6120	&omap44xx_l4_wkup__timer1,
6121	&omap44xx_l4_per__timer2,
6122	&omap44xx_l4_per__timer3,
6123	&omap44xx_l4_per__timer4,
6124	&omap44xx_l4_abe__timer5,
6125	&omap44xx_l4_abe__timer5_dma,
6126	&omap44xx_l4_abe__timer6,
6127	&omap44xx_l4_abe__timer6_dma,
6128	&omap44xx_l4_abe__timer7,
6129	&omap44xx_l4_abe__timer7_dma,
6130	&omap44xx_l4_abe__timer8,
6131	&omap44xx_l4_abe__timer8_dma,
6132	&omap44xx_l4_per__timer9,
6133	&omap44xx_l4_per__timer10,
6134	&omap44xx_l4_per__timer11,
6135	&omap44xx_l4_per__uart1,
6136	&omap44xx_l4_per__uart2,
6137	&omap44xx_l4_per__uart3,
6138	&omap44xx_l4_per__uart4,
6139	/* &omap44xx_l4_cfg__usb_host_fs, */
6140	&omap44xx_l4_cfg__usb_host_hs,
6141	&omap44xx_l4_cfg__usb_otg_hs,
6142	&omap44xx_l4_cfg__usb_tll_hs,
6143	&omap44xx_l4_wkup__wd_timer2,
6144	&omap44xx_l4_abe__wd_timer3,
6145	&omap44xx_l4_abe__wd_timer3_dma,
6146	NULL,
6147};
6148
6149int __init omap44xx_hwmod_init(void)
6150{
6151	return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
6152}
6153