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1/*
2 * SPI_PPC4XX SPI controller driver.
3 *
4 * Copyright (C) 2007 Gary Jennejohn <garyj@denx.de>
5 * Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
6 * Copyright 2009 Harris Corporation, Steven A. Falco <sfalco@harris.com>
7 *
8 * Based in part on drivers/spi/spi_s3c24xx.c
9 *
10 * Copyright (c) 2006 Ben Dooks
11 * Copyright (c) 2006 Simtec Electronics
12 * Ben Dooks <ben@simtec.co.uk>
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License version 2 as published
16 * by the Free Software Foundation.
17 */
18
19/*
20 * The PPC4xx SPI controller has no FIFO so each sent/received byte will
21 * generate an interrupt to the CPU. This can cause high CPU utilization.
22 * This driver allows platforms to reduce the interrupt load on the CPU
23 * during SPI transfers by setting max_speed_hz via the device tree.
24 */
25
26#include <linux/module.h>
27#include <linux/init.h>
28#include <linux/sched.h>
29#include <linux/slab.h>
30#include <linux/errno.h>
31#include <linux/wait.h>
32#include <linux/of_platform.h>
33#include <linux/of_gpio.h>
34#include <linux/interrupt.h>
35#include <linux/delay.h>
36
37#include <linux/gpio.h>
38#include <linux/spi/spi.h>
39#include <linux/spi/spi_bitbang.h>
40
41#include <asm/io.h>
42#include <asm/dcr.h>
43#include <asm/dcr-regs.h>
44
45/* bits in mode register - bit 0 is MSb */
46
47/*
48 * SPI_PPC4XX_MODE_SCP = 0 means "data latched on trailing edge of clock"
49 * SPI_PPC4XX_MODE_SCP = 1 means "data latched on leading edge of clock"
50 * Note: This is the inverse of CPHA.
51 */
52#define SPI_PPC4XX_MODE_SCP (0x80 >> 3)
53
54/* SPI_PPC4XX_MODE_SPE = 1 means "port enabled" */
55#define SPI_PPC4XX_MODE_SPE (0x80 >> 4)
56
57/*
58 * SPI_PPC4XX_MODE_RD = 0 means "MSB first" - this is the normal mode
59 * SPI_PPC4XX_MODE_RD = 1 means "LSB first" - this is bit-reversed mode
60 * Note: This is identical to SPI_LSB_FIRST.
61 */
62#define SPI_PPC4XX_MODE_RD (0x80 >> 5)
63
64/*
65 * SPI_PPC4XX_MODE_CI = 0 means "clock idles low"
66 * SPI_PPC4XX_MODE_CI = 1 means "clock idles high"
67 * Note: This is identical to CPOL.
68 */
69#define SPI_PPC4XX_MODE_CI (0x80 >> 6)
70
71/*
72 * SPI_PPC4XX_MODE_IL = 0 means "loopback disable"
73 * SPI_PPC4XX_MODE_IL = 1 means "loopback enable"
74 */
75#define SPI_PPC4XX_MODE_IL (0x80 >> 7)
76
77/* bits in control register */
78/* starts a transfer when set */
79#define SPI_PPC4XX_CR_STR (0x80 >> 7)
80
81/* bits in status register */
82/* port is busy with a transfer */
83#define SPI_PPC4XX_SR_BSY (0x80 >> 6)
84/* RxD ready */
85#define SPI_PPC4XX_SR_RBR (0x80 >> 7)
86
87/* clock settings (SCP and CI) for various SPI modes */
88#define SPI_CLK_MODE0 (SPI_PPC4XX_MODE_SCP | 0)
89#define SPI_CLK_MODE1 (0 | 0)
90#define SPI_CLK_MODE2 (SPI_PPC4XX_MODE_SCP | SPI_PPC4XX_MODE_CI)
91#define SPI_CLK_MODE3 (0 | SPI_PPC4XX_MODE_CI)
92
93#define DRIVER_NAME "spi_ppc4xx_of"
94
95struct spi_ppc4xx_regs {
96 u8 mode;
97 u8 rxd;
98 u8 txd;
99 u8 cr;
100 u8 sr;
101 u8 dummy;
102 /*
103 * Clock divisor modulus register
104 * This uses the follwing formula:
105 * SCPClkOut = OPBCLK/(4(CDM + 1))
106 * or
107 * CDM = (OPBCLK/4*SCPClkOut) - 1
108 * bit 0 is the MSb!
109 */
110 u8 cdm;
111};
112
113/* SPI Controller driver's private data. */
114struct ppc4xx_spi {
115 /* bitbang has to be first */
116 struct spi_bitbang bitbang;
117 struct completion done;
118
119 u64 mapbase;
120 u64 mapsize;
121 int irqnum;
122 /* need this to set the SPI clock */
123 unsigned int opb_freq;
124
125 /* for transfers */
126 int len;
127 int count;
128 /* data buffers */
129 const unsigned char *tx;
130 unsigned char *rx;
131
132 int *gpios;
133
134 struct spi_ppc4xx_regs __iomem *regs; /* pointer to the registers */
135 struct spi_master *master;
136 struct device *dev;
137};
138
139/* need this so we can set the clock in the chipselect routine */
140struct spi_ppc4xx_cs {
141 u8 mode;
142};
143
144static int spi_ppc4xx_txrx(struct spi_device *spi, struct spi_transfer *t)
145{
146 struct ppc4xx_spi *hw;
147 u8 data;
148
149 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
150 t->tx_buf, t->rx_buf, t->len);
151
152 hw = spi_master_get_devdata(spi->master);
153
154 hw->tx = t->tx_buf;
155 hw->rx = t->rx_buf;
156 hw->len = t->len;
157 hw->count = 0;
158
159 /* send the first byte */
160 data = hw->tx ? hw->tx[0] : 0;
161 out_8(&hw->regs->txd, data);
162 out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR);
163 wait_for_completion(&hw->done);
164
165 return hw->count;
166}
167
168static int spi_ppc4xx_setupxfer(struct spi_device *spi, struct spi_transfer *t)
169{
170 struct ppc4xx_spi *hw = spi_master_get_devdata(spi->master);
171 struct spi_ppc4xx_cs *cs = spi->controller_state;
172 int scr;
173 u8 cdm = 0;
174 u32 speed;
175 u8 bits_per_word;
176
177 /* Start with the generic configuration for this device. */
178 bits_per_word = spi->bits_per_word;
179 speed = spi->max_speed_hz;
180
181 /*
182 * Modify the configuration if the transfer overrides it. Do not allow
183 * the transfer to overwrite the generic configuration with zeros.
184 */
185 if (t) {
186 if (t->bits_per_word)
187 bits_per_word = t->bits_per_word;
188
189 if (t->speed_hz)
190 speed = min(t->speed_hz, spi->max_speed_hz);
191 }
192
193 if (bits_per_word != 8) {
194 dev_err(&spi->dev, "invalid bits-per-word (%d)\n",
195 bits_per_word);
196 return -EINVAL;
197 }
198
199 if (!speed || (speed > spi->max_speed_hz)) {
200 dev_err(&spi->dev, "invalid speed_hz (%d)\n", speed);
201 return -EINVAL;
202 }
203
204 /* Write new configration */
205 out_8(&hw->regs->mode, cs->mode);
206
207 /* Set the clock */
208 /* opb_freq was already divided by 4 */
209 scr = (hw->opb_freq / speed) - 1;
210 if (scr > 0)
211 cdm = min(scr, 0xff);
212
213 dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", cdm, speed);
214
215 if (in_8(&hw->regs->cdm) != cdm)
216 out_8(&hw->regs->cdm, cdm);
217
218 spin_lock(&hw->bitbang.lock);
219 if (!hw->bitbang.busy) {
220 hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
221 /* Need to ndelay here? */
222 }
223 spin_unlock(&hw->bitbang.lock);
224
225 return 0;
226}
227
228static int spi_ppc4xx_setup(struct spi_device *spi)
229{
230 struct spi_ppc4xx_cs *cs = spi->controller_state;
231
232 if (spi->bits_per_word != 8) {
233 dev_err(&spi->dev, "invalid bits-per-word (%d)\n",
234 spi->bits_per_word);
235 return -EINVAL;
236 }
237
238 if (!spi->max_speed_hz) {
239 dev_err(&spi->dev, "invalid max_speed_hz (must be non-zero)\n");
240 return -EINVAL;
241 }
242
243 if (cs == NULL) {
244 cs = kzalloc(sizeof *cs, GFP_KERNEL);
245 if (!cs)
246 return -ENOMEM;
247 spi->controller_state = cs;
248 }
249
250 /*
251 * We set all bits of the SPI0_MODE register, so,
252 * no need to read-modify-write
253 */
254 cs->mode = SPI_PPC4XX_MODE_SPE;
255
256 switch (spi->mode & (SPI_CPHA | SPI_CPOL)) {
257 case SPI_MODE_0:
258 cs->mode |= SPI_CLK_MODE0;
259 break;
260 case SPI_MODE_1:
261 cs->mode |= SPI_CLK_MODE1;
262 break;
263 case SPI_MODE_2:
264 cs->mode |= SPI_CLK_MODE2;
265 break;
266 case SPI_MODE_3:
267 cs->mode |= SPI_CLK_MODE3;
268 break;
269 }
270
271 if (spi->mode & SPI_LSB_FIRST)
272 cs->mode |= SPI_PPC4XX_MODE_RD;
273
274 return 0;
275}
276
277static void spi_ppc4xx_chipsel(struct spi_device *spi, int value)
278{
279 struct ppc4xx_spi *hw = spi_master_get_devdata(spi->master);
280 unsigned int cs = spi->chip_select;
281 unsigned int cspol;
282
283 /*
284 * If there are no chip selects at all, or if this is the special
285 * case of a non-existent (dummy) chip select, do nothing.
286 */
287
288 if (!hw->master->num_chipselect || hw->gpios[cs] == -EEXIST)
289 return;
290
291 cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
292 if (value == BITBANG_CS_INACTIVE)
293 cspol = !cspol;
294
295 gpio_set_value(hw->gpios[cs], cspol);
296}
297
298static irqreturn_t spi_ppc4xx_int(int irq, void *dev_id)
299{
300 struct ppc4xx_spi *hw;
301 u8 status;
302 u8 data;
303 unsigned int count;
304
305 hw = (struct ppc4xx_spi *)dev_id;
306
307 status = in_8(&hw->regs->sr);
308 if (!status)
309 return IRQ_NONE;
310
311 /*
312 * BSY de-asserts one cycle after the transfer is complete. The
313 * interrupt is asserted after the transfer is complete. The exact
314 * relationship is not documented, hence this code.
315 */
316
317 if (unlikely(status & SPI_PPC4XX_SR_BSY)) {
318 u8 lstatus;
319 int cnt = 0;
320
321 dev_dbg(hw->dev, "got interrupt but spi still busy?\n");
322 do {
323 ndelay(10);
324 lstatus = in_8(&hw->regs->sr);
325 } while (++cnt < 100 && lstatus & SPI_PPC4XX_SR_BSY);
326
327 if (cnt >= 100) {
328 dev_err(hw->dev, "busywait: too many loops!\n");
329 complete(&hw->done);
330 return IRQ_HANDLED;
331 } else {
332 /* status is always 1 (RBR) here */
333 status = in_8(&hw->regs->sr);
334 dev_dbg(hw->dev, "loops %d status %x\n", cnt, status);
335 }
336 }
337
338 count = hw->count;
339 hw->count++;
340
341 /* RBR triggered this interrupt. Therefore, data must be ready. */
342 data = in_8(&hw->regs->rxd);
343 if (hw->rx)
344 hw->rx[count] = data;
345
346 count++;
347
348 if (count < hw->len) {
349 data = hw->tx ? hw->tx[count] : 0;
350 out_8(&hw->regs->txd, data);
351 out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR);
352 } else {
353 complete(&hw->done);
354 }
355
356 return IRQ_HANDLED;
357}
358
359static void spi_ppc4xx_cleanup(struct spi_device *spi)
360{
361 kfree(spi->controller_state);
362}
363
364static void spi_ppc4xx_enable(struct ppc4xx_spi *hw)
365{
366 /*
367 * On all 4xx PPC's the SPI bus is shared/multiplexed with
368 * the 2nd I2C bus. We need to enable the the SPI bus before
369 * using it.
370 */
371
372 /* need to clear bit 14 to enable SPC */
373 dcri_clrset(SDR0, SDR0_PFC1, 0x80000000 >> 14, 0);
374}
375
376static void free_gpios(struct ppc4xx_spi *hw)
377{
378 if (hw->master->num_chipselect) {
379 int i;
380 for (i = 0; i < hw->master->num_chipselect; i++)
381 if (gpio_is_valid(hw->gpios[i]))
382 gpio_free(hw->gpios[i]);
383
384 kfree(hw->gpios);
385 hw->gpios = NULL;
386 }
387}
388
389/*
390 * platform_device layer stuff...
391 */
392static int __init spi_ppc4xx_of_probe(struct platform_device *op)
393{
394 struct ppc4xx_spi *hw;
395 struct spi_master *master;
396 struct spi_bitbang *bbp;
397 struct resource resource;
398 struct device_node *np = op->dev.of_node;
399 struct device *dev = &op->dev;
400 struct device_node *opbnp;
401 int ret;
402 int num_gpios;
403 const unsigned int *clk;
404
405 master = spi_alloc_master(dev, sizeof *hw);
406 if (master == NULL)
407 return -ENOMEM;
408 master->dev.of_node = np;
409 dev_set_drvdata(dev, master);
410 hw = spi_master_get_devdata(master);
411 hw->master = spi_master_get(master);
412 hw->dev = dev;
413
414 init_completion(&hw->done);
415
416 /*
417 * A count of zero implies a single SPI device without any chip-select.
418 * Note that of_gpio_count counts all gpios assigned to this spi master.
419 * This includes both "null" gpio's and real ones.
420 */
421 num_gpios = of_gpio_count(np);
422 if (num_gpios) {
423 int i;
424
425 hw->gpios = kzalloc(sizeof(int) * num_gpios, GFP_KERNEL);
426 if (!hw->gpios) {
427 ret = -ENOMEM;
428 goto free_master;
429 }
430
431 for (i = 0; i < num_gpios; i++) {
432 int gpio;
433 enum of_gpio_flags flags;
434
435 gpio = of_get_gpio_flags(np, i, &flags);
436 hw->gpios[i] = gpio;
437
438 if (gpio_is_valid(gpio)) {
439 /* Real CS - set the initial state. */
440 ret = gpio_request(gpio, np->name);
441 if (ret < 0) {
442 dev_err(dev, "can't request gpio "
443 "#%d: %d\n", i, ret);
444 goto free_gpios;
445 }
446
447 gpio_direction_output(gpio,
448 !!(flags & OF_GPIO_ACTIVE_LOW));
449 } else if (gpio == -EEXIST) {
450 ; /* No CS, but that's OK. */
451 } else {
452 dev_err(dev, "invalid gpio #%d: %d\n", i, gpio);
453 ret = -EINVAL;
454 goto free_gpios;
455 }
456 }
457 }
458
459 /* Setup the state for the bitbang driver */
460 bbp = &hw->bitbang;
461 bbp->master = hw->master;
462 bbp->setup_transfer = spi_ppc4xx_setupxfer;
463 bbp->chipselect = spi_ppc4xx_chipsel;
464 bbp->txrx_bufs = spi_ppc4xx_txrx;
465 bbp->use_dma = 0;
466 bbp->master->setup = spi_ppc4xx_setup;
467 bbp->master->cleanup = spi_ppc4xx_cleanup;
468
469 /* the spi->mode bits understood by this driver: */
470 bbp->master->mode_bits =
471 SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST;
472
473 /* this many pins in all GPIO controllers */
474 bbp->master->num_chipselect = num_gpios;
475
476 /* Get the clock for the OPB */
477 opbnp = of_find_compatible_node(NULL, NULL, "ibm,opb");
478 if (opbnp == NULL) {
479 dev_err(dev, "OPB: cannot find node\n");
480 ret = -ENODEV;
481 goto free_gpios;
482 }
483 /* Get the clock (Hz) for the OPB */
484 clk = of_get_property(opbnp, "clock-frequency", NULL);
485 if (clk == NULL) {
486 dev_err(dev, "OPB: no clock-frequency property set\n");
487 of_node_put(opbnp);
488 ret = -ENODEV;
489 goto free_gpios;
490 }
491 hw->opb_freq = *clk;
492 hw->opb_freq >>= 2;
493 of_node_put(opbnp);
494
495 ret = of_address_to_resource(np, 0, &resource);
496 if (ret) {
497 dev_err(dev, "error while parsing device node resource\n");
498 goto free_gpios;
499 }
500 hw->mapbase = resource.start;
501 hw->mapsize = resource_size(&resource);
502
503 /* Sanity check */
504 if (hw->mapsize < sizeof(struct spi_ppc4xx_regs)) {
505 dev_err(dev, "too small to map registers\n");
506 ret = -EINVAL;
507 goto free_gpios;
508 }
509
510 /* Request IRQ */
511 hw->irqnum = irq_of_parse_and_map(np, 0);
512 ret = request_irq(hw->irqnum, spi_ppc4xx_int,
513 0, "spi_ppc4xx_of", (void *)hw);
514 if (ret) {
515 dev_err(dev, "unable to allocate interrupt\n");
516 goto free_gpios;
517 }
518
519 if (!request_mem_region(hw->mapbase, hw->mapsize, DRIVER_NAME)) {
520 dev_err(dev, "resource unavailable\n");
521 ret = -EBUSY;
522 goto request_mem_error;
523 }
524
525 hw->regs = ioremap(hw->mapbase, sizeof(struct spi_ppc4xx_regs));
526
527 if (!hw->regs) {
528 dev_err(dev, "unable to memory map registers\n");
529 ret = -ENXIO;
530 goto map_io_error;
531 }
532
533 spi_ppc4xx_enable(hw);
534
535 /* Finally register our spi controller */
536 dev->dma_mask = 0;
537 ret = spi_bitbang_start(bbp);
538 if (ret) {
539 dev_err(dev, "failed to register SPI master\n");
540 goto unmap_regs;
541 }
542
543 dev_info(dev, "driver initialized\n");
544
545 return 0;
546
547unmap_regs:
548 iounmap(hw->regs);
549map_io_error:
550 release_mem_region(hw->mapbase, hw->mapsize);
551request_mem_error:
552 free_irq(hw->irqnum, hw);
553free_gpios:
554 free_gpios(hw);
555free_master:
556 dev_set_drvdata(dev, NULL);
557 spi_master_put(master);
558
559 dev_err(dev, "initialization failed\n");
560 return ret;
561}
562
563static int __exit spi_ppc4xx_of_remove(struct platform_device *op)
564{
565 struct spi_master *master = dev_get_drvdata(&op->dev);
566 struct ppc4xx_spi *hw = spi_master_get_devdata(master);
567
568 spi_bitbang_stop(&hw->bitbang);
569 dev_set_drvdata(&op->dev, NULL);
570 release_mem_region(hw->mapbase, hw->mapsize);
571 free_irq(hw->irqnum, hw);
572 iounmap(hw->regs);
573 free_gpios(hw);
574 return 0;
575}
576
577static const struct of_device_id spi_ppc4xx_of_match[] = {
578 { .compatible = "ibm,ppc4xx-spi", },
579 {},
580};
581
582MODULE_DEVICE_TABLE(of, spi_ppc4xx_of_match);
583
584static struct platform_driver spi_ppc4xx_of_driver = {
585 .probe = spi_ppc4xx_of_probe,
586 .remove = __exit_p(spi_ppc4xx_of_remove),
587 .driver = {
588 .name = DRIVER_NAME,
589 .owner = THIS_MODULE,
590 .of_match_table = spi_ppc4xx_of_match,
591 },
592};
593module_platform_driver(spi_ppc4xx_of_driver);
594
595MODULE_AUTHOR("Gary Jennejohn & Stefan Roese");
596MODULE_DESCRIPTION("Simple PPC4xx SPI Driver");
597MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * SPI_PPC4XX SPI controller driver.
4 *
5 * Copyright (C) 2007 Gary Jennejohn <garyj@denx.de>
6 * Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
7 * Copyright 2009 Harris Corporation, Steven A. Falco <sfalco@harris.com>
8 *
9 * Based in part on drivers/spi/spi_s3c24xx.c
10 *
11 * Copyright (c) 2006 Ben Dooks
12 * Copyright (c) 2006 Simtec Electronics
13 * Ben Dooks <ben@simtec.co.uk>
14 */
15
16/*
17 * The PPC4xx SPI controller has no FIFO so each sent/received byte will
18 * generate an interrupt to the CPU. This can cause high CPU utilization.
19 * This driver allows platforms to reduce the interrupt load on the CPU
20 * during SPI transfers by setting max_speed_hz via the device tree.
21 */
22
23#include <linux/module.h>
24#include <linux/sched.h>
25#include <linux/slab.h>
26#include <linux/errno.h>
27#include <linux/wait.h>
28#include <linux/of_address.h>
29#include <linux/of_irq.h>
30#include <linux/of_platform.h>
31#include <linux/interrupt.h>
32#include <linux/delay.h>
33
34#include <linux/spi/spi.h>
35#include <linux/spi/spi_bitbang.h>
36
37#include <linux/io.h>
38#include <asm/dcr.h>
39#include <asm/dcr-regs.h>
40
41/* bits in mode register - bit 0 is MSb */
42
43/*
44 * SPI_PPC4XX_MODE_SCP = 0 means "data latched on trailing edge of clock"
45 * SPI_PPC4XX_MODE_SCP = 1 means "data latched on leading edge of clock"
46 * Note: This is the inverse of CPHA.
47 */
48#define SPI_PPC4XX_MODE_SCP (0x80 >> 3)
49
50/* SPI_PPC4XX_MODE_SPE = 1 means "port enabled" */
51#define SPI_PPC4XX_MODE_SPE (0x80 >> 4)
52
53/*
54 * SPI_PPC4XX_MODE_RD = 0 means "MSB first" - this is the normal mode
55 * SPI_PPC4XX_MODE_RD = 1 means "LSB first" - this is bit-reversed mode
56 * Note: This is identical to SPI_LSB_FIRST.
57 */
58#define SPI_PPC4XX_MODE_RD (0x80 >> 5)
59
60/*
61 * SPI_PPC4XX_MODE_CI = 0 means "clock idles low"
62 * SPI_PPC4XX_MODE_CI = 1 means "clock idles high"
63 * Note: This is identical to CPOL.
64 */
65#define SPI_PPC4XX_MODE_CI (0x80 >> 6)
66
67/*
68 * SPI_PPC4XX_MODE_IL = 0 means "loopback disable"
69 * SPI_PPC4XX_MODE_IL = 1 means "loopback enable"
70 */
71#define SPI_PPC4XX_MODE_IL (0x80 >> 7)
72
73/* bits in control register */
74/* starts a transfer when set */
75#define SPI_PPC4XX_CR_STR (0x80 >> 7)
76
77/* bits in status register */
78/* port is busy with a transfer */
79#define SPI_PPC4XX_SR_BSY (0x80 >> 6)
80/* RxD ready */
81#define SPI_PPC4XX_SR_RBR (0x80 >> 7)
82
83/* clock settings (SCP and CI) for various SPI modes */
84#define SPI_CLK_MODE0 (SPI_PPC4XX_MODE_SCP | 0)
85#define SPI_CLK_MODE1 (0 | 0)
86#define SPI_CLK_MODE2 (SPI_PPC4XX_MODE_SCP | SPI_PPC4XX_MODE_CI)
87#define SPI_CLK_MODE3 (0 | SPI_PPC4XX_MODE_CI)
88
89#define DRIVER_NAME "spi_ppc4xx_of"
90
91struct spi_ppc4xx_regs {
92 u8 mode;
93 u8 rxd;
94 u8 txd;
95 u8 cr;
96 u8 sr;
97 u8 dummy;
98 /*
99 * Clock divisor modulus register
100 * This uses the following formula:
101 * SCPClkOut = OPBCLK/(4(CDM + 1))
102 * or
103 * CDM = (OPBCLK/4*SCPClkOut) - 1
104 * bit 0 is the MSb!
105 */
106 u8 cdm;
107};
108
109/* SPI Controller driver's private data. */
110struct ppc4xx_spi {
111 /* bitbang has to be first */
112 struct spi_bitbang bitbang;
113 struct completion done;
114
115 u64 mapbase;
116 u64 mapsize;
117 int irqnum;
118 /* need this to set the SPI clock */
119 unsigned int opb_freq;
120
121 /* for transfers */
122 int len;
123 int count;
124 /* data buffers */
125 const unsigned char *tx;
126 unsigned char *rx;
127
128 struct spi_ppc4xx_regs __iomem *regs; /* pointer to the registers */
129 struct spi_master *master;
130 struct device *dev;
131};
132
133/* need this so we can set the clock in the chipselect routine */
134struct spi_ppc4xx_cs {
135 u8 mode;
136};
137
138static int spi_ppc4xx_txrx(struct spi_device *spi, struct spi_transfer *t)
139{
140 struct ppc4xx_spi *hw;
141 u8 data;
142
143 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
144 t->tx_buf, t->rx_buf, t->len);
145
146 hw = spi_master_get_devdata(spi->master);
147
148 hw->tx = t->tx_buf;
149 hw->rx = t->rx_buf;
150 hw->len = t->len;
151 hw->count = 0;
152
153 /* send the first byte */
154 data = hw->tx ? hw->tx[0] : 0;
155 out_8(&hw->regs->txd, data);
156 out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR);
157 wait_for_completion(&hw->done);
158
159 return hw->count;
160}
161
162static int spi_ppc4xx_setupxfer(struct spi_device *spi, struct spi_transfer *t)
163{
164 struct ppc4xx_spi *hw = spi_master_get_devdata(spi->master);
165 struct spi_ppc4xx_cs *cs = spi->controller_state;
166 int scr;
167 u8 cdm = 0;
168 u32 speed;
169 u8 bits_per_word;
170
171 /* Start with the generic configuration for this device. */
172 bits_per_word = spi->bits_per_word;
173 speed = spi->max_speed_hz;
174
175 /*
176 * Modify the configuration if the transfer overrides it. Do not allow
177 * the transfer to overwrite the generic configuration with zeros.
178 */
179 if (t) {
180 if (t->bits_per_word)
181 bits_per_word = t->bits_per_word;
182
183 if (t->speed_hz)
184 speed = min(t->speed_hz, spi->max_speed_hz);
185 }
186
187 if (!speed || (speed > spi->max_speed_hz)) {
188 dev_err(&spi->dev, "invalid speed_hz (%d)\n", speed);
189 return -EINVAL;
190 }
191
192 /* Write new configuration */
193 out_8(&hw->regs->mode, cs->mode);
194
195 /* Set the clock */
196 /* opb_freq was already divided by 4 */
197 scr = (hw->opb_freq / speed) - 1;
198 if (scr > 0)
199 cdm = min(scr, 0xff);
200
201 dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", cdm, speed);
202
203 if (in_8(&hw->regs->cdm) != cdm)
204 out_8(&hw->regs->cdm, cdm);
205
206 mutex_lock(&hw->bitbang.lock);
207 if (!hw->bitbang.busy) {
208 hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
209 /* Need to ndelay here? */
210 }
211 mutex_unlock(&hw->bitbang.lock);
212
213 return 0;
214}
215
216static int spi_ppc4xx_setup(struct spi_device *spi)
217{
218 struct spi_ppc4xx_cs *cs = spi->controller_state;
219
220 if (!spi->max_speed_hz) {
221 dev_err(&spi->dev, "invalid max_speed_hz (must be non-zero)\n");
222 return -EINVAL;
223 }
224
225 if (cs == NULL) {
226 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
227 if (!cs)
228 return -ENOMEM;
229 spi->controller_state = cs;
230 }
231
232 /*
233 * We set all bits of the SPI0_MODE register, so,
234 * no need to read-modify-write
235 */
236 cs->mode = SPI_PPC4XX_MODE_SPE;
237
238 switch (spi->mode & SPI_MODE_X_MASK) {
239 case SPI_MODE_0:
240 cs->mode |= SPI_CLK_MODE0;
241 break;
242 case SPI_MODE_1:
243 cs->mode |= SPI_CLK_MODE1;
244 break;
245 case SPI_MODE_2:
246 cs->mode |= SPI_CLK_MODE2;
247 break;
248 case SPI_MODE_3:
249 cs->mode |= SPI_CLK_MODE3;
250 break;
251 }
252
253 if (spi->mode & SPI_LSB_FIRST)
254 cs->mode |= SPI_PPC4XX_MODE_RD;
255
256 return 0;
257}
258
259static irqreturn_t spi_ppc4xx_int(int irq, void *dev_id)
260{
261 struct ppc4xx_spi *hw;
262 u8 status;
263 u8 data;
264 unsigned int count;
265
266 hw = (struct ppc4xx_spi *)dev_id;
267
268 status = in_8(&hw->regs->sr);
269 if (!status)
270 return IRQ_NONE;
271
272 /*
273 * BSY de-asserts one cycle after the transfer is complete. The
274 * interrupt is asserted after the transfer is complete. The exact
275 * relationship is not documented, hence this code.
276 */
277
278 if (unlikely(status & SPI_PPC4XX_SR_BSY)) {
279 u8 lstatus;
280 int cnt = 0;
281
282 dev_dbg(hw->dev, "got interrupt but spi still busy?\n");
283 do {
284 ndelay(10);
285 lstatus = in_8(&hw->regs->sr);
286 } while (++cnt < 100 && lstatus & SPI_PPC4XX_SR_BSY);
287
288 if (cnt >= 100) {
289 dev_err(hw->dev, "busywait: too many loops!\n");
290 complete(&hw->done);
291 return IRQ_HANDLED;
292 } else {
293 /* status is always 1 (RBR) here */
294 status = in_8(&hw->regs->sr);
295 dev_dbg(hw->dev, "loops %d status %x\n", cnt, status);
296 }
297 }
298
299 count = hw->count;
300 hw->count++;
301
302 /* RBR triggered this interrupt. Therefore, data must be ready. */
303 data = in_8(&hw->regs->rxd);
304 if (hw->rx)
305 hw->rx[count] = data;
306
307 count++;
308
309 if (count < hw->len) {
310 data = hw->tx ? hw->tx[count] : 0;
311 out_8(&hw->regs->txd, data);
312 out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR);
313 } else {
314 complete(&hw->done);
315 }
316
317 return IRQ_HANDLED;
318}
319
320static void spi_ppc4xx_cleanup(struct spi_device *spi)
321{
322 kfree(spi->controller_state);
323}
324
325static void spi_ppc4xx_enable(struct ppc4xx_spi *hw)
326{
327 /*
328 * On all 4xx PPC's the SPI bus is shared/multiplexed with
329 * the 2nd I2C bus. We need to enable the SPI bus before
330 * using it.
331 */
332
333 /* need to clear bit 14 to enable SPC */
334 dcri_clrset(SDR0, SDR0_PFC1, 0x80000000 >> 14, 0);
335}
336
337/*
338 * platform_device layer stuff...
339 */
340static int spi_ppc4xx_of_probe(struct platform_device *op)
341{
342 struct ppc4xx_spi *hw;
343 struct spi_master *master;
344 struct spi_bitbang *bbp;
345 struct resource resource;
346 struct device_node *np = op->dev.of_node;
347 struct device *dev = &op->dev;
348 struct device_node *opbnp;
349 int ret;
350 const unsigned int *clk;
351
352 master = spi_alloc_master(dev, sizeof(*hw));
353 if (master == NULL)
354 return -ENOMEM;
355 master->dev.of_node = np;
356 platform_set_drvdata(op, master);
357 hw = spi_master_get_devdata(master);
358 hw->master = master;
359 hw->dev = dev;
360
361 init_completion(&hw->done);
362
363 /* Setup the state for the bitbang driver */
364 bbp = &hw->bitbang;
365 bbp->master = hw->master;
366 bbp->setup_transfer = spi_ppc4xx_setupxfer;
367 bbp->txrx_bufs = spi_ppc4xx_txrx;
368 bbp->use_dma = 0;
369 bbp->master->setup = spi_ppc4xx_setup;
370 bbp->master->cleanup = spi_ppc4xx_cleanup;
371 bbp->master->bits_per_word_mask = SPI_BPW_MASK(8);
372 bbp->master->use_gpio_descriptors = true;
373 /*
374 * The SPI core will count the number of GPIO descriptors to figure
375 * out the number of chip selects available on the platform.
376 */
377 bbp->master->num_chipselect = 0;
378
379 /* the spi->mode bits understood by this driver: */
380 bbp->master->mode_bits =
381 SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST;
382
383 /* Get the clock for the OPB */
384 opbnp = of_find_compatible_node(NULL, NULL, "ibm,opb");
385 if (opbnp == NULL) {
386 dev_err(dev, "OPB: cannot find node\n");
387 ret = -ENODEV;
388 goto free_master;
389 }
390 /* Get the clock (Hz) for the OPB */
391 clk = of_get_property(opbnp, "clock-frequency", NULL);
392 if (clk == NULL) {
393 dev_err(dev, "OPB: no clock-frequency property set\n");
394 of_node_put(opbnp);
395 ret = -ENODEV;
396 goto free_master;
397 }
398 hw->opb_freq = *clk;
399 hw->opb_freq >>= 2;
400 of_node_put(opbnp);
401
402 ret = of_address_to_resource(np, 0, &resource);
403 if (ret) {
404 dev_err(dev, "error while parsing device node resource\n");
405 goto free_master;
406 }
407 hw->mapbase = resource.start;
408 hw->mapsize = resource_size(&resource);
409
410 /* Sanity check */
411 if (hw->mapsize < sizeof(struct spi_ppc4xx_regs)) {
412 dev_err(dev, "too small to map registers\n");
413 ret = -EINVAL;
414 goto free_master;
415 }
416
417 /* Request IRQ */
418 hw->irqnum = irq_of_parse_and_map(np, 0);
419 ret = request_irq(hw->irqnum, spi_ppc4xx_int,
420 0, "spi_ppc4xx_of", (void *)hw);
421 if (ret) {
422 dev_err(dev, "unable to allocate interrupt\n");
423 goto free_master;
424 }
425
426 if (!request_mem_region(hw->mapbase, hw->mapsize, DRIVER_NAME)) {
427 dev_err(dev, "resource unavailable\n");
428 ret = -EBUSY;
429 goto request_mem_error;
430 }
431
432 hw->regs = ioremap(hw->mapbase, sizeof(struct spi_ppc4xx_regs));
433
434 if (!hw->regs) {
435 dev_err(dev, "unable to memory map registers\n");
436 ret = -ENXIO;
437 goto map_io_error;
438 }
439
440 spi_ppc4xx_enable(hw);
441
442 /* Finally register our spi controller */
443 dev->dma_mask = 0;
444 ret = spi_bitbang_start(bbp);
445 if (ret) {
446 dev_err(dev, "failed to register SPI master\n");
447 goto unmap_regs;
448 }
449
450 dev_info(dev, "driver initialized\n");
451
452 return 0;
453
454unmap_regs:
455 iounmap(hw->regs);
456map_io_error:
457 release_mem_region(hw->mapbase, hw->mapsize);
458request_mem_error:
459 free_irq(hw->irqnum, hw);
460free_master:
461 spi_master_put(master);
462
463 dev_err(dev, "initialization failed\n");
464 return ret;
465}
466
467static int spi_ppc4xx_of_remove(struct platform_device *op)
468{
469 struct spi_master *master = platform_get_drvdata(op);
470 struct ppc4xx_spi *hw = spi_master_get_devdata(master);
471
472 spi_bitbang_stop(&hw->bitbang);
473 release_mem_region(hw->mapbase, hw->mapsize);
474 free_irq(hw->irqnum, hw);
475 iounmap(hw->regs);
476 spi_master_put(master);
477 return 0;
478}
479
480static const struct of_device_id spi_ppc4xx_of_match[] = {
481 { .compatible = "ibm,ppc4xx-spi", },
482 {},
483};
484
485MODULE_DEVICE_TABLE(of, spi_ppc4xx_of_match);
486
487static struct platform_driver spi_ppc4xx_of_driver = {
488 .probe = spi_ppc4xx_of_probe,
489 .remove = spi_ppc4xx_of_remove,
490 .driver = {
491 .name = DRIVER_NAME,
492 .of_match_table = spi_ppc4xx_of_match,
493 },
494};
495module_platform_driver(spi_ppc4xx_of_driver);
496
497MODULE_AUTHOR("Gary Jennejohn & Stefan Roese");
498MODULE_DESCRIPTION("Simple PPC4xx SPI Driver");
499MODULE_LICENSE("GPL");