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1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright 2013 Freescale Semiconductor, Inc.
4// Copyright 2020 NXP
5//
6// Freescale DSPI driver
7// This file contains a driver for the Freescale DSPI
8
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/dmaengine.h>
12#include <linux/dma-mapping.h>
13#include <linux/interrupt.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/of_device.h>
17#include <linux/pinctrl/consumer.h>
18#include <linux/regmap.h>
19#include <linux/spi/spi.h>
20#include <linux/spi/spi-fsl-dspi.h>
21
22#define DRIVER_NAME "fsl-dspi"
23
24#define SPI_MCR 0x00
25#define SPI_MCR_MASTER BIT(31)
26#define SPI_MCR_PCSIS(x) ((x) << 16)
27#define SPI_MCR_CLR_TXF BIT(11)
28#define SPI_MCR_CLR_RXF BIT(10)
29#define SPI_MCR_XSPI BIT(3)
30#define SPI_MCR_DIS_TXF BIT(13)
31#define SPI_MCR_DIS_RXF BIT(12)
32#define SPI_MCR_HALT BIT(0)
33
34#define SPI_TCR 0x08
35#define SPI_TCR_GET_TCNT(x) (((x) & GENMASK(31, 16)) >> 16)
36
37#define SPI_CTAR(x) (0x0c + (((x) & GENMASK(1, 0)) * 4))
38#define SPI_CTAR_FMSZ(x) (((x) << 27) & GENMASK(30, 27))
39#define SPI_CTAR_CPOL BIT(26)
40#define SPI_CTAR_CPHA BIT(25)
41#define SPI_CTAR_LSBFE BIT(24)
42#define SPI_CTAR_PCSSCK(x) (((x) << 22) & GENMASK(23, 22))
43#define SPI_CTAR_PASC(x) (((x) << 20) & GENMASK(21, 20))
44#define SPI_CTAR_PDT(x) (((x) << 18) & GENMASK(19, 18))
45#define SPI_CTAR_PBR(x) (((x) << 16) & GENMASK(17, 16))
46#define SPI_CTAR_CSSCK(x) (((x) << 12) & GENMASK(15, 12))
47#define SPI_CTAR_ASC(x) (((x) << 8) & GENMASK(11, 8))
48#define SPI_CTAR_DT(x) (((x) << 4) & GENMASK(7, 4))
49#define SPI_CTAR_BR(x) ((x) & GENMASK(3, 0))
50#define SPI_CTAR_SCALE_BITS 0xf
51
52#define SPI_CTAR0_SLAVE 0x0c
53
54#define SPI_SR 0x2c
55#define SPI_SR_TCFQF BIT(31)
56#define SPI_SR_TFUF BIT(27)
57#define SPI_SR_TFFF BIT(25)
58#define SPI_SR_CMDTCF BIT(23)
59#define SPI_SR_SPEF BIT(21)
60#define SPI_SR_RFOF BIT(19)
61#define SPI_SR_TFIWF BIT(18)
62#define SPI_SR_RFDF BIT(17)
63#define SPI_SR_CMDFFF BIT(16)
64#define SPI_SR_CLEAR (SPI_SR_TCFQF | \
65 SPI_SR_TFUF | SPI_SR_TFFF | \
66 SPI_SR_CMDTCF | SPI_SR_SPEF | \
67 SPI_SR_RFOF | SPI_SR_TFIWF | \
68 SPI_SR_RFDF | SPI_SR_CMDFFF)
69
70#define SPI_RSER_TFFFE BIT(25)
71#define SPI_RSER_TFFFD BIT(24)
72#define SPI_RSER_RFDFE BIT(17)
73#define SPI_RSER_RFDFD BIT(16)
74
75#define SPI_RSER 0x30
76#define SPI_RSER_TCFQE BIT(31)
77#define SPI_RSER_CMDTCFE BIT(23)
78
79#define SPI_PUSHR 0x34
80#define SPI_PUSHR_CMD_CONT BIT(15)
81#define SPI_PUSHR_CMD_CTAS(x) (((x) << 12 & GENMASK(14, 12)))
82#define SPI_PUSHR_CMD_EOQ BIT(11)
83#define SPI_PUSHR_CMD_CTCNT BIT(10)
84#define SPI_PUSHR_CMD_PCS(x) (BIT(x) & GENMASK(5, 0))
85
86#define SPI_PUSHR_SLAVE 0x34
87
88#define SPI_POPR 0x38
89
90#define SPI_TXFR0 0x3c
91#define SPI_TXFR1 0x40
92#define SPI_TXFR2 0x44
93#define SPI_TXFR3 0x48
94#define SPI_RXFR0 0x7c
95#define SPI_RXFR1 0x80
96#define SPI_RXFR2 0x84
97#define SPI_RXFR3 0x88
98
99#define SPI_CTARE(x) (0x11c + (((x) & GENMASK(1, 0)) * 4))
100#define SPI_CTARE_FMSZE(x) (((x) & 0x1) << 16)
101#define SPI_CTARE_DTCP(x) ((x) & 0x7ff)
102
103#define SPI_SREX 0x13c
104
105#define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1)
106#define SPI_FRAME_EBITS(bits) SPI_CTARE_FMSZE(((bits) - 1) >> 4)
107
108#define DMA_COMPLETION_TIMEOUT msecs_to_jiffies(3000)
109
110struct chip_data {
111 u32 ctar_val;
112};
113
114enum dspi_trans_mode {
115 DSPI_XSPI_MODE,
116 DSPI_DMA_MODE,
117};
118
119struct fsl_dspi_devtype_data {
120 enum dspi_trans_mode trans_mode;
121 u8 max_clock_factor;
122 int fifo_size;
123};
124
125enum {
126 LS1021A,
127 LS1012A,
128 LS1028A,
129 LS1043A,
130 LS1046A,
131 LS2080A,
132 LS2085A,
133 LX2160A,
134 MCF5441X,
135 VF610,
136};
137
138static const struct fsl_dspi_devtype_data devtype_data[] = {
139 [VF610] = {
140 .trans_mode = DSPI_DMA_MODE,
141 .max_clock_factor = 2,
142 .fifo_size = 4,
143 },
144 [LS1021A] = {
145 /* Has A-011218 DMA erratum */
146 .trans_mode = DSPI_XSPI_MODE,
147 .max_clock_factor = 8,
148 .fifo_size = 4,
149 },
150 [LS1012A] = {
151 /* Has A-011218 DMA erratum */
152 .trans_mode = DSPI_XSPI_MODE,
153 .max_clock_factor = 8,
154 .fifo_size = 16,
155 },
156 [LS1028A] = {
157 .trans_mode = DSPI_XSPI_MODE,
158 .max_clock_factor = 8,
159 .fifo_size = 4,
160 },
161 [LS1043A] = {
162 /* Has A-011218 DMA erratum */
163 .trans_mode = DSPI_XSPI_MODE,
164 .max_clock_factor = 8,
165 .fifo_size = 16,
166 },
167 [LS1046A] = {
168 /* Has A-011218 DMA erratum */
169 .trans_mode = DSPI_XSPI_MODE,
170 .max_clock_factor = 8,
171 .fifo_size = 16,
172 },
173 [LS2080A] = {
174 .trans_mode = DSPI_XSPI_MODE,
175 .max_clock_factor = 8,
176 .fifo_size = 4,
177 },
178 [LS2085A] = {
179 .trans_mode = DSPI_XSPI_MODE,
180 .max_clock_factor = 8,
181 .fifo_size = 4,
182 },
183 [LX2160A] = {
184 .trans_mode = DSPI_XSPI_MODE,
185 .max_clock_factor = 8,
186 .fifo_size = 4,
187 },
188 [MCF5441X] = {
189 .trans_mode = DSPI_DMA_MODE,
190 .max_clock_factor = 8,
191 .fifo_size = 16,
192 },
193};
194
195struct fsl_dspi_dma {
196 u32 *tx_dma_buf;
197 struct dma_chan *chan_tx;
198 dma_addr_t tx_dma_phys;
199 struct completion cmd_tx_complete;
200 struct dma_async_tx_descriptor *tx_desc;
201
202 u32 *rx_dma_buf;
203 struct dma_chan *chan_rx;
204 dma_addr_t rx_dma_phys;
205 struct completion cmd_rx_complete;
206 struct dma_async_tx_descriptor *rx_desc;
207};
208
209struct fsl_dspi {
210 struct spi_controller *ctlr;
211 struct platform_device *pdev;
212
213 struct regmap *regmap;
214 struct regmap *regmap_pushr;
215 int irq;
216 struct clk *clk;
217
218 struct spi_transfer *cur_transfer;
219 struct spi_message *cur_msg;
220 struct chip_data *cur_chip;
221 size_t progress;
222 size_t len;
223 const void *tx;
224 void *rx;
225 u16 tx_cmd;
226 const struct fsl_dspi_devtype_data *devtype_data;
227
228 struct completion xfer_done;
229
230 struct fsl_dspi_dma *dma;
231
232 int oper_word_size;
233 int oper_bits_per_word;
234
235 int words_in_flight;
236
237 /*
238 * Offsets for CMD and TXDATA within SPI_PUSHR when accessed
239 * individually (in XSPI mode)
240 */
241 int pushr_cmd;
242 int pushr_tx;
243
244 void (*host_to_dev)(struct fsl_dspi *dspi, u32 *txdata);
245 void (*dev_to_host)(struct fsl_dspi *dspi, u32 rxdata);
246};
247
248static void dspi_native_host_to_dev(struct fsl_dspi *dspi, u32 *txdata)
249{
250 switch (dspi->oper_word_size) {
251 case 1:
252 *txdata = *(u8 *)dspi->tx;
253 break;
254 case 2:
255 *txdata = *(u16 *)dspi->tx;
256 break;
257 case 4:
258 *txdata = *(u32 *)dspi->tx;
259 break;
260 }
261 dspi->tx += dspi->oper_word_size;
262}
263
264static void dspi_native_dev_to_host(struct fsl_dspi *dspi, u32 rxdata)
265{
266 switch (dspi->oper_word_size) {
267 case 1:
268 *(u8 *)dspi->rx = rxdata;
269 break;
270 case 2:
271 *(u16 *)dspi->rx = rxdata;
272 break;
273 case 4:
274 *(u32 *)dspi->rx = rxdata;
275 break;
276 }
277 dspi->rx += dspi->oper_word_size;
278}
279
280static void dspi_8on32_host_to_dev(struct fsl_dspi *dspi, u32 *txdata)
281{
282 *txdata = cpu_to_be32(*(u32 *)dspi->tx);
283 dspi->tx += sizeof(u32);
284}
285
286static void dspi_8on32_dev_to_host(struct fsl_dspi *dspi, u32 rxdata)
287{
288 *(u32 *)dspi->rx = be32_to_cpu(rxdata);
289 dspi->rx += sizeof(u32);
290}
291
292static void dspi_8on16_host_to_dev(struct fsl_dspi *dspi, u32 *txdata)
293{
294 *txdata = cpu_to_be16(*(u16 *)dspi->tx);
295 dspi->tx += sizeof(u16);
296}
297
298static void dspi_8on16_dev_to_host(struct fsl_dspi *dspi, u32 rxdata)
299{
300 *(u16 *)dspi->rx = be16_to_cpu(rxdata);
301 dspi->rx += sizeof(u16);
302}
303
304static void dspi_16on32_host_to_dev(struct fsl_dspi *dspi, u32 *txdata)
305{
306 u16 hi = *(u16 *)dspi->tx;
307 u16 lo = *(u16 *)(dspi->tx + 2);
308
309 *txdata = (u32)hi << 16 | lo;
310 dspi->tx += sizeof(u32);
311}
312
313static void dspi_16on32_dev_to_host(struct fsl_dspi *dspi, u32 rxdata)
314{
315 u16 hi = rxdata & 0xffff;
316 u16 lo = rxdata >> 16;
317
318 *(u16 *)dspi->rx = lo;
319 *(u16 *)(dspi->rx + 2) = hi;
320 dspi->rx += sizeof(u32);
321}
322
323/*
324 * Pop one word from the TX buffer for pushing into the
325 * PUSHR register (TX FIFO)
326 */
327static u32 dspi_pop_tx(struct fsl_dspi *dspi)
328{
329 u32 txdata = 0;
330
331 if (dspi->tx)
332 dspi->host_to_dev(dspi, &txdata);
333 dspi->len -= dspi->oper_word_size;
334 return txdata;
335}
336
337/* Prepare one TX FIFO entry (txdata plus cmd) */
338static u32 dspi_pop_tx_pushr(struct fsl_dspi *dspi)
339{
340 u16 cmd = dspi->tx_cmd, data = dspi_pop_tx(dspi);
341
342 if (spi_controller_is_slave(dspi->ctlr))
343 return data;
344
345 if (dspi->len > 0)
346 cmd |= SPI_PUSHR_CMD_CONT;
347 return cmd << 16 | data;
348}
349
350/* Push one word to the RX buffer from the POPR register (RX FIFO) */
351static void dspi_push_rx(struct fsl_dspi *dspi, u32 rxdata)
352{
353 if (!dspi->rx)
354 return;
355 dspi->dev_to_host(dspi, rxdata);
356}
357
358static void dspi_tx_dma_callback(void *arg)
359{
360 struct fsl_dspi *dspi = arg;
361 struct fsl_dspi_dma *dma = dspi->dma;
362
363 complete(&dma->cmd_tx_complete);
364}
365
366static void dspi_rx_dma_callback(void *arg)
367{
368 struct fsl_dspi *dspi = arg;
369 struct fsl_dspi_dma *dma = dspi->dma;
370 int i;
371
372 if (dspi->rx) {
373 for (i = 0; i < dspi->words_in_flight; i++)
374 dspi_push_rx(dspi, dspi->dma->rx_dma_buf[i]);
375 }
376
377 complete(&dma->cmd_rx_complete);
378}
379
380static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi)
381{
382 struct device *dev = &dspi->pdev->dev;
383 struct fsl_dspi_dma *dma = dspi->dma;
384 int time_left;
385 int i;
386
387 for (i = 0; i < dspi->words_in_flight; i++)
388 dspi->dma->tx_dma_buf[i] = dspi_pop_tx_pushr(dspi);
389
390 dma->tx_desc = dmaengine_prep_slave_single(dma->chan_tx,
391 dma->tx_dma_phys,
392 dspi->words_in_flight *
393 DMA_SLAVE_BUSWIDTH_4_BYTES,
394 DMA_MEM_TO_DEV,
395 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
396 if (!dma->tx_desc) {
397 dev_err(dev, "Not able to get desc for DMA xfer\n");
398 return -EIO;
399 }
400
401 dma->tx_desc->callback = dspi_tx_dma_callback;
402 dma->tx_desc->callback_param = dspi;
403 if (dma_submit_error(dmaengine_submit(dma->tx_desc))) {
404 dev_err(dev, "DMA submit failed\n");
405 return -EINVAL;
406 }
407
408 dma->rx_desc = dmaengine_prep_slave_single(dma->chan_rx,
409 dma->rx_dma_phys,
410 dspi->words_in_flight *
411 DMA_SLAVE_BUSWIDTH_4_BYTES,
412 DMA_DEV_TO_MEM,
413 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
414 if (!dma->rx_desc) {
415 dev_err(dev, "Not able to get desc for DMA xfer\n");
416 return -EIO;
417 }
418
419 dma->rx_desc->callback = dspi_rx_dma_callback;
420 dma->rx_desc->callback_param = dspi;
421 if (dma_submit_error(dmaengine_submit(dma->rx_desc))) {
422 dev_err(dev, "DMA submit failed\n");
423 return -EINVAL;
424 }
425
426 reinit_completion(&dspi->dma->cmd_rx_complete);
427 reinit_completion(&dspi->dma->cmd_tx_complete);
428
429 dma_async_issue_pending(dma->chan_rx);
430 dma_async_issue_pending(dma->chan_tx);
431
432 if (spi_controller_is_slave(dspi->ctlr)) {
433 wait_for_completion_interruptible(&dspi->dma->cmd_rx_complete);
434 return 0;
435 }
436
437 time_left = wait_for_completion_timeout(&dspi->dma->cmd_tx_complete,
438 DMA_COMPLETION_TIMEOUT);
439 if (time_left == 0) {
440 dev_err(dev, "DMA tx timeout\n");
441 dmaengine_terminate_all(dma->chan_tx);
442 dmaengine_terminate_all(dma->chan_rx);
443 return -ETIMEDOUT;
444 }
445
446 time_left = wait_for_completion_timeout(&dspi->dma->cmd_rx_complete,
447 DMA_COMPLETION_TIMEOUT);
448 if (time_left == 0) {
449 dev_err(dev, "DMA rx timeout\n");
450 dmaengine_terminate_all(dma->chan_tx);
451 dmaengine_terminate_all(dma->chan_rx);
452 return -ETIMEDOUT;
453 }
454
455 return 0;
456}
457
458static void dspi_setup_accel(struct fsl_dspi *dspi);
459
460static int dspi_dma_xfer(struct fsl_dspi *dspi)
461{
462 struct spi_message *message = dspi->cur_msg;
463 struct device *dev = &dspi->pdev->dev;
464 int ret = 0;
465
466 /*
467 * dspi->len gets decremented by dspi_pop_tx_pushr in
468 * dspi_next_xfer_dma_submit
469 */
470 while (dspi->len) {
471 /* Figure out operational bits-per-word for this chunk */
472 dspi_setup_accel(dspi);
473
474 dspi->words_in_flight = dspi->len / dspi->oper_word_size;
475 if (dspi->words_in_flight > dspi->devtype_data->fifo_size)
476 dspi->words_in_flight = dspi->devtype_data->fifo_size;
477
478 message->actual_length += dspi->words_in_flight *
479 dspi->oper_word_size;
480
481 ret = dspi_next_xfer_dma_submit(dspi);
482 if (ret) {
483 dev_err(dev, "DMA transfer failed\n");
484 break;
485 }
486 }
487
488 return ret;
489}
490
491static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr)
492{
493 int dma_bufsize = dspi->devtype_data->fifo_size * 2;
494 struct device *dev = &dspi->pdev->dev;
495 struct dma_slave_config cfg;
496 struct fsl_dspi_dma *dma;
497 int ret;
498
499 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
500 if (!dma)
501 return -ENOMEM;
502
503 dma->chan_rx = dma_request_chan(dev, "rx");
504 if (IS_ERR(dma->chan_rx)) {
505 dev_err(dev, "rx dma channel not available\n");
506 ret = PTR_ERR(dma->chan_rx);
507 return ret;
508 }
509
510 dma->chan_tx = dma_request_chan(dev, "tx");
511 if (IS_ERR(dma->chan_tx)) {
512 dev_err(dev, "tx dma channel not available\n");
513 ret = PTR_ERR(dma->chan_tx);
514 goto err_tx_channel;
515 }
516
517 dma->tx_dma_buf = dma_alloc_coherent(dma->chan_tx->device->dev,
518 dma_bufsize, &dma->tx_dma_phys,
519 GFP_KERNEL);
520 if (!dma->tx_dma_buf) {
521 ret = -ENOMEM;
522 goto err_tx_dma_buf;
523 }
524
525 dma->rx_dma_buf = dma_alloc_coherent(dma->chan_rx->device->dev,
526 dma_bufsize, &dma->rx_dma_phys,
527 GFP_KERNEL);
528 if (!dma->rx_dma_buf) {
529 ret = -ENOMEM;
530 goto err_rx_dma_buf;
531 }
532
533 memset(&cfg, 0, sizeof(cfg));
534 cfg.src_addr = phy_addr + SPI_POPR;
535 cfg.dst_addr = phy_addr + SPI_PUSHR;
536 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
537 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
538 cfg.src_maxburst = 1;
539 cfg.dst_maxburst = 1;
540
541 cfg.direction = DMA_DEV_TO_MEM;
542 ret = dmaengine_slave_config(dma->chan_rx, &cfg);
543 if (ret) {
544 dev_err(dev, "can't configure rx dma channel\n");
545 ret = -EINVAL;
546 goto err_slave_config;
547 }
548
549 cfg.direction = DMA_MEM_TO_DEV;
550 ret = dmaengine_slave_config(dma->chan_tx, &cfg);
551 if (ret) {
552 dev_err(dev, "can't configure tx dma channel\n");
553 ret = -EINVAL;
554 goto err_slave_config;
555 }
556
557 dspi->dma = dma;
558 init_completion(&dma->cmd_tx_complete);
559 init_completion(&dma->cmd_rx_complete);
560
561 return 0;
562
563err_slave_config:
564 dma_free_coherent(dma->chan_rx->device->dev,
565 dma_bufsize, dma->rx_dma_buf, dma->rx_dma_phys);
566err_rx_dma_buf:
567 dma_free_coherent(dma->chan_tx->device->dev,
568 dma_bufsize, dma->tx_dma_buf, dma->tx_dma_phys);
569err_tx_dma_buf:
570 dma_release_channel(dma->chan_tx);
571err_tx_channel:
572 dma_release_channel(dma->chan_rx);
573
574 devm_kfree(dev, dma);
575 dspi->dma = NULL;
576
577 return ret;
578}
579
580static void dspi_release_dma(struct fsl_dspi *dspi)
581{
582 int dma_bufsize = dspi->devtype_data->fifo_size * 2;
583 struct fsl_dspi_dma *dma = dspi->dma;
584
585 if (!dma)
586 return;
587
588 if (dma->chan_tx) {
589 dma_free_coherent(dma->chan_tx->device->dev, dma_bufsize,
590 dma->tx_dma_buf, dma->tx_dma_phys);
591 dma_release_channel(dma->chan_tx);
592 }
593
594 if (dma->chan_rx) {
595 dma_free_coherent(dma->chan_rx->device->dev, dma_bufsize,
596 dma->rx_dma_buf, dma->rx_dma_phys);
597 dma_release_channel(dma->chan_rx);
598 }
599}
600
601static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
602 unsigned long clkrate)
603{
604 /* Valid baud rate pre-scaler values */
605 int pbr_tbl[4] = {2, 3, 5, 7};
606 int brs[16] = { 2, 4, 6, 8,
607 16, 32, 64, 128,
608 256, 512, 1024, 2048,
609 4096, 8192, 16384, 32768 };
610 int scale_needed, scale, minscale = INT_MAX;
611 int i, j;
612
613 scale_needed = clkrate / speed_hz;
614 if (clkrate % speed_hz)
615 scale_needed++;
616
617 for (i = 0; i < ARRAY_SIZE(brs); i++)
618 for (j = 0; j < ARRAY_SIZE(pbr_tbl); j++) {
619 scale = brs[i] * pbr_tbl[j];
620 if (scale >= scale_needed) {
621 if (scale < minscale) {
622 minscale = scale;
623 *br = i;
624 *pbr = j;
625 }
626 break;
627 }
628 }
629
630 if (minscale == INT_MAX) {
631 pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld, we use the max prescaler value.\n",
632 speed_hz, clkrate);
633 *pbr = ARRAY_SIZE(pbr_tbl) - 1;
634 *br = ARRAY_SIZE(brs) - 1;
635 }
636}
637
638static void ns_delay_scale(char *psc, char *sc, int delay_ns,
639 unsigned long clkrate)
640{
641 int scale_needed, scale, minscale = INT_MAX;
642 int pscale_tbl[4] = {1, 3, 5, 7};
643 u32 remainder;
644 int i, j;
645
646 scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC,
647 &remainder);
648 if (remainder)
649 scale_needed++;
650
651 for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++)
652 for (j = 0; j <= SPI_CTAR_SCALE_BITS; j++) {
653 scale = pscale_tbl[i] * (2 << j);
654 if (scale >= scale_needed) {
655 if (scale < minscale) {
656 minscale = scale;
657 *psc = i;
658 *sc = j;
659 }
660 break;
661 }
662 }
663
664 if (minscale == INT_MAX) {
665 pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value",
666 delay_ns, clkrate);
667 *psc = ARRAY_SIZE(pscale_tbl) - 1;
668 *sc = SPI_CTAR_SCALE_BITS;
669 }
670}
671
672static void dspi_pushr_cmd_write(struct fsl_dspi *dspi, u16 cmd)
673{
674 /*
675 * The only time when the PCS doesn't need continuation after this word
676 * is when it's last. We need to look ahead, because we actually call
677 * dspi_pop_tx (the function that decrements dspi->len) _after_
678 * dspi_pushr_cmd_write with XSPI mode. As for how much in advance? One
679 * word is enough. If there's more to transmit than that,
680 * dspi_xspi_write will know to split the FIFO writes in 2, and
681 * generate a new PUSHR command with the final word that will have PCS
682 * deasserted (not continued) here.
683 */
684 if (dspi->len > dspi->oper_word_size)
685 cmd |= SPI_PUSHR_CMD_CONT;
686 regmap_write(dspi->regmap_pushr, dspi->pushr_cmd, cmd);
687}
688
689static void dspi_pushr_txdata_write(struct fsl_dspi *dspi, u16 txdata)
690{
691 regmap_write(dspi->regmap_pushr, dspi->pushr_tx, txdata);
692}
693
694static void dspi_xspi_fifo_write(struct fsl_dspi *dspi, int num_words)
695{
696 int num_bytes = num_words * dspi->oper_word_size;
697 u16 tx_cmd = dspi->tx_cmd;
698
699 /*
700 * If the PCS needs to de-assert (i.e. we're at the end of the buffer
701 * and cs_change does not want the PCS to stay on), then we need a new
702 * PUSHR command, since this one (for the body of the buffer)
703 * necessarily has the CONT bit set.
704 * So send one word less during this go, to force a split and a command
705 * with a single word next time, when CONT will be unset.
706 */
707 if (!(dspi->tx_cmd & SPI_PUSHR_CMD_CONT) && num_bytes == dspi->len)
708 tx_cmd |= SPI_PUSHR_CMD_EOQ;
709
710 /* Update CTARE */
711 regmap_write(dspi->regmap, SPI_CTARE(0),
712 SPI_FRAME_EBITS(dspi->oper_bits_per_word) |
713 SPI_CTARE_DTCP(num_words));
714
715 /*
716 * Write the CMD FIFO entry first, and then the two
717 * corresponding TX FIFO entries (or one...).
718 */
719 dspi_pushr_cmd_write(dspi, tx_cmd);
720
721 /* Fill TX FIFO with as many transfers as possible */
722 while (num_words--) {
723 u32 data = dspi_pop_tx(dspi);
724
725 dspi_pushr_txdata_write(dspi, data & 0xFFFF);
726 if (dspi->oper_bits_per_word > 16)
727 dspi_pushr_txdata_write(dspi, data >> 16);
728 }
729}
730
731static u32 dspi_popr_read(struct fsl_dspi *dspi)
732{
733 u32 rxdata = 0;
734
735 regmap_read(dspi->regmap, SPI_POPR, &rxdata);
736 return rxdata;
737}
738
739static void dspi_fifo_read(struct fsl_dspi *dspi)
740{
741 int num_fifo_entries = dspi->words_in_flight;
742
743 /* Read one FIFO entry and push to rx buffer */
744 while (num_fifo_entries--)
745 dspi_push_rx(dspi, dspi_popr_read(dspi));
746}
747
748static void dspi_setup_accel(struct fsl_dspi *dspi)
749{
750 struct spi_transfer *xfer = dspi->cur_transfer;
751 bool odd = !!(dspi->len & 1);
752
753 /* No accel for frames not multiple of 8 bits at the moment */
754 if (xfer->bits_per_word % 8)
755 goto no_accel;
756
757 if (!odd && dspi->len <= dspi->devtype_data->fifo_size * 2) {
758 dspi->oper_bits_per_word = 16;
759 } else if (odd && dspi->len <= dspi->devtype_data->fifo_size) {
760 dspi->oper_bits_per_word = 8;
761 } else {
762 /* Start off with maximum supported by hardware */
763 if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
764 dspi->oper_bits_per_word = 32;
765 else
766 dspi->oper_bits_per_word = 16;
767
768 /*
769 * And go down only if the buffer can't be sent with
770 * words this big
771 */
772 do {
773 if (dspi->len >= DIV_ROUND_UP(dspi->oper_bits_per_word, 8))
774 break;
775
776 dspi->oper_bits_per_word /= 2;
777 } while (dspi->oper_bits_per_word > 8);
778 }
779
780 if (xfer->bits_per_word == 8 && dspi->oper_bits_per_word == 32) {
781 dspi->dev_to_host = dspi_8on32_dev_to_host;
782 dspi->host_to_dev = dspi_8on32_host_to_dev;
783 } else if (xfer->bits_per_word == 8 && dspi->oper_bits_per_word == 16) {
784 dspi->dev_to_host = dspi_8on16_dev_to_host;
785 dspi->host_to_dev = dspi_8on16_host_to_dev;
786 } else if (xfer->bits_per_word == 16 && dspi->oper_bits_per_word == 32) {
787 dspi->dev_to_host = dspi_16on32_dev_to_host;
788 dspi->host_to_dev = dspi_16on32_host_to_dev;
789 } else {
790no_accel:
791 dspi->dev_to_host = dspi_native_dev_to_host;
792 dspi->host_to_dev = dspi_native_host_to_dev;
793 dspi->oper_bits_per_word = xfer->bits_per_word;
794 }
795
796 dspi->oper_word_size = DIV_ROUND_UP(dspi->oper_bits_per_word, 8);
797
798 /*
799 * Update CTAR here (code is common for XSPI and DMA modes).
800 * We will update CTARE in the portion specific to XSPI, when we
801 * also know the preload value (DTCP).
802 */
803 regmap_write(dspi->regmap, SPI_CTAR(0),
804 dspi->cur_chip->ctar_val |
805 SPI_FRAME_BITS(dspi->oper_bits_per_word));
806}
807
808static void dspi_fifo_write(struct fsl_dspi *dspi)
809{
810 int num_fifo_entries = dspi->devtype_data->fifo_size;
811 struct spi_transfer *xfer = dspi->cur_transfer;
812 struct spi_message *msg = dspi->cur_msg;
813 int num_words, num_bytes;
814
815 dspi_setup_accel(dspi);
816
817 /* In XSPI mode each 32-bit word occupies 2 TX FIFO entries */
818 if (dspi->oper_word_size == 4)
819 num_fifo_entries /= 2;
820
821 /*
822 * Integer division intentionally trims off odd (or non-multiple of 4)
823 * numbers of bytes at the end of the buffer, which will be sent next
824 * time using a smaller oper_word_size.
825 */
826 num_words = dspi->len / dspi->oper_word_size;
827 if (num_words > num_fifo_entries)
828 num_words = num_fifo_entries;
829
830 /* Update total number of bytes that were transferred */
831 num_bytes = num_words * dspi->oper_word_size;
832 msg->actual_length += num_bytes;
833 dspi->progress += num_bytes / DIV_ROUND_UP(xfer->bits_per_word, 8);
834
835 /*
836 * Update shared variable for use in the next interrupt (both in
837 * dspi_fifo_read and in dspi_fifo_write).
838 */
839 dspi->words_in_flight = num_words;
840
841 spi_take_timestamp_pre(dspi->ctlr, xfer, dspi->progress, !dspi->irq);
842
843 dspi_xspi_fifo_write(dspi, num_words);
844 /*
845 * Everything after this point is in a potential race with the next
846 * interrupt, so we must never use dspi->words_in_flight again since it
847 * might already be modified by the next dspi_fifo_write.
848 */
849
850 spi_take_timestamp_post(dspi->ctlr, dspi->cur_transfer,
851 dspi->progress, !dspi->irq);
852}
853
854static int dspi_rxtx(struct fsl_dspi *dspi)
855{
856 dspi_fifo_read(dspi);
857
858 if (!dspi->len)
859 /* Success! */
860 return 0;
861
862 dspi_fifo_write(dspi);
863
864 return -EINPROGRESS;
865}
866
867static int dspi_poll(struct fsl_dspi *dspi)
868{
869 int tries = 1000;
870 u32 spi_sr;
871
872 do {
873 regmap_read(dspi->regmap, SPI_SR, &spi_sr);
874 regmap_write(dspi->regmap, SPI_SR, spi_sr);
875
876 if (spi_sr & SPI_SR_CMDTCF)
877 break;
878 } while (--tries);
879
880 if (!tries)
881 return -ETIMEDOUT;
882
883 return dspi_rxtx(dspi);
884}
885
886static irqreturn_t dspi_interrupt(int irq, void *dev_id)
887{
888 struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id;
889 u32 spi_sr;
890
891 regmap_read(dspi->regmap, SPI_SR, &spi_sr);
892 regmap_write(dspi->regmap, SPI_SR, spi_sr);
893
894 if (!(spi_sr & SPI_SR_CMDTCF))
895 return IRQ_NONE;
896
897 if (dspi_rxtx(dspi) == 0)
898 complete(&dspi->xfer_done);
899
900 return IRQ_HANDLED;
901}
902
903static void dspi_assert_cs(struct spi_device *spi, bool *cs)
904{
905 if (!spi->cs_gpiod || *cs)
906 return;
907
908 gpiod_set_value_cansleep(spi->cs_gpiod, true);
909 *cs = true;
910}
911
912static void dspi_deassert_cs(struct spi_device *spi, bool *cs)
913{
914 if (!spi->cs_gpiod || !*cs)
915 return;
916
917 gpiod_set_value_cansleep(spi->cs_gpiod, false);
918 *cs = false;
919}
920
921static int dspi_transfer_one_message(struct spi_controller *ctlr,
922 struct spi_message *message)
923{
924 struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
925 struct spi_device *spi = message->spi;
926 struct spi_transfer *transfer;
927 bool cs = false;
928 int status = 0;
929
930 message->actual_length = 0;
931
932 list_for_each_entry(transfer, &message->transfers, transfer_list) {
933 dspi->cur_transfer = transfer;
934 dspi->cur_msg = message;
935 dspi->cur_chip = spi_get_ctldata(spi);
936
937 dspi_assert_cs(spi, &cs);
938
939 /* Prepare command word for CMD FIFO */
940 dspi->tx_cmd = SPI_PUSHR_CMD_CTAS(0);
941 if (!spi->cs_gpiod)
942 dspi->tx_cmd |= SPI_PUSHR_CMD_PCS(spi->chip_select);
943
944 if (list_is_last(&dspi->cur_transfer->transfer_list,
945 &dspi->cur_msg->transfers)) {
946 /* Leave PCS activated after last transfer when
947 * cs_change is set.
948 */
949 if (transfer->cs_change)
950 dspi->tx_cmd |= SPI_PUSHR_CMD_CONT;
951 } else {
952 /* Keep PCS active between transfers in same message
953 * when cs_change is not set, and de-activate PCS
954 * between transfers in the same message when
955 * cs_change is set.
956 */
957 if (!transfer->cs_change)
958 dspi->tx_cmd |= SPI_PUSHR_CMD_CONT;
959 }
960
961 dspi->tx = transfer->tx_buf;
962 dspi->rx = transfer->rx_buf;
963 dspi->len = transfer->len;
964 dspi->progress = 0;
965
966 regmap_update_bits(dspi->regmap, SPI_MCR,
967 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
968 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
969
970 spi_take_timestamp_pre(dspi->ctlr, dspi->cur_transfer,
971 dspi->progress, !dspi->irq);
972
973 if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) {
974 status = dspi_dma_xfer(dspi);
975 } else {
976 dspi_fifo_write(dspi);
977
978 if (dspi->irq) {
979 wait_for_completion(&dspi->xfer_done);
980 reinit_completion(&dspi->xfer_done);
981 } else {
982 do {
983 status = dspi_poll(dspi);
984 } while (status == -EINPROGRESS);
985 }
986 }
987 if (status)
988 break;
989
990 spi_transfer_delay_exec(transfer);
991
992 if (!(dspi->tx_cmd & SPI_PUSHR_CMD_CONT))
993 dspi_deassert_cs(spi, &cs);
994 }
995
996 message->status = status;
997 spi_finalize_current_message(ctlr);
998
999 return status;
1000}
1001
1002static int dspi_setup(struct spi_device *spi)
1003{
1004 struct fsl_dspi *dspi = spi_controller_get_devdata(spi->controller);
1005 unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0;
1006 u32 cs_sck_delay = 0, sck_cs_delay = 0;
1007 struct fsl_dspi_platform_data *pdata;
1008 unsigned char pasc = 0, asc = 0;
1009 struct chip_data *chip;
1010 unsigned long clkrate;
1011 bool cs = true;
1012
1013 /* Only alloc on first setup */
1014 chip = spi_get_ctldata(spi);
1015 if (chip == NULL) {
1016 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1017 if (!chip)
1018 return -ENOMEM;
1019 }
1020
1021 pdata = dev_get_platdata(&dspi->pdev->dev);
1022
1023 if (!pdata) {
1024 of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay",
1025 &cs_sck_delay);
1026
1027 of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay",
1028 &sck_cs_delay);
1029 } else {
1030 cs_sck_delay = pdata->cs_sck_delay;
1031 sck_cs_delay = pdata->sck_cs_delay;
1032 }
1033
1034 clkrate = clk_get_rate(dspi->clk);
1035 hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate);
1036
1037 /* Set PCS to SCK delay scale values */
1038 ns_delay_scale(&pcssck, &cssck, cs_sck_delay, clkrate);
1039
1040 /* Set After SCK delay scale values */
1041 ns_delay_scale(&pasc, &asc, sck_cs_delay, clkrate);
1042
1043 chip->ctar_val = 0;
1044 if (spi->mode & SPI_CPOL)
1045 chip->ctar_val |= SPI_CTAR_CPOL;
1046 if (spi->mode & SPI_CPHA)
1047 chip->ctar_val |= SPI_CTAR_CPHA;
1048
1049 if (!spi_controller_is_slave(dspi->ctlr)) {
1050 chip->ctar_val |= SPI_CTAR_PCSSCK(pcssck) |
1051 SPI_CTAR_CSSCK(cssck) |
1052 SPI_CTAR_PASC(pasc) |
1053 SPI_CTAR_ASC(asc) |
1054 SPI_CTAR_PBR(pbr) |
1055 SPI_CTAR_BR(br);
1056
1057 if (spi->mode & SPI_LSB_FIRST)
1058 chip->ctar_val |= SPI_CTAR_LSBFE;
1059 }
1060
1061 gpiod_direction_output(spi->cs_gpiod, false);
1062 dspi_deassert_cs(spi, &cs);
1063
1064 spi_set_ctldata(spi, chip);
1065
1066 return 0;
1067}
1068
1069static void dspi_cleanup(struct spi_device *spi)
1070{
1071 struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);
1072
1073 dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n",
1074 spi->controller->bus_num, spi->chip_select);
1075
1076 kfree(chip);
1077}
1078
1079static const struct of_device_id fsl_dspi_dt_ids[] = {
1080 {
1081 .compatible = "fsl,vf610-dspi",
1082 .data = &devtype_data[VF610],
1083 }, {
1084 .compatible = "fsl,ls1021a-v1.0-dspi",
1085 .data = &devtype_data[LS1021A],
1086 }, {
1087 .compatible = "fsl,ls1012a-dspi",
1088 .data = &devtype_data[LS1012A],
1089 }, {
1090 .compatible = "fsl,ls1028a-dspi",
1091 .data = &devtype_data[LS1028A],
1092 }, {
1093 .compatible = "fsl,ls1043a-dspi",
1094 .data = &devtype_data[LS1043A],
1095 }, {
1096 .compatible = "fsl,ls1046a-dspi",
1097 .data = &devtype_data[LS1046A],
1098 }, {
1099 .compatible = "fsl,ls2080a-dspi",
1100 .data = &devtype_data[LS2080A],
1101 }, {
1102 .compatible = "fsl,ls2085a-dspi",
1103 .data = &devtype_data[LS2085A],
1104 }, {
1105 .compatible = "fsl,lx2160a-dspi",
1106 .data = &devtype_data[LX2160A],
1107 },
1108 { /* sentinel */ }
1109};
1110MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);
1111
1112#ifdef CONFIG_PM_SLEEP
1113static int dspi_suspend(struct device *dev)
1114{
1115 struct fsl_dspi *dspi = dev_get_drvdata(dev);
1116
1117 if (dspi->irq)
1118 disable_irq(dspi->irq);
1119 spi_controller_suspend(dspi->ctlr);
1120 clk_disable_unprepare(dspi->clk);
1121
1122 pinctrl_pm_select_sleep_state(dev);
1123
1124 return 0;
1125}
1126
1127static int dspi_resume(struct device *dev)
1128{
1129 struct fsl_dspi *dspi = dev_get_drvdata(dev);
1130 int ret;
1131
1132 pinctrl_pm_select_default_state(dev);
1133
1134 ret = clk_prepare_enable(dspi->clk);
1135 if (ret)
1136 return ret;
1137 spi_controller_resume(dspi->ctlr);
1138 if (dspi->irq)
1139 enable_irq(dspi->irq);
1140
1141 return 0;
1142}
1143#endif /* CONFIG_PM_SLEEP */
1144
1145static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);
1146
1147static const struct regmap_range dspi_volatile_ranges[] = {
1148 regmap_reg_range(SPI_MCR, SPI_TCR),
1149 regmap_reg_range(SPI_SR, SPI_SR),
1150 regmap_reg_range(SPI_PUSHR, SPI_RXFR3),
1151};
1152
1153static const struct regmap_access_table dspi_volatile_table = {
1154 .yes_ranges = dspi_volatile_ranges,
1155 .n_yes_ranges = ARRAY_SIZE(dspi_volatile_ranges),
1156};
1157
1158static const struct regmap_config dspi_regmap_config = {
1159 .reg_bits = 32,
1160 .val_bits = 32,
1161 .reg_stride = 4,
1162 .max_register = 0x88,
1163 .volatile_table = &dspi_volatile_table,
1164};
1165
1166static const struct regmap_range dspi_xspi_volatile_ranges[] = {
1167 regmap_reg_range(SPI_MCR, SPI_TCR),
1168 regmap_reg_range(SPI_SR, SPI_SR),
1169 regmap_reg_range(SPI_PUSHR, SPI_RXFR3),
1170 regmap_reg_range(SPI_SREX, SPI_SREX),
1171};
1172
1173static const struct regmap_access_table dspi_xspi_volatile_table = {
1174 .yes_ranges = dspi_xspi_volatile_ranges,
1175 .n_yes_ranges = ARRAY_SIZE(dspi_xspi_volatile_ranges),
1176};
1177
1178static const struct regmap_config dspi_xspi_regmap_config[] = {
1179 {
1180 .reg_bits = 32,
1181 .val_bits = 32,
1182 .reg_stride = 4,
1183 .max_register = 0x13c,
1184 .volatile_table = &dspi_xspi_volatile_table,
1185 },
1186 {
1187 .name = "pushr",
1188 .reg_bits = 16,
1189 .val_bits = 16,
1190 .reg_stride = 2,
1191 .max_register = 0x2,
1192 },
1193};
1194
1195static int dspi_init(struct fsl_dspi *dspi)
1196{
1197 unsigned int mcr;
1198
1199 /* Set idle states for all chip select signals to high */
1200 mcr = SPI_MCR_PCSIS(GENMASK(dspi->ctlr->max_native_cs - 1, 0));
1201
1202 if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
1203 mcr |= SPI_MCR_XSPI;
1204 if (!spi_controller_is_slave(dspi->ctlr))
1205 mcr |= SPI_MCR_MASTER;
1206
1207 regmap_write(dspi->regmap, SPI_MCR, mcr);
1208 regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR);
1209
1210 switch (dspi->devtype_data->trans_mode) {
1211 case DSPI_XSPI_MODE:
1212 regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_CMDTCFE);
1213 break;
1214 case DSPI_DMA_MODE:
1215 regmap_write(dspi->regmap, SPI_RSER,
1216 SPI_RSER_TFFFE | SPI_RSER_TFFFD |
1217 SPI_RSER_RFDFE | SPI_RSER_RFDFD);
1218 break;
1219 default:
1220 dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n",
1221 dspi->devtype_data->trans_mode);
1222 return -EINVAL;
1223 }
1224
1225 return 0;
1226}
1227
1228static int dspi_slave_abort(struct spi_master *master)
1229{
1230 struct fsl_dspi *dspi = spi_master_get_devdata(master);
1231
1232 /*
1233 * Terminate all pending DMA transactions for the SPI working
1234 * in SLAVE mode.
1235 */
1236 if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) {
1237 dmaengine_terminate_sync(dspi->dma->chan_rx);
1238 dmaengine_terminate_sync(dspi->dma->chan_tx);
1239 }
1240
1241 /* Clear the internal DSPI RX and TX FIFO buffers */
1242 regmap_update_bits(dspi->regmap, SPI_MCR,
1243 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
1244 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
1245
1246 return 0;
1247}
1248
1249static int dspi_probe(struct platform_device *pdev)
1250{
1251 struct device_node *np = pdev->dev.of_node;
1252 const struct regmap_config *regmap_config;
1253 struct fsl_dspi_platform_data *pdata;
1254 struct spi_controller *ctlr;
1255 int ret, cs_num, bus_num = -1;
1256 struct fsl_dspi *dspi;
1257 struct resource *res;
1258 void __iomem *base;
1259 bool big_endian;
1260
1261 dspi = devm_kzalloc(&pdev->dev, sizeof(*dspi), GFP_KERNEL);
1262 if (!dspi)
1263 return -ENOMEM;
1264
1265 ctlr = spi_alloc_master(&pdev->dev, 0);
1266 if (!ctlr)
1267 return -ENOMEM;
1268
1269 spi_controller_set_devdata(ctlr, dspi);
1270 platform_set_drvdata(pdev, dspi);
1271
1272 dspi->pdev = pdev;
1273 dspi->ctlr = ctlr;
1274
1275 ctlr->setup = dspi_setup;
1276 ctlr->transfer_one_message = dspi_transfer_one_message;
1277 ctlr->dev.of_node = pdev->dev.of_node;
1278
1279 ctlr->cleanup = dspi_cleanup;
1280 ctlr->slave_abort = dspi_slave_abort;
1281 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1282 ctlr->use_gpio_descriptors = true;
1283
1284 pdata = dev_get_platdata(&pdev->dev);
1285 if (pdata) {
1286 ctlr->num_chipselect = ctlr->max_native_cs = pdata->cs_num;
1287 ctlr->bus_num = pdata->bus_num;
1288
1289 /* Only Coldfire uses platform data */
1290 dspi->devtype_data = &devtype_data[MCF5441X];
1291 big_endian = true;
1292 } else {
1293
1294 ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num);
1295 if (ret < 0) {
1296 dev_err(&pdev->dev, "can't get spi-num-chipselects\n");
1297 goto out_ctlr_put;
1298 }
1299 ctlr->num_chipselect = ctlr->max_native_cs = cs_num;
1300
1301 of_property_read_u32(np, "bus-num", &bus_num);
1302 ctlr->bus_num = bus_num;
1303
1304 if (of_property_read_bool(np, "spi-slave"))
1305 ctlr->slave = true;
1306
1307 dspi->devtype_data = of_device_get_match_data(&pdev->dev);
1308 if (!dspi->devtype_data) {
1309 dev_err(&pdev->dev, "can't get devtype_data\n");
1310 ret = -EFAULT;
1311 goto out_ctlr_put;
1312 }
1313
1314 big_endian = of_device_is_big_endian(np);
1315 }
1316 if (big_endian) {
1317 dspi->pushr_cmd = 0;
1318 dspi->pushr_tx = 2;
1319 } else {
1320 dspi->pushr_cmd = 2;
1321 dspi->pushr_tx = 0;
1322 }
1323
1324 if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
1325 ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1326 else
1327 ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1328
1329 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1330 if (IS_ERR(base)) {
1331 ret = PTR_ERR(base);
1332 goto out_ctlr_put;
1333 }
1334
1335 if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
1336 regmap_config = &dspi_xspi_regmap_config[0];
1337 else
1338 regmap_config = &dspi_regmap_config;
1339 dspi->regmap = devm_regmap_init_mmio(&pdev->dev, base, regmap_config);
1340 if (IS_ERR(dspi->regmap)) {
1341 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
1342 PTR_ERR(dspi->regmap));
1343 ret = PTR_ERR(dspi->regmap);
1344 goto out_ctlr_put;
1345 }
1346
1347 if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) {
1348 dspi->regmap_pushr = devm_regmap_init_mmio(
1349 &pdev->dev, base + SPI_PUSHR,
1350 &dspi_xspi_regmap_config[1]);
1351 if (IS_ERR(dspi->regmap_pushr)) {
1352 dev_err(&pdev->dev,
1353 "failed to init pushr regmap: %ld\n",
1354 PTR_ERR(dspi->regmap_pushr));
1355 ret = PTR_ERR(dspi->regmap_pushr);
1356 goto out_ctlr_put;
1357 }
1358 }
1359
1360 dspi->clk = devm_clk_get(&pdev->dev, "dspi");
1361 if (IS_ERR(dspi->clk)) {
1362 ret = PTR_ERR(dspi->clk);
1363 dev_err(&pdev->dev, "unable to get clock\n");
1364 goto out_ctlr_put;
1365 }
1366 ret = clk_prepare_enable(dspi->clk);
1367 if (ret)
1368 goto out_ctlr_put;
1369
1370 ret = dspi_init(dspi);
1371 if (ret)
1372 goto out_clk_put;
1373
1374 dspi->irq = platform_get_irq(pdev, 0);
1375 if (dspi->irq <= 0) {
1376 dev_info(&pdev->dev,
1377 "can't get platform irq, using poll mode\n");
1378 dspi->irq = 0;
1379 goto poll_mode;
1380 }
1381
1382 init_completion(&dspi->xfer_done);
1383
1384 ret = request_threaded_irq(dspi->irq, dspi_interrupt, NULL,
1385 IRQF_SHARED, pdev->name, dspi);
1386 if (ret < 0) {
1387 dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n");
1388 goto out_clk_put;
1389 }
1390
1391poll_mode:
1392
1393 if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) {
1394 ret = dspi_request_dma(dspi, res->start);
1395 if (ret < 0) {
1396 dev_err(&pdev->dev, "can't get dma channels\n");
1397 goto out_free_irq;
1398 }
1399 }
1400
1401 ctlr->max_speed_hz =
1402 clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor;
1403
1404 if (dspi->devtype_data->trans_mode != DSPI_DMA_MODE)
1405 ctlr->ptp_sts_supported = true;
1406
1407 ret = spi_register_controller(ctlr);
1408 if (ret != 0) {
1409 dev_err(&pdev->dev, "Problem registering DSPI ctlr\n");
1410 goto out_release_dma;
1411 }
1412
1413 return ret;
1414
1415out_release_dma:
1416 dspi_release_dma(dspi);
1417out_free_irq:
1418 if (dspi->irq)
1419 free_irq(dspi->irq, dspi);
1420out_clk_put:
1421 clk_disable_unprepare(dspi->clk);
1422out_ctlr_put:
1423 spi_controller_put(ctlr);
1424
1425 return ret;
1426}
1427
1428static int dspi_remove(struct platform_device *pdev)
1429{
1430 struct fsl_dspi *dspi = platform_get_drvdata(pdev);
1431
1432 /* Disconnect from the SPI framework */
1433 spi_unregister_controller(dspi->ctlr);
1434
1435 /* Disable RX and TX */
1436 regmap_update_bits(dspi->regmap, SPI_MCR,
1437 SPI_MCR_DIS_TXF | SPI_MCR_DIS_RXF,
1438 SPI_MCR_DIS_TXF | SPI_MCR_DIS_RXF);
1439
1440 /* Stop Running */
1441 regmap_update_bits(dspi->regmap, SPI_MCR, SPI_MCR_HALT, SPI_MCR_HALT);
1442
1443 dspi_release_dma(dspi);
1444 if (dspi->irq)
1445 free_irq(dspi->irq, dspi);
1446 clk_disable_unprepare(dspi->clk);
1447
1448 return 0;
1449}
1450
1451static void dspi_shutdown(struct platform_device *pdev)
1452{
1453 dspi_remove(pdev);
1454}
1455
1456static struct platform_driver fsl_dspi_driver = {
1457 .driver.name = DRIVER_NAME,
1458 .driver.of_match_table = fsl_dspi_dt_ids,
1459 .driver.owner = THIS_MODULE,
1460 .driver.pm = &dspi_pm,
1461 .probe = dspi_probe,
1462 .remove = dspi_remove,
1463 .shutdown = dspi_shutdown,
1464};
1465module_platform_driver(fsl_dspi_driver);
1466
1467MODULE_DESCRIPTION("Freescale DSPI Controller Driver");
1468MODULE_LICENSE("GPL");
1469MODULE_ALIAS("platform:" DRIVER_NAME);