Loading...
Note: File does not exist in v3.5.6.
1/* SPDX-License-Identifier: GPL-2.0-only */
2
3#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
4#define __SOC_MEDIATEK_MT8195_MMSYS_H
5
6#define MT8195_VDO0_OVL_MOUT_EN 0xf14
7#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0)
8#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1)
9#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2)
10#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(4)
11#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(5)
12#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6)
13
14#define MT8195_VDO0_SEL_IN 0xf34
15#define MT8195_SEL_IN_VPP_MERGE_FROM_MASK GENMASK(1, 0)
16#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0)
17#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << 0)
18#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << 0)
19#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK GENMASK(4, 4)
20#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 << 4)
21#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << 4)
22#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK GENMASK(5, 5)
23#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 (0 << 5)
24#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 << 5)
25#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK GENMASK(8, 8)
26#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << 8)
27#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT (1 << 8)
28#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK GENMASK(9, 9)
29#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT (0 << 9)
30#define MT8195_SEL_IN_DP_INTF0_FROM_MASK GENMASK(13, 12)
31#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 << 0)
32#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 12)
33#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 << 12)
34#define MT8195_SEL_IN_DSI0_FROM_MASK GENMASK(16, 16)
35#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 16)
36#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 16)
37#define MT8195_SEL_IN_DSI1_FROM_MASK GENMASK(17, 17)
38#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT (0 << 17)
39#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE (1 << 17)
40#define MT8195_SEL_IN_DISP_WDMA1_FROM_MASK GENMASK(20, 20)
41#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 (0 << 20)
42#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE (1 << 20)
43#define MT8195_SEL_IN_DSC_WRAP1_FROM_MASK GENMASK(21, 21)
44#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN (0 << 21)
45#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 (1 << 21)
46#define MT8195_SEL_IN_DISP_WDMA0_FROM_MASK GENMASK(22, 22)
47#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 (0 << 22)
48
49#define MT8195_VDO0_SEL_OUT 0xf38
50#define MT8195_SOUT_DISP_DITHER0_TO_MASK BIT(0)
51#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0)
52#define MT8195_SOUT_DISP_DITHER0_TO_DSI0 (1 << 0)
53#define MT8195_SOUT_DISP_DITHER1_TO_MASK GENMASK(2, 1)
54#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 << 1)
55#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE (1 << 1)
56#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT (2 << 1)
57#define MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK GENMASK(4, 4)
58#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE (0 << 4)
59#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 (1 << 4)
60#define MT8195_SOUT_VPP_MERGE_TO_MASK GENMASK(10, 8)
61#define MT8195_SOUT_VPP_MERGE_TO_DSI1 (0 << 8)
62#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 (1 << 8)
63#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 (2 << 8)
64#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1 (3 << 8)
65#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN (4 << 8)
66#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK GENMASK(11, 11)
67#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN (0 << 11)
68#define MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK GENMASK(13, 12)
69#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 (0 << 12)
70#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 (1 << 12)
71#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE (2 << 12)
72#define MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK GENMASK(17, 16)
73#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 (0 << 16)
74#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 (1 << 16)
75#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16)
76#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16)
77
78static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
79 {
80 DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
81 MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0,
82 MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
83 }, {
84 DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
85 MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0,
86 MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0
87 }, {
88 DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL1,
89 MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1,
90 MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1
91 }, {
92 DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
93 MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1,
94 MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1
95 }, {
96 DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
97 MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1,
98 MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1
99 }, {
100 DDP_COMPONENT_OVL1, DDP_COMPONENT_OVL0,
101 MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0,
102 MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0
103 }, {
104 DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
105 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
106 MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
107 }, {
108 DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
109 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
110 MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1
111 }, {
112 DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
113 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
114 MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0
115 }, {
116 DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
117 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
118 MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
119 }, {
120 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
121 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
122 MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE
123 }, {
124 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
125 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
126 MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1
127 }, {
128 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
129 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
130 MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE
131 }, {
132 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
133 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
134 MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
135 }, {
136 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
137 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
138 MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
139 }, {
140 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
141 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
142 MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
143 }, {
144 DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
145 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
146 MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
147 }, {
148 DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
149 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
150 MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
151 }, {
152 DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
153 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
154 MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
155 }, {
156 DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
157 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
158 MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
159 }, {
160 DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
161 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
162 MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
163 }, {
164 DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
165 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
166 MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
167 }, {
168 DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
169 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
170 MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT
171 }, {
172 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
173 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
174 MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE
175 }, {
176 DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
177 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
178 MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0
179 }, {
180 DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
181 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
182 MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
183 }, {
184 DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
185 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
186 MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
187 }, {
188 DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
189 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
190 MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT
191 }, {
192 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
193 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
194 MT8195_SEL_IN_DSI1_FROM_VPP_MERGE
195 }, {
196 DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
197 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
198 MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1
199 }, {
200 DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
201 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
202 MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE
203 }, {
204 DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
205 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
206 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
207 }, {
208 DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
209 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
210 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
211 }, {
212 DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
213 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
214 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
215 }, {
216 DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
217 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
218 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
219 }, {
220 DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
221 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
222 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
223 }, {
224 DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
225 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
226 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
227 }, {
228 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
229 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
230 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
231 }, {
232 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
233 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
234 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
235 }, {
236 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
237 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
238 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
239 }, {
240 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
241 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
242 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
243 }, {
244 DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
245 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
246 MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
247 }, {
248 DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
249 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
250 MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
251 }, {
252 DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
253 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
254 MT8195_SOUT_DISP_DITHER0_TO_DSI0
255 }, {
256 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
257 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
258 MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN
259 }, {
260 DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
261 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
262 MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE
263 }, {
264 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
265 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
266 MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
267 }, {
268 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
269 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
270 MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
271 }, {
272 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF1,
273 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
274 MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
275 }, {
276 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
277 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
278 MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
279 }, {
280 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
281 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
282 MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
283 }, {
284 DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
285 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
286 MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE
287 }, {
288 DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
289 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
290 MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0
291 }, {
292 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
293 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
294 MT8195_SOUT_VPP_MERGE_TO_DSI1
295 }, {
296 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
297 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
298 MT8195_SOUT_VPP_MERGE_TO_DP_INTF0
299 }, {
300 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
301 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
302 MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
303 }, {
304 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
305 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
306 MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
307 }, {
308 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
309 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
310 MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
311 }, {
312 DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
313 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
314 MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1
315 }, {
316 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
317 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
318 MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN
319 }, {
320 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
321 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK,
322 MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN
323 }, {
324 DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
325 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
326 MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0
327 }, {
328 DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
329 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
330 MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
331 }, {
332 DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
333 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
334 MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
335 }, {
336 DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
337 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
338 MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
339 }, {
340 DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
341 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
342 MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
343 }, {
344 DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
345 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
346 MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1
347 }, {
348 DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
349 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
350 MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0
351 }, {
352 DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
353 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
354 MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
355 }, {
356 DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
357 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
358 MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
359 }, {
360 DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
361 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
362 MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
363 }, {
364 DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
365 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
366 MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE
367 }
368};
369
370#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */