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1/*
2 * Au1xxx counter0 (aka Time-Of-Year counter) RTC interface driver.
3 *
4 * Copyright (C) 2008 Manuel Lauss <mano@roarinelk.homelinux.net>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11/* All current Au1xxx SoCs have 2 counters fed by an external 32.768 kHz
12 * crystal. Counter 0, which keeps counting during sleep/powerdown, is
13 * used to count seconds since the beginning of the unix epoch.
14 *
15 * The counters must be configured and enabled by bootloader/board code;
16 * no checks as to whether they really get a proper 32.768kHz clock are
17 * made as this would take far too long.
18 */
19
20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/rtc.h>
23#include <linux/init.h>
24#include <linux/platform_device.h>
25#include <linux/io.h>
26#include <asm/mach-au1x00/au1000.h>
27
28/* 32kHz clock enabled and detected */
29#define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S)
30
31static int au1xtoy_rtc_read_time(struct device *dev, struct rtc_time *tm)
32{
33 unsigned long t;
34
35 t = au_readl(SYS_TOYREAD);
36
37 rtc_time_to_tm(t, tm);
38
39 return rtc_valid_tm(tm);
40}
41
42static int au1xtoy_rtc_set_time(struct device *dev, struct rtc_time *tm)
43{
44 unsigned long t;
45
46 rtc_tm_to_time(tm, &t);
47
48 au_writel(t, SYS_TOYWRITE);
49 au_sync();
50
51 /* wait for the pending register write to succeed. This can
52 * take up to 6 seconds...
53 */
54 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S)
55 msleep(1);
56
57 return 0;
58}
59
60static struct rtc_class_ops au1xtoy_rtc_ops = {
61 .read_time = au1xtoy_rtc_read_time,
62 .set_time = au1xtoy_rtc_set_time,
63};
64
65static int __devinit au1xtoy_rtc_probe(struct platform_device *pdev)
66{
67 struct rtc_device *rtcdev;
68 unsigned long t;
69 int ret;
70
71 t = au_readl(SYS_COUNTER_CNTRL);
72 if (!(t & CNTR_OK)) {
73 dev_err(&pdev->dev, "counters not working; aborting.\n");
74 ret = -ENODEV;
75 goto out_err;
76 }
77
78 ret = -ETIMEDOUT;
79
80 /* set counter0 tickrate to 1Hz if necessary */
81 if (au_readl(SYS_TOYTRIM) != 32767) {
82 /* wait until hardware gives access to TRIM register */
83 t = 0x00100000;
84 while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S) && --t)
85 msleep(1);
86
87 if (!t) {
88 /* timed out waiting for register access; assume
89 * counters are unusable.
90 */
91 dev_err(&pdev->dev, "timeout waiting for access\n");
92 goto out_err;
93 }
94
95 /* set 1Hz TOY tick rate */
96 au_writel(32767, SYS_TOYTRIM);
97 au_sync();
98 }
99
100 /* wait until the hardware allows writes to the counter reg */
101 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S)
102 msleep(1);
103
104 rtcdev = rtc_device_register("rtc-au1xxx", &pdev->dev,
105 &au1xtoy_rtc_ops, THIS_MODULE);
106 if (IS_ERR(rtcdev)) {
107 ret = PTR_ERR(rtcdev);
108 goto out_err;
109 }
110
111 platform_set_drvdata(pdev, rtcdev);
112
113 return 0;
114
115out_err:
116 return ret;
117}
118
119static int __devexit au1xtoy_rtc_remove(struct platform_device *pdev)
120{
121 struct rtc_device *rtcdev = platform_get_drvdata(pdev);
122
123 rtc_device_unregister(rtcdev);
124 platform_set_drvdata(pdev, NULL);
125
126 return 0;
127}
128
129static struct platform_driver au1xrtc_driver = {
130 .driver = {
131 .name = "rtc-au1xxx",
132 .owner = THIS_MODULE,
133 },
134 .remove = __devexit_p(au1xtoy_rtc_remove),
135};
136
137static int __init au1xtoy_rtc_init(void)
138{
139 return platform_driver_probe(&au1xrtc_driver, au1xtoy_rtc_probe);
140}
141
142static void __exit au1xtoy_rtc_exit(void)
143{
144 platform_driver_unregister(&au1xrtc_driver);
145}
146
147module_init(au1xtoy_rtc_init);
148module_exit(au1xtoy_rtc_exit);
149
150MODULE_DESCRIPTION("Au1xxx TOY-counter-based RTC driver");
151MODULE_AUTHOR("Manuel Lauss <manuel.lauss@gmail.com>");
152MODULE_LICENSE("GPL");
153MODULE_ALIAS("platform:rtc-au1xxx");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Au1xxx counter0 (aka Time-Of-Year counter) RTC interface driver.
4 *
5 * Copyright (C) 2008 Manuel Lauss <mano@roarinelk.homelinux.net>
6 */
7
8/* All current Au1xxx SoCs have 2 counters fed by an external 32.768 kHz
9 * crystal. Counter 0, which keeps counting during sleep/powerdown, is
10 * used to count seconds since the beginning of the unix epoch.
11 *
12 * The counters must be configured and enabled by bootloader/board code;
13 * no checks as to whether they really get a proper 32.768kHz clock are
14 * made as this would take far too long.
15 */
16
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/rtc.h>
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/io.h>
23#include <asm/mach-au1x00/au1000.h>
24
25/* 32kHz clock enabled and detected */
26#define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S)
27
28static int au1xtoy_rtc_read_time(struct device *dev, struct rtc_time *tm)
29{
30 unsigned long t;
31
32 t = alchemy_rdsys(AU1000_SYS_TOYREAD);
33
34 rtc_time64_to_tm(t, tm);
35
36 return 0;
37}
38
39static int au1xtoy_rtc_set_time(struct device *dev, struct rtc_time *tm)
40{
41 unsigned long t;
42
43 t = rtc_tm_to_time64(tm);
44
45 alchemy_wrsys(t, AU1000_SYS_TOYWRITE);
46
47 /* wait for the pending register write to succeed. This can
48 * take up to 6 seconds...
49 */
50 while (alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_C0S)
51 msleep(1);
52
53 return 0;
54}
55
56static const struct rtc_class_ops au1xtoy_rtc_ops = {
57 .read_time = au1xtoy_rtc_read_time,
58 .set_time = au1xtoy_rtc_set_time,
59};
60
61static int au1xtoy_rtc_probe(struct platform_device *pdev)
62{
63 struct rtc_device *rtcdev;
64 unsigned long t;
65
66 t = alchemy_rdsys(AU1000_SYS_CNTRCTRL);
67 if (!(t & CNTR_OK)) {
68 dev_err(&pdev->dev, "counters not working; aborting.\n");
69 return -ENODEV;
70 }
71
72 /* set counter0 tickrate to 1Hz if necessary */
73 if (alchemy_rdsys(AU1000_SYS_TOYTRIM) != 32767) {
74 /* wait until hardware gives access to TRIM register */
75 t = 0x00100000;
76 while ((alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_T0S) && --t)
77 msleep(1);
78
79 if (!t) {
80 /* timed out waiting for register access; assume
81 * counters are unusable.
82 */
83 dev_err(&pdev->dev, "timeout waiting for access\n");
84 return -ETIMEDOUT;
85 }
86
87 /* set 1Hz TOY tick rate */
88 alchemy_wrsys(32767, AU1000_SYS_TOYTRIM);
89 }
90
91 /* wait until the hardware allows writes to the counter reg */
92 while (alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_C0S)
93 msleep(1);
94
95 rtcdev = devm_rtc_allocate_device(&pdev->dev);
96 if (IS_ERR(rtcdev))
97 return PTR_ERR(rtcdev);
98
99 rtcdev->ops = &au1xtoy_rtc_ops;
100 rtcdev->range_max = U32_MAX;
101
102 platform_set_drvdata(pdev, rtcdev);
103
104 return devm_rtc_register_device(rtcdev);
105}
106
107static struct platform_driver au1xrtc_driver = {
108 .driver = {
109 .name = "rtc-au1xxx",
110 },
111};
112
113module_platform_driver_probe(au1xrtc_driver, au1xtoy_rtc_probe);
114
115MODULE_DESCRIPTION("Au1xxx TOY-counter-based RTC driver");
116MODULE_AUTHOR("Manuel Lauss <manuel.lauss@gmail.com>");
117MODULE_LICENSE("GPL");
118MODULE_ALIAS("platform:rtc-au1xxx");