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1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include "e1000.h"
30
31static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
32static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
33static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);
34static s32 e1000_wait_autoneg(struct e1000_hw *hw);
35static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg);
36static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
37 u16 *data, bool read, bool page_set);
38static u32 e1000_get_phy_addr_for_hv_page(u32 page);
39static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
40 u16 *data, bool read);
41
42/* Cable length tables */
43static const u16 e1000_m88_cable_length_table[] = {
44 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
45#define M88E1000_CABLE_LENGTH_TABLE_SIZE \
46 ARRAY_SIZE(e1000_m88_cable_length_table)
47
48static const u16 e1000_igp_2_cable_length_table[] = {
49 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
50 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
51 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
52 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
53 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
54 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
55 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
56 124};
57#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
58 ARRAY_SIZE(e1000_igp_2_cable_length_table)
59
60#define BM_PHY_REG_PAGE(offset) \
61 ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))
62#define BM_PHY_REG_NUM(offset) \
63 ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\
64 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\
65 ~MAX_PHY_REG_ADDRESS)))
66
67#define HV_INTC_FC_PAGE_START 768
68#define I82578_ADDR_REG 29
69#define I82577_ADDR_REG 16
70#define I82577_CFG_REG 22
71#define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15)
72#define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */
73#define I82577_CTRL_REG 23
74
75/* 82577 specific PHY registers */
76#define I82577_PHY_CTRL_2 18
77#define I82577_PHY_STATUS_2 26
78#define I82577_PHY_DIAG_STATUS 31
79
80/* I82577 PHY Status 2 */
81#define I82577_PHY_STATUS2_REV_POLARITY 0x0400
82#define I82577_PHY_STATUS2_MDIX 0x0800
83#define I82577_PHY_STATUS2_SPEED_MASK 0x0300
84#define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200
85
86/* I82577 PHY Control 2 */
87#define I82577_PHY_CTRL2_AUTO_MDIX 0x0400
88#define I82577_PHY_CTRL2_FORCE_MDI_MDIX 0x0200
89
90/* I82577 PHY Diagnostics Status */
91#define I82577_DSTATUS_CABLE_LENGTH 0x03FC
92#define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2
93
94/* BM PHY Copper Specific Control 1 */
95#define BM_CS_CTRL1 16
96
97#define HV_MUX_DATA_CTRL PHY_REG(776, 16)
98#define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400
99#define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004
100
101/**
102 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
103 * @hw: pointer to the HW structure
104 *
105 * Read the PHY management control register and check whether a PHY reset
106 * is blocked. If a reset is not blocked return 0, otherwise
107 * return E1000_BLK_PHY_RESET (12).
108 **/
109s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)
110{
111 u32 manc;
112
113 manc = er32(MANC);
114
115 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
116 E1000_BLK_PHY_RESET : 0;
117}
118
119/**
120 * e1000e_get_phy_id - Retrieve the PHY ID and revision
121 * @hw: pointer to the HW structure
122 *
123 * Reads the PHY registers and stores the PHY ID and possibly the PHY
124 * revision in the hardware structure.
125 **/
126s32 e1000e_get_phy_id(struct e1000_hw *hw)
127{
128 struct e1000_phy_info *phy = &hw->phy;
129 s32 ret_val = 0;
130 u16 phy_id;
131 u16 retry_count = 0;
132
133 if (!phy->ops.read_reg)
134 return 0;
135
136 while (retry_count < 2) {
137 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
138 if (ret_val)
139 return ret_val;
140
141 phy->id = (u32)(phy_id << 16);
142 udelay(20);
143 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
144 if (ret_val)
145 return ret_val;
146
147 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
148 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
149
150 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
151 return 0;
152
153 retry_count++;
154 }
155
156 return 0;
157}
158
159/**
160 * e1000e_phy_reset_dsp - Reset PHY DSP
161 * @hw: pointer to the HW structure
162 *
163 * Reset the digital signal processor.
164 **/
165s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
166{
167 s32 ret_val;
168
169 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
170 if (ret_val)
171 return ret_val;
172
173 return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);
174}
175
176/**
177 * e1000e_read_phy_reg_mdic - Read MDI control register
178 * @hw: pointer to the HW structure
179 * @offset: register offset to be read
180 * @data: pointer to the read data
181 *
182 * Reads the MDI control register in the PHY at offset and stores the
183 * information read to data.
184 **/
185s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
186{
187 struct e1000_phy_info *phy = &hw->phy;
188 u32 i, mdic = 0;
189
190 if (offset > MAX_PHY_REG_ADDRESS) {
191 e_dbg("PHY Address %d is out of range\n", offset);
192 return -E1000_ERR_PARAM;
193 }
194
195 /*
196 * Set up Op-code, Phy Address, and register offset in the MDI
197 * Control register. The MAC will take care of interfacing with the
198 * PHY to retrieve the desired data.
199 */
200 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
201 (phy->addr << E1000_MDIC_PHY_SHIFT) |
202 (E1000_MDIC_OP_READ));
203
204 ew32(MDIC, mdic);
205
206 /*
207 * Poll the ready bit to see if the MDI read completed
208 * Increasing the time out as testing showed failures with
209 * the lower time out
210 */
211 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
212 udelay(50);
213 mdic = er32(MDIC);
214 if (mdic & E1000_MDIC_READY)
215 break;
216 }
217 if (!(mdic & E1000_MDIC_READY)) {
218 e_dbg("MDI Read did not complete\n");
219 return -E1000_ERR_PHY;
220 }
221 if (mdic & E1000_MDIC_ERROR) {
222 e_dbg("MDI Error\n");
223 return -E1000_ERR_PHY;
224 }
225 *data = (u16) mdic;
226
227 /*
228 * Allow some time after each MDIC transaction to avoid
229 * reading duplicate data in the next MDIC transaction.
230 */
231 if (hw->mac.type == e1000_pch2lan)
232 udelay(100);
233
234 return 0;
235}
236
237/**
238 * e1000e_write_phy_reg_mdic - Write MDI control register
239 * @hw: pointer to the HW structure
240 * @offset: register offset to write to
241 * @data: data to write to register at offset
242 *
243 * Writes data to MDI control register in the PHY at offset.
244 **/
245s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
246{
247 struct e1000_phy_info *phy = &hw->phy;
248 u32 i, mdic = 0;
249
250 if (offset > MAX_PHY_REG_ADDRESS) {
251 e_dbg("PHY Address %d is out of range\n", offset);
252 return -E1000_ERR_PARAM;
253 }
254
255 /*
256 * Set up Op-code, Phy Address, and register offset in the MDI
257 * Control register. The MAC will take care of interfacing with the
258 * PHY to retrieve the desired data.
259 */
260 mdic = (((u32)data) |
261 (offset << E1000_MDIC_REG_SHIFT) |
262 (phy->addr << E1000_MDIC_PHY_SHIFT) |
263 (E1000_MDIC_OP_WRITE));
264
265 ew32(MDIC, mdic);
266
267 /*
268 * Poll the ready bit to see if the MDI read completed
269 * Increasing the time out as testing showed failures with
270 * the lower time out
271 */
272 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
273 udelay(50);
274 mdic = er32(MDIC);
275 if (mdic & E1000_MDIC_READY)
276 break;
277 }
278 if (!(mdic & E1000_MDIC_READY)) {
279 e_dbg("MDI Write did not complete\n");
280 return -E1000_ERR_PHY;
281 }
282 if (mdic & E1000_MDIC_ERROR) {
283 e_dbg("MDI Error\n");
284 return -E1000_ERR_PHY;
285 }
286
287 /*
288 * Allow some time after each MDIC transaction to avoid
289 * reading duplicate data in the next MDIC transaction.
290 */
291 if (hw->mac.type == e1000_pch2lan)
292 udelay(100);
293
294 return 0;
295}
296
297/**
298 * e1000e_read_phy_reg_m88 - Read m88 PHY register
299 * @hw: pointer to the HW structure
300 * @offset: register offset to be read
301 * @data: pointer to the read data
302 *
303 * Acquires semaphore, if necessary, then reads the PHY register at offset
304 * and storing the retrieved information in data. Release any acquired
305 * semaphores before exiting.
306 **/
307s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
308{
309 s32 ret_val;
310
311 ret_val = hw->phy.ops.acquire(hw);
312 if (ret_val)
313 return ret_val;
314
315 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
316 data);
317
318 hw->phy.ops.release(hw);
319
320 return ret_val;
321}
322
323/**
324 * e1000e_write_phy_reg_m88 - Write m88 PHY register
325 * @hw: pointer to the HW structure
326 * @offset: register offset to write to
327 * @data: data to write at register offset
328 *
329 * Acquires semaphore, if necessary, then writes the data to PHY register
330 * at the offset. Release any acquired semaphores before exiting.
331 **/
332s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
333{
334 s32 ret_val;
335
336 ret_val = hw->phy.ops.acquire(hw);
337 if (ret_val)
338 return ret_val;
339
340 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
341 data);
342
343 hw->phy.ops.release(hw);
344
345 return ret_val;
346}
347
348/**
349 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
350 * @hw: pointer to the HW structure
351 * @page: page to set (shifted left when necessary)
352 *
353 * Sets PHY page required for PHY register access. Assumes semaphore is
354 * already acquired. Note, this function sets phy.addr to 1 so the caller
355 * must set it appropriately (if necessary) after this function returns.
356 **/
357s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
358{
359 e_dbg("Setting page 0x%x\n", page);
360
361 hw->phy.addr = 1;
362
363 return e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
364}
365
366/**
367 * __e1000e_read_phy_reg_igp - Read igp PHY register
368 * @hw: pointer to the HW structure
369 * @offset: register offset to be read
370 * @data: pointer to the read data
371 * @locked: semaphore has already been acquired or not
372 *
373 * Acquires semaphore, if necessary, then reads the PHY register at offset
374 * and stores the retrieved information in data. Release any acquired
375 * semaphores before exiting.
376 **/
377static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
378 bool locked)
379{
380 s32 ret_val = 0;
381
382 if (!locked) {
383 if (!hw->phy.ops.acquire)
384 return 0;
385
386 ret_val = hw->phy.ops.acquire(hw);
387 if (ret_val)
388 return ret_val;
389 }
390
391 if (offset > MAX_PHY_MULTI_PAGE_REG)
392 ret_val = e1000e_write_phy_reg_mdic(hw,
393 IGP01E1000_PHY_PAGE_SELECT,
394 (u16)offset);
395 if (!ret_val)
396 ret_val = e1000e_read_phy_reg_mdic(hw,
397 MAX_PHY_REG_ADDRESS & offset,
398 data);
399 if (!locked)
400 hw->phy.ops.release(hw);
401
402 return ret_val;
403}
404
405/**
406 * e1000e_read_phy_reg_igp - Read igp PHY register
407 * @hw: pointer to the HW structure
408 * @offset: register offset to be read
409 * @data: pointer to the read data
410 *
411 * Acquires semaphore then reads the PHY register at offset and stores the
412 * retrieved information in data.
413 * Release the acquired semaphore before exiting.
414 **/
415s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
416{
417 return __e1000e_read_phy_reg_igp(hw, offset, data, false);
418}
419
420/**
421 * e1000e_read_phy_reg_igp_locked - Read igp PHY register
422 * @hw: pointer to the HW structure
423 * @offset: register offset to be read
424 * @data: pointer to the read data
425 *
426 * Reads the PHY register at offset and stores the retrieved information
427 * in data. Assumes semaphore already acquired.
428 **/
429s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
430{
431 return __e1000e_read_phy_reg_igp(hw, offset, data, true);
432}
433
434/**
435 * e1000e_write_phy_reg_igp - Write igp PHY register
436 * @hw: pointer to the HW structure
437 * @offset: register offset to write to
438 * @data: data to write at register offset
439 * @locked: semaphore has already been acquired or not
440 *
441 * Acquires semaphore, if necessary, then writes the data to PHY register
442 * at the offset. Release any acquired semaphores before exiting.
443 **/
444static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
445 bool locked)
446{
447 s32 ret_val = 0;
448
449 if (!locked) {
450 if (!hw->phy.ops.acquire)
451 return 0;
452
453 ret_val = hw->phy.ops.acquire(hw);
454 if (ret_val)
455 return ret_val;
456 }
457
458 if (offset > MAX_PHY_MULTI_PAGE_REG)
459 ret_val = e1000e_write_phy_reg_mdic(hw,
460 IGP01E1000_PHY_PAGE_SELECT,
461 (u16)offset);
462 if (!ret_val)
463 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
464 offset,
465 data);
466 if (!locked)
467 hw->phy.ops.release(hw);
468
469 return ret_val;
470}
471
472/**
473 * e1000e_write_phy_reg_igp - Write igp PHY register
474 * @hw: pointer to the HW structure
475 * @offset: register offset to write to
476 * @data: data to write at register offset
477 *
478 * Acquires semaphore then writes the data to PHY register
479 * at the offset. Release any acquired semaphores before exiting.
480 **/
481s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
482{
483 return __e1000e_write_phy_reg_igp(hw, offset, data, false);
484}
485
486/**
487 * e1000e_write_phy_reg_igp_locked - Write igp PHY register
488 * @hw: pointer to the HW structure
489 * @offset: register offset to write to
490 * @data: data to write at register offset
491 *
492 * Writes the data to PHY register at the offset.
493 * Assumes semaphore already acquired.
494 **/
495s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
496{
497 return __e1000e_write_phy_reg_igp(hw, offset, data, true);
498}
499
500/**
501 * __e1000_read_kmrn_reg - Read kumeran register
502 * @hw: pointer to the HW structure
503 * @offset: register offset to be read
504 * @data: pointer to the read data
505 * @locked: semaphore has already been acquired or not
506 *
507 * Acquires semaphore, if necessary. Then reads the PHY register at offset
508 * using the kumeran interface. The information retrieved is stored in data.
509 * Release any acquired semaphores before exiting.
510 **/
511static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
512 bool locked)
513{
514 u32 kmrnctrlsta;
515
516 if (!locked) {
517 s32 ret_val = 0;
518
519 if (!hw->phy.ops.acquire)
520 return 0;
521
522 ret_val = hw->phy.ops.acquire(hw);
523 if (ret_val)
524 return ret_val;
525 }
526
527 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
528 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
529 ew32(KMRNCTRLSTA, kmrnctrlsta);
530 e1e_flush();
531
532 udelay(2);
533
534 kmrnctrlsta = er32(KMRNCTRLSTA);
535 *data = (u16)kmrnctrlsta;
536
537 if (!locked)
538 hw->phy.ops.release(hw);
539
540 return 0;
541}
542
543/**
544 * e1000e_read_kmrn_reg - Read kumeran register
545 * @hw: pointer to the HW structure
546 * @offset: register offset to be read
547 * @data: pointer to the read data
548 *
549 * Acquires semaphore then reads the PHY register at offset using the
550 * kumeran interface. The information retrieved is stored in data.
551 * Release the acquired semaphore before exiting.
552 **/
553s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)
554{
555 return __e1000_read_kmrn_reg(hw, offset, data, false);
556}
557
558/**
559 * e1000e_read_kmrn_reg_locked - Read kumeran register
560 * @hw: pointer to the HW structure
561 * @offset: register offset to be read
562 * @data: pointer to the read data
563 *
564 * Reads the PHY register at offset using the kumeran interface. The
565 * information retrieved is stored in data.
566 * Assumes semaphore already acquired.
567 **/
568s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
569{
570 return __e1000_read_kmrn_reg(hw, offset, data, true);
571}
572
573/**
574 * __e1000_write_kmrn_reg - Write kumeran register
575 * @hw: pointer to the HW structure
576 * @offset: register offset to write to
577 * @data: data to write at register offset
578 * @locked: semaphore has already been acquired or not
579 *
580 * Acquires semaphore, if necessary. Then write the data to PHY register
581 * at the offset using the kumeran interface. Release any acquired semaphores
582 * before exiting.
583 **/
584static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
585 bool locked)
586{
587 u32 kmrnctrlsta;
588
589 if (!locked) {
590 s32 ret_val = 0;
591
592 if (!hw->phy.ops.acquire)
593 return 0;
594
595 ret_val = hw->phy.ops.acquire(hw);
596 if (ret_val)
597 return ret_val;
598 }
599
600 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
601 E1000_KMRNCTRLSTA_OFFSET) | data;
602 ew32(KMRNCTRLSTA, kmrnctrlsta);
603 e1e_flush();
604
605 udelay(2);
606
607 if (!locked)
608 hw->phy.ops.release(hw);
609
610 return 0;
611}
612
613/**
614 * e1000e_write_kmrn_reg - Write kumeran register
615 * @hw: pointer to the HW structure
616 * @offset: register offset to write to
617 * @data: data to write at register offset
618 *
619 * Acquires semaphore then writes the data to the PHY register at the offset
620 * using the kumeran interface. Release the acquired semaphore before exiting.
621 **/
622s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
623{
624 return __e1000_write_kmrn_reg(hw, offset, data, false);
625}
626
627/**
628 * e1000e_write_kmrn_reg_locked - Write kumeran register
629 * @hw: pointer to the HW structure
630 * @offset: register offset to write to
631 * @data: data to write at register offset
632 *
633 * Write the data to PHY register at the offset using the kumeran interface.
634 * Assumes semaphore already acquired.
635 **/
636s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
637{
638 return __e1000_write_kmrn_reg(hw, offset, data, true);
639}
640
641/**
642 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode
643 * @hw: pointer to the HW structure
644 *
645 * Sets up Master/slave mode
646 **/
647static s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
648{
649 s32 ret_val;
650 u16 phy_data;
651
652 /* Resolve Master/Slave mode */
653 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &phy_data);
654 if (ret_val)
655 return ret_val;
656
657 /* load defaults for future use */
658 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
659 ((phy_data & CR_1000T_MS_VALUE) ?
660 e1000_ms_force_master : e1000_ms_force_slave) : e1000_ms_auto;
661
662 switch (hw->phy.ms_type) {
663 case e1000_ms_force_master:
664 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
665 break;
666 case e1000_ms_force_slave:
667 phy_data |= CR_1000T_MS_ENABLE;
668 phy_data &= ~(CR_1000T_MS_VALUE);
669 break;
670 case e1000_ms_auto:
671 phy_data &= ~CR_1000T_MS_ENABLE;
672 /* fall-through */
673 default:
674 break;
675 }
676
677 return e1e_wphy(hw, PHY_1000T_CTRL, phy_data);
678}
679
680/**
681 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
682 * @hw: pointer to the HW structure
683 *
684 * Sets up Carrier-sense on Transmit and downshift values.
685 **/
686s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
687{
688 s32 ret_val;
689 u16 phy_data;
690
691 /* Enable CRS on Tx. This must be set for half-duplex operation. */
692 ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data);
693 if (ret_val)
694 return ret_val;
695
696 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
697
698 /* Enable downshift */
699 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
700
701 ret_val = e1e_wphy(hw, I82577_CFG_REG, phy_data);
702 if (ret_val)
703 return ret_val;
704
705 return e1000_set_master_slave_mode(hw);
706}
707
708/**
709 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link
710 * @hw: pointer to the HW structure
711 *
712 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
713 * and downshift values are set also.
714 **/
715s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
716{
717 struct e1000_phy_info *phy = &hw->phy;
718 s32 ret_val;
719 u16 phy_data;
720
721 /* Enable CRS on Tx. This must be set for half-duplex operation. */
722 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
723 if (ret_val)
724 return ret_val;
725
726 /* For BM PHY this bit is downshift enable */
727 if (phy->type != e1000_phy_bm)
728 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
729
730 /*
731 * Options:
732 * MDI/MDI-X = 0 (default)
733 * 0 - Auto for all speeds
734 * 1 - MDI mode
735 * 2 - MDI-X mode
736 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
737 */
738 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
739
740 switch (phy->mdix) {
741 case 1:
742 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
743 break;
744 case 2:
745 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
746 break;
747 case 3:
748 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
749 break;
750 case 0:
751 default:
752 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
753 break;
754 }
755
756 /*
757 * Options:
758 * disable_polarity_correction = 0 (default)
759 * Automatic Correction for Reversed Cable Polarity
760 * 0 - Disabled
761 * 1 - Enabled
762 */
763 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
764 if (phy->disable_polarity_correction)
765 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
766
767 /* Enable downshift on BM (disabled by default) */
768 if (phy->type == e1000_phy_bm) {
769 /* For 82574/82583, first disable then enable downshift */
770 if (phy->id == BME1000_E_PHY_ID_R2) {
771 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT;
772 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL,
773 phy_data);
774 if (ret_val)
775 return ret_val;
776 /* Commit the changes. */
777 ret_val = e1000e_commit_phy(hw);
778 if (ret_val) {
779 e_dbg("Error committing the PHY changes\n");
780 return ret_val;
781 }
782 }
783
784 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
785 }
786
787 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
788 if (ret_val)
789 return ret_val;
790
791 if ((phy->type == e1000_phy_m88) &&
792 (phy->revision < E1000_REVISION_4) &&
793 (phy->id != BME1000_E_PHY_ID_R2)) {
794 /*
795 * Force TX_CLK in the Extended PHY Specific Control Register
796 * to 25MHz clock.
797 */
798 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
799 if (ret_val)
800 return ret_val;
801
802 phy_data |= M88E1000_EPSCR_TX_CLK_25;
803
804 if ((phy->revision == 2) &&
805 (phy->id == M88E1111_I_PHY_ID)) {
806 /* 82573L PHY - set the downshift counter to 5x. */
807 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
808 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
809 } else {
810 /* Configure Master and Slave downshift values */
811 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
812 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
813 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
814 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
815 }
816 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
817 if (ret_val)
818 return ret_val;
819 }
820
821 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
822 /* Set PHY page 0, register 29 to 0x0003 */
823 ret_val = e1e_wphy(hw, 29, 0x0003);
824 if (ret_val)
825 return ret_val;
826
827 /* Set PHY page 0, register 30 to 0x0000 */
828 ret_val = e1e_wphy(hw, 30, 0x0000);
829 if (ret_val)
830 return ret_val;
831 }
832
833 /* Commit the changes. */
834 ret_val = e1000e_commit_phy(hw);
835 if (ret_val) {
836 e_dbg("Error committing the PHY changes\n");
837 return ret_val;
838 }
839
840 if (phy->type == e1000_phy_82578) {
841 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
842 if (ret_val)
843 return ret_val;
844
845 /* 82578 PHY - set the downshift count to 1x. */
846 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
847 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
848 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
849 if (ret_val)
850 return ret_val;
851 }
852
853 return 0;
854}
855
856/**
857 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link
858 * @hw: pointer to the HW structure
859 *
860 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
861 * igp PHY's.
862 **/
863s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
864{
865 struct e1000_phy_info *phy = &hw->phy;
866 s32 ret_val;
867 u16 data;
868
869 ret_val = e1000_phy_hw_reset(hw);
870 if (ret_val) {
871 e_dbg("Error resetting the PHY.\n");
872 return ret_val;
873 }
874
875 /*
876 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
877 * timeout issues when LFS is enabled.
878 */
879 msleep(100);
880
881 /* disable lplu d0 during driver init */
882 ret_val = e1000_set_d0_lplu_state(hw, false);
883 if (ret_val) {
884 e_dbg("Error Disabling LPLU D0\n");
885 return ret_val;
886 }
887 /* Configure mdi-mdix settings */
888 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data);
889 if (ret_val)
890 return ret_val;
891
892 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
893
894 switch (phy->mdix) {
895 case 1:
896 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
897 break;
898 case 2:
899 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
900 break;
901 case 0:
902 default:
903 data |= IGP01E1000_PSCR_AUTO_MDIX;
904 break;
905 }
906 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data);
907 if (ret_val)
908 return ret_val;
909
910 /* set auto-master slave resolution settings */
911 if (hw->mac.autoneg) {
912 /*
913 * when autonegotiation advertisement is only 1000Mbps then we
914 * should disable SmartSpeed and enable Auto MasterSlave
915 * resolution as hardware default.
916 */
917 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
918 /* Disable SmartSpeed */
919 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
920 &data);
921 if (ret_val)
922 return ret_val;
923
924 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
925 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
926 data);
927 if (ret_val)
928 return ret_val;
929
930 /* Set auto Master/Slave resolution process */
931 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data);
932 if (ret_val)
933 return ret_val;
934
935 data &= ~CR_1000T_MS_ENABLE;
936 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data);
937 if (ret_val)
938 return ret_val;
939 }
940
941 ret_val = e1000_set_master_slave_mode(hw);
942 }
943
944 return ret_val;
945}
946
947/**
948 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
949 * @hw: pointer to the HW structure
950 *
951 * Reads the MII auto-neg advertisement register and/or the 1000T control
952 * register and if the PHY is already setup for auto-negotiation, then
953 * return successful. Otherwise, setup advertisement and flow control to
954 * the appropriate values for the wanted auto-negotiation.
955 **/
956static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
957{
958 struct e1000_phy_info *phy = &hw->phy;
959 s32 ret_val;
960 u16 mii_autoneg_adv_reg;
961 u16 mii_1000t_ctrl_reg = 0;
962
963 phy->autoneg_advertised &= phy->autoneg_mask;
964
965 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
966 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
967 if (ret_val)
968 return ret_val;
969
970 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
971 /* Read the MII 1000Base-T Control Register (Address 9). */
972 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
973 if (ret_val)
974 return ret_val;
975 }
976
977 /*
978 * Need to parse both autoneg_advertised and fc and set up
979 * the appropriate PHY registers. First we will parse for
980 * autoneg_advertised software override. Since we can advertise
981 * a plethora of combinations, we need to check each bit
982 * individually.
983 */
984
985 /*
986 * First we clear all the 10/100 mb speed bits in the Auto-Neg
987 * Advertisement Register (Address 4) and the 1000 mb speed bits in
988 * the 1000Base-T Control Register (Address 9).
989 */
990 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
991 NWAY_AR_100TX_HD_CAPS |
992 NWAY_AR_10T_FD_CAPS |
993 NWAY_AR_10T_HD_CAPS);
994 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
995
996 e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
997
998 /* Do we want to advertise 10 Mb Half Duplex? */
999 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1000 e_dbg("Advertise 10mb Half duplex\n");
1001 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1002 }
1003
1004 /* Do we want to advertise 10 Mb Full Duplex? */
1005 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1006 e_dbg("Advertise 10mb Full duplex\n");
1007 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1008 }
1009
1010 /* Do we want to advertise 100 Mb Half Duplex? */
1011 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1012 e_dbg("Advertise 100mb Half duplex\n");
1013 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1014 }
1015
1016 /* Do we want to advertise 100 Mb Full Duplex? */
1017 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1018 e_dbg("Advertise 100mb Full duplex\n");
1019 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1020 }
1021
1022 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1023 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1024 e_dbg("Advertise 1000mb Half duplex request denied!\n");
1025
1026 /* Do we want to advertise 1000 Mb Full Duplex? */
1027 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1028 e_dbg("Advertise 1000mb Full duplex\n");
1029 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1030 }
1031
1032 /*
1033 * Check for a software override of the flow control settings, and
1034 * setup the PHY advertisement registers accordingly. If
1035 * auto-negotiation is enabled, then software will have to set the
1036 * "PAUSE" bits to the correct value in the Auto-Negotiation
1037 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1038 * negotiation.
1039 *
1040 * The possible values of the "fc" parameter are:
1041 * 0: Flow control is completely disabled
1042 * 1: Rx flow control is enabled (we can receive pause frames
1043 * but not send pause frames).
1044 * 2: Tx flow control is enabled (we can send pause frames
1045 * but we do not support receiving pause frames).
1046 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1047 * other: No software override. The flow control configuration
1048 * in the EEPROM is used.
1049 */
1050 switch (hw->fc.current_mode) {
1051 case e1000_fc_none:
1052 /*
1053 * Flow control (Rx & Tx) is completely disabled by a
1054 * software over-ride.
1055 */
1056 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1057 break;
1058 case e1000_fc_rx_pause:
1059 /*
1060 * Rx Flow control is enabled, and Tx Flow control is
1061 * disabled, by a software over-ride.
1062 *
1063 * Since there really isn't a way to advertise that we are
1064 * capable of Rx Pause ONLY, we will advertise that we
1065 * support both symmetric and asymmetric Rx PAUSE. Later
1066 * (in e1000e_config_fc_after_link_up) we will disable the
1067 * hw's ability to send PAUSE frames.
1068 */
1069 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1070 break;
1071 case e1000_fc_tx_pause:
1072 /*
1073 * Tx Flow control is enabled, and Rx Flow control is
1074 * disabled, by a software over-ride.
1075 */
1076 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1077 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1078 break;
1079 case e1000_fc_full:
1080 /*
1081 * Flow control (both Rx and Tx) is enabled by a software
1082 * over-ride.
1083 */
1084 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1085 break;
1086 default:
1087 e_dbg("Flow control param set incorrectly\n");
1088 return -E1000_ERR_CONFIG;
1089 }
1090
1091 ret_val = e1e_wphy(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1092 if (ret_val)
1093 return ret_val;
1094
1095 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1096
1097 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1098 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
1099
1100 return ret_val;
1101}
1102
1103/**
1104 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1105 * @hw: pointer to the HW structure
1106 *
1107 * Performs initial bounds checking on autoneg advertisement parameter, then
1108 * configure to advertise the full capability. Setup the PHY to autoneg
1109 * and restart the negotiation process between the link partner. If
1110 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1111 **/
1112static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1113{
1114 struct e1000_phy_info *phy = &hw->phy;
1115 s32 ret_val;
1116 u16 phy_ctrl;
1117
1118 /*
1119 * Perform some bounds checking on the autoneg advertisement
1120 * parameter.
1121 */
1122 phy->autoneg_advertised &= phy->autoneg_mask;
1123
1124 /*
1125 * If autoneg_advertised is zero, we assume it was not defaulted
1126 * by the calling code so we set to advertise full capability.
1127 */
1128 if (!phy->autoneg_advertised)
1129 phy->autoneg_advertised = phy->autoneg_mask;
1130
1131 e_dbg("Reconfiguring auto-neg advertisement params\n");
1132 ret_val = e1000_phy_setup_autoneg(hw);
1133 if (ret_val) {
1134 e_dbg("Error Setting up Auto-Negotiation\n");
1135 return ret_val;
1136 }
1137 e_dbg("Restarting Auto-Neg\n");
1138
1139 /*
1140 * Restart auto-negotiation by setting the Auto Neg Enable bit and
1141 * the Auto Neg Restart bit in the PHY control register.
1142 */
1143 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
1144 if (ret_val)
1145 return ret_val;
1146
1147 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1148 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
1149 if (ret_val)
1150 return ret_val;
1151
1152 /*
1153 * Does the user want to wait for Auto-Neg to complete here, or
1154 * check at a later time (for example, callback routine).
1155 */
1156 if (phy->autoneg_wait_to_complete) {
1157 ret_val = e1000_wait_autoneg(hw);
1158 if (ret_val) {
1159 e_dbg("Error while waiting for autoneg to complete\n");
1160 return ret_val;
1161 }
1162 }
1163
1164 hw->mac.get_link_status = true;
1165
1166 return ret_val;
1167}
1168
1169/**
1170 * e1000e_setup_copper_link - Configure copper link settings
1171 * @hw: pointer to the HW structure
1172 *
1173 * Calls the appropriate function to configure the link for auto-neg or forced
1174 * speed and duplex. Then we check for link, once link is established calls
1175 * to configure collision distance and flow control are called. If link is
1176 * not established, we return -E1000_ERR_PHY (-2).
1177 **/
1178s32 e1000e_setup_copper_link(struct e1000_hw *hw)
1179{
1180 s32 ret_val;
1181 bool link;
1182
1183 if (hw->mac.autoneg) {
1184 /*
1185 * Setup autoneg and flow control advertisement and perform
1186 * autonegotiation.
1187 */
1188 ret_val = e1000_copper_link_autoneg(hw);
1189 if (ret_val)
1190 return ret_val;
1191 } else {
1192 /*
1193 * PHY will be set to 10H, 10F, 100H or 100F
1194 * depending on user settings.
1195 */
1196 e_dbg("Forcing Speed and Duplex\n");
1197 ret_val = e1000_phy_force_speed_duplex(hw);
1198 if (ret_val) {
1199 e_dbg("Error Forcing Speed and Duplex\n");
1200 return ret_val;
1201 }
1202 }
1203
1204 /*
1205 * Check link status. Wait up to 100 microseconds for link to become
1206 * valid.
1207 */
1208 ret_val = e1000e_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1209 &link);
1210 if (ret_val)
1211 return ret_val;
1212
1213 if (link) {
1214 e_dbg("Valid link established!!!\n");
1215 hw->mac.ops.config_collision_dist(hw);
1216 ret_val = e1000e_config_fc_after_link_up(hw);
1217 } else {
1218 e_dbg("Unable to establish link!!!\n");
1219 }
1220
1221 return ret_val;
1222}
1223
1224/**
1225 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1226 * @hw: pointer to the HW structure
1227 *
1228 * Calls the PHY setup function to force speed and duplex. Clears the
1229 * auto-crossover to force MDI manually. Waits for link and returns
1230 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1231 **/
1232s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1233{
1234 struct e1000_phy_info *phy = &hw->phy;
1235 s32 ret_val;
1236 u16 phy_data;
1237 bool link;
1238
1239 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
1240 if (ret_val)
1241 return ret_val;
1242
1243 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1244
1245 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
1246 if (ret_val)
1247 return ret_val;
1248
1249 /*
1250 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
1251 * forced whenever speed and duplex are forced.
1252 */
1253 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1254 if (ret_val)
1255 return ret_val;
1256
1257 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1258 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1259
1260 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1261 if (ret_val)
1262 return ret_val;
1263
1264 e_dbg("IGP PSCR: %X\n", phy_data);
1265
1266 udelay(1);
1267
1268 if (phy->autoneg_wait_to_complete) {
1269 e_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1270
1271 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1272 100000, &link);
1273 if (ret_val)
1274 return ret_val;
1275
1276 if (!link)
1277 e_dbg("Link taking longer than expected.\n");
1278
1279 /* Try once more */
1280 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1281 100000, &link);
1282 }
1283
1284 return ret_val;
1285}
1286
1287/**
1288 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1289 * @hw: pointer to the HW structure
1290 *
1291 * Calls the PHY setup function to force speed and duplex. Clears the
1292 * auto-crossover to force MDI manually. Resets the PHY to commit the
1293 * changes. If time expires while waiting for link up, we reset the DSP.
1294 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1295 * successful completion, else return corresponding error code.
1296 **/
1297s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1298{
1299 struct e1000_phy_info *phy = &hw->phy;
1300 s32 ret_val;
1301 u16 phy_data;
1302 bool link;
1303
1304 /*
1305 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1306 * forced whenever speed and duplex are forced.
1307 */
1308 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1309 if (ret_val)
1310 return ret_val;
1311
1312 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1313 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1314 if (ret_val)
1315 return ret_val;
1316
1317 e_dbg("M88E1000 PSCR: %X\n", phy_data);
1318
1319 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
1320 if (ret_val)
1321 return ret_val;
1322
1323 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1324
1325 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
1326 if (ret_val)
1327 return ret_val;
1328
1329 /* Reset the phy to commit changes. */
1330 ret_val = e1000e_commit_phy(hw);
1331 if (ret_val)
1332 return ret_val;
1333
1334 if (phy->autoneg_wait_to_complete) {
1335 e_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1336
1337 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1338 100000, &link);
1339 if (ret_val)
1340 return ret_val;
1341
1342 if (!link) {
1343 if (hw->phy.type != e1000_phy_m88) {
1344 e_dbg("Link taking longer than expected.\n");
1345 } else {
1346 /*
1347 * We didn't get link.
1348 * Reset the DSP and cross our fingers.
1349 */
1350 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT,
1351 0x001d);
1352 if (ret_val)
1353 return ret_val;
1354 ret_val = e1000e_phy_reset_dsp(hw);
1355 if (ret_val)
1356 return ret_val;
1357 }
1358 }
1359
1360 /* Try once more */
1361 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1362 100000, &link);
1363 if (ret_val)
1364 return ret_val;
1365 }
1366
1367 if (hw->phy.type != e1000_phy_m88)
1368 return 0;
1369
1370 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1371 if (ret_val)
1372 return ret_val;
1373
1374 /*
1375 * Resetting the phy means we need to re-force TX_CLK in the
1376 * Extended PHY Specific Control Register to 25MHz clock from
1377 * the reset value of 2.5MHz.
1378 */
1379 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1380 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1381 if (ret_val)
1382 return ret_val;
1383
1384 /*
1385 * In addition, we must re-enable CRS on Tx for both half and full
1386 * duplex.
1387 */
1388 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1389 if (ret_val)
1390 return ret_val;
1391
1392 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1393 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1394
1395 return ret_val;
1396}
1397
1398/**
1399 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1400 * @hw: pointer to the HW structure
1401 *
1402 * Forces the speed and duplex settings of the PHY.
1403 * This is a function pointer entry point only called by
1404 * PHY setup routines.
1405 **/
1406s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1407{
1408 struct e1000_phy_info *phy = &hw->phy;
1409 s32 ret_val;
1410 u16 data;
1411 bool link;
1412
1413 ret_val = e1e_rphy(hw, PHY_CONTROL, &data);
1414 if (ret_val)
1415 return ret_val;
1416
1417 e1000e_phy_force_speed_duplex_setup(hw, &data);
1418
1419 ret_val = e1e_wphy(hw, PHY_CONTROL, data);
1420 if (ret_val)
1421 return ret_val;
1422
1423 /* Disable MDI-X support for 10/100 */
1424 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
1425 if (ret_val)
1426 return ret_val;
1427
1428 data &= ~IFE_PMC_AUTO_MDIX;
1429 data &= ~IFE_PMC_FORCE_MDIX;
1430
1431 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
1432 if (ret_val)
1433 return ret_val;
1434
1435 e_dbg("IFE PMC: %X\n", data);
1436
1437 udelay(1);
1438
1439 if (phy->autoneg_wait_to_complete) {
1440 e_dbg("Waiting for forced speed/duplex link on IFE phy.\n");
1441
1442 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1443 100000, &link);
1444 if (ret_val)
1445 return ret_val;
1446
1447 if (!link)
1448 e_dbg("Link taking longer than expected.\n");
1449
1450 /* Try once more */
1451 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1452 100000, &link);
1453 if (ret_val)
1454 return ret_val;
1455 }
1456
1457 return 0;
1458}
1459
1460/**
1461 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1462 * @hw: pointer to the HW structure
1463 * @phy_ctrl: pointer to current value of PHY_CONTROL
1464 *
1465 * Forces speed and duplex on the PHY by doing the following: disable flow
1466 * control, force speed/duplex on the MAC, disable auto speed detection,
1467 * disable auto-negotiation, configure duplex, configure speed, configure
1468 * the collision distance, write configuration to CTRL register. The
1469 * caller must write to the PHY_CONTROL register for these settings to
1470 * take affect.
1471 **/
1472void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1473{
1474 struct e1000_mac_info *mac = &hw->mac;
1475 u32 ctrl;
1476
1477 /* Turn off flow control when forcing speed/duplex */
1478 hw->fc.current_mode = e1000_fc_none;
1479
1480 /* Force speed/duplex on the mac */
1481 ctrl = er32(CTRL);
1482 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1483 ctrl &= ~E1000_CTRL_SPD_SEL;
1484
1485 /* Disable Auto Speed Detection */
1486 ctrl &= ~E1000_CTRL_ASDE;
1487
1488 /* Disable autoneg on the phy */
1489 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1490
1491 /* Forcing Full or Half Duplex? */
1492 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1493 ctrl &= ~E1000_CTRL_FD;
1494 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1495 e_dbg("Half Duplex\n");
1496 } else {
1497 ctrl |= E1000_CTRL_FD;
1498 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1499 e_dbg("Full Duplex\n");
1500 }
1501
1502 /* Forcing 10mb or 100mb? */
1503 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1504 ctrl |= E1000_CTRL_SPD_100;
1505 *phy_ctrl |= MII_CR_SPEED_100;
1506 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1507 e_dbg("Forcing 100mb\n");
1508 } else {
1509 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1510 *phy_ctrl |= MII_CR_SPEED_10;
1511 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1512 e_dbg("Forcing 10mb\n");
1513 }
1514
1515 hw->mac.ops.config_collision_dist(hw);
1516
1517 ew32(CTRL, ctrl);
1518}
1519
1520/**
1521 * e1000e_set_d3_lplu_state - Sets low power link up state for D3
1522 * @hw: pointer to the HW structure
1523 * @active: boolean used to enable/disable lplu
1524 *
1525 * Success returns 0, Failure returns 1
1526 *
1527 * The low power link up (lplu) state is set to the power management level D3
1528 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1529 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1530 * is used during Dx states where the power conservation is most important.
1531 * During driver activity, SmartSpeed should be enabled so performance is
1532 * maintained.
1533 **/
1534s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1535{
1536 struct e1000_phy_info *phy = &hw->phy;
1537 s32 ret_val;
1538 u16 data;
1539
1540 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1541 if (ret_val)
1542 return ret_val;
1543
1544 if (!active) {
1545 data &= ~IGP02E1000_PM_D3_LPLU;
1546 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1547 if (ret_val)
1548 return ret_val;
1549 /*
1550 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1551 * during Dx states where the power conservation is most
1552 * important. During driver activity we should enable
1553 * SmartSpeed, so performance is maintained.
1554 */
1555 if (phy->smart_speed == e1000_smart_speed_on) {
1556 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1557 &data);
1558 if (ret_val)
1559 return ret_val;
1560
1561 data |= IGP01E1000_PSCFR_SMART_SPEED;
1562 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1563 data);
1564 if (ret_val)
1565 return ret_val;
1566 } else if (phy->smart_speed == e1000_smart_speed_off) {
1567 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1568 &data);
1569 if (ret_val)
1570 return ret_val;
1571
1572 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1573 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1574 data);
1575 if (ret_val)
1576 return ret_val;
1577 }
1578 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1579 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1580 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1581 data |= IGP02E1000_PM_D3_LPLU;
1582 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1583 if (ret_val)
1584 return ret_val;
1585
1586 /* When LPLU is enabled, we should disable SmartSpeed */
1587 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1588 if (ret_val)
1589 return ret_val;
1590
1591 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1592 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1593 }
1594
1595 return ret_val;
1596}
1597
1598/**
1599 * e1000e_check_downshift - Checks whether a downshift in speed occurred
1600 * @hw: pointer to the HW structure
1601 *
1602 * Success returns 0, Failure returns 1
1603 *
1604 * A downshift is detected by querying the PHY link health.
1605 **/
1606s32 e1000e_check_downshift(struct e1000_hw *hw)
1607{
1608 struct e1000_phy_info *phy = &hw->phy;
1609 s32 ret_val;
1610 u16 phy_data, offset, mask;
1611
1612 switch (phy->type) {
1613 case e1000_phy_m88:
1614 case e1000_phy_gg82563:
1615 case e1000_phy_bm:
1616 case e1000_phy_82578:
1617 offset = M88E1000_PHY_SPEC_STATUS;
1618 mask = M88E1000_PSSR_DOWNSHIFT;
1619 break;
1620 case e1000_phy_igp_2:
1621 case e1000_phy_igp_3:
1622 offset = IGP01E1000_PHY_LINK_HEALTH;
1623 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1624 break;
1625 default:
1626 /* speed downshift not supported */
1627 phy->speed_downgraded = false;
1628 return 0;
1629 }
1630
1631 ret_val = e1e_rphy(hw, offset, &phy_data);
1632
1633 if (!ret_val)
1634 phy->speed_downgraded = !!(phy_data & mask);
1635
1636 return ret_val;
1637}
1638
1639/**
1640 * e1000_check_polarity_m88 - Checks the polarity.
1641 * @hw: pointer to the HW structure
1642 *
1643 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1644 *
1645 * Polarity is determined based on the PHY specific status register.
1646 **/
1647s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1648{
1649 struct e1000_phy_info *phy = &hw->phy;
1650 s32 ret_val;
1651 u16 data;
1652
1653 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data);
1654
1655 if (!ret_val)
1656 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1657 ? e1000_rev_polarity_reversed
1658 : e1000_rev_polarity_normal;
1659
1660 return ret_val;
1661}
1662
1663/**
1664 * e1000_check_polarity_igp - Checks the polarity.
1665 * @hw: pointer to the HW structure
1666 *
1667 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1668 *
1669 * Polarity is determined based on the PHY port status register, and the
1670 * current speed (since there is no polarity at 100Mbps).
1671 **/
1672s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1673{
1674 struct e1000_phy_info *phy = &hw->phy;
1675 s32 ret_val;
1676 u16 data, offset, mask;
1677
1678 /*
1679 * Polarity is determined based on the speed of
1680 * our connection.
1681 */
1682 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1683 if (ret_val)
1684 return ret_val;
1685
1686 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1687 IGP01E1000_PSSR_SPEED_1000MBPS) {
1688 offset = IGP01E1000_PHY_PCS_INIT_REG;
1689 mask = IGP01E1000_PHY_POLARITY_MASK;
1690 } else {
1691 /*
1692 * This really only applies to 10Mbps since
1693 * there is no polarity for 100Mbps (always 0).
1694 */
1695 offset = IGP01E1000_PHY_PORT_STATUS;
1696 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1697 }
1698
1699 ret_val = e1e_rphy(hw, offset, &data);
1700
1701 if (!ret_val)
1702 phy->cable_polarity = (data & mask)
1703 ? e1000_rev_polarity_reversed
1704 : e1000_rev_polarity_normal;
1705
1706 return ret_val;
1707}
1708
1709/**
1710 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
1711 * @hw: pointer to the HW structure
1712 *
1713 * Polarity is determined on the polarity reversal feature being enabled.
1714 **/
1715s32 e1000_check_polarity_ife(struct e1000_hw *hw)
1716{
1717 struct e1000_phy_info *phy = &hw->phy;
1718 s32 ret_val;
1719 u16 phy_data, offset, mask;
1720
1721 /*
1722 * Polarity is determined based on the reversal feature being enabled.
1723 */
1724 if (phy->polarity_correction) {
1725 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1726 mask = IFE_PESC_POLARITY_REVERSED;
1727 } else {
1728 offset = IFE_PHY_SPECIAL_CONTROL;
1729 mask = IFE_PSC_FORCE_POLARITY;
1730 }
1731
1732 ret_val = e1e_rphy(hw, offset, &phy_data);
1733
1734 if (!ret_val)
1735 phy->cable_polarity = (phy_data & mask)
1736 ? e1000_rev_polarity_reversed
1737 : e1000_rev_polarity_normal;
1738
1739 return ret_val;
1740}
1741
1742/**
1743 * e1000_wait_autoneg - Wait for auto-neg completion
1744 * @hw: pointer to the HW structure
1745 *
1746 * Waits for auto-negotiation to complete or for the auto-negotiation time
1747 * limit to expire, which ever happens first.
1748 **/
1749static s32 e1000_wait_autoneg(struct e1000_hw *hw)
1750{
1751 s32 ret_val = 0;
1752 u16 i, phy_status;
1753
1754 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1755 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1756 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1757 if (ret_val)
1758 break;
1759 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1760 if (ret_val)
1761 break;
1762 if (phy_status & MII_SR_AUTONEG_COMPLETE)
1763 break;
1764 msleep(100);
1765 }
1766
1767 /*
1768 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1769 * has completed.
1770 */
1771 return ret_val;
1772}
1773
1774/**
1775 * e1000e_phy_has_link_generic - Polls PHY for link
1776 * @hw: pointer to the HW structure
1777 * @iterations: number of times to poll for link
1778 * @usec_interval: delay between polling attempts
1779 * @success: pointer to whether polling was successful or not
1780 *
1781 * Polls the PHY status register for link, 'iterations' number of times.
1782 **/
1783s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1784 u32 usec_interval, bool *success)
1785{
1786 s32 ret_val = 0;
1787 u16 i, phy_status;
1788
1789 for (i = 0; i < iterations; i++) {
1790 /*
1791 * Some PHYs require the PHY_STATUS register to be read
1792 * twice due to the link bit being sticky. No harm doing
1793 * it across the board.
1794 */
1795 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1796 if (ret_val)
1797 /*
1798 * If the first read fails, another entity may have
1799 * ownership of the resources, wait and try again to
1800 * see if they have relinquished the resources yet.
1801 */
1802 udelay(usec_interval);
1803 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1804 if (ret_val)
1805 break;
1806 if (phy_status & MII_SR_LINK_STATUS)
1807 break;
1808 if (usec_interval >= 1000)
1809 mdelay(usec_interval/1000);
1810 else
1811 udelay(usec_interval);
1812 }
1813
1814 *success = (i < iterations);
1815
1816 return ret_val;
1817}
1818
1819/**
1820 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY
1821 * @hw: pointer to the HW structure
1822 *
1823 * Reads the PHY specific status register to retrieve the cable length
1824 * information. The cable length is determined by averaging the minimum and
1825 * maximum values to get the "average" cable length. The m88 PHY has four
1826 * possible cable length values, which are:
1827 * Register Value Cable Length
1828 * 0 < 50 meters
1829 * 1 50 - 80 meters
1830 * 2 80 - 110 meters
1831 * 3 110 - 140 meters
1832 * 4 > 140 meters
1833 **/
1834s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
1835{
1836 struct e1000_phy_info *phy = &hw->phy;
1837 s32 ret_val;
1838 u16 phy_data, index;
1839
1840 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1841 if (ret_val)
1842 return ret_val;
1843
1844 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1845 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1846
1847 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
1848 return -E1000_ERR_PHY;
1849
1850 phy->min_cable_length = e1000_m88_cable_length_table[index];
1851 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1852
1853 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1854
1855 return 0;
1856}
1857
1858/**
1859 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1860 * @hw: pointer to the HW structure
1861 *
1862 * The automatic gain control (agc) normalizes the amplitude of the
1863 * received signal, adjusting for the attenuation produced by the
1864 * cable. By reading the AGC registers, which represent the
1865 * combination of coarse and fine gain value, the value can be put
1866 * into a lookup table to obtain the approximate cable length
1867 * for each channel.
1868 **/
1869s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
1870{
1871 struct e1000_phy_info *phy = &hw->phy;
1872 s32 ret_val;
1873 u16 phy_data, i, agc_value = 0;
1874 u16 cur_agc_index, max_agc_index = 0;
1875 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1876 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
1877 IGP02E1000_PHY_AGC_A,
1878 IGP02E1000_PHY_AGC_B,
1879 IGP02E1000_PHY_AGC_C,
1880 IGP02E1000_PHY_AGC_D
1881 };
1882
1883 /* Read the AGC registers for all channels */
1884 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1885 ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data);
1886 if (ret_val)
1887 return ret_val;
1888
1889 /*
1890 * Getting bits 15:9, which represent the combination of
1891 * coarse and fine gain values. The result is a number
1892 * that can be put into the lookup table to obtain the
1893 * approximate cable length.
1894 */
1895 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1896 IGP02E1000_AGC_LENGTH_MASK;
1897
1898 /* Array index bound check. */
1899 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1900 (cur_agc_index == 0))
1901 return -E1000_ERR_PHY;
1902
1903 /* Remove min & max AGC values from calculation. */
1904 if (e1000_igp_2_cable_length_table[min_agc_index] >
1905 e1000_igp_2_cable_length_table[cur_agc_index])
1906 min_agc_index = cur_agc_index;
1907 if (e1000_igp_2_cable_length_table[max_agc_index] <
1908 e1000_igp_2_cable_length_table[cur_agc_index])
1909 max_agc_index = cur_agc_index;
1910
1911 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1912 }
1913
1914 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1915 e1000_igp_2_cable_length_table[max_agc_index]);
1916 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1917
1918 /* Calculate cable length with the error range of +/- 10 meters. */
1919 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1920 (agc_value - IGP02E1000_AGC_RANGE) : 0;
1921 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1922
1923 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1924
1925 return 0;
1926}
1927
1928/**
1929 * e1000e_get_phy_info_m88 - Retrieve PHY information
1930 * @hw: pointer to the HW structure
1931 *
1932 * Valid for only copper links. Read the PHY status register (sticky read)
1933 * to verify that link is up. Read the PHY special control register to
1934 * determine the polarity and 10base-T extended distance. Read the PHY
1935 * special status register to determine MDI/MDIx and current speed. If
1936 * speed is 1000, then determine cable length, local and remote receiver.
1937 **/
1938s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
1939{
1940 struct e1000_phy_info *phy = &hw->phy;
1941 s32 ret_val;
1942 u16 phy_data;
1943 bool link;
1944
1945 if (phy->media_type != e1000_media_type_copper) {
1946 e_dbg("Phy info is only valid for copper media\n");
1947 return -E1000_ERR_CONFIG;
1948 }
1949
1950 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1951 if (ret_val)
1952 return ret_val;
1953
1954 if (!link) {
1955 e_dbg("Phy info is only valid if link is up\n");
1956 return -E1000_ERR_CONFIG;
1957 }
1958
1959 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1960 if (ret_val)
1961 return ret_val;
1962
1963 phy->polarity_correction = !!(phy_data &
1964 M88E1000_PSCR_POLARITY_REVERSAL);
1965
1966 ret_val = e1000_check_polarity_m88(hw);
1967 if (ret_val)
1968 return ret_val;
1969
1970 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1971 if (ret_val)
1972 return ret_val;
1973
1974 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
1975
1976 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1977 ret_val = e1000_get_cable_length(hw);
1978 if (ret_val)
1979 return ret_val;
1980
1981 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &phy_data);
1982 if (ret_val)
1983 return ret_val;
1984
1985 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
1986 ? e1000_1000t_rx_status_ok
1987 : e1000_1000t_rx_status_not_ok;
1988
1989 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
1990 ? e1000_1000t_rx_status_ok
1991 : e1000_1000t_rx_status_not_ok;
1992 } else {
1993 /* Set values to "undefined" */
1994 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1995 phy->local_rx = e1000_1000t_rx_status_undefined;
1996 phy->remote_rx = e1000_1000t_rx_status_undefined;
1997 }
1998
1999 return ret_val;
2000}
2001
2002/**
2003 * e1000e_get_phy_info_igp - Retrieve igp PHY information
2004 * @hw: pointer to the HW structure
2005 *
2006 * Read PHY status to determine if link is up. If link is up, then
2007 * set/determine 10base-T extended distance and polarity correction. Read
2008 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2009 * determine on the cable length, local and remote receiver.
2010 **/
2011s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
2012{
2013 struct e1000_phy_info *phy = &hw->phy;
2014 s32 ret_val;
2015 u16 data;
2016 bool link;
2017
2018 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2019 if (ret_val)
2020 return ret_val;
2021
2022 if (!link) {
2023 e_dbg("Phy info is only valid if link is up\n");
2024 return -E1000_ERR_CONFIG;
2025 }
2026
2027 phy->polarity_correction = true;
2028
2029 ret_val = e1000_check_polarity_igp(hw);
2030 if (ret_val)
2031 return ret_val;
2032
2033 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2034 if (ret_val)
2035 return ret_val;
2036
2037 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
2038
2039 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2040 IGP01E1000_PSSR_SPEED_1000MBPS) {
2041 ret_val = e1000_get_cable_length(hw);
2042 if (ret_val)
2043 return ret_val;
2044
2045 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data);
2046 if (ret_val)
2047 return ret_val;
2048
2049 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2050 ? e1000_1000t_rx_status_ok
2051 : e1000_1000t_rx_status_not_ok;
2052
2053 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2054 ? e1000_1000t_rx_status_ok
2055 : e1000_1000t_rx_status_not_ok;
2056 } else {
2057 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2058 phy->local_rx = e1000_1000t_rx_status_undefined;
2059 phy->remote_rx = e1000_1000t_rx_status_undefined;
2060 }
2061
2062 return ret_val;
2063}
2064
2065/**
2066 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2067 * @hw: pointer to the HW structure
2068 *
2069 * Populates "phy" structure with various feature states.
2070 **/
2071s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2072{
2073 struct e1000_phy_info *phy = &hw->phy;
2074 s32 ret_val;
2075 u16 data;
2076 bool link;
2077
2078 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2079 if (ret_val)
2080 return ret_val;
2081
2082 if (!link) {
2083 e_dbg("Phy info is only valid if link is up\n");
2084 return -E1000_ERR_CONFIG;
2085 }
2086
2087 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2088 if (ret_val)
2089 return ret_val;
2090 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2091
2092 if (phy->polarity_correction) {
2093 ret_val = e1000_check_polarity_ife(hw);
2094 if (ret_val)
2095 return ret_val;
2096 } else {
2097 /* Polarity is forced */
2098 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
2099 ? e1000_rev_polarity_reversed
2100 : e1000_rev_polarity_normal;
2101 }
2102
2103 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
2104 if (ret_val)
2105 return ret_val;
2106
2107 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2108
2109 /* The following parameters are undefined for 10/100 operation. */
2110 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2111 phy->local_rx = e1000_1000t_rx_status_undefined;
2112 phy->remote_rx = e1000_1000t_rx_status_undefined;
2113
2114 return 0;
2115}
2116
2117/**
2118 * e1000e_phy_sw_reset - PHY software reset
2119 * @hw: pointer to the HW structure
2120 *
2121 * Does a software reset of the PHY by reading the PHY control register and
2122 * setting/write the control register reset bit to the PHY.
2123 **/
2124s32 e1000e_phy_sw_reset(struct e1000_hw *hw)
2125{
2126 s32 ret_val;
2127 u16 phy_ctrl;
2128
2129 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
2130 if (ret_val)
2131 return ret_val;
2132
2133 phy_ctrl |= MII_CR_RESET;
2134 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
2135 if (ret_val)
2136 return ret_val;
2137
2138 udelay(1);
2139
2140 return ret_val;
2141}
2142
2143/**
2144 * e1000e_phy_hw_reset_generic - PHY hardware reset
2145 * @hw: pointer to the HW structure
2146 *
2147 * Verify the reset block is not blocking us from resetting. Acquire
2148 * semaphore (if necessary) and read/set/write the device control reset
2149 * bit in the PHY. Wait the appropriate delay time for the device to
2150 * reset and release the semaphore (if necessary).
2151 **/
2152s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
2153{
2154 struct e1000_phy_info *phy = &hw->phy;
2155 s32 ret_val;
2156 u32 ctrl;
2157
2158 if (phy->ops.check_reset_block) {
2159 ret_val = phy->ops.check_reset_block(hw);
2160 if (ret_val)
2161 return 0;
2162 }
2163
2164 ret_val = phy->ops.acquire(hw);
2165 if (ret_val)
2166 return ret_val;
2167
2168 ctrl = er32(CTRL);
2169 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
2170 e1e_flush();
2171
2172 udelay(phy->reset_delay_us);
2173
2174 ew32(CTRL, ctrl);
2175 e1e_flush();
2176
2177 udelay(150);
2178
2179 phy->ops.release(hw);
2180
2181 return e1000_get_phy_cfg_done(hw);
2182}
2183
2184/**
2185 * e1000e_get_cfg_done - Generic configuration done
2186 * @hw: pointer to the HW structure
2187 *
2188 * Generic function to wait 10 milli-seconds for configuration to complete
2189 * and return success.
2190 **/
2191s32 e1000e_get_cfg_done(struct e1000_hw *hw)
2192{
2193 mdelay(10);
2194
2195 return 0;
2196}
2197
2198/**
2199 * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY
2200 * @hw: pointer to the HW structure
2201 *
2202 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2203 **/
2204s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw)
2205{
2206 e_dbg("Running IGP 3 PHY init script\n");
2207
2208 /* PHY init IGP 3 */
2209 /* Enable rise/fall, 10-mode work in class-A */
2210 e1e_wphy(hw, 0x2F5B, 0x9018);
2211 /* Remove all caps from Replica path filter */
2212 e1e_wphy(hw, 0x2F52, 0x0000);
2213 /* Bias trimming for ADC, AFE and Driver (Default) */
2214 e1e_wphy(hw, 0x2FB1, 0x8B24);
2215 /* Increase Hybrid poly bias */
2216 e1e_wphy(hw, 0x2FB2, 0xF8F0);
2217 /* Add 4% to Tx amplitude in Gig mode */
2218 e1e_wphy(hw, 0x2010, 0x10B0);
2219 /* Disable trimming (TTT) */
2220 e1e_wphy(hw, 0x2011, 0x0000);
2221 /* Poly DC correction to 94.6% + 2% for all channels */
2222 e1e_wphy(hw, 0x20DD, 0x249A);
2223 /* ABS DC correction to 95.9% */
2224 e1e_wphy(hw, 0x20DE, 0x00D3);
2225 /* BG temp curve trim */
2226 e1e_wphy(hw, 0x28B4, 0x04CE);
2227 /* Increasing ADC OPAMP stage 1 currents to max */
2228 e1e_wphy(hw, 0x2F70, 0x29E4);
2229 /* Force 1000 ( required for enabling PHY regs configuration) */
2230 e1e_wphy(hw, 0x0000, 0x0140);
2231 /* Set upd_freq to 6 */
2232 e1e_wphy(hw, 0x1F30, 0x1606);
2233 /* Disable NPDFE */
2234 e1e_wphy(hw, 0x1F31, 0xB814);
2235 /* Disable adaptive fixed FFE (Default) */
2236 e1e_wphy(hw, 0x1F35, 0x002A);
2237 /* Enable FFE hysteresis */
2238 e1e_wphy(hw, 0x1F3E, 0x0067);
2239 /* Fixed FFE for short cable lengths */
2240 e1e_wphy(hw, 0x1F54, 0x0065);
2241 /* Fixed FFE for medium cable lengths */
2242 e1e_wphy(hw, 0x1F55, 0x002A);
2243 /* Fixed FFE for long cable lengths */
2244 e1e_wphy(hw, 0x1F56, 0x002A);
2245 /* Enable Adaptive Clip Threshold */
2246 e1e_wphy(hw, 0x1F72, 0x3FB0);
2247 /* AHT reset limit to 1 */
2248 e1e_wphy(hw, 0x1F76, 0xC0FF);
2249 /* Set AHT master delay to 127 msec */
2250 e1e_wphy(hw, 0x1F77, 0x1DEC);
2251 /* Set scan bits for AHT */
2252 e1e_wphy(hw, 0x1F78, 0xF9EF);
2253 /* Set AHT Preset bits */
2254 e1e_wphy(hw, 0x1F79, 0x0210);
2255 /* Change integ_factor of channel A to 3 */
2256 e1e_wphy(hw, 0x1895, 0x0003);
2257 /* Change prop_factor of channels BCD to 8 */
2258 e1e_wphy(hw, 0x1796, 0x0008);
2259 /* Change cg_icount + enable integbp for channels BCD */
2260 e1e_wphy(hw, 0x1798, 0xD008);
2261 /*
2262 * Change cg_icount + enable integbp + change prop_factor_master
2263 * to 8 for channel A
2264 */
2265 e1e_wphy(hw, 0x1898, 0xD918);
2266 /* Disable AHT in Slave mode on channel A */
2267 e1e_wphy(hw, 0x187A, 0x0800);
2268 /*
2269 * Enable LPLU and disable AN to 1000 in non-D0a states,
2270 * Enable SPD+B2B
2271 */
2272 e1e_wphy(hw, 0x0019, 0x008D);
2273 /* Enable restart AN on an1000_dis change */
2274 e1e_wphy(hw, 0x001B, 0x2080);
2275 /* Enable wh_fifo read clock in 10/100 modes */
2276 e1e_wphy(hw, 0x0014, 0x0045);
2277 /* Restart AN, Speed selection is 1000 */
2278 e1e_wphy(hw, 0x0000, 0x1340);
2279
2280 return 0;
2281}
2282
2283/* Internal function pointers */
2284
2285/**
2286 * e1000_get_phy_cfg_done - Generic PHY configuration done
2287 * @hw: pointer to the HW structure
2288 *
2289 * Return success if silicon family did not implement a family specific
2290 * get_cfg_done function.
2291 **/
2292static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
2293{
2294 if (hw->phy.ops.get_cfg_done)
2295 return hw->phy.ops.get_cfg_done(hw);
2296
2297 return 0;
2298}
2299
2300/**
2301 * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex
2302 * @hw: pointer to the HW structure
2303 *
2304 * When the silicon family has not implemented a forced speed/duplex
2305 * function for the PHY, simply return 0.
2306 **/
2307static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2308{
2309 if (hw->phy.ops.force_speed_duplex)
2310 return hw->phy.ops.force_speed_duplex(hw);
2311
2312 return 0;
2313}
2314
2315/**
2316 * e1000e_get_phy_type_from_id - Get PHY type from id
2317 * @phy_id: phy_id read from the phy
2318 *
2319 * Returns the phy type from the id.
2320 **/
2321enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
2322{
2323 enum e1000_phy_type phy_type = e1000_phy_unknown;
2324
2325 switch (phy_id) {
2326 case M88E1000_I_PHY_ID:
2327 case M88E1000_E_PHY_ID:
2328 case M88E1111_I_PHY_ID:
2329 case M88E1011_I_PHY_ID:
2330 phy_type = e1000_phy_m88;
2331 break;
2332 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2333 phy_type = e1000_phy_igp_2;
2334 break;
2335 case GG82563_E_PHY_ID:
2336 phy_type = e1000_phy_gg82563;
2337 break;
2338 case IGP03E1000_E_PHY_ID:
2339 phy_type = e1000_phy_igp_3;
2340 break;
2341 case IFE_E_PHY_ID:
2342 case IFE_PLUS_E_PHY_ID:
2343 case IFE_C_E_PHY_ID:
2344 phy_type = e1000_phy_ife;
2345 break;
2346 case BME1000_E_PHY_ID:
2347 case BME1000_E_PHY_ID_R2:
2348 phy_type = e1000_phy_bm;
2349 break;
2350 case I82578_E_PHY_ID:
2351 phy_type = e1000_phy_82578;
2352 break;
2353 case I82577_E_PHY_ID:
2354 phy_type = e1000_phy_82577;
2355 break;
2356 case I82579_E_PHY_ID:
2357 phy_type = e1000_phy_82579;
2358 break;
2359 case I217_E_PHY_ID:
2360 phy_type = e1000_phy_i217;
2361 break;
2362 default:
2363 phy_type = e1000_phy_unknown;
2364 break;
2365 }
2366 return phy_type;
2367}
2368
2369/**
2370 * e1000e_determine_phy_address - Determines PHY address.
2371 * @hw: pointer to the HW structure
2372 *
2373 * This uses a trial and error method to loop through possible PHY
2374 * addresses. It tests each by reading the PHY ID registers and
2375 * checking for a match.
2376 **/
2377s32 e1000e_determine_phy_address(struct e1000_hw *hw)
2378{
2379 u32 phy_addr = 0;
2380 u32 i;
2381 enum e1000_phy_type phy_type = e1000_phy_unknown;
2382
2383 hw->phy.id = phy_type;
2384
2385 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2386 hw->phy.addr = phy_addr;
2387 i = 0;
2388
2389 do {
2390 e1000e_get_phy_id(hw);
2391 phy_type = e1000e_get_phy_type_from_id(hw->phy.id);
2392
2393 /*
2394 * If phy_type is valid, break - we found our
2395 * PHY address
2396 */
2397 if (phy_type != e1000_phy_unknown)
2398 return 0;
2399
2400 usleep_range(1000, 2000);
2401 i++;
2402 } while (i < 10);
2403 }
2404
2405 return -E1000_ERR_PHY_TYPE;
2406}
2407
2408/**
2409 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
2410 * @page: page to access
2411 *
2412 * Returns the phy address for the page requested.
2413 **/
2414static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
2415{
2416 u32 phy_addr = 2;
2417
2418 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
2419 phy_addr = 1;
2420
2421 return phy_addr;
2422}
2423
2424/**
2425 * e1000e_write_phy_reg_bm - Write BM PHY register
2426 * @hw: pointer to the HW structure
2427 * @offset: register offset to write to
2428 * @data: data to write at register offset
2429 *
2430 * Acquires semaphore, if necessary, then writes the data to PHY register
2431 * at the offset. Release any acquired semaphores before exiting.
2432 **/
2433s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
2434{
2435 s32 ret_val;
2436 u32 page = offset >> IGP_PAGE_SHIFT;
2437
2438 ret_val = hw->phy.ops.acquire(hw);
2439 if (ret_val)
2440 return ret_val;
2441
2442 /* Page 800 works differently than the rest so it has its own func */
2443 if (page == BM_WUC_PAGE) {
2444 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2445 false, false);
2446 goto release;
2447 }
2448
2449 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2450
2451 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2452 u32 page_shift, page_select;
2453
2454 /*
2455 * Page select is register 31 for phy address 1 and 22 for
2456 * phy address 2 and 3. Page select is shifted only for
2457 * phy address 1.
2458 */
2459 if (hw->phy.addr == 1) {
2460 page_shift = IGP_PAGE_SHIFT;
2461 page_select = IGP01E1000_PHY_PAGE_SELECT;
2462 } else {
2463 page_shift = 0;
2464 page_select = BM_PHY_PAGE_SELECT;
2465 }
2466
2467 /* Page is shifted left, PHY expects (page x 32) */
2468 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2469 (page << page_shift));
2470 if (ret_val)
2471 goto release;
2472 }
2473
2474 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2475 data);
2476
2477release:
2478 hw->phy.ops.release(hw);
2479 return ret_val;
2480}
2481
2482/**
2483 * e1000e_read_phy_reg_bm - Read BM PHY register
2484 * @hw: pointer to the HW structure
2485 * @offset: register offset to be read
2486 * @data: pointer to the read data
2487 *
2488 * Acquires semaphore, if necessary, then reads the PHY register at offset
2489 * and storing the retrieved information in data. Release any acquired
2490 * semaphores before exiting.
2491 **/
2492s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
2493{
2494 s32 ret_val;
2495 u32 page = offset >> IGP_PAGE_SHIFT;
2496
2497 ret_val = hw->phy.ops.acquire(hw);
2498 if (ret_val)
2499 return ret_val;
2500
2501 /* Page 800 works differently than the rest so it has its own func */
2502 if (page == BM_WUC_PAGE) {
2503 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2504 true, false);
2505 goto release;
2506 }
2507
2508 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2509
2510 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2511 u32 page_shift, page_select;
2512
2513 /*
2514 * Page select is register 31 for phy address 1 and 22 for
2515 * phy address 2 and 3. Page select is shifted only for
2516 * phy address 1.
2517 */
2518 if (hw->phy.addr == 1) {
2519 page_shift = IGP_PAGE_SHIFT;
2520 page_select = IGP01E1000_PHY_PAGE_SELECT;
2521 } else {
2522 page_shift = 0;
2523 page_select = BM_PHY_PAGE_SELECT;
2524 }
2525
2526 /* Page is shifted left, PHY expects (page x 32) */
2527 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2528 (page << page_shift));
2529 if (ret_val)
2530 goto release;
2531 }
2532
2533 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2534 data);
2535release:
2536 hw->phy.ops.release(hw);
2537 return ret_val;
2538}
2539
2540/**
2541 * e1000e_read_phy_reg_bm2 - Read BM PHY register
2542 * @hw: pointer to the HW structure
2543 * @offset: register offset to be read
2544 * @data: pointer to the read data
2545 *
2546 * Acquires semaphore, if necessary, then reads the PHY register at offset
2547 * and storing the retrieved information in data. Release any acquired
2548 * semaphores before exiting.
2549 **/
2550s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
2551{
2552 s32 ret_val;
2553 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2554
2555 ret_val = hw->phy.ops.acquire(hw);
2556 if (ret_val)
2557 return ret_val;
2558
2559 /* Page 800 works differently than the rest so it has its own func */
2560 if (page == BM_WUC_PAGE) {
2561 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2562 true, false);
2563 goto release;
2564 }
2565
2566 hw->phy.addr = 1;
2567
2568 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2569
2570 /* Page is shifted left, PHY expects (page x 32) */
2571 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2572 page);
2573
2574 if (ret_val)
2575 goto release;
2576 }
2577
2578 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2579 data);
2580release:
2581 hw->phy.ops.release(hw);
2582 return ret_val;
2583}
2584
2585/**
2586 * e1000e_write_phy_reg_bm2 - Write BM PHY register
2587 * @hw: pointer to the HW structure
2588 * @offset: register offset to write to
2589 * @data: data to write at register offset
2590 *
2591 * Acquires semaphore, if necessary, then writes the data to PHY register
2592 * at the offset. Release any acquired semaphores before exiting.
2593 **/
2594s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
2595{
2596 s32 ret_val;
2597 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2598
2599 ret_val = hw->phy.ops.acquire(hw);
2600 if (ret_val)
2601 return ret_val;
2602
2603 /* Page 800 works differently than the rest so it has its own func */
2604 if (page == BM_WUC_PAGE) {
2605 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2606 false, false);
2607 goto release;
2608 }
2609
2610 hw->phy.addr = 1;
2611
2612 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2613 /* Page is shifted left, PHY expects (page x 32) */
2614 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2615 page);
2616
2617 if (ret_val)
2618 goto release;
2619 }
2620
2621 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2622 data);
2623
2624release:
2625 hw->phy.ops.release(hw);
2626 return ret_val;
2627}
2628
2629/**
2630 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
2631 * @hw: pointer to the HW structure
2632 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
2633 *
2634 * Assumes semaphore already acquired and phy_reg points to a valid memory
2635 * address to store contents of the BM_WUC_ENABLE_REG register.
2636 **/
2637s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2638{
2639 s32 ret_val;
2640 u16 temp;
2641
2642 /* All page select, port ctrl and wakeup registers use phy address 1 */
2643 hw->phy.addr = 1;
2644
2645 /* Select Port Control Registers page */
2646 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2647 if (ret_val) {
2648 e_dbg("Could not set Port Control page\n");
2649 return ret_val;
2650 }
2651
2652 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2653 if (ret_val) {
2654 e_dbg("Could not read PHY register %d.%d\n",
2655 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2656 return ret_val;
2657 }
2658
2659 /*
2660 * Enable both PHY wakeup mode and Wakeup register page writes.
2661 * Prevent a power state change by disabling ME and Host PHY wakeup.
2662 */
2663 temp = *phy_reg;
2664 temp |= BM_WUC_ENABLE_BIT;
2665 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
2666
2667 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
2668 if (ret_val) {
2669 e_dbg("Could not write PHY register %d.%d\n",
2670 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2671 return ret_val;
2672 }
2673
2674 /*
2675 * Select Host Wakeup Registers page - caller now able to write
2676 * registers on the Wakeup registers page
2677 */
2678 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
2679}
2680
2681/**
2682 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
2683 * @hw: pointer to the HW structure
2684 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
2685 *
2686 * Restore BM_WUC_ENABLE_REG to its original value.
2687 *
2688 * Assumes semaphore already acquired and *phy_reg is the contents of the
2689 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
2690 * caller.
2691 **/
2692s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2693{
2694 s32 ret_val = 0;
2695
2696 /* Select Port Control Registers page */
2697 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2698 if (ret_val) {
2699 e_dbg("Could not set Port Control page\n");
2700 return ret_val;
2701 }
2702
2703 /* Restore 769.17 to its original value */
2704 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
2705 if (ret_val)
2706 e_dbg("Could not restore PHY register %d.%d\n",
2707 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2708
2709 return ret_val;
2710}
2711
2712/**
2713 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
2714 * @hw: pointer to the HW structure
2715 * @offset: register offset to be read or written
2716 * @data: pointer to the data to read or write
2717 * @read: determines if operation is read or write
2718 * @page_set: BM_WUC_PAGE already set and access enabled
2719 *
2720 * Read the PHY register at offset and store the retrieved information in
2721 * data, or write data to PHY register at offset. Note the procedure to
2722 * access the PHY wakeup registers is different than reading the other PHY
2723 * registers. It works as such:
2724 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1
2725 * 2) Set page to 800 for host (801 if we were manageability)
2726 * 3) Write the address using the address opcode (0x11)
2727 * 4) Read or write the data using the data opcode (0x12)
2728 * 5) Restore 769.17.2 to its original value
2729 *
2730 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
2731 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
2732 *
2733 * Assumes semaphore is already acquired. When page_set==true, assumes
2734 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
2735 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
2736 **/
2737static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2738 u16 *data, bool read, bool page_set)
2739{
2740 s32 ret_val;
2741 u16 reg = BM_PHY_REG_NUM(offset);
2742 u16 page = BM_PHY_REG_PAGE(offset);
2743 u16 phy_reg = 0;
2744
2745 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
2746 if ((hw->mac.type == e1000_pchlan) &&
2747 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
2748 e_dbg("Attempting to access page %d while gig enabled.\n",
2749 page);
2750
2751 if (!page_set) {
2752 /* Enable access to PHY wakeup registers */
2753 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2754 if (ret_val) {
2755 e_dbg("Could not enable PHY wakeup reg access\n");
2756 return ret_val;
2757 }
2758 }
2759
2760 e_dbg("Accessing PHY page %d reg 0x%x\n", page, reg);
2761
2762 /* Write the Wakeup register page offset value using opcode 0x11 */
2763 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
2764 if (ret_val) {
2765 e_dbg("Could not write address opcode to page %d\n", page);
2766 return ret_val;
2767 }
2768
2769 if (read) {
2770 /* Read the Wakeup register page value using opcode 0x12 */
2771 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2772 data);
2773 } else {
2774 /* Write the Wakeup register page value using opcode 0x12 */
2775 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2776 *data);
2777 }
2778
2779 if (ret_val) {
2780 e_dbg("Could not access PHY reg %d.%d\n", page, reg);
2781 return ret_val;
2782 }
2783
2784 if (!page_set)
2785 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2786
2787 return ret_val;
2788}
2789
2790/**
2791 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
2792 * @hw: pointer to the HW structure
2793 *
2794 * In the case of a PHY power down to save power, or to turn off link during a
2795 * driver unload, or wake on lan is not enabled, restore the link to previous
2796 * settings.
2797 **/
2798void e1000_power_up_phy_copper(struct e1000_hw *hw)
2799{
2800 u16 mii_reg = 0;
2801
2802 /* The PHY will retain its settings across a power down/up cycle */
2803 e1e_rphy(hw, PHY_CONTROL, &mii_reg);
2804 mii_reg &= ~MII_CR_POWER_DOWN;
2805 e1e_wphy(hw, PHY_CONTROL, mii_reg);
2806}
2807
2808/**
2809 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
2810 * @hw: pointer to the HW structure
2811 *
2812 * In the case of a PHY power down to save power, or to turn off link during a
2813 * driver unload, or wake on lan is not enabled, restore the link to previous
2814 * settings.
2815 **/
2816void e1000_power_down_phy_copper(struct e1000_hw *hw)
2817{
2818 u16 mii_reg = 0;
2819
2820 /* The PHY will retain its settings across a power down/up cycle */
2821 e1e_rphy(hw, PHY_CONTROL, &mii_reg);
2822 mii_reg |= MII_CR_POWER_DOWN;
2823 e1e_wphy(hw, PHY_CONTROL, mii_reg);
2824 usleep_range(1000, 2000);
2825}
2826
2827/**
2828 * e1000e_commit_phy - Soft PHY reset
2829 * @hw: pointer to the HW structure
2830 *
2831 * Performs a soft PHY reset on those that apply. This is a function pointer
2832 * entry point called by drivers.
2833 **/
2834s32 e1000e_commit_phy(struct e1000_hw *hw)
2835{
2836 if (hw->phy.ops.commit)
2837 return hw->phy.ops.commit(hw);
2838
2839 return 0;
2840}
2841
2842/**
2843 * e1000_set_d0_lplu_state - Sets low power link up state for D0
2844 * @hw: pointer to the HW structure
2845 * @active: boolean used to enable/disable lplu
2846 *
2847 * Success returns 0, Failure returns 1
2848 *
2849 * The low power link up (lplu) state is set to the power management level D0
2850 * and SmartSpeed is disabled when active is true, else clear lplu for D0
2851 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
2852 * is used during Dx states where the power conservation is most important.
2853 * During driver activity, SmartSpeed should be enabled so performance is
2854 * maintained. This is a function pointer entry point called by drivers.
2855 **/
2856static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
2857{
2858 if (hw->phy.ops.set_d0_lplu_state)
2859 return hw->phy.ops.set_d0_lplu_state(hw, active);
2860
2861 return 0;
2862}
2863
2864/**
2865 * __e1000_read_phy_reg_hv - Read HV PHY register
2866 * @hw: pointer to the HW structure
2867 * @offset: register offset to be read
2868 * @data: pointer to the read data
2869 * @locked: semaphore has already been acquired or not
2870 *
2871 * Acquires semaphore, if necessary, then reads the PHY register at offset
2872 * and stores the retrieved information in data. Release any acquired
2873 * semaphore before exiting.
2874 **/
2875static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
2876 bool locked, bool page_set)
2877{
2878 s32 ret_val;
2879 u16 page = BM_PHY_REG_PAGE(offset);
2880 u16 reg = BM_PHY_REG_NUM(offset);
2881 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2882
2883 if (!locked) {
2884 ret_val = hw->phy.ops.acquire(hw);
2885 if (ret_val)
2886 return ret_val;
2887 }
2888
2889 /* Page 800 works differently than the rest so it has its own func */
2890 if (page == BM_WUC_PAGE) {
2891 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2892 true, page_set);
2893 goto out;
2894 }
2895
2896 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2897 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2898 data, true);
2899 goto out;
2900 }
2901
2902 if (!page_set) {
2903 if (page == HV_INTC_FC_PAGE_START)
2904 page = 0;
2905
2906 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2907 /* Page is shifted left, PHY expects (page x 32) */
2908 ret_val = e1000_set_page_igp(hw,
2909 (page << IGP_PAGE_SHIFT));
2910
2911 hw->phy.addr = phy_addr;
2912
2913 if (ret_val)
2914 goto out;
2915 }
2916 }
2917
2918 e_dbg("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
2919 page << IGP_PAGE_SHIFT, reg);
2920
2921 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
2922 data);
2923out:
2924 if (!locked)
2925 hw->phy.ops.release(hw);
2926
2927 return ret_val;
2928}
2929
2930/**
2931 * e1000_read_phy_reg_hv - Read HV PHY register
2932 * @hw: pointer to the HW structure
2933 * @offset: register offset to be read
2934 * @data: pointer to the read data
2935 *
2936 * Acquires semaphore then reads the PHY register at offset and stores
2937 * the retrieved information in data. Release the acquired semaphore
2938 * before exiting.
2939 **/
2940s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2941{
2942 return __e1000_read_phy_reg_hv(hw, offset, data, false, false);
2943}
2944
2945/**
2946 * e1000_read_phy_reg_hv_locked - Read HV PHY register
2947 * @hw: pointer to the HW structure
2948 * @offset: register offset to be read
2949 * @data: pointer to the read data
2950 *
2951 * Reads the PHY register at offset and stores the retrieved information
2952 * in data. Assumes semaphore already acquired.
2953 **/
2954s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
2955{
2956 return __e1000_read_phy_reg_hv(hw, offset, data, true, false);
2957}
2958
2959/**
2960 * e1000_read_phy_reg_page_hv - Read HV PHY register
2961 * @hw: pointer to the HW structure
2962 * @offset: register offset to write to
2963 * @data: data to write at register offset
2964 *
2965 * Reads the PHY register at offset and stores the retrieved information
2966 * in data. Assumes semaphore already acquired and page already set.
2967 **/
2968s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2969{
2970 return __e1000_read_phy_reg_hv(hw, offset, data, true, true);
2971}
2972
2973/**
2974 * __e1000_write_phy_reg_hv - Write HV PHY register
2975 * @hw: pointer to the HW structure
2976 * @offset: register offset to write to
2977 * @data: data to write at register offset
2978 * @locked: semaphore has already been acquired or not
2979 *
2980 * Acquires semaphore, if necessary, then writes the data to PHY register
2981 * at the offset. Release any acquired semaphores before exiting.
2982 **/
2983static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
2984 bool locked, bool page_set)
2985{
2986 s32 ret_val;
2987 u16 page = BM_PHY_REG_PAGE(offset);
2988 u16 reg = BM_PHY_REG_NUM(offset);
2989 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2990
2991 if (!locked) {
2992 ret_val = hw->phy.ops.acquire(hw);
2993 if (ret_val)
2994 return ret_val;
2995 }
2996
2997 /* Page 800 works differently than the rest so it has its own func */
2998 if (page == BM_WUC_PAGE) {
2999 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3000 false, page_set);
3001 goto out;
3002 }
3003
3004 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3005 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3006 &data, false);
3007 goto out;
3008 }
3009
3010 if (!page_set) {
3011 if (page == HV_INTC_FC_PAGE_START)
3012 page = 0;
3013
3014 /*
3015 * Workaround MDIO accesses being disabled after entering IEEE
3016 * Power Down (when bit 11 of the PHY Control register is set)
3017 */
3018 if ((hw->phy.type == e1000_phy_82578) &&
3019 (hw->phy.revision >= 1) &&
3020 (hw->phy.addr == 2) &&
3021 !(MAX_PHY_REG_ADDRESS & reg) && (data & (1 << 11))) {
3022 u16 data2 = 0x7EFF;
3023 ret_val = e1000_access_phy_debug_regs_hv(hw,
3024 (1 << 6) | 0x3,
3025 &data2, false);
3026 if (ret_val)
3027 goto out;
3028 }
3029
3030 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3031 /* Page is shifted left, PHY expects (page x 32) */
3032 ret_val = e1000_set_page_igp(hw,
3033 (page << IGP_PAGE_SHIFT));
3034
3035 hw->phy.addr = phy_addr;
3036
3037 if (ret_val)
3038 goto out;
3039 }
3040 }
3041
3042 e_dbg("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3043 page << IGP_PAGE_SHIFT, reg);
3044
3045 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3046 data);
3047
3048out:
3049 if (!locked)
3050 hw->phy.ops.release(hw);
3051
3052 return ret_val;
3053}
3054
3055/**
3056 * e1000_write_phy_reg_hv - Write HV PHY register
3057 * @hw: pointer to the HW structure
3058 * @offset: register offset to write to
3059 * @data: data to write at register offset
3060 *
3061 * Acquires semaphore then writes the data to PHY register at the offset.
3062 * Release the acquired semaphores before exiting.
3063 **/
3064s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
3065{
3066 return __e1000_write_phy_reg_hv(hw, offset, data, false, false);
3067}
3068
3069/**
3070 * e1000_write_phy_reg_hv_locked - Write HV PHY register
3071 * @hw: pointer to the HW structure
3072 * @offset: register offset to write to
3073 * @data: data to write at register offset
3074 *
3075 * Writes the data to PHY register at the offset. Assumes semaphore
3076 * already acquired.
3077 **/
3078s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
3079{
3080 return __e1000_write_phy_reg_hv(hw, offset, data, true, false);
3081}
3082
3083/**
3084 * e1000_write_phy_reg_page_hv - Write HV PHY register
3085 * @hw: pointer to the HW structure
3086 * @offset: register offset to write to
3087 * @data: data to write at register offset
3088 *
3089 * Writes the data to PHY register at the offset. Assumes semaphore
3090 * already acquired and page already set.
3091 **/
3092s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
3093{
3094 return __e1000_write_phy_reg_hv(hw, offset, data, true, true);
3095}
3096
3097/**
3098 * e1000_get_phy_addr_for_hv_page - Get PHY address based on page
3099 * @page: page to be accessed
3100 **/
3101static u32 e1000_get_phy_addr_for_hv_page(u32 page)
3102{
3103 u32 phy_addr = 2;
3104
3105 if (page >= HV_INTC_FC_PAGE_START)
3106 phy_addr = 1;
3107
3108 return phy_addr;
3109}
3110
3111/**
3112 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
3113 * @hw: pointer to the HW structure
3114 * @offset: register offset to be read or written
3115 * @data: pointer to the data to be read or written
3116 * @read: determines if operation is read or write
3117 *
3118 * Reads the PHY register at offset and stores the retreived information
3119 * in data. Assumes semaphore already acquired. Note that the procedure
3120 * to access these regs uses the address port and data port to read/write.
3121 * These accesses done with PHY address 2 and without using pages.
3122 **/
3123static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3124 u16 *data, bool read)
3125{
3126 s32 ret_val;
3127 u32 addr_reg = 0;
3128 u32 data_reg = 0;
3129
3130 /* This takes care of the difference with desktop vs mobile phy */
3131 addr_reg = (hw->phy.type == e1000_phy_82578) ?
3132 I82578_ADDR_REG : I82577_ADDR_REG;
3133 data_reg = addr_reg + 1;
3134
3135 /* All operations in this function are phy address 2 */
3136 hw->phy.addr = 2;
3137
3138 /* masking with 0x3F to remove the page from offset */
3139 ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3140 if (ret_val) {
3141 e_dbg("Could not write the Address Offset port register\n");
3142 return ret_val;
3143 }
3144
3145 /* Read or write the data value next */
3146 if (read)
3147 ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data);
3148 else
3149 ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data);
3150
3151 if (ret_val)
3152 e_dbg("Could not access the Data port register\n");
3153
3154 return ret_val;
3155}
3156
3157/**
3158 * e1000_link_stall_workaround_hv - Si workaround
3159 * @hw: pointer to the HW structure
3160 *
3161 * This function works around a Si bug where the link partner can get
3162 * a link up indication before the PHY does. If small packets are sent
3163 * by the link partner they can be placed in the packet buffer without
3164 * being properly accounted for by the PHY and will stall preventing
3165 * further packets from being received. The workaround is to clear the
3166 * packet buffer after the PHY detects link up.
3167 **/
3168s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3169{
3170 s32 ret_val = 0;
3171 u16 data;
3172
3173 if (hw->phy.type != e1000_phy_82578)
3174 return 0;
3175
3176 /* Do not apply workaround if in PHY loopback bit 14 set */
3177 e1e_rphy(hw, PHY_CONTROL, &data);
3178 if (data & PHY_CONTROL_LB)
3179 return 0;
3180
3181 /* check if link is up and at 1Gbps */
3182 ret_val = e1e_rphy(hw, BM_CS_STATUS, &data);
3183 if (ret_val)
3184 return ret_val;
3185
3186 data &= BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3187 BM_CS_STATUS_SPEED_MASK;
3188
3189 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3190 BM_CS_STATUS_SPEED_1000))
3191 return 0;
3192
3193 msleep(200);
3194
3195 /* flush the packets in the fifo buffer */
3196 ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC |
3197 HV_MUX_DATA_CTRL_FORCE_SPEED);
3198 if (ret_val)
3199 return ret_val;
3200
3201 return e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC);
3202}
3203
3204/**
3205 * e1000_check_polarity_82577 - Checks the polarity.
3206 * @hw: pointer to the HW structure
3207 *
3208 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3209 *
3210 * Polarity is determined based on the PHY specific status register.
3211 **/
3212s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3213{
3214 struct e1000_phy_info *phy = &hw->phy;
3215 s32 ret_val;
3216 u16 data;
3217
3218 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3219
3220 if (!ret_val)
3221 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY)
3222 ? e1000_rev_polarity_reversed
3223 : e1000_rev_polarity_normal;
3224
3225 return ret_val;
3226}
3227
3228/**
3229 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3230 * @hw: pointer to the HW structure
3231 *
3232 * Calls the PHY setup function to force speed and duplex.
3233 **/
3234s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3235{
3236 struct e1000_phy_info *phy = &hw->phy;
3237 s32 ret_val;
3238 u16 phy_data;
3239 bool link;
3240
3241 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
3242 if (ret_val)
3243 return ret_val;
3244
3245 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
3246
3247 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
3248 if (ret_val)
3249 return ret_val;
3250
3251 udelay(1);
3252
3253 if (phy->autoneg_wait_to_complete) {
3254 e_dbg("Waiting for forced speed/duplex link on 82577 phy\n");
3255
3256 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3257 100000, &link);
3258 if (ret_val)
3259 return ret_val;
3260
3261 if (!link)
3262 e_dbg("Link taking longer than expected.\n");
3263
3264 /* Try once more */
3265 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3266 100000, &link);
3267 }
3268
3269 return ret_val;
3270}
3271
3272/**
3273 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3274 * @hw: pointer to the HW structure
3275 *
3276 * Read PHY status to determine if link is up. If link is up, then
3277 * set/determine 10base-T extended distance and polarity correction. Read
3278 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3279 * determine on the cable length, local and remote receiver.
3280 **/
3281s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3282{
3283 struct e1000_phy_info *phy = &hw->phy;
3284 s32 ret_val;
3285 u16 data;
3286 bool link;
3287
3288 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3289 if (ret_val)
3290 return ret_val;
3291
3292 if (!link) {
3293 e_dbg("Phy info is only valid if link is up\n");
3294 return -E1000_ERR_CONFIG;
3295 }
3296
3297 phy->polarity_correction = true;
3298
3299 ret_val = e1000_check_polarity_82577(hw);
3300 if (ret_val)
3301 return ret_val;
3302
3303 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3304 if (ret_val)
3305 return ret_val;
3306
3307 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
3308
3309 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3310 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3311 ret_val = hw->phy.ops.get_cable_length(hw);
3312 if (ret_val)
3313 return ret_val;
3314
3315 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data);
3316 if (ret_val)
3317 return ret_val;
3318
3319 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
3320 ? e1000_1000t_rx_status_ok
3321 : e1000_1000t_rx_status_not_ok;
3322
3323 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
3324 ? e1000_1000t_rx_status_ok
3325 : e1000_1000t_rx_status_not_ok;
3326 } else {
3327 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3328 phy->local_rx = e1000_1000t_rx_status_undefined;
3329 phy->remote_rx = e1000_1000t_rx_status_undefined;
3330 }
3331
3332 return 0;
3333}
3334
3335/**
3336 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3337 * @hw: pointer to the HW structure
3338 *
3339 * Reads the diagnostic status register and verifies result is valid before
3340 * placing it in the phy_cable_length field.
3341 **/
3342s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3343{
3344 struct e1000_phy_info *phy = &hw->phy;
3345 s32 ret_val;
3346 u16 phy_data, length;
3347
3348 ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data);
3349 if (ret_val)
3350 return ret_val;
3351
3352 length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
3353 I82577_DSTATUS_CABLE_LENGTH_SHIFT;
3354
3355 if (length == E1000_CABLE_LENGTH_UNDEFINED)
3356 ret_val = -E1000_ERR_PHY;
3357
3358 phy->cable_length = length;
3359
3360 return 0;
3361}
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4#include "e1000.h"
5
6static s32 e1000_wait_autoneg(struct e1000_hw *hw);
7static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
8 u16 *data, bool read, bool page_set);
9static u32 e1000_get_phy_addr_for_hv_page(u32 page);
10static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
11 u16 *data, bool read);
12
13/* Cable length tables */
14static const u16 e1000_m88_cable_length_table[] = {
15 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED
16};
17
18#define M88E1000_CABLE_LENGTH_TABLE_SIZE \
19 ARRAY_SIZE(e1000_m88_cable_length_table)
20
21static const u16 e1000_igp_2_cable_length_table[] = {
22 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
23 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
24 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
25 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
26 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
27 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
28 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
29 124
30};
31
32#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
33 ARRAY_SIZE(e1000_igp_2_cable_length_table)
34
35/**
36 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
37 * @hw: pointer to the HW structure
38 *
39 * Read the PHY management control register and check whether a PHY reset
40 * is blocked. If a reset is not blocked return 0, otherwise
41 * return E1000_BLK_PHY_RESET (12).
42 **/
43s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)
44{
45 u32 manc;
46
47 manc = er32(MANC);
48
49 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? E1000_BLK_PHY_RESET : 0;
50}
51
52/**
53 * e1000e_get_phy_id - Retrieve the PHY ID and revision
54 * @hw: pointer to the HW structure
55 *
56 * Reads the PHY registers and stores the PHY ID and possibly the PHY
57 * revision in the hardware structure.
58 **/
59s32 e1000e_get_phy_id(struct e1000_hw *hw)
60{
61 struct e1000_phy_info *phy = &hw->phy;
62 s32 ret_val = 0;
63 u16 phy_id;
64 u16 retry_count = 0;
65
66 if (!phy->ops.read_reg)
67 return 0;
68
69 while (retry_count < 2) {
70 ret_val = e1e_rphy(hw, MII_PHYSID1, &phy_id);
71 if (ret_val)
72 return ret_val;
73
74 phy->id = (u32)(phy_id << 16);
75 usleep_range(20, 40);
76 ret_val = e1e_rphy(hw, MII_PHYSID2, &phy_id);
77 if (ret_val)
78 return ret_val;
79
80 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
81 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
82
83 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
84 return 0;
85
86 retry_count++;
87 }
88
89 return 0;
90}
91
92/**
93 * e1000e_phy_reset_dsp - Reset PHY DSP
94 * @hw: pointer to the HW structure
95 *
96 * Reset the digital signal processor.
97 **/
98s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
99{
100 s32 ret_val;
101
102 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
103 if (ret_val)
104 return ret_val;
105
106 return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);
107}
108
109/**
110 * e1000e_read_phy_reg_mdic - Read MDI control register
111 * @hw: pointer to the HW structure
112 * @offset: register offset to be read
113 * @data: pointer to the read data
114 *
115 * Reads the MDI control register in the PHY at offset and stores the
116 * information read to data.
117 **/
118s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
119{
120 struct e1000_phy_info *phy = &hw->phy;
121 u32 i, mdic = 0;
122
123 if (offset > MAX_PHY_REG_ADDRESS) {
124 e_dbg("PHY Address %d is out of range\n", offset);
125 return -E1000_ERR_PARAM;
126 }
127
128 /* Set up Op-code, Phy Address, and register offset in the MDI
129 * Control register. The MAC will take care of interfacing with the
130 * PHY to retrieve the desired data.
131 */
132 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
133 (phy->addr << E1000_MDIC_PHY_SHIFT) |
134 (E1000_MDIC_OP_READ));
135
136 ew32(MDIC, mdic);
137
138 /* Poll the ready bit to see if the MDI read completed
139 * Increasing the time out as testing showed failures with
140 * the lower time out
141 */
142 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
143 udelay(50);
144 mdic = er32(MDIC);
145 if (mdic & E1000_MDIC_READY)
146 break;
147 }
148 if (!(mdic & E1000_MDIC_READY)) {
149 e_dbg("MDI Read PHY Reg Address %d did not complete\n", offset);
150 return -E1000_ERR_PHY;
151 }
152 if (mdic & E1000_MDIC_ERROR) {
153 e_dbg("MDI Read PHY Reg Address %d Error\n", offset);
154 return -E1000_ERR_PHY;
155 }
156 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
157 e_dbg("MDI Read offset error - requested %d, returned %d\n",
158 offset,
159 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
160 return -E1000_ERR_PHY;
161 }
162 *data = (u16)mdic;
163
164 /* Allow some time after each MDIC transaction to avoid
165 * reading duplicate data in the next MDIC transaction.
166 */
167 if (hw->mac.type == e1000_pch2lan)
168 udelay(100);
169
170 return 0;
171}
172
173/**
174 * e1000e_write_phy_reg_mdic - Write MDI control register
175 * @hw: pointer to the HW structure
176 * @offset: register offset to write to
177 * @data: data to write to register at offset
178 *
179 * Writes data to MDI control register in the PHY at offset.
180 **/
181s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
182{
183 struct e1000_phy_info *phy = &hw->phy;
184 u32 i, mdic = 0;
185
186 if (offset > MAX_PHY_REG_ADDRESS) {
187 e_dbg("PHY Address %d is out of range\n", offset);
188 return -E1000_ERR_PARAM;
189 }
190
191 /* Set up Op-code, Phy Address, and register offset in the MDI
192 * Control register. The MAC will take care of interfacing with the
193 * PHY to retrieve the desired data.
194 */
195 mdic = (((u32)data) |
196 (offset << E1000_MDIC_REG_SHIFT) |
197 (phy->addr << E1000_MDIC_PHY_SHIFT) |
198 (E1000_MDIC_OP_WRITE));
199
200 ew32(MDIC, mdic);
201
202 /* Poll the ready bit to see if the MDI read completed
203 * Increasing the time out as testing showed failures with
204 * the lower time out
205 */
206 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
207 udelay(50);
208 mdic = er32(MDIC);
209 if (mdic & E1000_MDIC_READY)
210 break;
211 }
212 if (!(mdic & E1000_MDIC_READY)) {
213 e_dbg("MDI Write PHY Reg Address %d did not complete\n", offset);
214 return -E1000_ERR_PHY;
215 }
216 if (mdic & E1000_MDIC_ERROR) {
217 e_dbg("MDI Write PHY Red Address %d Error\n", offset);
218 return -E1000_ERR_PHY;
219 }
220 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
221 e_dbg("MDI Write offset error - requested %d, returned %d\n",
222 offset,
223 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
224 return -E1000_ERR_PHY;
225 }
226
227 /* Allow some time after each MDIC transaction to avoid
228 * reading duplicate data in the next MDIC transaction.
229 */
230 if (hw->mac.type == e1000_pch2lan)
231 udelay(100);
232
233 return 0;
234}
235
236/**
237 * e1000e_read_phy_reg_m88 - Read m88 PHY register
238 * @hw: pointer to the HW structure
239 * @offset: register offset to be read
240 * @data: pointer to the read data
241 *
242 * Acquires semaphore, if necessary, then reads the PHY register at offset
243 * and storing the retrieved information in data. Release any acquired
244 * semaphores before exiting.
245 **/
246s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
247{
248 s32 ret_val;
249
250 ret_val = hw->phy.ops.acquire(hw);
251 if (ret_val)
252 return ret_val;
253
254 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
255 data);
256
257 hw->phy.ops.release(hw);
258
259 return ret_val;
260}
261
262/**
263 * e1000e_write_phy_reg_m88 - Write m88 PHY register
264 * @hw: pointer to the HW structure
265 * @offset: register offset to write to
266 * @data: data to write at register offset
267 *
268 * Acquires semaphore, if necessary, then writes the data to PHY register
269 * at the offset. Release any acquired semaphores before exiting.
270 **/
271s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
272{
273 s32 ret_val;
274
275 ret_val = hw->phy.ops.acquire(hw);
276 if (ret_val)
277 return ret_val;
278
279 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
280 data);
281
282 hw->phy.ops.release(hw);
283
284 return ret_val;
285}
286
287/**
288 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
289 * @hw: pointer to the HW structure
290 * @page: page to set (shifted left when necessary)
291 *
292 * Sets PHY page required for PHY register access. Assumes semaphore is
293 * already acquired. Note, this function sets phy.addr to 1 so the caller
294 * must set it appropriately (if necessary) after this function returns.
295 **/
296s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
297{
298 e_dbg("Setting page 0x%x\n", page);
299
300 hw->phy.addr = 1;
301
302 return e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
303}
304
305/**
306 * __e1000e_read_phy_reg_igp - Read igp PHY register
307 * @hw: pointer to the HW structure
308 * @offset: register offset to be read
309 * @data: pointer to the read data
310 * @locked: semaphore has already been acquired or not
311 *
312 * Acquires semaphore, if necessary, then reads the PHY register at offset
313 * and stores the retrieved information in data. Release any acquired
314 * semaphores before exiting.
315 **/
316static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
317 bool locked)
318{
319 s32 ret_val = 0;
320
321 if (!locked) {
322 if (!hw->phy.ops.acquire)
323 return 0;
324
325 ret_val = hw->phy.ops.acquire(hw);
326 if (ret_val)
327 return ret_val;
328 }
329
330 if (offset > MAX_PHY_MULTI_PAGE_REG)
331 ret_val = e1000e_write_phy_reg_mdic(hw,
332 IGP01E1000_PHY_PAGE_SELECT,
333 (u16)offset);
334 if (!ret_val)
335 ret_val = e1000e_read_phy_reg_mdic(hw,
336 MAX_PHY_REG_ADDRESS & offset,
337 data);
338 if (!locked)
339 hw->phy.ops.release(hw);
340
341 return ret_val;
342}
343
344/**
345 * e1000e_read_phy_reg_igp - Read igp PHY register
346 * @hw: pointer to the HW structure
347 * @offset: register offset to be read
348 * @data: pointer to the read data
349 *
350 * Acquires semaphore then reads the PHY register at offset and stores the
351 * retrieved information in data.
352 * Release the acquired semaphore before exiting.
353 **/
354s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
355{
356 return __e1000e_read_phy_reg_igp(hw, offset, data, false);
357}
358
359/**
360 * e1000e_read_phy_reg_igp_locked - Read igp PHY register
361 * @hw: pointer to the HW structure
362 * @offset: register offset to be read
363 * @data: pointer to the read data
364 *
365 * Reads the PHY register at offset and stores the retrieved information
366 * in data. Assumes semaphore already acquired.
367 **/
368s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
369{
370 return __e1000e_read_phy_reg_igp(hw, offset, data, true);
371}
372
373/**
374 * __e1000e_write_phy_reg_igp - Write igp PHY register
375 * @hw: pointer to the HW structure
376 * @offset: register offset to write to
377 * @data: data to write at register offset
378 * @locked: semaphore has already been acquired or not
379 *
380 * Acquires semaphore, if necessary, then writes the data to PHY register
381 * at the offset. Release any acquired semaphores before exiting.
382 **/
383static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
384 bool locked)
385{
386 s32 ret_val = 0;
387
388 if (!locked) {
389 if (!hw->phy.ops.acquire)
390 return 0;
391
392 ret_val = hw->phy.ops.acquire(hw);
393 if (ret_val)
394 return ret_val;
395 }
396
397 if (offset > MAX_PHY_MULTI_PAGE_REG)
398 ret_val = e1000e_write_phy_reg_mdic(hw,
399 IGP01E1000_PHY_PAGE_SELECT,
400 (u16)offset);
401 if (!ret_val)
402 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
403 offset, data);
404 if (!locked)
405 hw->phy.ops.release(hw);
406
407 return ret_val;
408}
409
410/**
411 * e1000e_write_phy_reg_igp - Write igp PHY register
412 * @hw: pointer to the HW structure
413 * @offset: register offset to write to
414 * @data: data to write at register offset
415 *
416 * Acquires semaphore then writes the data to PHY register
417 * at the offset. Release any acquired semaphores before exiting.
418 **/
419s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
420{
421 return __e1000e_write_phy_reg_igp(hw, offset, data, false);
422}
423
424/**
425 * e1000e_write_phy_reg_igp_locked - Write igp PHY register
426 * @hw: pointer to the HW structure
427 * @offset: register offset to write to
428 * @data: data to write at register offset
429 *
430 * Writes the data to PHY register at the offset.
431 * Assumes semaphore already acquired.
432 **/
433s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
434{
435 return __e1000e_write_phy_reg_igp(hw, offset, data, true);
436}
437
438/**
439 * __e1000_read_kmrn_reg - Read kumeran register
440 * @hw: pointer to the HW structure
441 * @offset: register offset to be read
442 * @data: pointer to the read data
443 * @locked: semaphore has already been acquired or not
444 *
445 * Acquires semaphore, if necessary. Then reads the PHY register at offset
446 * using the kumeran interface. The information retrieved is stored in data.
447 * Release any acquired semaphores before exiting.
448 **/
449static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
450 bool locked)
451{
452 u32 kmrnctrlsta;
453
454 if (!locked) {
455 s32 ret_val = 0;
456
457 if (!hw->phy.ops.acquire)
458 return 0;
459
460 ret_val = hw->phy.ops.acquire(hw);
461 if (ret_val)
462 return ret_val;
463 }
464
465 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
466 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
467 ew32(KMRNCTRLSTA, kmrnctrlsta);
468 e1e_flush();
469
470 udelay(2);
471
472 kmrnctrlsta = er32(KMRNCTRLSTA);
473 *data = (u16)kmrnctrlsta;
474
475 if (!locked)
476 hw->phy.ops.release(hw);
477
478 return 0;
479}
480
481/**
482 * e1000e_read_kmrn_reg - Read kumeran register
483 * @hw: pointer to the HW structure
484 * @offset: register offset to be read
485 * @data: pointer to the read data
486 *
487 * Acquires semaphore then reads the PHY register at offset using the
488 * kumeran interface. The information retrieved is stored in data.
489 * Release the acquired semaphore before exiting.
490 **/
491s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)
492{
493 return __e1000_read_kmrn_reg(hw, offset, data, false);
494}
495
496/**
497 * e1000e_read_kmrn_reg_locked - Read kumeran register
498 * @hw: pointer to the HW structure
499 * @offset: register offset to be read
500 * @data: pointer to the read data
501 *
502 * Reads the PHY register at offset using the kumeran interface. The
503 * information retrieved is stored in data.
504 * Assumes semaphore already acquired.
505 **/
506s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
507{
508 return __e1000_read_kmrn_reg(hw, offset, data, true);
509}
510
511/**
512 * __e1000_write_kmrn_reg - Write kumeran register
513 * @hw: pointer to the HW structure
514 * @offset: register offset to write to
515 * @data: data to write at register offset
516 * @locked: semaphore has already been acquired or not
517 *
518 * Acquires semaphore, if necessary. Then write the data to PHY register
519 * at the offset using the kumeran interface. Release any acquired semaphores
520 * before exiting.
521 **/
522static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
523 bool locked)
524{
525 u32 kmrnctrlsta;
526
527 if (!locked) {
528 s32 ret_val = 0;
529
530 if (!hw->phy.ops.acquire)
531 return 0;
532
533 ret_val = hw->phy.ops.acquire(hw);
534 if (ret_val)
535 return ret_val;
536 }
537
538 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
539 E1000_KMRNCTRLSTA_OFFSET) | data;
540 ew32(KMRNCTRLSTA, kmrnctrlsta);
541 e1e_flush();
542
543 udelay(2);
544
545 if (!locked)
546 hw->phy.ops.release(hw);
547
548 return 0;
549}
550
551/**
552 * e1000e_write_kmrn_reg - Write kumeran register
553 * @hw: pointer to the HW structure
554 * @offset: register offset to write to
555 * @data: data to write at register offset
556 *
557 * Acquires semaphore then writes the data to the PHY register at the offset
558 * using the kumeran interface. Release the acquired semaphore before exiting.
559 **/
560s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
561{
562 return __e1000_write_kmrn_reg(hw, offset, data, false);
563}
564
565/**
566 * e1000e_write_kmrn_reg_locked - Write kumeran register
567 * @hw: pointer to the HW structure
568 * @offset: register offset to write to
569 * @data: data to write at register offset
570 *
571 * Write the data to PHY register at the offset using the kumeran interface.
572 * Assumes semaphore already acquired.
573 **/
574s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
575{
576 return __e1000_write_kmrn_reg(hw, offset, data, true);
577}
578
579/**
580 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode
581 * @hw: pointer to the HW structure
582 *
583 * Sets up Master/slave mode
584 **/
585static s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
586{
587 s32 ret_val;
588 u16 phy_data;
589
590 /* Resolve Master/Slave mode */
591 ret_val = e1e_rphy(hw, MII_CTRL1000, &phy_data);
592 if (ret_val)
593 return ret_val;
594
595 /* load defaults for future use */
596 hw->phy.original_ms_type = (phy_data & CTL1000_ENABLE_MASTER) ?
597 ((phy_data & CTL1000_AS_MASTER) ?
598 e1000_ms_force_master : e1000_ms_force_slave) : e1000_ms_auto;
599
600 switch (hw->phy.ms_type) {
601 case e1000_ms_force_master:
602 phy_data |= (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
603 break;
604 case e1000_ms_force_slave:
605 phy_data |= CTL1000_ENABLE_MASTER;
606 phy_data &= ~(CTL1000_AS_MASTER);
607 break;
608 case e1000_ms_auto:
609 phy_data &= ~CTL1000_ENABLE_MASTER;
610 fallthrough;
611 default:
612 break;
613 }
614
615 return e1e_wphy(hw, MII_CTRL1000, phy_data);
616}
617
618/**
619 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
620 * @hw: pointer to the HW structure
621 *
622 * Sets up Carrier-sense on Transmit and downshift values.
623 **/
624s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
625{
626 s32 ret_val;
627 u16 phy_data;
628
629 /* Enable CRS on Tx. This must be set for half-duplex operation. */
630 ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data);
631 if (ret_val)
632 return ret_val;
633
634 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
635
636 /* Enable downshift */
637 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
638
639 ret_val = e1e_wphy(hw, I82577_CFG_REG, phy_data);
640 if (ret_val)
641 return ret_val;
642
643 /* Set MDI/MDIX mode */
644 ret_val = e1e_rphy(hw, I82577_PHY_CTRL_2, &phy_data);
645 if (ret_val)
646 return ret_val;
647 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;
648 /* Options:
649 * 0 - Auto (default)
650 * 1 - MDI mode
651 * 2 - MDI-X mode
652 */
653 switch (hw->phy.mdix) {
654 case 1:
655 break;
656 case 2:
657 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX;
658 break;
659 case 0:
660 default:
661 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX;
662 break;
663 }
664 ret_val = e1e_wphy(hw, I82577_PHY_CTRL_2, phy_data);
665 if (ret_val)
666 return ret_val;
667
668 return e1000_set_master_slave_mode(hw);
669}
670
671/**
672 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link
673 * @hw: pointer to the HW structure
674 *
675 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
676 * and downshift values are set also.
677 **/
678s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
679{
680 struct e1000_phy_info *phy = &hw->phy;
681 s32 ret_val;
682 u16 phy_data;
683
684 /* Enable CRS on Tx. This must be set for half-duplex operation. */
685 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
686 if (ret_val)
687 return ret_val;
688
689 /* For BM PHY this bit is downshift enable */
690 if (phy->type != e1000_phy_bm)
691 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
692
693 /* Options:
694 * MDI/MDI-X = 0 (default)
695 * 0 - Auto for all speeds
696 * 1 - MDI mode
697 * 2 - MDI-X mode
698 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
699 */
700 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
701
702 switch (phy->mdix) {
703 case 1:
704 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
705 break;
706 case 2:
707 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
708 break;
709 case 3:
710 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
711 break;
712 case 0:
713 default:
714 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
715 break;
716 }
717
718 /* Options:
719 * disable_polarity_correction = 0 (default)
720 * Automatic Correction for Reversed Cable Polarity
721 * 0 - Disabled
722 * 1 - Enabled
723 */
724 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
725 if (phy->disable_polarity_correction)
726 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
727
728 /* Enable downshift on BM (disabled by default) */
729 if (phy->type == e1000_phy_bm) {
730 /* For 82574/82583, first disable then enable downshift */
731 if (phy->id == BME1000_E_PHY_ID_R2) {
732 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT;
733 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL,
734 phy_data);
735 if (ret_val)
736 return ret_val;
737 /* Commit the changes. */
738 ret_val = phy->ops.commit(hw);
739 if (ret_val) {
740 e_dbg("Error committing the PHY changes\n");
741 return ret_val;
742 }
743 }
744
745 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
746 }
747
748 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
749 if (ret_val)
750 return ret_val;
751
752 if ((phy->type == e1000_phy_m88) &&
753 (phy->revision < E1000_REVISION_4) &&
754 (phy->id != BME1000_E_PHY_ID_R2)) {
755 /* Force TX_CLK in the Extended PHY Specific Control Register
756 * to 25MHz clock.
757 */
758 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
759 if (ret_val)
760 return ret_val;
761
762 phy_data |= M88E1000_EPSCR_TX_CLK_25;
763
764 if ((phy->revision == 2) && (phy->id == M88E1111_I_PHY_ID)) {
765 /* 82573L PHY - set the downshift counter to 5x. */
766 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
767 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
768 } else {
769 /* Configure Master and Slave downshift values */
770 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
771 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
772 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
773 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
774 }
775 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
776 if (ret_val)
777 return ret_val;
778 }
779
780 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
781 /* Set PHY page 0, register 29 to 0x0003 */
782 ret_val = e1e_wphy(hw, 29, 0x0003);
783 if (ret_val)
784 return ret_val;
785
786 /* Set PHY page 0, register 30 to 0x0000 */
787 ret_val = e1e_wphy(hw, 30, 0x0000);
788 if (ret_val)
789 return ret_val;
790 }
791
792 /* Commit the changes. */
793 if (phy->ops.commit) {
794 ret_val = phy->ops.commit(hw);
795 if (ret_val) {
796 e_dbg("Error committing the PHY changes\n");
797 return ret_val;
798 }
799 }
800
801 if (phy->type == e1000_phy_82578) {
802 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
803 if (ret_val)
804 return ret_val;
805
806 /* 82578 PHY - set the downshift count to 1x. */
807 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
808 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
809 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
810 if (ret_val)
811 return ret_val;
812 }
813
814 return 0;
815}
816
817/**
818 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link
819 * @hw: pointer to the HW structure
820 *
821 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
822 * igp PHY's.
823 **/
824s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
825{
826 struct e1000_phy_info *phy = &hw->phy;
827 s32 ret_val;
828 u16 data;
829
830 ret_val = e1000_phy_hw_reset(hw);
831 if (ret_val) {
832 e_dbg("Error resetting the PHY.\n");
833 return ret_val;
834 }
835
836 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
837 * timeout issues when LFS is enabled.
838 */
839 msleep(100);
840
841 /* disable lplu d0 during driver init */
842 if (hw->phy.ops.set_d0_lplu_state) {
843 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
844 if (ret_val) {
845 e_dbg("Error Disabling LPLU D0\n");
846 return ret_val;
847 }
848 }
849 /* Configure mdi-mdix settings */
850 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data);
851 if (ret_val)
852 return ret_val;
853
854 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
855
856 switch (phy->mdix) {
857 case 1:
858 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
859 break;
860 case 2:
861 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
862 break;
863 case 0:
864 default:
865 data |= IGP01E1000_PSCR_AUTO_MDIX;
866 break;
867 }
868 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data);
869 if (ret_val)
870 return ret_val;
871
872 /* set auto-master slave resolution settings */
873 if (hw->mac.autoneg) {
874 /* when autonegotiation advertisement is only 1000Mbps then we
875 * should disable SmartSpeed and enable Auto MasterSlave
876 * resolution as hardware default.
877 */
878 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
879 /* Disable SmartSpeed */
880 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
881 &data);
882 if (ret_val)
883 return ret_val;
884
885 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
886 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
887 data);
888 if (ret_val)
889 return ret_val;
890
891 /* Set auto Master/Slave resolution process */
892 ret_val = e1e_rphy(hw, MII_CTRL1000, &data);
893 if (ret_val)
894 return ret_val;
895
896 data &= ~CTL1000_ENABLE_MASTER;
897 ret_val = e1e_wphy(hw, MII_CTRL1000, data);
898 if (ret_val)
899 return ret_val;
900 }
901
902 ret_val = e1000_set_master_slave_mode(hw);
903 }
904
905 return ret_val;
906}
907
908/**
909 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
910 * @hw: pointer to the HW structure
911 *
912 * Reads the MII auto-neg advertisement register and/or the 1000T control
913 * register and if the PHY is already setup for auto-negotiation, then
914 * return successful. Otherwise, setup advertisement and flow control to
915 * the appropriate values for the wanted auto-negotiation.
916 **/
917static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
918{
919 struct e1000_phy_info *phy = &hw->phy;
920 s32 ret_val;
921 u16 mii_autoneg_adv_reg;
922 u16 mii_1000t_ctrl_reg = 0;
923
924 phy->autoneg_advertised &= phy->autoneg_mask;
925
926 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
927 ret_val = e1e_rphy(hw, MII_ADVERTISE, &mii_autoneg_adv_reg);
928 if (ret_val)
929 return ret_val;
930
931 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
932 /* Read the MII 1000Base-T Control Register (Address 9). */
933 ret_val = e1e_rphy(hw, MII_CTRL1000, &mii_1000t_ctrl_reg);
934 if (ret_val)
935 return ret_val;
936 }
937
938 /* Need to parse both autoneg_advertised and fc and set up
939 * the appropriate PHY registers. First we will parse for
940 * autoneg_advertised software override. Since we can advertise
941 * a plethora of combinations, we need to check each bit
942 * individually.
943 */
944
945 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
946 * Advertisement Register (Address 4) and the 1000 mb speed bits in
947 * the 1000Base-T Control Register (Address 9).
948 */
949 mii_autoneg_adv_reg &= ~(ADVERTISE_100FULL |
950 ADVERTISE_100HALF |
951 ADVERTISE_10FULL | ADVERTISE_10HALF);
952 mii_1000t_ctrl_reg &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL);
953
954 e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
955
956 /* Do we want to advertise 10 Mb Half Duplex? */
957 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
958 e_dbg("Advertise 10mb Half duplex\n");
959 mii_autoneg_adv_reg |= ADVERTISE_10HALF;
960 }
961
962 /* Do we want to advertise 10 Mb Full Duplex? */
963 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
964 e_dbg("Advertise 10mb Full duplex\n");
965 mii_autoneg_adv_reg |= ADVERTISE_10FULL;
966 }
967
968 /* Do we want to advertise 100 Mb Half Duplex? */
969 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
970 e_dbg("Advertise 100mb Half duplex\n");
971 mii_autoneg_adv_reg |= ADVERTISE_100HALF;
972 }
973
974 /* Do we want to advertise 100 Mb Full Duplex? */
975 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
976 e_dbg("Advertise 100mb Full duplex\n");
977 mii_autoneg_adv_reg |= ADVERTISE_100FULL;
978 }
979
980 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
981 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
982 e_dbg("Advertise 1000mb Half duplex request denied!\n");
983
984 /* Do we want to advertise 1000 Mb Full Duplex? */
985 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
986 e_dbg("Advertise 1000mb Full duplex\n");
987 mii_1000t_ctrl_reg |= ADVERTISE_1000FULL;
988 }
989
990 /* Check for a software override of the flow control settings, and
991 * setup the PHY advertisement registers accordingly. If
992 * auto-negotiation is enabled, then software will have to set the
993 * "PAUSE" bits to the correct value in the Auto-Negotiation
994 * Advertisement Register (MII_ADVERTISE) and re-start auto-
995 * negotiation.
996 *
997 * The possible values of the "fc" parameter are:
998 * 0: Flow control is completely disabled
999 * 1: Rx flow control is enabled (we can receive pause frames
1000 * but not send pause frames).
1001 * 2: Tx flow control is enabled (we can send pause frames
1002 * but we do not support receiving pause frames).
1003 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1004 * other: No software override. The flow control configuration
1005 * in the EEPROM is used.
1006 */
1007 switch (hw->fc.current_mode) {
1008 case e1000_fc_none:
1009 /* Flow control (Rx & Tx) is completely disabled by a
1010 * software over-ride.
1011 */
1012 mii_autoneg_adv_reg &=
1013 ~(ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1014 break;
1015 case e1000_fc_rx_pause:
1016 /* Rx Flow control is enabled, and Tx Flow control is
1017 * disabled, by a software over-ride.
1018 *
1019 * Since there really isn't a way to advertise that we are
1020 * capable of Rx Pause ONLY, we will advertise that we
1021 * support both symmetric and asymmetric Rx PAUSE. Later
1022 * (in e1000e_config_fc_after_link_up) we will disable the
1023 * hw's ability to send PAUSE frames.
1024 */
1025 mii_autoneg_adv_reg |=
1026 (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1027 break;
1028 case e1000_fc_tx_pause:
1029 /* Tx Flow control is enabled, and Rx Flow control is
1030 * disabled, by a software over-ride.
1031 */
1032 mii_autoneg_adv_reg |= ADVERTISE_PAUSE_ASYM;
1033 mii_autoneg_adv_reg &= ~ADVERTISE_PAUSE_CAP;
1034 break;
1035 case e1000_fc_full:
1036 /* Flow control (both Rx and Tx) is enabled by a software
1037 * over-ride.
1038 */
1039 mii_autoneg_adv_reg |=
1040 (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1041 break;
1042 default:
1043 e_dbg("Flow control param set incorrectly\n");
1044 return -E1000_ERR_CONFIG;
1045 }
1046
1047 ret_val = e1e_wphy(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
1048 if (ret_val)
1049 return ret_val;
1050
1051 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1052
1053 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1054 ret_val = e1e_wphy(hw, MII_CTRL1000, mii_1000t_ctrl_reg);
1055
1056 return ret_val;
1057}
1058
1059/**
1060 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1061 * @hw: pointer to the HW structure
1062 *
1063 * Performs initial bounds checking on autoneg advertisement parameter, then
1064 * configure to advertise the full capability. Setup the PHY to autoneg
1065 * and restart the negotiation process between the link partner. If
1066 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1067 **/
1068static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1069{
1070 struct e1000_phy_info *phy = &hw->phy;
1071 s32 ret_val;
1072 u16 phy_ctrl;
1073
1074 /* Perform some bounds checking on the autoneg advertisement
1075 * parameter.
1076 */
1077 phy->autoneg_advertised &= phy->autoneg_mask;
1078
1079 /* If autoneg_advertised is zero, we assume it was not defaulted
1080 * by the calling code so we set to advertise full capability.
1081 */
1082 if (!phy->autoneg_advertised)
1083 phy->autoneg_advertised = phy->autoneg_mask;
1084
1085 e_dbg("Reconfiguring auto-neg advertisement params\n");
1086 ret_val = e1000_phy_setup_autoneg(hw);
1087 if (ret_val) {
1088 e_dbg("Error Setting up Auto-Negotiation\n");
1089 return ret_val;
1090 }
1091 e_dbg("Restarting Auto-Neg\n");
1092
1093 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1094 * the Auto Neg Restart bit in the PHY control register.
1095 */
1096 ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl);
1097 if (ret_val)
1098 return ret_val;
1099
1100 phy_ctrl |= (BMCR_ANENABLE | BMCR_ANRESTART);
1101 ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl);
1102 if (ret_val)
1103 return ret_val;
1104
1105 /* Does the user want to wait for Auto-Neg to complete here, or
1106 * check at a later time (for example, callback routine).
1107 */
1108 if (phy->autoneg_wait_to_complete) {
1109 ret_val = e1000_wait_autoneg(hw);
1110 if (ret_val) {
1111 e_dbg("Error while waiting for autoneg to complete\n");
1112 return ret_val;
1113 }
1114 }
1115
1116 hw->mac.get_link_status = true;
1117
1118 return ret_val;
1119}
1120
1121/**
1122 * e1000e_setup_copper_link - Configure copper link settings
1123 * @hw: pointer to the HW structure
1124 *
1125 * Calls the appropriate function to configure the link for auto-neg or forced
1126 * speed and duplex. Then we check for link, once link is established calls
1127 * to configure collision distance and flow control are called. If link is
1128 * not established, we return -E1000_ERR_PHY (-2).
1129 **/
1130s32 e1000e_setup_copper_link(struct e1000_hw *hw)
1131{
1132 s32 ret_val;
1133 bool link;
1134
1135 if (hw->mac.autoneg) {
1136 /* Setup autoneg and flow control advertisement and perform
1137 * autonegotiation.
1138 */
1139 ret_val = e1000_copper_link_autoneg(hw);
1140 if (ret_val)
1141 return ret_val;
1142 } else {
1143 /* PHY will be set to 10H, 10F, 100H or 100F
1144 * depending on user settings.
1145 */
1146 e_dbg("Forcing Speed and Duplex\n");
1147 ret_val = hw->phy.ops.force_speed_duplex(hw);
1148 if (ret_val) {
1149 e_dbg("Error Forcing Speed and Duplex\n");
1150 return ret_val;
1151 }
1152 }
1153
1154 /* Check link status. Wait up to 100 microseconds for link to become
1155 * valid.
1156 */
1157 ret_val = e1000e_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1158 &link);
1159 if (ret_val)
1160 return ret_val;
1161
1162 if (link) {
1163 e_dbg("Valid link established!!!\n");
1164 hw->mac.ops.config_collision_dist(hw);
1165 ret_val = e1000e_config_fc_after_link_up(hw);
1166 } else {
1167 e_dbg("Unable to establish link!!!\n");
1168 }
1169
1170 return ret_val;
1171}
1172
1173/**
1174 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1175 * @hw: pointer to the HW structure
1176 *
1177 * Calls the PHY setup function to force speed and duplex. Clears the
1178 * auto-crossover to force MDI manually. Waits for link and returns
1179 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1180 **/
1181s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1182{
1183 struct e1000_phy_info *phy = &hw->phy;
1184 s32 ret_val;
1185 u16 phy_data;
1186 bool link;
1187
1188 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
1189 if (ret_val)
1190 return ret_val;
1191
1192 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1193
1194 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
1195 if (ret_val)
1196 return ret_val;
1197
1198 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1199 * forced whenever speed and duplex are forced.
1200 */
1201 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1202 if (ret_val)
1203 return ret_val;
1204
1205 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1206 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1207
1208 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1209 if (ret_val)
1210 return ret_val;
1211
1212 e_dbg("IGP PSCR: %X\n", phy_data);
1213
1214 udelay(1);
1215
1216 if (phy->autoneg_wait_to_complete) {
1217 e_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1218
1219 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1220 100000, &link);
1221 if (ret_val)
1222 return ret_val;
1223
1224 if (!link)
1225 e_dbg("Link taking longer than expected.\n");
1226
1227 /* Try once more */
1228 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1229 100000, &link);
1230 }
1231
1232 return ret_val;
1233}
1234
1235/**
1236 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1237 * @hw: pointer to the HW structure
1238 *
1239 * Calls the PHY setup function to force speed and duplex. Clears the
1240 * auto-crossover to force MDI manually. Resets the PHY to commit the
1241 * changes. If time expires while waiting for link up, we reset the DSP.
1242 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1243 * successful completion, else return corresponding error code.
1244 **/
1245s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1246{
1247 struct e1000_phy_info *phy = &hw->phy;
1248 s32 ret_val;
1249 u16 phy_data;
1250 bool link;
1251
1252 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1253 * forced whenever speed and duplex are forced.
1254 */
1255 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1256 if (ret_val)
1257 return ret_val;
1258
1259 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1260 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1261 if (ret_val)
1262 return ret_val;
1263
1264 e_dbg("M88E1000 PSCR: %X\n", phy_data);
1265
1266 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
1267 if (ret_val)
1268 return ret_val;
1269
1270 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1271
1272 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
1273 if (ret_val)
1274 return ret_val;
1275
1276 /* Reset the phy to commit changes. */
1277 if (hw->phy.ops.commit) {
1278 ret_val = hw->phy.ops.commit(hw);
1279 if (ret_val)
1280 return ret_val;
1281 }
1282
1283 if (phy->autoneg_wait_to_complete) {
1284 e_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1285
1286 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1287 100000, &link);
1288 if (ret_val)
1289 return ret_val;
1290
1291 if (!link) {
1292 if (hw->phy.type != e1000_phy_m88) {
1293 e_dbg("Link taking longer than expected.\n");
1294 } else {
1295 /* We didn't get link.
1296 * Reset the DSP and cross our fingers.
1297 */
1298 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT,
1299 0x001d);
1300 if (ret_val)
1301 return ret_val;
1302 ret_val = e1000e_phy_reset_dsp(hw);
1303 if (ret_val)
1304 return ret_val;
1305 }
1306 }
1307
1308 /* Try once more */
1309 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1310 100000, &link);
1311 if (ret_val)
1312 return ret_val;
1313 }
1314
1315 if (hw->phy.type != e1000_phy_m88)
1316 return 0;
1317
1318 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1319 if (ret_val)
1320 return ret_val;
1321
1322 /* Resetting the phy means we need to re-force TX_CLK in the
1323 * Extended PHY Specific Control Register to 25MHz clock from
1324 * the reset value of 2.5MHz.
1325 */
1326 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1327 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1328 if (ret_val)
1329 return ret_val;
1330
1331 /* In addition, we must re-enable CRS on Tx for both half and full
1332 * duplex.
1333 */
1334 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1335 if (ret_val)
1336 return ret_val;
1337
1338 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1339 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1340
1341 return ret_val;
1342}
1343
1344/**
1345 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1346 * @hw: pointer to the HW structure
1347 *
1348 * Forces the speed and duplex settings of the PHY.
1349 * This is a function pointer entry point only called by
1350 * PHY setup routines.
1351 **/
1352s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1353{
1354 struct e1000_phy_info *phy = &hw->phy;
1355 s32 ret_val;
1356 u16 data;
1357 bool link;
1358
1359 ret_val = e1e_rphy(hw, MII_BMCR, &data);
1360 if (ret_val)
1361 return ret_val;
1362
1363 e1000e_phy_force_speed_duplex_setup(hw, &data);
1364
1365 ret_val = e1e_wphy(hw, MII_BMCR, data);
1366 if (ret_val)
1367 return ret_val;
1368
1369 /* Disable MDI-X support for 10/100 */
1370 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
1371 if (ret_val)
1372 return ret_val;
1373
1374 data &= ~IFE_PMC_AUTO_MDIX;
1375 data &= ~IFE_PMC_FORCE_MDIX;
1376
1377 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
1378 if (ret_val)
1379 return ret_val;
1380
1381 e_dbg("IFE PMC: %X\n", data);
1382
1383 udelay(1);
1384
1385 if (phy->autoneg_wait_to_complete) {
1386 e_dbg("Waiting for forced speed/duplex link on IFE phy.\n");
1387
1388 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1389 100000, &link);
1390 if (ret_val)
1391 return ret_val;
1392
1393 if (!link)
1394 e_dbg("Link taking longer than expected.\n");
1395
1396 /* Try once more */
1397 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1398 100000, &link);
1399 if (ret_val)
1400 return ret_val;
1401 }
1402
1403 return 0;
1404}
1405
1406/**
1407 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1408 * @hw: pointer to the HW structure
1409 * @phy_ctrl: pointer to current value of MII_BMCR
1410 *
1411 * Forces speed and duplex on the PHY by doing the following: disable flow
1412 * control, force speed/duplex on the MAC, disable auto speed detection,
1413 * disable auto-negotiation, configure duplex, configure speed, configure
1414 * the collision distance, write configuration to CTRL register. The
1415 * caller must write to the MII_BMCR register for these settings to
1416 * take affect.
1417 **/
1418void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1419{
1420 struct e1000_mac_info *mac = &hw->mac;
1421 u32 ctrl;
1422
1423 /* Turn off flow control when forcing speed/duplex */
1424 hw->fc.current_mode = e1000_fc_none;
1425
1426 /* Force speed/duplex on the mac */
1427 ctrl = er32(CTRL);
1428 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1429 ctrl &= ~E1000_CTRL_SPD_SEL;
1430
1431 /* Disable Auto Speed Detection */
1432 ctrl &= ~E1000_CTRL_ASDE;
1433
1434 /* Disable autoneg on the phy */
1435 *phy_ctrl &= ~BMCR_ANENABLE;
1436
1437 /* Forcing Full or Half Duplex? */
1438 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1439 ctrl &= ~E1000_CTRL_FD;
1440 *phy_ctrl &= ~BMCR_FULLDPLX;
1441 e_dbg("Half Duplex\n");
1442 } else {
1443 ctrl |= E1000_CTRL_FD;
1444 *phy_ctrl |= BMCR_FULLDPLX;
1445 e_dbg("Full Duplex\n");
1446 }
1447
1448 /* Forcing 10mb or 100mb? */
1449 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1450 ctrl |= E1000_CTRL_SPD_100;
1451 *phy_ctrl |= BMCR_SPEED100;
1452 *phy_ctrl &= ~BMCR_SPEED1000;
1453 e_dbg("Forcing 100mb\n");
1454 } else {
1455 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1456 *phy_ctrl &= ~(BMCR_SPEED1000 | BMCR_SPEED100);
1457 e_dbg("Forcing 10mb\n");
1458 }
1459
1460 hw->mac.ops.config_collision_dist(hw);
1461
1462 ew32(CTRL, ctrl);
1463}
1464
1465/**
1466 * e1000e_set_d3_lplu_state - Sets low power link up state for D3
1467 * @hw: pointer to the HW structure
1468 * @active: boolean used to enable/disable lplu
1469 *
1470 * Success returns 0, Failure returns 1
1471 *
1472 * The low power link up (lplu) state is set to the power management level D3
1473 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1474 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1475 * is used during Dx states where the power conservation is most important.
1476 * During driver activity, SmartSpeed should be enabled so performance is
1477 * maintained.
1478 **/
1479s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1480{
1481 struct e1000_phy_info *phy = &hw->phy;
1482 s32 ret_val;
1483 u16 data;
1484
1485 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1486 if (ret_val)
1487 return ret_val;
1488
1489 if (!active) {
1490 data &= ~IGP02E1000_PM_D3_LPLU;
1491 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1492 if (ret_val)
1493 return ret_val;
1494 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1495 * during Dx states where the power conservation is most
1496 * important. During driver activity we should enable
1497 * SmartSpeed, so performance is maintained.
1498 */
1499 if (phy->smart_speed == e1000_smart_speed_on) {
1500 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1501 &data);
1502 if (ret_val)
1503 return ret_val;
1504
1505 data |= IGP01E1000_PSCFR_SMART_SPEED;
1506 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1507 data);
1508 if (ret_val)
1509 return ret_val;
1510 } else if (phy->smart_speed == e1000_smart_speed_off) {
1511 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1512 &data);
1513 if (ret_val)
1514 return ret_val;
1515
1516 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1517 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1518 data);
1519 if (ret_val)
1520 return ret_val;
1521 }
1522 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1523 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1524 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1525 data |= IGP02E1000_PM_D3_LPLU;
1526 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1527 if (ret_val)
1528 return ret_val;
1529
1530 /* When LPLU is enabled, we should disable SmartSpeed */
1531 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1532 if (ret_val)
1533 return ret_val;
1534
1535 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1536 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1537 }
1538
1539 return ret_val;
1540}
1541
1542/**
1543 * e1000e_check_downshift - Checks whether a downshift in speed occurred
1544 * @hw: pointer to the HW structure
1545 *
1546 * Success returns 0, Failure returns 1
1547 *
1548 * A downshift is detected by querying the PHY link health.
1549 **/
1550s32 e1000e_check_downshift(struct e1000_hw *hw)
1551{
1552 struct e1000_phy_info *phy = &hw->phy;
1553 s32 ret_val;
1554 u16 phy_data, offset, mask;
1555
1556 switch (phy->type) {
1557 case e1000_phy_m88:
1558 case e1000_phy_gg82563:
1559 case e1000_phy_bm:
1560 case e1000_phy_82578:
1561 offset = M88E1000_PHY_SPEC_STATUS;
1562 mask = M88E1000_PSSR_DOWNSHIFT;
1563 break;
1564 case e1000_phy_igp_2:
1565 case e1000_phy_igp_3:
1566 offset = IGP01E1000_PHY_LINK_HEALTH;
1567 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1568 break;
1569 default:
1570 /* speed downshift not supported */
1571 phy->speed_downgraded = false;
1572 return 0;
1573 }
1574
1575 ret_val = e1e_rphy(hw, offset, &phy_data);
1576
1577 if (!ret_val)
1578 phy->speed_downgraded = !!(phy_data & mask);
1579
1580 return ret_val;
1581}
1582
1583/**
1584 * e1000_check_polarity_m88 - Checks the polarity.
1585 * @hw: pointer to the HW structure
1586 *
1587 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1588 *
1589 * Polarity is determined based on the PHY specific status register.
1590 **/
1591s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1592{
1593 struct e1000_phy_info *phy = &hw->phy;
1594 s32 ret_val;
1595 u16 data;
1596
1597 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data);
1598
1599 if (!ret_val)
1600 phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY)
1601 ? e1000_rev_polarity_reversed
1602 : e1000_rev_polarity_normal);
1603
1604 return ret_val;
1605}
1606
1607/**
1608 * e1000_check_polarity_igp - Checks the polarity.
1609 * @hw: pointer to the HW structure
1610 *
1611 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1612 *
1613 * Polarity is determined based on the PHY port status register, and the
1614 * current speed (since there is no polarity at 100Mbps).
1615 **/
1616s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1617{
1618 struct e1000_phy_info *phy = &hw->phy;
1619 s32 ret_val;
1620 u16 data, offset, mask;
1621
1622 /* Polarity is determined based on the speed of
1623 * our connection.
1624 */
1625 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1626 if (ret_val)
1627 return ret_val;
1628
1629 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1630 IGP01E1000_PSSR_SPEED_1000MBPS) {
1631 offset = IGP01E1000_PHY_PCS_INIT_REG;
1632 mask = IGP01E1000_PHY_POLARITY_MASK;
1633 } else {
1634 /* This really only applies to 10Mbps since
1635 * there is no polarity for 100Mbps (always 0).
1636 */
1637 offset = IGP01E1000_PHY_PORT_STATUS;
1638 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1639 }
1640
1641 ret_val = e1e_rphy(hw, offset, &data);
1642
1643 if (!ret_val)
1644 phy->cable_polarity = ((data & mask)
1645 ? e1000_rev_polarity_reversed
1646 : e1000_rev_polarity_normal);
1647
1648 return ret_val;
1649}
1650
1651/**
1652 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
1653 * @hw: pointer to the HW structure
1654 *
1655 * Polarity is determined on the polarity reversal feature being enabled.
1656 **/
1657s32 e1000_check_polarity_ife(struct e1000_hw *hw)
1658{
1659 struct e1000_phy_info *phy = &hw->phy;
1660 s32 ret_val;
1661 u16 phy_data, offset, mask;
1662
1663 /* Polarity is determined based on the reversal feature being enabled.
1664 */
1665 if (phy->polarity_correction) {
1666 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1667 mask = IFE_PESC_POLARITY_REVERSED;
1668 } else {
1669 offset = IFE_PHY_SPECIAL_CONTROL;
1670 mask = IFE_PSC_FORCE_POLARITY;
1671 }
1672
1673 ret_val = e1e_rphy(hw, offset, &phy_data);
1674
1675 if (!ret_val)
1676 phy->cable_polarity = ((phy_data & mask)
1677 ? e1000_rev_polarity_reversed
1678 : e1000_rev_polarity_normal);
1679
1680 return ret_val;
1681}
1682
1683/**
1684 * e1000_wait_autoneg - Wait for auto-neg completion
1685 * @hw: pointer to the HW structure
1686 *
1687 * Waits for auto-negotiation to complete or for the auto-negotiation time
1688 * limit to expire, which ever happens first.
1689 **/
1690static s32 e1000_wait_autoneg(struct e1000_hw *hw)
1691{
1692 s32 ret_val = 0;
1693 u16 i, phy_status;
1694
1695 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1696 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1697 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1698 if (ret_val)
1699 break;
1700 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1701 if (ret_val)
1702 break;
1703 if (phy_status & BMSR_ANEGCOMPLETE)
1704 break;
1705 msleep(100);
1706 }
1707
1708 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1709 * has completed.
1710 */
1711 return ret_val;
1712}
1713
1714/**
1715 * e1000e_phy_has_link_generic - Polls PHY for link
1716 * @hw: pointer to the HW structure
1717 * @iterations: number of times to poll for link
1718 * @usec_interval: delay between polling attempts
1719 * @success: pointer to whether polling was successful or not
1720 *
1721 * Polls the PHY status register for link, 'iterations' number of times.
1722 **/
1723s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1724 u32 usec_interval, bool *success)
1725{
1726 s32 ret_val = 0;
1727 u16 i, phy_status;
1728
1729 *success = false;
1730 for (i = 0; i < iterations; i++) {
1731 /* Some PHYs require the MII_BMSR register to be read
1732 * twice due to the link bit being sticky. No harm doing
1733 * it across the board.
1734 */
1735 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1736 if (ret_val) {
1737 /* If the first read fails, another entity may have
1738 * ownership of the resources, wait and try again to
1739 * see if they have relinquished the resources yet.
1740 */
1741 if (usec_interval >= 1000)
1742 msleep(usec_interval / 1000);
1743 else
1744 udelay(usec_interval);
1745 }
1746 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1747 if (ret_val)
1748 break;
1749 if (phy_status & BMSR_LSTATUS) {
1750 *success = true;
1751 break;
1752 }
1753 if (usec_interval >= 1000)
1754 msleep(usec_interval / 1000);
1755 else
1756 udelay(usec_interval);
1757 }
1758
1759 return ret_val;
1760}
1761
1762/**
1763 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY
1764 * @hw: pointer to the HW structure
1765 *
1766 * Reads the PHY specific status register to retrieve the cable length
1767 * information. The cable length is determined by averaging the minimum and
1768 * maximum values to get the "average" cable length. The m88 PHY has four
1769 * possible cable length values, which are:
1770 * Register Value Cable Length
1771 * 0 < 50 meters
1772 * 1 50 - 80 meters
1773 * 2 80 - 110 meters
1774 * 3 110 - 140 meters
1775 * 4 > 140 meters
1776 **/
1777s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
1778{
1779 struct e1000_phy_info *phy = &hw->phy;
1780 s32 ret_val;
1781 u16 phy_data, index;
1782
1783 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1784 if (ret_val)
1785 return ret_val;
1786
1787 index = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1788 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
1789
1790 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
1791 return -E1000_ERR_PHY;
1792
1793 phy->min_cable_length = e1000_m88_cable_length_table[index];
1794 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1795
1796 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1797
1798 return 0;
1799}
1800
1801/**
1802 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1803 * @hw: pointer to the HW structure
1804 *
1805 * The automatic gain control (agc) normalizes the amplitude of the
1806 * received signal, adjusting for the attenuation produced by the
1807 * cable. By reading the AGC registers, which represent the
1808 * combination of coarse and fine gain value, the value can be put
1809 * into a lookup table to obtain the approximate cable length
1810 * for each channel.
1811 **/
1812s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
1813{
1814 struct e1000_phy_info *phy = &hw->phy;
1815 s32 ret_val;
1816 u16 phy_data, i, agc_value = 0;
1817 u16 cur_agc_index, max_agc_index = 0;
1818 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1819 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
1820 IGP02E1000_PHY_AGC_A,
1821 IGP02E1000_PHY_AGC_B,
1822 IGP02E1000_PHY_AGC_C,
1823 IGP02E1000_PHY_AGC_D
1824 };
1825
1826 /* Read the AGC registers for all channels */
1827 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1828 ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data);
1829 if (ret_val)
1830 return ret_val;
1831
1832 /* Getting bits 15:9, which represent the combination of
1833 * coarse and fine gain values. The result is a number
1834 * that can be put into the lookup table to obtain the
1835 * approximate cable length.
1836 */
1837 cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1838 IGP02E1000_AGC_LENGTH_MASK);
1839
1840 /* Array index bound check. */
1841 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1842 (cur_agc_index == 0))
1843 return -E1000_ERR_PHY;
1844
1845 /* Remove min & max AGC values from calculation. */
1846 if (e1000_igp_2_cable_length_table[min_agc_index] >
1847 e1000_igp_2_cable_length_table[cur_agc_index])
1848 min_agc_index = cur_agc_index;
1849 if (e1000_igp_2_cable_length_table[max_agc_index] <
1850 e1000_igp_2_cable_length_table[cur_agc_index])
1851 max_agc_index = cur_agc_index;
1852
1853 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1854 }
1855
1856 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1857 e1000_igp_2_cable_length_table[max_agc_index]);
1858 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1859
1860 /* Calculate cable length with the error range of +/- 10 meters. */
1861 phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1862 (agc_value - IGP02E1000_AGC_RANGE) : 0);
1863 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1864
1865 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1866
1867 return 0;
1868}
1869
1870/**
1871 * e1000e_get_phy_info_m88 - Retrieve PHY information
1872 * @hw: pointer to the HW structure
1873 *
1874 * Valid for only copper links. Read the PHY status register (sticky read)
1875 * to verify that link is up. Read the PHY special control register to
1876 * determine the polarity and 10base-T extended distance. Read the PHY
1877 * special status register to determine MDI/MDIx and current speed. If
1878 * speed is 1000, then determine cable length, local and remote receiver.
1879 **/
1880s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
1881{
1882 struct e1000_phy_info *phy = &hw->phy;
1883 s32 ret_val;
1884 u16 phy_data;
1885 bool link;
1886
1887 if (phy->media_type != e1000_media_type_copper) {
1888 e_dbg("Phy info is only valid for copper media\n");
1889 return -E1000_ERR_CONFIG;
1890 }
1891
1892 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1893 if (ret_val)
1894 return ret_val;
1895
1896 if (!link) {
1897 e_dbg("Phy info is only valid if link is up\n");
1898 return -E1000_ERR_CONFIG;
1899 }
1900
1901 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1902 if (ret_val)
1903 return ret_val;
1904
1905 phy->polarity_correction = !!(phy_data &
1906 M88E1000_PSCR_POLARITY_REVERSAL);
1907
1908 ret_val = e1000_check_polarity_m88(hw);
1909 if (ret_val)
1910 return ret_val;
1911
1912 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1913 if (ret_val)
1914 return ret_val;
1915
1916 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
1917
1918 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1919 ret_val = hw->phy.ops.get_cable_length(hw);
1920 if (ret_val)
1921 return ret_val;
1922
1923 ret_val = e1e_rphy(hw, MII_STAT1000, &phy_data);
1924 if (ret_val)
1925 return ret_val;
1926
1927 phy->local_rx = (phy_data & LPA_1000LOCALRXOK)
1928 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1929
1930 phy->remote_rx = (phy_data & LPA_1000REMRXOK)
1931 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1932 } else {
1933 /* Set values to "undefined" */
1934 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1935 phy->local_rx = e1000_1000t_rx_status_undefined;
1936 phy->remote_rx = e1000_1000t_rx_status_undefined;
1937 }
1938
1939 return ret_val;
1940}
1941
1942/**
1943 * e1000e_get_phy_info_igp - Retrieve igp PHY information
1944 * @hw: pointer to the HW structure
1945 *
1946 * Read PHY status to determine if link is up. If link is up, then
1947 * set/determine 10base-T extended distance and polarity correction. Read
1948 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1949 * determine on the cable length, local and remote receiver.
1950 **/
1951s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
1952{
1953 struct e1000_phy_info *phy = &hw->phy;
1954 s32 ret_val;
1955 u16 data;
1956 bool link;
1957
1958 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1959 if (ret_val)
1960 return ret_val;
1961
1962 if (!link) {
1963 e_dbg("Phy info is only valid if link is up\n");
1964 return -E1000_ERR_CONFIG;
1965 }
1966
1967 phy->polarity_correction = true;
1968
1969 ret_val = e1000_check_polarity_igp(hw);
1970 if (ret_val)
1971 return ret_val;
1972
1973 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1974 if (ret_val)
1975 return ret_val;
1976
1977 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
1978
1979 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1980 IGP01E1000_PSSR_SPEED_1000MBPS) {
1981 ret_val = phy->ops.get_cable_length(hw);
1982 if (ret_val)
1983 return ret_val;
1984
1985 ret_val = e1e_rphy(hw, MII_STAT1000, &data);
1986 if (ret_val)
1987 return ret_val;
1988
1989 phy->local_rx = (data & LPA_1000LOCALRXOK)
1990 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1991
1992 phy->remote_rx = (data & LPA_1000REMRXOK)
1993 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1994 } else {
1995 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1996 phy->local_rx = e1000_1000t_rx_status_undefined;
1997 phy->remote_rx = e1000_1000t_rx_status_undefined;
1998 }
1999
2000 return ret_val;
2001}
2002
2003/**
2004 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2005 * @hw: pointer to the HW structure
2006 *
2007 * Populates "phy" structure with various feature states.
2008 **/
2009s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2010{
2011 struct e1000_phy_info *phy = &hw->phy;
2012 s32 ret_val;
2013 u16 data;
2014 bool link;
2015
2016 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2017 if (ret_val)
2018 return ret_val;
2019
2020 if (!link) {
2021 e_dbg("Phy info is only valid if link is up\n");
2022 return -E1000_ERR_CONFIG;
2023 }
2024
2025 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2026 if (ret_val)
2027 return ret_val;
2028 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2029
2030 if (phy->polarity_correction) {
2031 ret_val = e1000_check_polarity_ife(hw);
2032 if (ret_val)
2033 return ret_val;
2034 } else {
2035 /* Polarity is forced */
2036 phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY)
2037 ? e1000_rev_polarity_reversed
2038 : e1000_rev_polarity_normal);
2039 }
2040
2041 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
2042 if (ret_val)
2043 return ret_val;
2044
2045 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2046
2047 /* The following parameters are undefined for 10/100 operation. */
2048 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2049 phy->local_rx = e1000_1000t_rx_status_undefined;
2050 phy->remote_rx = e1000_1000t_rx_status_undefined;
2051
2052 return 0;
2053}
2054
2055/**
2056 * e1000e_phy_sw_reset - PHY software reset
2057 * @hw: pointer to the HW structure
2058 *
2059 * Does a software reset of the PHY by reading the PHY control register and
2060 * setting/write the control register reset bit to the PHY.
2061 **/
2062s32 e1000e_phy_sw_reset(struct e1000_hw *hw)
2063{
2064 s32 ret_val;
2065 u16 phy_ctrl;
2066
2067 ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl);
2068 if (ret_val)
2069 return ret_val;
2070
2071 phy_ctrl |= BMCR_RESET;
2072 ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl);
2073 if (ret_val)
2074 return ret_val;
2075
2076 udelay(1);
2077
2078 return ret_val;
2079}
2080
2081/**
2082 * e1000e_phy_hw_reset_generic - PHY hardware reset
2083 * @hw: pointer to the HW structure
2084 *
2085 * Verify the reset block is not blocking us from resetting. Acquire
2086 * semaphore (if necessary) and read/set/write the device control reset
2087 * bit in the PHY. Wait the appropriate delay time for the device to
2088 * reset and release the semaphore (if necessary).
2089 **/
2090s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
2091{
2092 struct e1000_phy_info *phy = &hw->phy;
2093 s32 ret_val;
2094 u32 ctrl;
2095
2096 if (phy->ops.check_reset_block) {
2097 ret_val = phy->ops.check_reset_block(hw);
2098 if (ret_val)
2099 return 0;
2100 }
2101
2102 ret_val = phy->ops.acquire(hw);
2103 if (ret_val)
2104 return ret_val;
2105
2106 ctrl = er32(CTRL);
2107 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
2108 e1e_flush();
2109
2110 udelay(phy->reset_delay_us);
2111
2112 ew32(CTRL, ctrl);
2113 e1e_flush();
2114
2115 usleep_range(150, 300);
2116
2117 phy->ops.release(hw);
2118
2119 return phy->ops.get_cfg_done(hw);
2120}
2121
2122/**
2123 * e1000e_get_cfg_done_generic - Generic configuration done
2124 * @hw: pointer to the HW structure
2125 *
2126 * Generic function to wait 10 milli-seconds for configuration to complete
2127 * and return success.
2128 **/
2129s32 e1000e_get_cfg_done_generic(struct e1000_hw __always_unused *hw)
2130{
2131 mdelay(10);
2132
2133 return 0;
2134}
2135
2136/**
2137 * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY
2138 * @hw: pointer to the HW structure
2139 *
2140 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2141 **/
2142s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw)
2143{
2144 e_dbg("Running IGP 3 PHY init script\n");
2145
2146 /* PHY init IGP 3 */
2147 /* Enable rise/fall, 10-mode work in class-A */
2148 e1e_wphy(hw, 0x2F5B, 0x9018);
2149 /* Remove all caps from Replica path filter */
2150 e1e_wphy(hw, 0x2F52, 0x0000);
2151 /* Bias trimming for ADC, AFE and Driver (Default) */
2152 e1e_wphy(hw, 0x2FB1, 0x8B24);
2153 /* Increase Hybrid poly bias */
2154 e1e_wphy(hw, 0x2FB2, 0xF8F0);
2155 /* Add 4% to Tx amplitude in Gig mode */
2156 e1e_wphy(hw, 0x2010, 0x10B0);
2157 /* Disable trimming (TTT) */
2158 e1e_wphy(hw, 0x2011, 0x0000);
2159 /* Poly DC correction to 94.6% + 2% for all channels */
2160 e1e_wphy(hw, 0x20DD, 0x249A);
2161 /* ABS DC correction to 95.9% */
2162 e1e_wphy(hw, 0x20DE, 0x00D3);
2163 /* BG temp curve trim */
2164 e1e_wphy(hw, 0x28B4, 0x04CE);
2165 /* Increasing ADC OPAMP stage 1 currents to max */
2166 e1e_wphy(hw, 0x2F70, 0x29E4);
2167 /* Force 1000 ( required for enabling PHY regs configuration) */
2168 e1e_wphy(hw, 0x0000, 0x0140);
2169 /* Set upd_freq to 6 */
2170 e1e_wphy(hw, 0x1F30, 0x1606);
2171 /* Disable NPDFE */
2172 e1e_wphy(hw, 0x1F31, 0xB814);
2173 /* Disable adaptive fixed FFE (Default) */
2174 e1e_wphy(hw, 0x1F35, 0x002A);
2175 /* Enable FFE hysteresis */
2176 e1e_wphy(hw, 0x1F3E, 0x0067);
2177 /* Fixed FFE for short cable lengths */
2178 e1e_wphy(hw, 0x1F54, 0x0065);
2179 /* Fixed FFE for medium cable lengths */
2180 e1e_wphy(hw, 0x1F55, 0x002A);
2181 /* Fixed FFE for long cable lengths */
2182 e1e_wphy(hw, 0x1F56, 0x002A);
2183 /* Enable Adaptive Clip Threshold */
2184 e1e_wphy(hw, 0x1F72, 0x3FB0);
2185 /* AHT reset limit to 1 */
2186 e1e_wphy(hw, 0x1F76, 0xC0FF);
2187 /* Set AHT master delay to 127 msec */
2188 e1e_wphy(hw, 0x1F77, 0x1DEC);
2189 /* Set scan bits for AHT */
2190 e1e_wphy(hw, 0x1F78, 0xF9EF);
2191 /* Set AHT Preset bits */
2192 e1e_wphy(hw, 0x1F79, 0x0210);
2193 /* Change integ_factor of channel A to 3 */
2194 e1e_wphy(hw, 0x1895, 0x0003);
2195 /* Change prop_factor of channels BCD to 8 */
2196 e1e_wphy(hw, 0x1796, 0x0008);
2197 /* Change cg_icount + enable integbp for channels BCD */
2198 e1e_wphy(hw, 0x1798, 0xD008);
2199 /* Change cg_icount + enable integbp + change prop_factor_master
2200 * to 8 for channel A
2201 */
2202 e1e_wphy(hw, 0x1898, 0xD918);
2203 /* Disable AHT in Slave mode on channel A */
2204 e1e_wphy(hw, 0x187A, 0x0800);
2205 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2206 * Enable SPD+B2B
2207 */
2208 e1e_wphy(hw, 0x0019, 0x008D);
2209 /* Enable restart AN on an1000_dis change */
2210 e1e_wphy(hw, 0x001B, 0x2080);
2211 /* Enable wh_fifo read clock in 10/100 modes */
2212 e1e_wphy(hw, 0x0014, 0x0045);
2213 /* Restart AN, Speed selection is 1000 */
2214 e1e_wphy(hw, 0x0000, 0x1340);
2215
2216 return 0;
2217}
2218
2219/**
2220 * e1000e_get_phy_type_from_id - Get PHY type from id
2221 * @phy_id: phy_id read from the phy
2222 *
2223 * Returns the phy type from the id.
2224 **/
2225enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
2226{
2227 enum e1000_phy_type phy_type = e1000_phy_unknown;
2228
2229 switch (phy_id) {
2230 case M88E1000_I_PHY_ID:
2231 case M88E1000_E_PHY_ID:
2232 case M88E1111_I_PHY_ID:
2233 case M88E1011_I_PHY_ID:
2234 phy_type = e1000_phy_m88;
2235 break;
2236 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2237 phy_type = e1000_phy_igp_2;
2238 break;
2239 case GG82563_E_PHY_ID:
2240 phy_type = e1000_phy_gg82563;
2241 break;
2242 case IGP03E1000_E_PHY_ID:
2243 phy_type = e1000_phy_igp_3;
2244 break;
2245 case IFE_E_PHY_ID:
2246 case IFE_PLUS_E_PHY_ID:
2247 case IFE_C_E_PHY_ID:
2248 phy_type = e1000_phy_ife;
2249 break;
2250 case BME1000_E_PHY_ID:
2251 case BME1000_E_PHY_ID_R2:
2252 phy_type = e1000_phy_bm;
2253 break;
2254 case I82578_E_PHY_ID:
2255 phy_type = e1000_phy_82578;
2256 break;
2257 case I82577_E_PHY_ID:
2258 phy_type = e1000_phy_82577;
2259 break;
2260 case I82579_E_PHY_ID:
2261 phy_type = e1000_phy_82579;
2262 break;
2263 case I217_E_PHY_ID:
2264 phy_type = e1000_phy_i217;
2265 break;
2266 default:
2267 phy_type = e1000_phy_unknown;
2268 break;
2269 }
2270 return phy_type;
2271}
2272
2273/**
2274 * e1000e_determine_phy_address - Determines PHY address.
2275 * @hw: pointer to the HW structure
2276 *
2277 * This uses a trial and error method to loop through possible PHY
2278 * addresses. It tests each by reading the PHY ID registers and
2279 * checking for a match.
2280 **/
2281s32 e1000e_determine_phy_address(struct e1000_hw *hw)
2282{
2283 u32 phy_addr = 0;
2284 u32 i;
2285 enum e1000_phy_type phy_type = e1000_phy_unknown;
2286
2287 hw->phy.id = phy_type;
2288
2289 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2290 hw->phy.addr = phy_addr;
2291 i = 0;
2292
2293 do {
2294 e1000e_get_phy_id(hw);
2295 phy_type = e1000e_get_phy_type_from_id(hw->phy.id);
2296
2297 /* If phy_type is valid, break - we found our
2298 * PHY address
2299 */
2300 if (phy_type != e1000_phy_unknown)
2301 return 0;
2302
2303 usleep_range(1000, 2000);
2304 i++;
2305 } while (i < 10);
2306 }
2307
2308 return -E1000_ERR_PHY_TYPE;
2309}
2310
2311/**
2312 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
2313 * @page: page to access
2314 * @reg: register to check
2315 *
2316 * Returns the phy address for the page requested.
2317 **/
2318static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
2319{
2320 u32 phy_addr = 2;
2321
2322 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
2323 phy_addr = 1;
2324
2325 return phy_addr;
2326}
2327
2328/**
2329 * e1000e_write_phy_reg_bm - Write BM PHY register
2330 * @hw: pointer to the HW structure
2331 * @offset: register offset to write to
2332 * @data: data to write at register offset
2333 *
2334 * Acquires semaphore, if necessary, then writes the data to PHY register
2335 * at the offset. Release any acquired semaphores before exiting.
2336 **/
2337s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
2338{
2339 s32 ret_val;
2340 u32 page = offset >> IGP_PAGE_SHIFT;
2341
2342 ret_val = hw->phy.ops.acquire(hw);
2343 if (ret_val)
2344 return ret_val;
2345
2346 /* Page 800 works differently than the rest so it has its own func */
2347 if (page == BM_WUC_PAGE) {
2348 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2349 false, false);
2350 goto release;
2351 }
2352
2353 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2354
2355 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2356 u32 page_shift, page_select;
2357
2358 /* Page select is register 31 for phy address 1 and 22 for
2359 * phy address 2 and 3. Page select is shifted only for
2360 * phy address 1.
2361 */
2362 if (hw->phy.addr == 1) {
2363 page_shift = IGP_PAGE_SHIFT;
2364 page_select = IGP01E1000_PHY_PAGE_SELECT;
2365 } else {
2366 page_shift = 0;
2367 page_select = BM_PHY_PAGE_SELECT;
2368 }
2369
2370 /* Page is shifted left, PHY expects (page x 32) */
2371 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2372 (page << page_shift));
2373 if (ret_val)
2374 goto release;
2375 }
2376
2377 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2378 data);
2379
2380release:
2381 hw->phy.ops.release(hw);
2382 return ret_val;
2383}
2384
2385/**
2386 * e1000e_read_phy_reg_bm - Read BM PHY register
2387 * @hw: pointer to the HW structure
2388 * @offset: register offset to be read
2389 * @data: pointer to the read data
2390 *
2391 * Acquires semaphore, if necessary, then reads the PHY register at offset
2392 * and storing the retrieved information in data. Release any acquired
2393 * semaphores before exiting.
2394 **/
2395s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
2396{
2397 s32 ret_val;
2398 u32 page = offset >> IGP_PAGE_SHIFT;
2399
2400 ret_val = hw->phy.ops.acquire(hw);
2401 if (ret_val)
2402 return ret_val;
2403
2404 /* Page 800 works differently than the rest so it has its own func */
2405 if (page == BM_WUC_PAGE) {
2406 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2407 true, false);
2408 goto release;
2409 }
2410
2411 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2412
2413 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2414 u32 page_shift, page_select;
2415
2416 /* Page select is register 31 for phy address 1 and 22 for
2417 * phy address 2 and 3. Page select is shifted only for
2418 * phy address 1.
2419 */
2420 if (hw->phy.addr == 1) {
2421 page_shift = IGP_PAGE_SHIFT;
2422 page_select = IGP01E1000_PHY_PAGE_SELECT;
2423 } else {
2424 page_shift = 0;
2425 page_select = BM_PHY_PAGE_SELECT;
2426 }
2427
2428 /* Page is shifted left, PHY expects (page x 32) */
2429 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2430 (page << page_shift));
2431 if (ret_val)
2432 goto release;
2433 }
2434
2435 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2436 data);
2437release:
2438 hw->phy.ops.release(hw);
2439 return ret_val;
2440}
2441
2442/**
2443 * e1000e_read_phy_reg_bm2 - Read BM PHY register
2444 * @hw: pointer to the HW structure
2445 * @offset: register offset to be read
2446 * @data: pointer to the read data
2447 *
2448 * Acquires semaphore, if necessary, then reads the PHY register at offset
2449 * and storing the retrieved information in data. Release any acquired
2450 * semaphores before exiting.
2451 **/
2452s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
2453{
2454 s32 ret_val;
2455 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2456
2457 ret_val = hw->phy.ops.acquire(hw);
2458 if (ret_val)
2459 return ret_val;
2460
2461 /* Page 800 works differently than the rest so it has its own func */
2462 if (page == BM_WUC_PAGE) {
2463 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2464 true, false);
2465 goto release;
2466 }
2467
2468 hw->phy.addr = 1;
2469
2470 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2471 /* Page is shifted left, PHY expects (page x 32) */
2472 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2473 page);
2474
2475 if (ret_val)
2476 goto release;
2477 }
2478
2479 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2480 data);
2481release:
2482 hw->phy.ops.release(hw);
2483 return ret_val;
2484}
2485
2486/**
2487 * e1000e_write_phy_reg_bm2 - Write BM PHY register
2488 * @hw: pointer to the HW structure
2489 * @offset: register offset to write to
2490 * @data: data to write at register offset
2491 *
2492 * Acquires semaphore, if necessary, then writes the data to PHY register
2493 * at the offset. Release any acquired semaphores before exiting.
2494 **/
2495s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
2496{
2497 s32 ret_val;
2498 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2499
2500 ret_val = hw->phy.ops.acquire(hw);
2501 if (ret_val)
2502 return ret_val;
2503
2504 /* Page 800 works differently than the rest so it has its own func */
2505 if (page == BM_WUC_PAGE) {
2506 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2507 false, false);
2508 goto release;
2509 }
2510
2511 hw->phy.addr = 1;
2512
2513 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2514 /* Page is shifted left, PHY expects (page x 32) */
2515 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2516 page);
2517
2518 if (ret_val)
2519 goto release;
2520 }
2521
2522 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2523 data);
2524
2525release:
2526 hw->phy.ops.release(hw);
2527 return ret_val;
2528}
2529
2530/**
2531 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
2532 * @hw: pointer to the HW structure
2533 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
2534 *
2535 * Assumes semaphore already acquired and phy_reg points to a valid memory
2536 * address to store contents of the BM_WUC_ENABLE_REG register.
2537 **/
2538s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2539{
2540 s32 ret_val;
2541 u16 temp;
2542
2543 /* All page select, port ctrl and wakeup registers use phy address 1 */
2544 hw->phy.addr = 1;
2545
2546 /* Select Port Control Registers page */
2547 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2548 if (ret_val) {
2549 e_dbg("Could not set Port Control page\n");
2550 return ret_val;
2551 }
2552
2553 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2554 if (ret_val) {
2555 e_dbg("Could not read PHY register %d.%d\n",
2556 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2557 return ret_val;
2558 }
2559
2560 /* Enable both PHY wakeup mode and Wakeup register page writes.
2561 * Prevent a power state change by disabling ME and Host PHY wakeup.
2562 */
2563 temp = *phy_reg;
2564 temp |= BM_WUC_ENABLE_BIT;
2565 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
2566
2567 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
2568 if (ret_val) {
2569 e_dbg("Could not write PHY register %d.%d\n",
2570 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2571 return ret_val;
2572 }
2573
2574 /* Select Host Wakeup Registers page - caller now able to write
2575 * registers on the Wakeup registers page
2576 */
2577 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
2578}
2579
2580/**
2581 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
2582 * @hw: pointer to the HW structure
2583 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
2584 *
2585 * Restore BM_WUC_ENABLE_REG to its original value.
2586 *
2587 * Assumes semaphore already acquired and *phy_reg is the contents of the
2588 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
2589 * caller.
2590 **/
2591s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2592{
2593 s32 ret_val;
2594
2595 /* Select Port Control Registers page */
2596 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2597 if (ret_val) {
2598 e_dbg("Could not set Port Control page\n");
2599 return ret_val;
2600 }
2601
2602 /* Restore 769.17 to its original value */
2603 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
2604 if (ret_val)
2605 e_dbg("Could not restore PHY register %d.%d\n",
2606 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2607
2608 return ret_val;
2609}
2610
2611/**
2612 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
2613 * @hw: pointer to the HW structure
2614 * @offset: register offset to be read or written
2615 * @data: pointer to the data to read or write
2616 * @read: determines if operation is read or write
2617 * @page_set: BM_WUC_PAGE already set and access enabled
2618 *
2619 * Read the PHY register at offset and store the retrieved information in
2620 * data, or write data to PHY register at offset. Note the procedure to
2621 * access the PHY wakeup registers is different than reading the other PHY
2622 * registers. It works as such:
2623 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1
2624 * 2) Set page to 800 for host (801 if we were manageability)
2625 * 3) Write the address using the address opcode (0x11)
2626 * 4) Read or write the data using the data opcode (0x12)
2627 * 5) Restore 769.17.2 to its original value
2628 *
2629 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
2630 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
2631 *
2632 * Assumes semaphore is already acquired. When page_set==true, assumes
2633 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
2634 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
2635 **/
2636static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2637 u16 *data, bool read, bool page_set)
2638{
2639 s32 ret_val;
2640 u16 reg = BM_PHY_REG_NUM(offset);
2641 u16 page = BM_PHY_REG_PAGE(offset);
2642 u16 phy_reg = 0;
2643
2644 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
2645 if ((hw->mac.type == e1000_pchlan) &&
2646 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
2647 e_dbg("Attempting to access page %d while gig enabled.\n",
2648 page);
2649
2650 if (!page_set) {
2651 /* Enable access to PHY wakeup registers */
2652 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2653 if (ret_val) {
2654 e_dbg("Could not enable PHY wakeup reg access\n");
2655 return ret_val;
2656 }
2657 }
2658
2659 e_dbg("Accessing PHY page %d reg 0x%x\n", page, reg);
2660
2661 /* Write the Wakeup register page offset value using opcode 0x11 */
2662 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
2663 if (ret_val) {
2664 e_dbg("Could not write address opcode to page %d\n", page);
2665 return ret_val;
2666 }
2667
2668 if (read) {
2669 /* Read the Wakeup register page value using opcode 0x12 */
2670 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2671 data);
2672 } else {
2673 /* Write the Wakeup register page value using opcode 0x12 */
2674 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2675 *data);
2676 }
2677
2678 if (ret_val) {
2679 e_dbg("Could not access PHY reg %d.%d\n", page, reg);
2680 return ret_val;
2681 }
2682
2683 if (!page_set)
2684 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2685
2686 return ret_val;
2687}
2688
2689/**
2690 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
2691 * @hw: pointer to the HW structure
2692 *
2693 * In the case of a PHY power down to save power, or to turn off link during a
2694 * driver unload, or wake on lan is not enabled, restore the link to previous
2695 * settings.
2696 **/
2697void e1000_power_up_phy_copper(struct e1000_hw *hw)
2698{
2699 u16 mii_reg = 0;
2700 int ret;
2701
2702 /* The PHY will retain its settings across a power down/up cycle */
2703 ret = e1e_rphy(hw, MII_BMCR, &mii_reg);
2704 if (ret) {
2705 e_dbg("Error reading PHY register\n");
2706 return;
2707 }
2708 mii_reg &= ~BMCR_PDOWN;
2709 e1e_wphy(hw, MII_BMCR, mii_reg);
2710}
2711
2712/**
2713 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
2714 * @hw: pointer to the HW structure
2715 *
2716 * In the case of a PHY power down to save power, or to turn off link during a
2717 * driver unload, or wake on lan is not enabled, restore the link to previous
2718 * settings.
2719 **/
2720void e1000_power_down_phy_copper(struct e1000_hw *hw)
2721{
2722 u16 mii_reg = 0;
2723 int ret;
2724
2725 /* The PHY will retain its settings across a power down/up cycle */
2726 ret = e1e_rphy(hw, MII_BMCR, &mii_reg);
2727 if (ret) {
2728 e_dbg("Error reading PHY register\n");
2729 return;
2730 }
2731 mii_reg |= BMCR_PDOWN;
2732 e1e_wphy(hw, MII_BMCR, mii_reg);
2733 usleep_range(1000, 2000);
2734}
2735
2736/**
2737 * __e1000_read_phy_reg_hv - Read HV PHY register
2738 * @hw: pointer to the HW structure
2739 * @offset: register offset to be read
2740 * @data: pointer to the read data
2741 * @locked: semaphore has already been acquired or not
2742 * @page_set: BM_WUC_PAGE already set and access enabled
2743 *
2744 * Acquires semaphore, if necessary, then reads the PHY register at offset
2745 * and stores the retrieved information in data. Release any acquired
2746 * semaphore before exiting.
2747 **/
2748static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
2749 bool locked, bool page_set)
2750{
2751 s32 ret_val;
2752 u16 page = BM_PHY_REG_PAGE(offset);
2753 u16 reg = BM_PHY_REG_NUM(offset);
2754 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2755
2756 if (!locked) {
2757 ret_val = hw->phy.ops.acquire(hw);
2758 if (ret_val)
2759 return ret_val;
2760 }
2761
2762 /* Page 800 works differently than the rest so it has its own func */
2763 if (page == BM_WUC_PAGE) {
2764 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2765 true, page_set);
2766 goto out;
2767 }
2768
2769 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2770 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2771 data, true);
2772 goto out;
2773 }
2774
2775 if (!page_set) {
2776 if (page == HV_INTC_FC_PAGE_START)
2777 page = 0;
2778
2779 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2780 /* Page is shifted left, PHY expects (page x 32) */
2781 ret_val = e1000_set_page_igp(hw,
2782 (page << IGP_PAGE_SHIFT));
2783
2784 hw->phy.addr = phy_addr;
2785
2786 if (ret_val)
2787 goto out;
2788 }
2789 }
2790
2791 e_dbg("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
2792 page << IGP_PAGE_SHIFT, reg);
2793
2794 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, data);
2795out:
2796 if (!locked)
2797 hw->phy.ops.release(hw);
2798
2799 return ret_val;
2800}
2801
2802/**
2803 * e1000_read_phy_reg_hv - Read HV PHY register
2804 * @hw: pointer to the HW structure
2805 * @offset: register offset to be read
2806 * @data: pointer to the read data
2807 *
2808 * Acquires semaphore then reads the PHY register at offset and stores
2809 * the retrieved information in data. Release the acquired semaphore
2810 * before exiting.
2811 **/
2812s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2813{
2814 return __e1000_read_phy_reg_hv(hw, offset, data, false, false);
2815}
2816
2817/**
2818 * e1000_read_phy_reg_hv_locked - Read HV PHY register
2819 * @hw: pointer to the HW structure
2820 * @offset: register offset to be read
2821 * @data: pointer to the read data
2822 *
2823 * Reads the PHY register at offset and stores the retrieved information
2824 * in data. Assumes semaphore already acquired.
2825 **/
2826s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
2827{
2828 return __e1000_read_phy_reg_hv(hw, offset, data, true, false);
2829}
2830
2831/**
2832 * e1000_read_phy_reg_page_hv - Read HV PHY register
2833 * @hw: pointer to the HW structure
2834 * @offset: register offset to write to
2835 * @data: data to write at register offset
2836 *
2837 * Reads the PHY register at offset and stores the retrieved information
2838 * in data. Assumes semaphore already acquired and page already set.
2839 **/
2840s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2841{
2842 return __e1000_read_phy_reg_hv(hw, offset, data, true, true);
2843}
2844
2845/**
2846 * __e1000_write_phy_reg_hv - Write HV PHY register
2847 * @hw: pointer to the HW structure
2848 * @offset: register offset to write to
2849 * @data: data to write at register offset
2850 * @locked: semaphore has already been acquired or not
2851 * @page_set: BM_WUC_PAGE already set and access enabled
2852 *
2853 * Acquires semaphore, if necessary, then writes the data to PHY register
2854 * at the offset. Release any acquired semaphores before exiting.
2855 **/
2856static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
2857 bool locked, bool page_set)
2858{
2859 s32 ret_val;
2860 u16 page = BM_PHY_REG_PAGE(offset);
2861 u16 reg = BM_PHY_REG_NUM(offset);
2862 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2863
2864 if (!locked) {
2865 ret_val = hw->phy.ops.acquire(hw);
2866 if (ret_val)
2867 return ret_val;
2868 }
2869
2870 /* Page 800 works differently than the rest so it has its own func */
2871 if (page == BM_WUC_PAGE) {
2872 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2873 false, page_set);
2874 goto out;
2875 }
2876
2877 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2878 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2879 &data, false);
2880 goto out;
2881 }
2882
2883 if (!page_set) {
2884 if (page == HV_INTC_FC_PAGE_START)
2885 page = 0;
2886
2887 /* Workaround MDIO accesses being disabled after entering IEEE
2888 * Power Down (when bit 11 of the PHY Control register is set)
2889 */
2890 if ((hw->phy.type == e1000_phy_82578) &&
2891 (hw->phy.revision >= 1) &&
2892 (hw->phy.addr == 2) &&
2893 !(MAX_PHY_REG_ADDRESS & reg) && (data & BIT(11))) {
2894 u16 data2 = 0x7EFF;
2895
2896 ret_val = e1000_access_phy_debug_regs_hv(hw,
2897 BIT(6) | 0x3,
2898 &data2, false);
2899 if (ret_val)
2900 goto out;
2901 }
2902
2903 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2904 /* Page is shifted left, PHY expects (page x 32) */
2905 ret_val = e1000_set_page_igp(hw,
2906 (page << IGP_PAGE_SHIFT));
2907
2908 hw->phy.addr = phy_addr;
2909
2910 if (ret_val)
2911 goto out;
2912 }
2913 }
2914
2915 e_dbg("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
2916 page << IGP_PAGE_SHIFT, reg);
2917
2918 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
2919 data);
2920
2921out:
2922 if (!locked)
2923 hw->phy.ops.release(hw);
2924
2925 return ret_val;
2926}
2927
2928/**
2929 * e1000_write_phy_reg_hv - Write HV PHY register
2930 * @hw: pointer to the HW structure
2931 * @offset: register offset to write to
2932 * @data: data to write at register offset
2933 *
2934 * Acquires semaphore then writes the data to PHY register at the offset.
2935 * Release the acquired semaphores before exiting.
2936 **/
2937s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
2938{
2939 return __e1000_write_phy_reg_hv(hw, offset, data, false, false);
2940}
2941
2942/**
2943 * e1000_write_phy_reg_hv_locked - Write HV PHY register
2944 * @hw: pointer to the HW structure
2945 * @offset: register offset to write to
2946 * @data: data to write at register offset
2947 *
2948 * Writes the data to PHY register at the offset. Assumes semaphore
2949 * already acquired.
2950 **/
2951s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
2952{
2953 return __e1000_write_phy_reg_hv(hw, offset, data, true, false);
2954}
2955
2956/**
2957 * e1000_write_phy_reg_page_hv - Write HV PHY register
2958 * @hw: pointer to the HW structure
2959 * @offset: register offset to write to
2960 * @data: data to write at register offset
2961 *
2962 * Writes the data to PHY register at the offset. Assumes semaphore
2963 * already acquired and page already set.
2964 **/
2965s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
2966{
2967 return __e1000_write_phy_reg_hv(hw, offset, data, true, true);
2968}
2969
2970/**
2971 * e1000_get_phy_addr_for_hv_page - Get PHY address based on page
2972 * @page: page to be accessed
2973 **/
2974static u32 e1000_get_phy_addr_for_hv_page(u32 page)
2975{
2976 u32 phy_addr = 2;
2977
2978 if (page >= HV_INTC_FC_PAGE_START)
2979 phy_addr = 1;
2980
2981 return phy_addr;
2982}
2983
2984/**
2985 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
2986 * @hw: pointer to the HW structure
2987 * @offset: register offset to be read or written
2988 * @data: pointer to the data to be read or written
2989 * @read: determines if operation is read or write
2990 *
2991 * Reads the PHY register at offset and stores the retrieved information
2992 * in data. Assumes semaphore already acquired. Note that the procedure
2993 * to access these regs uses the address port and data port to read/write.
2994 * These accesses done with PHY address 2 and without using pages.
2995 **/
2996static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
2997 u16 *data, bool read)
2998{
2999 s32 ret_val;
3000 u32 addr_reg;
3001 u32 data_reg;
3002
3003 /* This takes care of the difference with desktop vs mobile phy */
3004 addr_reg = ((hw->phy.type == e1000_phy_82578) ?
3005 I82578_ADDR_REG : I82577_ADDR_REG);
3006 data_reg = addr_reg + 1;
3007
3008 /* All operations in this function are phy address 2 */
3009 hw->phy.addr = 2;
3010
3011 /* masking with 0x3F to remove the page from offset */
3012 ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3013 if (ret_val) {
3014 e_dbg("Could not write the Address Offset port register\n");
3015 return ret_val;
3016 }
3017
3018 /* Read or write the data value next */
3019 if (read)
3020 ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data);
3021 else
3022 ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data);
3023
3024 if (ret_val)
3025 e_dbg("Could not access the Data port register\n");
3026
3027 return ret_val;
3028}
3029
3030/**
3031 * e1000_link_stall_workaround_hv - Si workaround
3032 * @hw: pointer to the HW structure
3033 *
3034 * This function works around a Si bug where the link partner can get
3035 * a link up indication before the PHY does. If small packets are sent
3036 * by the link partner they can be placed in the packet buffer without
3037 * being properly accounted for by the PHY and will stall preventing
3038 * further packets from being received. The workaround is to clear the
3039 * packet buffer after the PHY detects link up.
3040 **/
3041s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3042{
3043 s32 ret_val = 0;
3044 u16 data;
3045
3046 if (hw->phy.type != e1000_phy_82578)
3047 return 0;
3048
3049 /* Do not apply workaround if in PHY loopback bit 14 set */
3050 ret_val = e1e_rphy(hw, MII_BMCR, &data);
3051 if (ret_val) {
3052 e_dbg("Error reading PHY register\n");
3053 return ret_val;
3054 }
3055 if (data & BMCR_LOOPBACK)
3056 return 0;
3057
3058 /* check if link is up and at 1Gbps */
3059 ret_val = e1e_rphy(hw, BM_CS_STATUS, &data);
3060 if (ret_val)
3061 return ret_val;
3062
3063 data &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3064 BM_CS_STATUS_SPEED_MASK);
3065
3066 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3067 BM_CS_STATUS_SPEED_1000))
3068 return 0;
3069
3070 msleep(200);
3071
3072 /* flush the packets in the fifo buffer */
3073 ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL,
3074 (HV_MUX_DATA_CTRL_GEN_TO_MAC |
3075 HV_MUX_DATA_CTRL_FORCE_SPEED));
3076 if (ret_val)
3077 return ret_val;
3078
3079 return e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC);
3080}
3081
3082/**
3083 * e1000_check_polarity_82577 - Checks the polarity.
3084 * @hw: pointer to the HW structure
3085 *
3086 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3087 *
3088 * Polarity is determined based on the PHY specific status register.
3089 **/
3090s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3091{
3092 struct e1000_phy_info *phy = &hw->phy;
3093 s32 ret_val;
3094 u16 data;
3095
3096 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3097
3098 if (!ret_val)
3099 phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY)
3100 ? e1000_rev_polarity_reversed
3101 : e1000_rev_polarity_normal);
3102
3103 return ret_val;
3104}
3105
3106/**
3107 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3108 * @hw: pointer to the HW structure
3109 *
3110 * Calls the PHY setup function to force speed and duplex.
3111 **/
3112s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3113{
3114 struct e1000_phy_info *phy = &hw->phy;
3115 s32 ret_val;
3116 u16 phy_data;
3117 bool link;
3118
3119 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
3120 if (ret_val)
3121 return ret_val;
3122
3123 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
3124
3125 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
3126 if (ret_val)
3127 return ret_val;
3128
3129 udelay(1);
3130
3131 if (phy->autoneg_wait_to_complete) {
3132 e_dbg("Waiting for forced speed/duplex link on 82577 phy\n");
3133
3134 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3135 100000, &link);
3136 if (ret_val)
3137 return ret_val;
3138
3139 if (!link)
3140 e_dbg("Link taking longer than expected.\n");
3141
3142 /* Try once more */
3143 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3144 100000, &link);
3145 }
3146
3147 return ret_val;
3148}
3149
3150/**
3151 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3152 * @hw: pointer to the HW structure
3153 *
3154 * Read PHY status to determine if link is up. If link is up, then
3155 * set/determine 10base-T extended distance and polarity correction. Read
3156 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3157 * determine on the cable length, local and remote receiver.
3158 **/
3159s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3160{
3161 struct e1000_phy_info *phy = &hw->phy;
3162 s32 ret_val;
3163 u16 data;
3164 bool link;
3165
3166 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3167 if (ret_val)
3168 return ret_val;
3169
3170 if (!link) {
3171 e_dbg("Phy info is only valid if link is up\n");
3172 return -E1000_ERR_CONFIG;
3173 }
3174
3175 phy->polarity_correction = true;
3176
3177 ret_val = e1000_check_polarity_82577(hw);
3178 if (ret_val)
3179 return ret_val;
3180
3181 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3182 if (ret_val)
3183 return ret_val;
3184
3185 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
3186
3187 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3188 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3189 ret_val = hw->phy.ops.get_cable_length(hw);
3190 if (ret_val)
3191 return ret_val;
3192
3193 ret_val = e1e_rphy(hw, MII_STAT1000, &data);
3194 if (ret_val)
3195 return ret_val;
3196
3197 phy->local_rx = (data & LPA_1000LOCALRXOK)
3198 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3199
3200 phy->remote_rx = (data & LPA_1000REMRXOK)
3201 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3202 } else {
3203 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3204 phy->local_rx = e1000_1000t_rx_status_undefined;
3205 phy->remote_rx = e1000_1000t_rx_status_undefined;
3206 }
3207
3208 return 0;
3209}
3210
3211/**
3212 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3213 * @hw: pointer to the HW structure
3214 *
3215 * Reads the diagnostic status register and verifies result is valid before
3216 * placing it in the phy_cable_length field.
3217 **/
3218s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3219{
3220 struct e1000_phy_info *phy = &hw->phy;
3221 s32 ret_val;
3222 u16 phy_data, length;
3223
3224 ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data);
3225 if (ret_val)
3226 return ret_val;
3227
3228 length = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
3229 I82577_DSTATUS_CABLE_LENGTH_SHIFT);
3230
3231 if (length == E1000_CABLE_LENGTH_UNDEFINED)
3232 return -E1000_ERR_PHY;
3233
3234 phy->cable_length = length;
3235
3236 return 0;
3237}