1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * This contains all required hardware related helper functions for
  4 * Trace Buffer Extension (TRBE) driver in the coresight framework.
  5 *
  6 * Copyright (C) 2020 ARM Ltd.
  7 *
  8 * Author: Anshuman Khandual <anshuman.khandual@arm.com>
  9 */
 10#include <linux/coresight.h>
 11#include <linux/device.h>
 12#include <linux/irq.h>
 13#include <linux/kernel.h>
 14#include <linux/of.h>
 15#include <linux/platform_device.h>
 16#include <linux/smp.h>
 17
 18#include "coresight-etm-perf.h"
 19
 20static inline bool is_trbe_available(void)
 21{
 22	u64 aa64dfr0 = read_sysreg_s(SYS_ID_AA64DFR0_EL1);
 23	unsigned int trbe = cpuid_feature_extract_unsigned_field(aa64dfr0,
 24								 ID_AA64DFR0_EL1_TraceBuffer_SHIFT);
 25
 26	return trbe >= 0b0001;
 27}
 28
 29static inline bool is_trbe_enabled(void)
 30{
 31	u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1);
 32
 33	return trblimitr & TRBLIMITR_ENABLE;
 34}
 35
 36#define TRBE_EC_OTHERS		0
 37#define TRBE_EC_STAGE1_ABORT	36
 38#define TRBE_EC_STAGE2_ABORT	37
 39
 40static inline int get_trbe_ec(u64 trbsr)
 41{
 42	return (trbsr >> TRBSR_EC_SHIFT) & TRBSR_EC_MASK;
 43}
 44
 45#define TRBE_BSC_NOT_STOPPED 0
 46#define TRBE_BSC_FILLED      1
 47#define TRBE_BSC_TRIGGERED   2
 48
 49static inline int get_trbe_bsc(u64 trbsr)
 50{
 51	return (trbsr >> TRBSR_BSC_SHIFT) & TRBSR_BSC_MASK;
 52}
 53
 54static inline void clr_trbe_irq(void)
 55{
 56	u64 trbsr = read_sysreg_s(SYS_TRBSR_EL1);
 57
 58	trbsr &= ~TRBSR_IRQ;
 59	write_sysreg_s(trbsr, SYS_TRBSR_EL1);
 60}
 61
 62static inline bool is_trbe_irq(u64 trbsr)
 63{
 64	return trbsr & TRBSR_IRQ;
 65}
 66
 67static inline bool is_trbe_trg(u64 trbsr)
 68{
 69	return trbsr & TRBSR_TRG;
 70}
 71
 72static inline bool is_trbe_wrap(u64 trbsr)
 73{
 74	return trbsr & TRBSR_WRAP;
 75}
 76
 77static inline bool is_trbe_abort(u64 trbsr)
 78{
 79	return trbsr & TRBSR_ABORT;
 80}
 81
 82static inline bool is_trbe_running(u64 trbsr)
 83{
 84	return !(trbsr & TRBSR_STOP);
 85}
 86
 87#define TRBE_TRIG_MODE_STOP		0
 88#define TRBE_TRIG_MODE_IRQ		1
 89#define TRBE_TRIG_MODE_IGNORE		3
 90
 91#define TRBE_FILL_MODE_FILL		0
 92#define TRBE_FILL_MODE_WRAP		1
 93#define TRBE_FILL_MODE_CIRCULAR_BUFFER	3
 94
 95static inline bool get_trbe_flag_update(u64 trbidr)
 96{
 97	return trbidr & TRBIDR_FLAG;
 98}
 99
100static inline bool is_trbe_programmable(u64 trbidr)
101{
102	return !(trbidr & TRBIDR_PROG);
103}
104
105static inline int get_trbe_address_align(u64 trbidr)
106{
107	return (trbidr >> TRBIDR_ALIGN_SHIFT) & TRBIDR_ALIGN_MASK;
108}
109
110static inline unsigned long get_trbe_write_pointer(void)
111{
112	return read_sysreg_s(SYS_TRBPTR_EL1);
113}
114
115static inline void set_trbe_write_pointer(unsigned long addr)
116{
117	WARN_ON(is_trbe_enabled());
118	write_sysreg_s(addr, SYS_TRBPTR_EL1);
119}
120
121static inline unsigned long get_trbe_limit_pointer(void)
122{
123	u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1);
124	unsigned long addr = trblimitr & (TRBLIMITR_LIMIT_MASK << TRBLIMITR_LIMIT_SHIFT);
125
126	WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
127	return addr;
128}
129
130static inline unsigned long get_trbe_base_pointer(void)
131{
132	u64 trbbaser = read_sysreg_s(SYS_TRBBASER_EL1);
133	unsigned long addr = trbbaser & (TRBBASER_BASE_MASK << TRBBASER_BASE_SHIFT);
134
135	WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
136	return addr;
137}
138
139static inline void set_trbe_base_pointer(unsigned long addr)
140{
141	WARN_ON(is_trbe_enabled());
142	WARN_ON(!IS_ALIGNED(addr, (1UL << TRBBASER_BASE_SHIFT)));
143	WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
144	write_sysreg_s(addr, SYS_TRBBASER_EL1);
145}