1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright (C) 2012 Regents of the University of California
  4 * Copyright (C) 2017 SiFive
  5 *
  6 * All RISC-V systems have a timer attached to every hart.  These timers can
  7 * either be read from the "time" and "timeh" CSRs, and can use the SBI to
  8 * setup events, or directly accessed using MMIO registers.
  9 */
 10
 11#define pr_fmt(fmt) "riscv-timer: " fmt
 12
 13#include <linux/clocksource.h>
 14#include <linux/clockchips.h>
 15#include <linux/cpu.h>
 16#include <linux/delay.h>
 17#include <linux/irq.h>
 18#include <linux/irqdomain.h>
 19#include <linux/module.h>
 20#include <linux/sched_clock.h>
 21#include <linux/io-64-nonatomic-lo-hi.h>
 22#include <linux/interrupt.h>
 23#include <linux/of_irq.h>
 24#include <clocksource/timer-riscv.h>
 25#include <asm/smp.h>
 26#include <asm/hwcap.h>
 27#include <asm/sbi.h>
 28#include <asm/timex.h>
 29
 30static DEFINE_STATIC_KEY_FALSE(riscv_sstc_available);
 31
 32static int riscv_clock_next_event(unsigned long delta,
 33		struct clock_event_device *ce)
 34{
 35	u64 next_tval = get_cycles64() + delta;
 36
 37	csr_set(CSR_IE, IE_TIE);
 38	if (static_branch_likely(&riscv_sstc_available)) {
 39#if defined(CONFIG_32BIT)
 40		csr_write(CSR_STIMECMP, next_tval & 0xFFFFFFFF);
 41		csr_write(CSR_STIMECMPH, next_tval >> 32);
 42#else
 43		csr_write(CSR_STIMECMP, next_tval);
 44#endif
 45	} else
 46		sbi_set_timer(next_tval);
 47
 48	return 0;
 49}
 50
 51static unsigned int riscv_clock_event_irq;
 52static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) = {
 53	.name			= "riscv_timer_clockevent",
 54	.features		= CLOCK_EVT_FEAT_ONESHOT,
 55	.rating			= 100,
 56	.set_next_event		= riscv_clock_next_event,
 57};
 58
 59/*
 60 * It is guaranteed that all the timers across all the harts are synchronized
 61 * within one tick of each other, so while this could technically go
 62 * backwards when hopping between CPUs, practically it won't happen.
 63 */
 64static unsigned long long riscv_clocksource_rdtime(struct clocksource *cs)
 65{
 66	return get_cycles64();
 67}
 68
 69static u64 notrace riscv_sched_clock(void)
 70{
 71	return get_cycles64();
 72}
 73
 74static struct clocksource riscv_clocksource = {
 75	.name		= "riscv_clocksource",
 76	.rating		= 300,
 77	.mask		= CLOCKSOURCE_MASK(64),
 78	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
 79	.read		= riscv_clocksource_rdtime,
 80};
 81
 82static int riscv_timer_starting_cpu(unsigned int cpu)
 83{
 84	struct clock_event_device *ce = per_cpu_ptr(&riscv_clock_event, cpu);
 85
 86	ce->cpumask = cpumask_of(cpu);
 87	ce->irq = riscv_clock_event_irq;
 88	clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff);
 89
 90	enable_percpu_irq(riscv_clock_event_irq,
 91			  irq_get_trigger_type(riscv_clock_event_irq));
 92	return 0;
 93}
 94
 95static int riscv_timer_dying_cpu(unsigned int cpu)
 96{
 97	disable_percpu_irq(riscv_clock_event_irq);
 98	return 0;
 99}
100
101void riscv_cs_get_mult_shift(u32 *mult, u32 *shift)
102{
103	*mult = riscv_clocksource.mult;
104	*shift = riscv_clocksource.shift;
105}
106EXPORT_SYMBOL_GPL(riscv_cs_get_mult_shift);
107
108/* called directly from the low-level interrupt handler */
109static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id)
110{
111	struct clock_event_device *evdev = this_cpu_ptr(&riscv_clock_event);
112
113	csr_clear(CSR_IE, IE_TIE);
114	evdev->event_handler(evdev);
115
116	return IRQ_HANDLED;
117}
118
119static int __init riscv_timer_init_dt(struct device_node *n)
120{
121	int cpuid, error;
122	unsigned long hartid;
123	struct device_node *child;
124	struct irq_domain *domain;
125
126	error = riscv_of_processor_hartid(n, &hartid);
127	if (error < 0) {
128		pr_warn("Not valid hartid for node [%pOF] error = [%lu]\n",
129			n, hartid);
130		return error;
131	}
132
133	cpuid = riscv_hartid_to_cpuid(hartid);
134	if (cpuid < 0) {
135		pr_warn("Invalid cpuid for hartid [%lu]\n", hartid);
136		return cpuid;
137	}
138
139	if (cpuid != smp_processor_id())
140		return 0;
141
142	domain = NULL;
143	child = of_get_compatible_child(n, "riscv,cpu-intc");
144	if (!child) {
145		pr_err("Failed to find INTC node [%pOF]\n", n);
146		return -ENODEV;
147	}
148	domain = irq_find_host(child);
149	of_node_put(child);
150	if (!domain) {
151		pr_err("Failed to find IRQ domain for node [%pOF]\n", n);
152		return -ENODEV;
153	}
154
155	riscv_clock_event_irq = irq_create_mapping(domain, RV_IRQ_TIMER);
156	if (!riscv_clock_event_irq) {
157		pr_err("Failed to map timer interrupt for node [%pOF]\n", n);
158		return -ENODEV;
159	}
160
161	pr_info("%s: Registering clocksource cpuid [%d] hartid [%lu]\n",
162	       __func__, cpuid, hartid);
163	error = clocksource_register_hz(&riscv_clocksource, riscv_timebase);
164	if (error) {
165		pr_err("RISCV timer register failed [%d] for cpu = [%d]\n",
166		       error, cpuid);
167		return error;
168	}
169
170	sched_clock_register(riscv_sched_clock, 64, riscv_timebase);
171
172	error = request_percpu_irq(riscv_clock_event_irq,
173				    riscv_timer_interrupt,
174				    "riscv-timer", &riscv_clock_event);
175	if (error) {
176		pr_err("registering percpu irq failed [%d]\n", error);
177		return error;
178	}
179
180	error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING,
181			 "clockevents/riscv/timer:starting",
182			 riscv_timer_starting_cpu, riscv_timer_dying_cpu);
183	if (error)
184		pr_err("cpu hp setup state failed for RISCV timer [%d]\n",
185		       error);
186
187	if (riscv_isa_extension_available(NULL, SSTC)) {
188		pr_info("Timer interrupt in S-mode is available via sstc extension\n");
189		static_branch_enable(&riscv_sstc_available);
190	}
191
192	return error;
193}
194
195TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt);