1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
   4 */
   5
   6#include <linux/err.h>
   7#include <linux/kernel.h>
   8#include <linux/module.h>
   9#include <linux/of_device.h>
  10#include <linux/clk-provider.h>
  11#include <linux/regmap.h>
  12#include <linux/reset-controller.h>
  13
  14#include <dt-bindings/clock/qcom,gcc-sm6115.h>
  15
  16#include "clk-alpha-pll.h"
  17#include "clk-branch.h"
  18#include "clk-pll.h"
  19#include "clk-rcg.h"
  20#include "clk-regmap.h"
  21#include "clk-regmap-divider.h"
  22#include "common.h"
  23#include "gdsc.h"
  24#include "reset.h"
  25
  26enum {
  27	P_BI_TCXO,
  28	P_GPLL0_OUT_AUX2,
  29	P_GPLL0_OUT_EARLY,
  30	P_GPLL10_OUT_MAIN,
  31	P_GPLL11_OUT_MAIN,
  32	P_GPLL3_OUT_EARLY,
  33	P_GPLL4_OUT_MAIN,
  34	P_GPLL6_OUT_EARLY,
  35	P_GPLL6_OUT_MAIN,
  36	P_GPLL7_OUT_MAIN,
  37	P_GPLL8_OUT_EARLY,
  38	P_GPLL8_OUT_MAIN,
  39	P_GPLL9_OUT_EARLY,
  40	P_GPLL9_OUT_MAIN,
  41	P_SLEEP_CLK,
  42};
  43
  44static struct pll_vco default_vco[] = {
  45	{ 500000000, 1000000000, 2 },
  46};
  47
  48static struct pll_vco gpll9_vco[] = {
  49	{ 500000000, 1250000000, 0 },
  50};
  51
  52static struct pll_vco gpll10_vco[] = {
  53	{ 750000000, 1500000000, 1 },
  54};
  55
  56static struct clk_alpha_pll gpll0 = {
  57	.offset = 0x0,
  58	.vco_table = default_vco,
  59	.num_vco = ARRAY_SIZE(default_vco),
  60	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
  61	.clkr = {
  62		.enable_reg = 0x79000,
  63		.enable_mask = BIT(0),
  64		.hw.init = &(struct clk_init_data){
  65			.name = "gpll0",
  66			.parent_data = &(const struct clk_parent_data){
  67				.fw_name = "bi_tcxo",
  68			},
  69			.num_parents = 1,
  70			.ops = &clk_alpha_pll_ops,
  71		},
  72	},
  73};
  74
  75static const struct clk_div_table post_div_table_gpll0_out_aux2[] = {
  76	{ 0x1, 2 },
  77	{ }
  78};
  79
  80static struct clk_alpha_pll_postdiv gpll0_out_aux2 = {
  81	.offset = 0x0,
  82	.post_div_shift = 8,
  83	.post_div_table = post_div_table_gpll0_out_aux2,
  84	.num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_aux2),
  85	.width = 4,
  86	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
  87	.clkr.hw.init = &(struct clk_init_data){
  88		.name = "gpll0_out_aux2",
  89		.parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
  90		.num_parents = 1,
  91		.ops = &clk_alpha_pll_postdiv_ro_ops,
  92	},
  93};
  94
  95static const struct clk_div_table post_div_table_gpll0_out_main[] = {
  96	{ 0x0, 1 },
  97	{ }
  98};
  99
 100static struct clk_alpha_pll_postdiv gpll0_out_main = {
 101	.offset = 0x0,
 102	.post_div_shift = 8,
 103	.post_div_table = post_div_table_gpll0_out_main,
 104	.num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_main),
 105	.width = 4,
 106	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
 107	.clkr.hw.init = &(struct clk_init_data){
 108		.name = "gpll0_out_main",
 109		.parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
 110		.num_parents = 1,
 111		.ops = &clk_alpha_pll_postdiv_ro_ops,
 112	},
 113};
 114
 115/* 1152MHz configuration */
 116static const struct alpha_pll_config gpll10_config = {
 117	.l = 0x3c,
 118	.vco_val = 0x1 << 20,
 119	.vco_mask = GENMASK(21, 20),
 120	.main_output_mask = BIT(0),
 121	.config_ctl_val = 0x4001055b,
 122};
 123
 124static struct clk_alpha_pll gpll10 = {
 125	.offset = 0xa000,
 126	.vco_table = gpll10_vco,
 127	.num_vco = ARRAY_SIZE(gpll10_vco),
 128	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
 129	.clkr = {
 130		.enable_reg = 0x79000,
 131		.enable_mask = BIT(10),
 132		.hw.init = &(struct clk_init_data){
 133			.name = "gpll10",
 134			.parent_data = &(const struct clk_parent_data){
 135				.fw_name = "bi_tcxo",
 136			},
 137			.num_parents = 1,
 138			.ops = &clk_alpha_pll_ops,
 139		},
 140	},
 141};
 142
 143static const struct clk_div_table post_div_table_gpll10_out_main[] = {
 144	{ 0x0, 1 },
 145	{ }
 146};
 147
 148static struct clk_alpha_pll_postdiv gpll10_out_main = {
 149	.offset = 0xa000,
 150	.post_div_shift = 8,
 151	.post_div_table = post_div_table_gpll10_out_main,
 152	.num_post_div = ARRAY_SIZE(post_div_table_gpll10_out_main),
 153	.width = 4,
 154	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
 155	.clkr.hw.init = &(struct clk_init_data){
 156		.name = "gpll10_out_main",
 157		.parent_hws = (const struct clk_hw *[]){ &gpll10.clkr.hw },
 158		.num_parents = 1,
 159		.flags = CLK_SET_RATE_PARENT,
 160		.ops = &clk_alpha_pll_postdiv_ops,
 161	},
 162};
 163
 164/* 600MHz configuration */
 165static const struct alpha_pll_config gpll11_config = {
 166	.l = 0x1F,
 167	.alpha = 0x0,
 168	.alpha_hi = 0x40,
 169	.alpha_en_mask = BIT(24),
 170	.vco_val = 0x2 << 20,
 171	.vco_mask = GENMASK(21, 20),
 172	.config_ctl_val = 0x4001055b,
 173};
 174
 175static struct clk_alpha_pll gpll11 = {
 176	.offset = 0xb000,
 177	.vco_table = default_vco,
 178	.num_vco = ARRAY_SIZE(default_vco),
 179	.flags = SUPPORTS_DYNAMIC_UPDATE,
 180	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
 181	.clkr = {
 182		.enable_reg = 0x79000,
 183		.enable_mask = BIT(11),
 184		.hw.init = &(struct clk_init_data){
 185			.name = "gpll11",
 186			.parent_data = &(const struct clk_parent_data){
 187				.fw_name = "bi_tcxo",
 188			},
 189			.num_parents = 1,
 190			.ops = &clk_alpha_pll_ops,
 191		},
 192	},
 193};
 194
 195static const struct clk_div_table post_div_table_gpll11_out_main[] = {
 196	{ 0x0, 1 },
 197	{ }
 198};
 199
 200static struct clk_alpha_pll_postdiv gpll11_out_main = {
 201	.offset = 0xb000,
 202	.post_div_shift = 8,
 203	.post_div_table = post_div_table_gpll11_out_main,
 204	.num_post_div = ARRAY_SIZE(post_div_table_gpll11_out_main),
 205	.width = 4,
 206	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
 207	.clkr.hw.init = &(struct clk_init_data){
 208		.name = "gpll11_out_main",
 209		.parent_hws = (const struct clk_hw *[]){ &gpll11.clkr.hw },
 210		.num_parents = 1,
 211		.flags = CLK_SET_RATE_PARENT,
 212		.ops = &clk_alpha_pll_postdiv_ops,
 213	},
 214};
 215
 216static struct clk_alpha_pll gpll3 = {
 217	.offset = 0x3000,
 218	.vco_table = default_vco,
 219	.num_vco = ARRAY_SIZE(default_vco),
 220	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
 221	.clkr = {
 222		.enable_reg = 0x79000,
 223		.enable_mask = BIT(3),
 224		.hw.init = &(struct clk_init_data){
 225			.name = "gpll3",
 226			.parent_data = &(const struct clk_parent_data){
 227				.fw_name = "bi_tcxo",
 228			},
 229			.num_parents = 1,
 230			.ops = &clk_alpha_pll_ops,
 231		},
 232	},
 233};
 234
 235static struct clk_alpha_pll gpll4 = {
 236	.offset = 0x4000,
 237	.vco_table = default_vco,
 238	.num_vco = ARRAY_SIZE(default_vco),
 239	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
 240	.clkr = {
 241		.enable_reg = 0x79000,
 242		.enable_mask = BIT(4),
 243		.hw.init = &(struct clk_init_data){
 244			.name = "gpll4",
 245			.parent_data = &(const struct clk_parent_data){
 246				.fw_name = "bi_tcxo",
 247			},
 248			.num_parents = 1,
 249			.ops = &clk_alpha_pll_ops,
 250		},
 251	},
 252};
 253
 254static const struct clk_div_table post_div_table_gpll4_out_main[] = {
 255	{ 0x0, 1 },
 256	{ }
 257};
 258
 259static struct clk_alpha_pll_postdiv gpll4_out_main = {
 260	.offset = 0x4000,
 261	.post_div_shift = 8,
 262	.post_div_table = post_div_table_gpll4_out_main,
 263	.num_post_div = ARRAY_SIZE(post_div_table_gpll4_out_main),
 264	.width = 4,
 265	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
 266	.clkr.hw.init = &(struct clk_init_data){
 267		.name = "gpll4_out_main",
 268		.parent_hws = (const struct clk_hw *[]){ &gpll4.clkr.hw },
 269		.num_parents = 1,
 270		.ops = &clk_alpha_pll_postdiv_ro_ops,
 271	},
 272};
 273
 274static struct clk_alpha_pll gpll6 = {
 275	.offset = 0x6000,
 276	.vco_table = default_vco,
 277	.num_vco = ARRAY_SIZE(default_vco),
 278	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
 279	.clkr = {
 280		.enable_reg = 0x79000,
 281		.enable_mask = BIT(6),
 282		.hw.init = &(struct clk_init_data){
 283			.name = "gpll6",
 284			.parent_data = &(const struct clk_parent_data){
 285				.fw_name = "bi_tcxo",
 286			},
 287			.num_parents = 1,
 288			.ops = &clk_alpha_pll_ops,
 289		},
 290	},
 291};
 292
 293static const struct clk_div_table post_div_table_gpll6_out_main[] = {
 294	{ 0x1, 2 },
 295	{ }
 296};
 297
 298static struct clk_alpha_pll_postdiv gpll6_out_main = {
 299	.offset = 0x6000,
 300	.post_div_shift = 8,
 301	.post_div_table = post_div_table_gpll6_out_main,
 302	.num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_main),
 303	.width = 4,
 304	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
 305	.clkr.hw.init = &(struct clk_init_data){
 306		.name = "gpll6_out_main",
 307		.parent_hws = (const struct clk_hw *[]){ &gpll6.clkr.hw },
 308		.num_parents = 1,
 309		.ops = &clk_alpha_pll_postdiv_ro_ops,
 310	},
 311};
 312
 313static struct clk_alpha_pll gpll7 = {
 314	.offset = 0x7000,
 315	.vco_table = default_vco,
 316	.num_vco = ARRAY_SIZE(default_vco),
 317	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
 318	.clkr = {
 319		.enable_reg = 0x79000,
 320		.enable_mask = BIT(7),
 321		.hw.init = &(struct clk_init_data){
 322			.name = "gpll7",
 323			.parent_data = &(const struct clk_parent_data){
 324				.fw_name = "bi_tcxo",
 325			},
 326			.num_parents = 1,
 327			.ops = &clk_alpha_pll_ops,
 328		},
 329	},
 330};
 331
 332static const struct clk_div_table post_div_table_gpll7_out_main[] = {
 333	{ 0x0, 1 },
 334	{ }
 335};
 336
 337static struct clk_alpha_pll_postdiv gpll7_out_main = {
 338	.offset = 0x7000,
 339	.post_div_shift = 8,
 340	.post_div_table = post_div_table_gpll7_out_main,
 341	.num_post_div = ARRAY_SIZE(post_div_table_gpll7_out_main),
 342	.width = 4,
 343	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
 344	.clkr.hw.init = &(struct clk_init_data){
 345		.name = "gpll7_out_main",
 346		.parent_hws = (const struct clk_hw *[]){ &gpll7.clkr.hw },
 347		.num_parents = 1,
 348		.ops = &clk_alpha_pll_postdiv_ro_ops,
 349	},
 350};
 351
 352/* 800MHz configuration */
 353static const struct alpha_pll_config gpll8_config = {
 354	.l = 0x29,
 355	.alpha = 0xAAAAAAAA,
 356	.alpha_hi = 0xAA,
 357	.alpha_en_mask = BIT(24),
 358	.vco_val = 0x2 << 20,
 359	.vco_mask = GENMASK(21, 20),
 360	.main_output_mask = BIT(0),
 361	.early_output_mask = BIT(3),
 362	.post_div_val = 0x1 << 8,
 363	.post_div_mask = GENMASK(11, 8),
 364	.config_ctl_val = 0x4001055b,
 365};
 366
 367static struct clk_alpha_pll gpll8 = {
 368	.offset = 0x8000,
 369	.vco_table = default_vco,
 370	.num_vco = ARRAY_SIZE(default_vco),
 371	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
 372	.flags = SUPPORTS_DYNAMIC_UPDATE,
 373	.clkr = {
 374		.enable_reg = 0x79000,
 375		.enable_mask = BIT(8),
 376		.hw.init = &(struct clk_init_data){
 377			.name = "gpll8",
 378			.parent_data = &(const struct clk_parent_data){
 379				.fw_name = "bi_tcxo",
 380			},
 381			.num_parents = 1,
 382			.ops = &clk_alpha_pll_ops,
 383		},
 384	},
 385};
 386
 387static const struct clk_div_table post_div_table_gpll8_out_main[] = {
 388	{ 0x1, 2 },
 389	{ }
 390};
 391
 392static struct clk_alpha_pll_postdiv gpll8_out_main = {
 393	.offset = 0x8000,
 394	.post_div_shift = 8,
 395	.post_div_table = post_div_table_gpll8_out_main,
 396	.num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_main),
 397	.width = 4,
 398	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
 399	.clkr.hw.init = &(struct clk_init_data){
 400		.name = "gpll8_out_main",
 401		.parent_hws = (const struct clk_hw *[]){ &gpll8.clkr.hw },
 402		.num_parents = 1,
 403		.flags = CLK_SET_RATE_PARENT,
 404		.ops = &clk_alpha_pll_postdiv_ro_ops,
 405	},
 406};
 407
 408/* 1152MHz configuration */
 409static const struct alpha_pll_config gpll9_config = {
 410	.l = 0x3C,
 411	.alpha = 0x0,
 412	.post_div_val = 0x1 << 8,
 413	.post_div_mask = GENMASK(9, 8),
 414	.main_output_mask = BIT(0),
 415	.config_ctl_val = 0x00004289,
 416};
 417
 418static struct clk_alpha_pll gpll9 = {
 419	.offset = 0x9000,
 420	.vco_table = gpll9_vco,
 421	.num_vco = ARRAY_SIZE(gpll9_vco),
 422	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO],
 423	.clkr = {
 424		.enable_reg = 0x79000,
 425		.enable_mask = BIT(9),
 426		.hw.init = &(struct clk_init_data){
 427			.name = "gpll9",
 428			.parent_data = &(const struct clk_parent_data){
 429				.fw_name = "bi_tcxo",
 430			},
 431			.num_parents = 1,
 432			.ops = &clk_alpha_pll_ops,
 433		},
 434	},
 435};
 436
 437static const struct clk_div_table post_div_table_gpll9_out_main[] = {
 438	{ 0x1, 2 },
 439	{ }
 440};
 441
 442static struct clk_alpha_pll_postdiv gpll9_out_main = {
 443	.offset = 0x9000,
 444	.post_div_shift = 8,
 445	.post_div_table = post_div_table_gpll9_out_main,
 446	.num_post_div = ARRAY_SIZE(post_div_table_gpll9_out_main),
 447	.width = 2,
 448	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO],
 449	.clkr.hw.init = &(struct clk_init_data){
 450		.name = "gpll9_out_main",
 451		.parent_hws = (const struct clk_hw *[]){ &gpll9.clkr.hw },
 452		.num_parents = 1,
 453		.flags = CLK_SET_RATE_PARENT,
 454		.ops = &clk_alpha_pll_postdiv_ops,
 455	},
 456};
 457
 458static const struct parent_map gcc_parent_map_0[] = {
 459	{ P_BI_TCXO, 0 },
 460	{ P_GPLL0_OUT_EARLY, 1 },
 461	{ P_GPLL0_OUT_AUX2, 2 },
 462};
 463
 464static const struct clk_parent_data gcc_parents_0[] = {
 465	{ .fw_name = "bi_tcxo" },
 466	{ .hw = &gpll0.clkr.hw },
 467	{ .hw = &gpll0_out_aux2.clkr.hw },
 468};
 469
 470static const struct parent_map gcc_parent_map_1[] = {
 471	{ P_BI_TCXO, 0 },
 472	{ P_GPLL0_OUT_EARLY, 1 },
 473	{ P_GPLL0_OUT_AUX2, 2 },
 474	{ P_GPLL6_OUT_MAIN, 4 },
 475};
 476
 477static const struct clk_parent_data gcc_parents_1[] = {
 478	{ .fw_name = "bi_tcxo" },
 479	{ .hw = &gpll0.clkr.hw },
 480	{ .hw = &gpll0_out_aux2.clkr.hw },
 481	{ .hw = &gpll6_out_main.clkr.hw },
 482};
 483
 484static const struct parent_map gcc_parent_map_2[] = {
 485	{ P_BI_TCXO, 0 },
 486	{ P_GPLL0_OUT_EARLY, 1 },
 487	{ P_GPLL0_OUT_AUX2, 2 },
 488	{ P_SLEEP_CLK, 5 },
 489};
 490
 491static const struct clk_parent_data gcc_parents_2[] = {
 492	{ .fw_name = "bi_tcxo" },
 493	{ .hw = &gpll0.clkr.hw },
 494	{ .hw = &gpll0_out_aux2.clkr.hw },
 495	{ .fw_name = "sleep_clk" },
 496};
 497
 498static const struct parent_map gcc_parent_map_3[] = {
 499	{ P_BI_TCXO, 0 },
 500	{ P_GPLL0_OUT_EARLY, 1 },
 501	{ P_GPLL9_OUT_EARLY, 2 },
 502	{ P_GPLL10_OUT_MAIN, 3 },
 503	{ P_GPLL9_OUT_MAIN, 5 },
 504};
 505
 506static const struct clk_parent_data gcc_parents_3[] = {
 507	{ .fw_name = "bi_tcxo" },
 508	{ .hw = &gpll0.clkr.hw },
 509	{ .hw = &gpll9.clkr.hw },
 510	{ .hw = &gpll10_out_main.clkr.hw },
 511	{ .hw = &gpll9_out_main.clkr.hw },
 512};
 513
 514static const struct parent_map gcc_parent_map_4[] = {
 515	{ P_BI_TCXO, 0 },
 516	{ P_GPLL0_OUT_EARLY, 1 },
 517	{ P_GPLL0_OUT_AUX2, 2 },
 518	{ P_GPLL4_OUT_MAIN, 5 },
 519};
 520
 521static const struct clk_parent_data gcc_parents_4[] = {
 522	{ .fw_name = "bi_tcxo" },
 523	{ .hw = &gpll0.clkr.hw },
 524	{ .hw = &gpll0_out_aux2.clkr.hw },
 525	{ .hw = &gpll4_out_main.clkr.hw },
 526};
 527
 528static const struct parent_map gcc_parent_map_5[] = {
 529	{ P_BI_TCXO, 0 },
 530	{ P_GPLL0_OUT_EARLY, 1 },
 531	{ P_GPLL8_OUT_EARLY, 2 },
 532	{ P_GPLL10_OUT_MAIN, 3 },
 533	{ P_GPLL8_OUT_MAIN, 4 },
 534	{ P_GPLL9_OUT_MAIN, 5 },
 535};
 536
 537static const struct clk_parent_data gcc_parents_5[] = {
 538	{ .fw_name = "bi_tcxo" },
 539	{ .hw = &gpll0.clkr.hw },
 540	{ .hw = &gpll8.clkr.hw },
 541	{ .hw = &gpll10_out_main.clkr.hw },
 542	{ .hw = &gpll8_out_main.clkr.hw },
 543	{ .hw = &gpll9_out_main.clkr.hw },
 544};
 545
 546static const struct parent_map gcc_parent_map_6[] = {
 547	{ P_BI_TCXO, 0 },
 548	{ P_GPLL0_OUT_EARLY, 1 },
 549	{ P_GPLL8_OUT_EARLY, 2 },
 550	{ P_GPLL10_OUT_MAIN, 3 },
 551	{ P_GPLL6_OUT_MAIN, 4 },
 552	{ P_GPLL9_OUT_MAIN, 5 },
 553	{ P_GPLL3_OUT_EARLY, 6 },
 554};
 555
 556static const struct clk_parent_data gcc_parents_6[] = {
 557	{ .fw_name = "bi_tcxo" },
 558	{ .hw = &gpll0.clkr.hw },
 559	{ .hw = &gpll8.clkr.hw },
 560	{ .hw = &gpll10_out_main.clkr.hw },
 561	{ .hw = &gpll6_out_main.clkr.hw },
 562	{ .hw = &gpll9_out_main.clkr.hw },
 563	{ .hw = &gpll3.clkr.hw },
 564};
 565
 566static const struct parent_map gcc_parent_map_7[] = {
 567	{ P_BI_TCXO, 0 },
 568	{ P_GPLL0_OUT_EARLY, 1 },
 569	{ P_GPLL0_OUT_AUX2, 2 },
 570	{ P_GPLL10_OUT_MAIN, 3 },
 571	{ P_GPLL4_OUT_MAIN, 5 },
 572	{ P_GPLL3_OUT_EARLY, 6 },
 573};
 574
 575static const struct clk_parent_data gcc_parents_7[] = {
 576	{ .fw_name = "bi_tcxo" },
 577	{ .hw = &gpll0.clkr.hw },
 578	{ .hw = &gpll0_out_aux2.clkr.hw },
 579	{ .hw = &gpll10_out_main.clkr.hw },
 580	{ .hw = &gpll4_out_main.clkr.hw },
 581	{ .hw = &gpll3.clkr.hw },
 582};
 583
 584static const struct parent_map gcc_parent_map_8[] = {
 585	{ P_BI_TCXO, 0 },
 586	{ P_GPLL0_OUT_EARLY, 1 },
 587	{ P_GPLL8_OUT_EARLY, 2 },
 588	{ P_GPLL10_OUT_MAIN, 3 },
 589	{ P_GPLL8_OUT_MAIN, 4 },
 590	{ P_GPLL9_OUT_MAIN, 5 },
 591	{ P_GPLL3_OUT_EARLY, 6 },
 592};
 593
 594static const struct clk_parent_data gcc_parents_8[] = {
 595	{ .fw_name = "bi_tcxo" },
 596	{ .hw = &gpll0.clkr.hw },
 597	{ .hw = &gpll8.clkr.hw },
 598	{ .hw = &gpll10_out_main.clkr.hw },
 599	{ .hw = &gpll8_out_main.clkr.hw },
 600	{ .hw = &gpll9_out_main.clkr.hw },
 601	{ .hw = &gpll3.clkr.hw },
 602};
 603
 604static const struct parent_map gcc_parent_map_9[] = {
 605	{ P_BI_TCXO, 0 },
 606	{ P_GPLL0_OUT_EARLY, 1 },
 607	{ P_GPLL0_OUT_AUX2, 2 },
 608	{ P_GPLL10_OUT_MAIN, 3 },
 609	{ P_GPLL8_OUT_MAIN, 4 },
 610	{ P_GPLL9_OUT_MAIN, 5 },
 611	{ P_GPLL3_OUT_EARLY, 6 },
 612};
 613
 614static const struct clk_parent_data gcc_parents_9[] = {
 615	{ .fw_name = "bi_tcxo" },
 616	{ .hw = &gpll0.clkr.hw },
 617	{ .hw = &gpll0_out_aux2.clkr.hw },
 618	{ .hw = &gpll10_out_main.clkr.hw },
 619	{ .hw = &gpll8_out_main.clkr.hw },
 620	{ .hw = &gpll9_out_main.clkr.hw },
 621	{ .hw = &gpll3.clkr.hw },
 622};
 623
 624static const struct parent_map gcc_parent_map_10[] = {
 625	{ P_BI_TCXO, 0 },
 626	{ P_GPLL0_OUT_EARLY, 1 },
 627	{ P_GPLL8_OUT_EARLY, 2 },
 628	{ P_GPLL10_OUT_MAIN, 3 },
 629	{ P_GPLL6_OUT_EARLY, 4 },
 630	{ P_GPLL9_OUT_MAIN, 5 },
 631};
 632
 633static const struct clk_parent_data gcc_parents_10[] = {
 634	{ .fw_name = "bi_tcxo" },
 635	{ .hw = &gpll0.clkr.hw },
 636	{ .hw = &gpll8.clkr.hw },
 637	{ .hw = &gpll10_out_main.clkr.hw },
 638	{ .hw = &gpll6.clkr.hw },
 639	{ .hw = &gpll9_out_main.clkr.hw },
 640};
 641
 642static const struct parent_map gcc_parent_map_11[] = {
 643	{ P_BI_TCXO, 0 },
 644	{ P_GPLL0_OUT_EARLY, 1 },
 645	{ P_GPLL0_OUT_AUX2, 2 },
 646	{ P_GPLL7_OUT_MAIN, 3 },
 647	{ P_GPLL4_OUT_MAIN, 5 },
 648};
 649
 650static const struct clk_parent_data gcc_parents_11[] = {
 651	{ .fw_name = "bi_tcxo" },
 652	{ .hw = &gpll0.clkr.hw },
 653	{ .hw = &gpll0_out_aux2.clkr.hw },
 654	{ .hw = &gpll7_out_main.clkr.hw },
 655	{ .hw = &gpll4_out_main.clkr.hw },
 656};
 657
 658static const struct parent_map gcc_parent_map_12[] = {
 659	{ P_BI_TCXO, 0 },
 660	{ P_SLEEP_CLK, 5 },
 661};
 662
 663static const struct clk_parent_data gcc_parents_12[] = {
 664	{ .fw_name = "bi_tcxo" },
 665	{ .fw_name = "sleep_clk" },
 666};
 667
 668static const struct parent_map gcc_parent_map_13[] = {
 669	{ P_BI_TCXO, 0 },
 670	{ P_GPLL11_OUT_MAIN, 1 },
 671};
 672
 673static const struct clk_parent_data gcc_parents_13[] = {
 674	{ .fw_name = "bi_tcxo" },
 675	{ .hw = &gpll11_out_main.clkr.hw },
 676};
 677
 678static const struct freq_tbl ftbl_gcc_camss_axi_clk_src[] = {
 679	F(19200000, P_BI_TCXO, 1, 0, 0),
 680	F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0),
 681	F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0),
 682	F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0),
 683	{ }
 684};
 685
 686static struct clk_rcg2 gcc_camss_axi_clk_src = {
 687	.cmd_rcgr = 0x5802c,
 688	.mnd_width = 0,
 689	.hid_width = 5,
 690	.parent_map = gcc_parent_map_7,
 691	.freq_tbl = ftbl_gcc_camss_axi_clk_src,
 692	.clkr.hw.init = &(struct clk_init_data){
 693		.name = "gcc_camss_axi_clk_src",
 694		.parent_data = gcc_parents_7,
 695		.num_parents = ARRAY_SIZE(gcc_parents_7),
 696		.flags = CLK_SET_RATE_PARENT,
 697		.ops = &clk_rcg2_ops,
 698	},
 699};
 700
 701static const struct freq_tbl ftbl_gcc_camss_cci_clk_src[] = {
 702	F(19200000, P_BI_TCXO, 1, 0, 0),
 703	F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0),
 704	{ }
 705};
 706
 707static struct clk_rcg2 gcc_camss_cci_clk_src = {
 708	.cmd_rcgr = 0x56000,
 709	.mnd_width = 0,
 710	.hid_width = 5,
 711	.parent_map = gcc_parent_map_9,
 712	.freq_tbl = ftbl_gcc_camss_cci_clk_src,
 713	.clkr.hw.init = &(struct clk_init_data){
 714		.name = "gcc_camss_cci_clk_src",
 715		.parent_data = gcc_parents_9,
 716		.num_parents = ARRAY_SIZE(gcc_parents_9),
 717		.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
 718		.ops = &clk_rcg2_ops,
 719	},
 720};
 721
 722static const struct freq_tbl ftbl_gcc_camss_csi0phytimer_clk_src[] = {
 723	F(19200000, P_BI_TCXO, 1, 0, 0),
 724	F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
 725	F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0),
 726	F(268800000, P_GPLL4_OUT_MAIN, 3, 0, 0),
 727	{ }
 728};
 729
 730static struct clk_rcg2 gcc_camss_csi0phytimer_clk_src = {
 731	.cmd_rcgr = 0x59000,
 732	.mnd_width = 0,
 733	.hid_width = 5,
 734	.parent_map = gcc_parent_map_4,
 735	.freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src,
 736	.clkr.hw.init = &(struct clk_init_data){
 737		.name = "gcc_camss_csi0phytimer_clk_src",
 738		.parent_data = gcc_parents_4,
 739		.num_parents = ARRAY_SIZE(gcc_parents_4),
 740		.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
 741		.ops = &clk_rcg2_ops,
 742	},
 743};
 744
 745static struct clk_rcg2 gcc_camss_csi1phytimer_clk_src = {
 746	.cmd_rcgr = 0x5901c,
 747	.mnd_width = 0,
 748	.hid_width = 5,
 749	.parent_map = gcc_parent_map_4,
 750	.freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src,
 751	.clkr.hw.init = &(struct clk_init_data){
 752		.name = "gcc_camss_csi1phytimer_clk_src",
 753		.parent_data = gcc_parents_4,
 754		.num_parents = ARRAY_SIZE(gcc_parents_4),
 755		.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
 756		.ops = &clk_rcg2_ops,
 757	},
 758};
 759
 760static struct clk_rcg2 gcc_camss_csi2phytimer_clk_src = {
 761	.cmd_rcgr = 0x59038,
 762	.mnd_width = 0,
 763	.hid_width = 5,
 764	.parent_map = gcc_parent_map_4,
 765	.freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src,
 766	.clkr.hw.init = &(struct clk_init_data){
 767		.name = "gcc_camss_csi2phytimer_clk_src",
 768		.parent_data = gcc_parents_4,
 769		.num_parents = ARRAY_SIZE(gcc_parents_4),
 770		.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
 771		.ops = &clk_rcg2_ops,
 772	},
 773};
 774
 775static const struct freq_tbl ftbl_gcc_camss_mclk0_clk_src[] = {
 776	F(19200000, P_BI_TCXO, 1, 0, 0),
 777	F(24000000, P_GPLL9_OUT_MAIN, 1, 1, 24),
 778	F(64000000, P_GPLL9_OUT_MAIN, 1, 1, 9),
 779	{ }
 780};
 781
 782static struct clk_rcg2 gcc_camss_mclk0_clk_src = {
 783	.cmd_rcgr = 0x51000,
 784	.mnd_width = 8,
 785	.hid_width = 5,
 786	.parent_map = gcc_parent_map_3,
 787	.freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
 788	.clkr.hw.init = &(struct clk_init_data){
 789		.name = "gcc_camss_mclk0_clk_src",
 790		.parent_data = gcc_parents_3,
 791		.num_parents = ARRAY_SIZE(gcc_parents_3),
 792		.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
 793		.ops = &clk_rcg2_ops,
 794	},
 795};
 796
 797static struct clk_rcg2 gcc_camss_mclk1_clk_src = {
 798	.cmd_rcgr = 0x5101c,
 799	.mnd_width = 8,
 800	.hid_width = 5,
 801	.parent_map = gcc_parent_map_3,
 802	.freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
 803	.clkr.hw.init = &(struct clk_init_data){
 804		.name = "gcc_camss_mclk1_clk_src",
 805		.parent_data = gcc_parents_3,
 806		.num_parents = ARRAY_SIZE(gcc_parents_3),
 807		.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
 808		.ops = &clk_rcg2_ops,
 809	},
 810};
 811
 812static struct clk_rcg2 gcc_camss_mclk2_clk_src = {
 813	.cmd_rcgr = 0x51038,
 814	.mnd_width = 8,
 815	.hid_width = 5,
 816	.parent_map = gcc_parent_map_3,
 817	.freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
 818	.clkr.hw.init = &(struct clk_init_data){
 819		.name = "gcc_camss_mclk2_clk_src",
 820		.parent_data = gcc_parents_3,
 821		.num_parents = ARRAY_SIZE(gcc_parents_3),
 822		.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
 823		.ops = &clk_rcg2_ops,
 824	},
 825};
 826
 827static struct clk_rcg2 gcc_camss_mclk3_clk_src = {
 828	.cmd_rcgr = 0x51054,
 829	.mnd_width = 8,
 830	.hid_width = 5,
 831	.parent_map = gcc_parent_map_3,
 832	.freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
 833	.clkr.hw.init = &(struct clk_init_data){
 834		.name = "gcc_camss_mclk3_clk_src",
 835		.parent_data = gcc_parents_3,
 836		.num_parents = ARRAY_SIZE(gcc_parents_3),
 837		.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
 838		.ops = &clk_rcg2_ops,
 839	},
 840};
 841
 842static const struct freq_tbl ftbl_gcc_camss_ope_ahb_clk_src[] = {
 843	F(19200000, P_BI_TCXO, 1, 0, 0),
 844	F(171428571, P_GPLL0_OUT_EARLY, 3.5, 0, 0),
 845	F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
 846	{ }
 847};
 848
 849static struct clk_rcg2 gcc_camss_ope_ahb_clk_src = {
 850	.cmd_rcgr = 0x55024,
 851	.mnd_width = 0,
 852	.hid_width = 5,
 853	.parent_map = gcc_parent_map_8,
 854	.freq_tbl = ftbl_gcc_camss_ope_ahb_clk_src,
 855	.clkr.hw.init = &(struct clk_init_data){
 856		.name = "gcc_camss_ope_ahb_clk_src",
 857		.parent_data = gcc_parents_8,
 858		.num_parents = ARRAY_SIZE(gcc_parents_8),
 859		.flags = CLK_SET_RATE_PARENT,
 860		.ops = &clk_rcg2_ops,
 861	},
 862};
 863
 864static const struct freq_tbl ftbl_gcc_camss_ope_clk_src[] = {
 865	F(19200000, P_BI_TCXO, 1, 0, 0),
 866	F(200000000, P_GPLL8_OUT_MAIN, 2, 0, 0),
 867	F(266600000, P_GPLL8_OUT_MAIN, 1, 0, 0),
 868	F(465000000, P_GPLL8_OUT_MAIN, 1, 0, 0),
 869	F(576000000, P_GPLL9_OUT_MAIN, 1, 0, 0),
 870	{ }
 871};
 872
 873static struct clk_rcg2 gcc_camss_ope_clk_src = {
 874	.cmd_rcgr = 0x55004,
 875	.mnd_width = 0,
 876	.hid_width = 5,
 877	.parent_map = gcc_parent_map_8,
 878	.freq_tbl = ftbl_gcc_camss_ope_clk_src,
 879	.clkr.hw.init = &(struct clk_init_data){
 880		.name = "gcc_camss_ope_clk_src",
 881		.parent_data = gcc_parents_8,
 882		.num_parents = ARRAY_SIZE(gcc_parents_8),
 883		.flags = CLK_SET_RATE_PARENT,
 884		.ops = &clk_rcg2_ops,
 885	},
 886};
 887
 888static const struct freq_tbl ftbl_gcc_camss_tfe_0_clk_src[] = {
 889	F(19200000, P_BI_TCXO, 1, 0, 0),
 890	F(128000000, P_GPLL10_OUT_MAIN, 9, 0, 0),
 891	F(135529412, P_GPLL10_OUT_MAIN, 8.5, 0, 0),
 892	F(144000000, P_GPLL10_OUT_MAIN, 8, 0, 0),
 893	F(153600000, P_GPLL10_OUT_MAIN, 7.5, 0, 0),
 894	F(164571429, P_GPLL10_OUT_MAIN, 7, 0, 0),
 895	F(177230769, P_GPLL10_OUT_MAIN, 6.5, 0, 0),
 896	F(192000000, P_GPLL10_OUT_MAIN, 6, 0, 0),
 897	F(209454545, P_GPLL10_OUT_MAIN, 5.5, 0, 0),
 898	F(230400000, P_GPLL10_OUT_MAIN, 5, 0, 0),
 899	F(256000000, P_GPLL10_OUT_MAIN, 4.5, 0, 0),
 900	F(288000000, P_GPLL10_OUT_MAIN, 4, 0, 0),
 901	F(329142857, P_GPLL10_OUT_MAIN, 3.5, 0, 0),
 902	F(384000000, P_GPLL10_OUT_MAIN, 3, 0, 0),
 903	F(460800000, P_GPLL10_OUT_MAIN, 2.5, 0, 0),
 904	F(576000000, P_GPLL10_OUT_MAIN, 2, 0, 0),
 905	{ }
 906};
 907
 908static struct clk_rcg2 gcc_camss_tfe_0_clk_src = {
 909	.cmd_rcgr = 0x52004,
 910	.mnd_width = 8,
 911	.hid_width = 5,
 912	.parent_map = gcc_parent_map_5,
 913	.freq_tbl = ftbl_gcc_camss_tfe_0_clk_src,
 914	.clkr.hw.init = &(struct clk_init_data){
 915		.name = "gcc_camss_tfe_0_clk_src",
 916		.parent_data = gcc_parents_5,
 917		.num_parents = ARRAY_SIZE(gcc_parents_5),
 918		.flags = CLK_SET_RATE_PARENT,
 919		.ops = &clk_rcg2_ops,
 920	},
 921};
 922
 923static const struct freq_tbl ftbl_gcc_camss_tfe_0_csid_clk_src[] = {
 924	F(19200000, P_BI_TCXO, 1, 0, 0),
 925	F(120000000, P_GPLL0_OUT_EARLY, 5, 0, 0),
 926	F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
 927	F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
 928	F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
 929	F(426400000, P_GPLL3_OUT_EARLY, 2.5, 0, 0),
 930	{ }
 931};
 932
 933static struct clk_rcg2 gcc_camss_tfe_0_csid_clk_src = {
 934	.cmd_rcgr = 0x52094,
 935	.mnd_width = 0,
 936	.hid_width = 5,
 937	.parent_map = gcc_parent_map_6,
 938	.freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src,
 939	.clkr.hw.init = &(struct clk_init_data){
 940		.name = "gcc_camss_tfe_0_csid_clk_src",
 941		.parent_data = gcc_parents_6,
 942		.num_parents = ARRAY_SIZE(gcc_parents_6),
 943		.flags = CLK_SET_RATE_PARENT,
 944		.ops = &clk_rcg2_ops,
 945	},
 946};
 947
 948static struct clk_rcg2 gcc_camss_tfe_1_clk_src = {
 949	.cmd_rcgr = 0x52024,
 950	.mnd_width = 8,
 951	.hid_width = 5,
 952	.parent_map = gcc_parent_map_5,
 953	.freq_tbl = ftbl_gcc_camss_tfe_0_clk_src,
 954	.clkr.hw.init = &(struct clk_init_data){
 955		.name = "gcc_camss_tfe_1_clk_src",
 956		.parent_data = gcc_parents_5,
 957		.num_parents = ARRAY_SIZE(gcc_parents_5),
 958		.flags = CLK_SET_RATE_PARENT,
 959		.ops = &clk_rcg2_ops,
 960	},
 961};
 962
 963static struct clk_rcg2 gcc_camss_tfe_1_csid_clk_src = {
 964	.cmd_rcgr = 0x520b4,
 965	.mnd_width = 0,
 966	.hid_width = 5,
 967	.parent_map = gcc_parent_map_6,
 968	.freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src,
 969	.clkr.hw.init = &(struct clk_init_data){
 970		.name = "gcc_camss_tfe_1_csid_clk_src",
 971		.parent_data = gcc_parents_6,
 972		.num_parents = ARRAY_SIZE(gcc_parents_6),
 973		.flags = CLK_SET_RATE_PARENT,
 974		.ops = &clk_rcg2_ops,
 975	},
 976};
 977
 978static struct clk_rcg2 gcc_camss_tfe_2_clk_src = {
 979	.cmd_rcgr = 0x52044,
 980	.mnd_width = 8,
 981	.hid_width = 5,
 982	.parent_map = gcc_parent_map_5,
 983	.freq_tbl = ftbl_gcc_camss_tfe_0_clk_src,
 984	.clkr.hw.init = &(struct clk_init_data){
 985		.name = "gcc_camss_tfe_2_clk_src",
 986		.parent_data = gcc_parents_5,
 987		.num_parents = ARRAY_SIZE(gcc_parents_5),
 988		.flags = CLK_SET_RATE_PARENT,
 989		.ops = &clk_rcg2_ops,
 990	},
 991};
 992
 993static struct clk_rcg2 gcc_camss_tfe_2_csid_clk_src = {
 994	.cmd_rcgr = 0x520d4,
 995	.mnd_width = 0,
 996	.hid_width = 5,
 997	.parent_map = gcc_parent_map_6,
 998	.freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src,
 999	.clkr.hw.init = &(struct clk_init_data){
1000		.name = "gcc_camss_tfe_2_csid_clk_src",
1001		.parent_data = gcc_parents_6,
1002		.num_parents = ARRAY_SIZE(gcc_parents_6),
1003		.flags = CLK_SET_RATE_PARENT,
1004		.ops = &clk_rcg2_ops,
1005	},
1006};
1007
1008static const struct freq_tbl ftbl_gcc_camss_tfe_cphy_rx_clk_src[] = {
1009	F(19200000, P_BI_TCXO, 1, 0, 0),
1010	F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
1011	F(341333333, P_GPLL6_OUT_EARLY, 1, 4, 9),
1012	F(384000000, P_GPLL6_OUT_EARLY, 2, 0, 0),
1013	{ }
1014};
1015
1016static struct clk_rcg2 gcc_camss_tfe_cphy_rx_clk_src = {
1017	.cmd_rcgr = 0x52064,
1018	.mnd_width = 16,
1019	.hid_width = 5,
1020	.parent_map = gcc_parent_map_10,
1021	.freq_tbl = ftbl_gcc_camss_tfe_cphy_rx_clk_src,
1022	.clkr.hw.init = &(struct clk_init_data){
1023		.name = "gcc_camss_tfe_cphy_rx_clk_src",
1024		.parent_data = gcc_parents_10,
1025		.num_parents = ARRAY_SIZE(gcc_parents_10),
1026		.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
1027		.ops = &clk_rcg2_ops,
1028	},
1029};
1030
1031static const struct freq_tbl ftbl_gcc_camss_top_ahb_clk_src[] = {
1032	F(19200000, P_BI_TCXO, 1, 0, 0),
1033	F(40000000, P_GPLL0_OUT_AUX2, 7.5, 0, 0),
1034	F(80000000, P_GPLL0_OUT_EARLY, 7.5, 0, 0),
1035	{ }
1036};
1037
1038static struct clk_rcg2 gcc_camss_top_ahb_clk_src = {
1039	.cmd_rcgr = 0x58010,
1040	.mnd_width = 0,
1041	.hid_width = 5,
1042	.parent_map = gcc_parent_map_7,
1043	.freq_tbl = ftbl_gcc_camss_top_ahb_clk_src,
1044	.clkr.hw.init = &(struct clk_init_data){
1045		.name = "gcc_camss_top_ahb_clk_src",
1046		.parent_data = gcc_parents_7,
1047		.num_parents = ARRAY_SIZE(gcc_parents_7),
1048		.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
1049		.ops = &clk_rcg2_ops,
1050	},
1051};
1052
1053static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
1054	F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
1055	F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
1056	F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1057	F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0),
1058	{ }
1059};
1060
1061static struct clk_rcg2 gcc_gp1_clk_src = {
1062	.cmd_rcgr = 0x4d004,
1063	.mnd_width = 8,
1064	.hid_width = 5,
1065	.parent_map = gcc_parent_map_2,
1066	.freq_tbl = ftbl_gcc_gp1_clk_src,
1067	.clkr.hw.init = &(struct clk_init_data){
1068		.name = "gcc_gp1_clk_src",
1069		.parent_data = gcc_parents_2,
1070		.num_parents = ARRAY_SIZE(gcc_parents_2),
1071		.ops = &clk_rcg2_ops,
1072	},
1073};
1074
1075static struct clk_rcg2 gcc_gp2_clk_src = {
1076	.cmd_rcgr = 0x4e004,
1077	.mnd_width = 8,
1078	.hid_width = 5,
1079	.parent_map = gcc_parent_map_2,
1080	.freq_tbl = ftbl_gcc_gp1_clk_src,
1081	.clkr.hw.init = &(struct clk_init_data){
1082		.name = "gcc_gp2_clk_src",
1083		.parent_data = gcc_parents_2,
1084		.num_parents = ARRAY_SIZE(gcc_parents_2),
1085		.ops = &clk_rcg2_ops,
1086	},
1087};
1088
1089static struct clk_rcg2 gcc_gp3_clk_src = {
1090	.cmd_rcgr = 0x4f004,
1091	.mnd_width = 8,
1092	.hid_width = 5,
1093	.parent_map = gcc_parent_map_2,
1094	.freq_tbl = ftbl_gcc_gp1_clk_src,
1095	.clkr.hw.init = &(struct clk_init_data){
1096		.name = "gcc_gp3_clk_src",
1097		.parent_data = gcc_parents_2,
1098		.num_parents = ARRAY_SIZE(gcc_parents_2),
1099		.ops = &clk_rcg2_ops,
1100	},
1101};
1102
1103static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
1104	F(19200000, P_BI_TCXO, 1, 0, 0),
1105	F(60000000, P_GPLL0_OUT_AUX2, 5, 0, 0),
1106	{ }
1107};
1108
1109static struct clk_rcg2 gcc_pdm2_clk_src = {
1110	.cmd_rcgr = 0x20010,
1111	.mnd_width = 0,
1112	.hid_width = 5,
1113	.parent_map = gcc_parent_map_0,
1114	.freq_tbl = ftbl_gcc_pdm2_clk_src,
1115	.clkr.hw.init = &(struct clk_init_data){
1116		.name = "gcc_pdm2_clk_src",
1117		.parent_data = gcc_parents_0,
1118		.num_parents = ARRAY_SIZE(gcc_parents_0),
1119		.ops = &clk_rcg2_ops,
1120	},
1121};
1122
1123static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
1124	F(7372800, P_GPLL0_OUT_AUX2, 1, 384, 15625),
1125	F(14745600, P_GPLL0_OUT_AUX2, 1, 768, 15625),
1126	F(19200000, P_BI_TCXO, 1, 0, 0),
1127	F(29491200, P_GPLL0_OUT_AUX2, 1, 1536, 15625),
1128	F(32000000, P_GPLL0_OUT_AUX2, 1, 8, 75),
1129	F(48000000, P_GPLL0_OUT_AUX2, 1, 4, 25),
1130	F(64000000, P_GPLL0_OUT_AUX2, 1, 16, 75),
1131	F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
1132	F(80000000, P_GPLL0_OUT_AUX2, 1, 4, 15),
1133	F(96000000, P_GPLL0_OUT_AUX2, 1, 8, 25),
1134	F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1135	F(102400000, P_GPLL0_OUT_AUX2, 1, 128, 375),
1136	F(112000000, P_GPLL0_OUT_AUX2, 1, 28, 75),
1137	F(117964800, P_GPLL0_OUT_AUX2, 1, 6144, 15625),
1138	F(120000000, P_GPLL0_OUT_AUX2, 2.5, 0, 0),
1139	F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0),
1140	{ }
1141};
1142
1143static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
1144	.name = "gcc_qupv3_wrap0_s0_clk_src",
1145	.parent_data = gcc_parents_1,
1146	.num_parents = ARRAY_SIZE(gcc_parents_1),
1147	.ops = &clk_rcg2_ops,
1148};
1149
1150static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
1151	.cmd_rcgr = 0x1f148,
1152	.mnd_width = 16,
1153	.hid_width = 5,
1154	.parent_map = gcc_parent_map_1,
1155	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1156	.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
1157};
1158
1159static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
1160	.name = "gcc_qupv3_wrap0_s1_clk_src",
1161	.parent_data = gcc_parents_1,
1162	.num_parents = ARRAY_SIZE(gcc_parents_1),
1163	.ops = &clk_rcg2_ops,
1164};
1165
1166static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
1167	.cmd_rcgr = 0x1f278,
1168	.mnd_width = 16,
1169	.hid_width = 5,
1170	.parent_map = gcc_parent_map_1,
1171	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1172	.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
1173};
1174
1175static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
1176	.name = "gcc_qupv3_wrap0_s2_clk_src",
1177	.parent_data = gcc_parents_1,
1178	.num_parents = ARRAY_SIZE(gcc_parents_1),
1179	.ops = &clk_rcg2_ops,
1180};
1181
1182static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
1183	.cmd_rcgr = 0x1f3a8,
1184	.mnd_width = 16,
1185	.hid_width = 5,
1186	.parent_map = gcc_parent_map_1,
1187	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1188	.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
1189};
1190
1191static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
1192	.name = "gcc_qupv3_wrap0_s3_clk_src",
1193	.parent_data = gcc_parents_1,
1194	.num_parents = ARRAY_SIZE(gcc_parents_1),
1195	.ops = &clk_rcg2_ops,
1196};
1197
1198static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
1199	.cmd_rcgr = 0x1f4d8,
1200	.mnd_width = 16,
1201	.hid_width = 5,
1202	.parent_map = gcc_parent_map_1,
1203	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1204	.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
1205};
1206
1207static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
1208	.name = "gcc_qupv3_wrap0_s4_clk_src",
1209	.parent_data = gcc_parents_1,
1210	.num_parents = ARRAY_SIZE(gcc_parents_1),
1211	.ops = &clk_rcg2_ops,
1212};
1213
1214static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
1215	.cmd_rcgr = 0x1f608,
1216	.mnd_width = 16,
1217	.hid_width = 5,
1218	.parent_map = gcc_parent_map_1,
1219	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1220	.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
1221};
1222
1223static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
1224	.name = "gcc_qupv3_wrap0_s5_clk_src",
1225	.parent_data = gcc_parents_1,
1226	.num_parents = ARRAY_SIZE(gcc_parents_1),
1227	.ops = &clk_rcg2_ops,
1228};
1229
1230static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
1231	.cmd_rcgr = 0x1f738,
1232	.mnd_width = 16,
1233	.hid_width = 5,
1234	.parent_map = gcc_parent_map_1,
1235	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1236	.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
1237};
1238
1239static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
1240	F(144000, P_BI_TCXO, 16, 3, 25),
1241	F(400000, P_BI_TCXO, 12, 1, 4),
1242	F(20000000, P_GPLL0_OUT_AUX2, 5, 1, 3),
1243	F(25000000, P_GPLL0_OUT_AUX2, 6, 1, 2),
1244	F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
1245	F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1246	F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
1247	F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
1248	{ }
1249};
1250
1251static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
1252	.cmd_rcgr = 0x38028,
1253	.mnd_width = 8,
1254	.hid_width = 5,
1255	.parent_map = gcc_parent_map_1,
1256	.freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
1257	.clkr.hw.init = &(struct clk_init_data){
1258		.name = "gcc_sdcc1_apps_clk_src",
1259		.parent_data = gcc_parents_1,
1260		.num_parents = ARRAY_SIZE(gcc_parents_1),
1261		.ops = &clk_rcg2_ops,
1262	},
1263};
1264
1265static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
1266	F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
1267	F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1268	F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0),
1269	F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
1270	F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0),
1271	{ }
1272};
1273
1274static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
1275	.cmd_rcgr = 0x38010,
1276	.mnd_width = 0,
1277	.hid_width = 5,
1278	.parent_map = gcc_parent_map_0,
1279	.freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
1280	.clkr.hw.init = &(struct clk_init_data){
1281		.name = "gcc_sdcc1_ice_core_clk_src",
1282		.parent_data = gcc_parents_0,
1283		.num_parents = ARRAY_SIZE(gcc_parents_0),
1284		.ops = &clk_rcg2_ops,
1285	},
1286};
1287
1288static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
1289	F(400000, P_BI_TCXO, 12, 1, 4),
1290	F(19200000, P_BI_TCXO, 1, 0, 0),
1291	F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
1292	F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
1293	F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1294	F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
1295	{ }
1296};
1297
1298static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
1299	.cmd_rcgr = 0x1e00c,
1300	.mnd_width = 8,
1301	.hid_width = 5,
1302	.parent_map = gcc_parent_map_11,
1303	.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
1304	.clkr.hw.init = &(struct clk_init_data){
1305		.name = "gcc_sdcc2_apps_clk_src",
1306		.parent_data = gcc_parents_11,
1307		.num_parents = ARRAY_SIZE(gcc_parents_11),
1308		.ops = &clk_rcg2_ops,
1309		.flags = CLK_OPS_PARENT_ENABLE,
1310	},
1311};
1312
1313static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
1314	F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
1315	F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
1316	F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1317	F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
1318	F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
1319	{ }
1320};
1321
1322static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
1323	.cmd_rcgr = 0x45020,
1324	.mnd_width = 8,
1325	.hid_width = 5,
1326	.parent_map = gcc_parent_map_0,
1327	.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
1328	.clkr.hw.init = &(struct clk_init_data){
1329		.name = "gcc_ufs_phy_axi_clk_src",
1330		.parent_data = gcc_parents_0,
1331		.num_parents = ARRAY_SIZE(gcc_parents_0),
1332		.ops = &clk_rcg2_ops,
1333	},
1334};
1335
1336static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
1337	F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0),
1338	F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
1339	F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0),
1340	F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0),
1341	{ }
1342};
1343
1344static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
1345	.cmd_rcgr = 0x45048,
1346	.mnd_width = 0,
1347	.hid_width = 5,
1348	.parent_map = gcc_parent_map_0,
1349	.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
1350	.clkr.hw.init = &(struct clk_init_data){
1351		.name = "gcc_ufs_phy_ice_core_clk_src",
1352		.parent_data = gcc_parents_0,
1353		.num_parents = ARRAY_SIZE(gcc_parents_0),
1354		.ops = &clk_rcg2_ops,
1355	},
1356};
1357
1358static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {
1359	F(9600000, P_BI_TCXO, 2, 0, 0),
1360	F(19200000, P_BI_TCXO, 1, 0, 0),
1361	{ }
1362};
1363
1364static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
1365	.cmd_rcgr = 0x4507c,
1366	.mnd_width = 0,
1367	.hid_width = 5,
1368	.parent_map = gcc_parent_map_0,
1369	.freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,
1370	.clkr.hw.init = &(struct clk_init_data){
1371		.name = "gcc_ufs_phy_phy_aux_clk_src",
1372		.parent_data = gcc_parents_0,
1373		.num_parents = ARRAY_SIZE(gcc_parents_0),
1374		.ops = &clk_rcg2_ops,
1375	},
1376};
1377
1378static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
1379	F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0),
1380	F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
1381	F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0),
1382	{ }
1383};
1384
1385static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
1386	.cmd_rcgr = 0x45060,
1387	.mnd_width = 0,
1388	.hid_width = 5,
1389	.parent_map = gcc_parent_map_0,
1390	.freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,
1391	.clkr.hw.init = &(struct clk_init_data){
1392		.name = "gcc_ufs_phy_unipro_core_clk_src",
1393		.parent_data = gcc_parents_0,
1394		.num_parents = ARRAY_SIZE(gcc_parents_0),
1395		.ops = &clk_rcg2_ops,
1396	},
1397};
1398
1399static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
1400	F(66666667, P_GPLL0_OUT_AUX2, 4.5, 0, 0),
1401	F(133333333, P_GPLL0_OUT_EARLY, 4.5, 0, 0),
1402	F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
1403	F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
1404	{ }
1405};
1406
1407static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1408	.cmd_rcgr = 0x1a01c,
1409	.mnd_width = 8,
1410	.hid_width = 5,
1411	.parent_map = gcc_parent_map_0,
1412	.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1413	.clkr.hw.init = &(struct clk_init_data){
1414		.name = "gcc_usb30_prim_master_clk_src",
1415		.parent_data = gcc_parents_0,
1416		.num_parents = ARRAY_SIZE(gcc_parents_0),
1417		.ops = &clk_rcg2_ops,
1418	},
1419};
1420
1421static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
1422	F(19200000, P_BI_TCXO, 1, 0, 0),
1423	{ }
1424};
1425
1426static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1427	.cmd_rcgr = 0x1a034,
1428	.mnd_width = 0,
1429	.hid_width = 5,
1430	.parent_map = gcc_parent_map_0,
1431	.freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1432	.clkr.hw.init = &(struct clk_init_data){
1433		.name = "gcc_usb30_prim_mock_utmi_clk_src",
1434		.parent_data = gcc_parents_0,
1435		.num_parents = ARRAY_SIZE(gcc_parents_0),
1436		.ops = &clk_rcg2_ops,
1437	},
1438};
1439
1440static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
1441	.reg = 0x1a04c,
1442	.shift = 0,
1443	.width = 2,
1444	.clkr.hw.init = &(struct clk_init_data) {
1445		.name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
1446		.parent_hws = (const struct clk_hw *[]) {
1447			&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw },
1448		.num_parents = 1,
1449		.ops = &clk_regmap_div_ro_ops,
1450	},
1451};
1452
1453static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1454	.cmd_rcgr = 0x1a060,
1455	.mnd_width = 0,
1456	.hid_width = 5,
1457	.parent_map = gcc_parent_map_12,
1458	.freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1459	.clkr.hw.init = &(struct clk_init_data){
1460		.name = "gcc_usb3_prim_phy_aux_clk_src",
1461		.parent_data = gcc_parents_12,
1462		.num_parents = ARRAY_SIZE(gcc_parents_12),
1463		.ops = &clk_rcg2_ops,
1464	},
1465};
1466
1467static const struct freq_tbl ftbl_gcc_video_venus_clk_src[] = {
1468	F(133333333, P_GPLL11_OUT_MAIN, 4.5, 0, 0),
1469	F(240000000, P_GPLL11_OUT_MAIN, 2.5, 0, 0),
1470	F(300000000, P_GPLL11_OUT_MAIN, 2, 0, 0),
1471	F(384000000, P_GPLL11_OUT_MAIN, 2, 0, 0),
1472	{ }
1473};
1474
1475static struct clk_rcg2 gcc_video_venus_clk_src = {
1476	.cmd_rcgr = 0x58060,
1477	.mnd_width = 0,
1478	.hid_width = 5,
1479	.parent_map = gcc_parent_map_13,
1480	.freq_tbl = ftbl_gcc_video_venus_clk_src,
1481	.clkr.hw.init = &(struct clk_init_data){
1482		.name = "gcc_video_venus_clk_src",
1483		.parent_data = gcc_parents_13,
1484		.num_parents = ARRAY_SIZE(gcc_parents_13),
1485		.flags = CLK_SET_RATE_PARENT,
1486		.ops = &clk_rcg2_ops,
1487	},
1488};
1489
1490static struct clk_branch gcc_ahb2phy_csi_clk = {
1491	.halt_reg = 0x1d004,
1492	.halt_check = BRANCH_HALT,
1493	.hwcg_reg = 0x1d004,
1494	.hwcg_bit = 1,
1495	.clkr = {
1496		.enable_reg = 0x1d004,
1497		.enable_mask = BIT(0),
1498		.hw.init = &(struct clk_init_data){
1499			.name = "gcc_ahb2phy_csi_clk",
1500			.ops = &clk_branch2_ops,
1501		},
1502	},
1503};
1504
1505static struct clk_branch gcc_ahb2phy_usb_clk = {
1506	.halt_reg = 0x1d008,
1507	.halt_check = BRANCH_HALT,
1508	.hwcg_reg = 0x1d008,
1509	.hwcg_bit = 1,
1510	.clkr = {
1511		.enable_reg = 0x1d008,
1512		.enable_mask = BIT(0),
1513		.hw.init = &(struct clk_init_data){
1514			.name = "gcc_ahb2phy_usb_clk",
1515			.ops = &clk_branch2_ops,
1516		},
1517	},
1518};
1519
1520static struct clk_branch gcc_bimc_gpu_axi_clk = {
1521	.halt_reg = 0x71154,
1522	.halt_check = BRANCH_HALT_DELAY,
1523	.hwcg_reg = 0x71154,
1524	.hwcg_bit = 1,
1525	.clkr = {
1526		.enable_reg = 0x71154,
1527		.enable_mask = BIT(0),
1528		.hw.init = &(struct clk_init_data){
1529			.name = "gcc_bimc_gpu_axi_clk",
1530			.ops = &clk_branch2_ops,
1531		},
1532	},
1533};
1534
1535static struct clk_branch gcc_boot_rom_ahb_clk = {
1536	.halt_reg = 0x23004,
1537	.halt_check = BRANCH_HALT_VOTED,
1538	.hwcg_reg = 0x23004,
1539	.hwcg_bit = 1,
1540	.clkr = {
1541		.enable_reg = 0x79004,
1542		.enable_mask = BIT(10),
1543		.hw.init = &(struct clk_init_data){
1544			.name = "gcc_boot_rom_ahb_clk",
1545			.ops = &clk_branch2_ops,
1546		},
1547	},
1548};
1549
1550static struct clk_branch gcc_cam_throttle_nrt_clk = {
1551	.halt_reg = 0x17070,
1552	.halt_check = BRANCH_HALT_VOTED,
1553	.hwcg_reg = 0x17070,
1554	.hwcg_bit = 1,
1555	.clkr = {
1556		.enable_reg = 0x79004,
1557		.enable_mask = BIT(27),
1558		.hw.init = &(struct clk_init_data){
1559			.name = "gcc_cam_throttle_nrt_clk",
1560			.ops = &clk_branch2_ops,
1561		},
1562	},
1563};
1564
1565static struct clk_branch gcc_cam_throttle_rt_clk = {
1566	.halt_reg = 0x1706c,
1567	.halt_check = BRANCH_HALT_VOTED,
1568	.hwcg_reg = 0x1706c,
1569	.hwcg_bit = 1,
1570	.clkr = {
1571		.enable_reg = 0x79004,
1572		.enable_mask = BIT(26),
1573		.hw.init = &(struct clk_init_data){
1574			.name = "gcc_cam_throttle_rt_clk",
1575			.ops = &clk_branch2_ops,
1576		},
1577	},
1578};
1579
1580static struct clk_branch gcc_camera_ahb_clk = {
1581	.halt_reg = 0x17008,
1582	.halt_check = BRANCH_HALT_DELAY,
1583	.hwcg_reg = 0x17008,
1584	.hwcg_bit = 1,
1585	.clkr = {
1586		.enable_reg = 0x17008,
1587		.enable_mask = BIT(0),
1588		.hw.init = &(struct clk_init_data){
1589			.name = "gcc_camera_ahb_clk",
1590			.flags = CLK_IS_CRITICAL,
1591			.ops = &clk_branch2_ops,
1592		},
1593	},
1594};
1595
1596static struct clk_branch gcc_camera_xo_clk = {
1597	.halt_reg = 0x17028,
1598	.halt_check = BRANCH_HALT,
1599	.clkr = {
1600		.enable_reg = 0x17028,
1601		.enable_mask = BIT(0),
1602		.hw.init = &(struct clk_init_data){
1603			.name = "gcc_camera_xo_clk",
1604			.flags = CLK_IS_CRITICAL,
1605			.ops = &clk_branch2_ops,
1606		},
1607	},
1608};
1609
1610static struct clk_branch gcc_camss_axi_clk = {
1611	.halt_reg = 0x58044,
1612	.halt_check = BRANCH_HALT,
1613	.clkr = {
1614		.enable_reg = 0x58044,
1615		.enable_mask = BIT(0),
1616		.hw.init = &(struct clk_init_data){
1617			.name = "gcc_camss_axi_clk",
1618			.parent_hws = (const struct clk_hw *[]){
1619				&gcc_camss_axi_clk_src.clkr.hw,
1620			},
1621			.num_parents = 1,
1622			.flags = CLK_SET_RATE_PARENT,
1623			.ops = &clk_branch2_ops,
1624		},
1625	},
1626};
1627
1628static struct clk_branch gcc_camss_camnoc_atb_clk = {
1629	.halt_reg = 0x5804c,
1630	.halt_check = BRANCH_HALT_DELAY,
1631	.hwcg_reg = 0x5804c,
1632	.hwcg_bit = 1,
1633	.clkr = {
1634		.enable_reg = 0x5804c,
1635		.enable_mask = BIT(0),
1636		.hw.init = &(struct clk_init_data){
1637			.name = "gcc_camss_camnoc_atb_clk",
1638			.ops = &clk_branch2_ops,
1639		},
1640	},
1641};
1642
1643static struct clk_branch gcc_camss_camnoc_nts_xo_clk = {
1644	.halt_reg = 0x58050,
1645	.halt_check = BRANCH_HALT_DELAY,
1646	.hwcg_reg = 0x58050,
1647	.hwcg_bit = 1,
1648	.clkr = {
1649		.enable_reg = 0x58050,
1650		.enable_mask = BIT(0),
1651		.hw.init = &(struct clk_init_data){
1652			.name = "gcc_camss_camnoc_nts_xo_clk",
1653			.ops = &clk_branch2_ops,
1654		},
1655	},
1656};
1657
1658static struct clk_branch gcc_camss_cci_0_clk = {
1659	.halt_reg = 0x56018,
1660	.halt_check = BRANCH_HALT,
1661	.clkr = {
1662		.enable_reg = 0x56018,
1663		.enable_mask = BIT(0),
1664		.hw.init = &(struct clk_init_data){
1665			.name = "gcc_camss_cci_0_clk",
1666			.parent_hws = (const struct clk_hw *[]){
1667				&gcc_camss_cci_clk_src.clkr.hw,
1668			},
1669			.num_parents = 1,
1670			.flags = CLK_SET_RATE_PARENT,
1671			.ops = &clk_branch2_ops,
1672		},
1673	},
1674};
1675
1676static struct clk_branch gcc_camss_cphy_0_clk = {
1677	.halt_reg = 0x52088,
1678	.halt_check = BRANCH_HALT,
1679	.clkr = {
1680		.enable_reg = 0x52088,
1681		.enable_mask = BIT(0),
1682		.hw.init = &(struct clk_init_data){
1683			.name = "gcc_camss_cphy_0_clk",
1684			.parent_hws = (const struct clk_hw *[]){
1685				&gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
1686			},
1687			.num_parents = 1,
1688			.flags = CLK_SET_RATE_PARENT,
1689			.ops = &clk_branch2_ops,
1690		},
1691	},
1692};
1693
1694static struct clk_branch gcc_camss_cphy_1_clk = {
1695	.halt_reg = 0x5208c,
1696	.halt_check = BRANCH_HALT,
1697	.clkr = {
1698		.enable_reg = 0x5208c,
1699		.enable_mask = BIT(0),
1700		.hw.init = &(struct clk_init_data){
1701			.name = "gcc_camss_cphy_1_clk",
1702			.parent_hws = (const struct clk_hw *[]){
1703				&gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
1704			},
1705			.num_parents = 1,
1706			.flags = CLK_SET_RATE_PARENT,
1707			.ops = &clk_branch2_ops,
1708		},
1709	},
1710};
1711
1712static struct clk_branch gcc_camss_cphy_2_clk = {
1713	.halt_reg = 0x52090,
1714	.halt_check = BRANCH_HALT,
1715	.clkr = {
1716		.enable_reg = 0x52090,
1717		.enable_mask = BIT(0),
1718		.hw.init = &(struct clk_init_data){
1719			.name = "gcc_camss_cphy_2_clk",
1720			.parent_hws = (const struct clk_hw *[]){
1721				&gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
1722			},
1723			.num_parents = 1,
1724			.flags = CLK_SET_RATE_PARENT,
1725			.ops = &clk_branch2_ops,
1726		},
1727	},
1728};
1729
1730static struct clk_branch gcc_camss_csi0phytimer_clk = {
1731	.halt_reg = 0x59018,
1732	.halt_check = BRANCH_HALT,
1733	.clkr = {
1734		.enable_reg = 0x59018,
1735		.enable_mask = BIT(0),
1736		.hw.init = &(struct clk_init_data){
1737			.name = "gcc_camss_csi0phytimer_clk",
1738			.parent_hws = (const struct clk_hw *[]){
1739				&gcc_camss_csi0phytimer_clk_src.clkr.hw,
1740			},
1741			.num_parents = 1,
1742			.flags = CLK_SET_RATE_PARENT,
1743			.ops = &clk_branch2_ops,
1744		},
1745	},
1746};
1747
1748static struct clk_branch gcc_camss_csi1phytimer_clk = {
1749	.halt_reg = 0x59034,
1750	.halt_check = BRANCH_HALT,
1751	.clkr = {
1752		.enable_reg = 0x59034,
1753		.enable_mask = BIT(0),
1754		.hw.init = &(struct clk_init_data){
1755			.name = "gcc_camss_csi1phytimer_clk",
1756			.parent_hws = (const struct clk_hw *[]){
1757				&gcc_camss_csi1phytimer_clk_src.clkr.hw,
1758			},
1759			.num_parents = 1,
1760			.flags = CLK_SET_RATE_PARENT,
1761			.ops = &clk_branch2_ops,
1762		},
1763	},
1764};
1765
1766static struct clk_branch gcc_camss_csi2phytimer_clk = {
1767	.halt_reg = 0x59050,
1768	.halt_check = BRANCH_HALT,
1769	.clkr = {
1770		.enable_reg = 0x59050,
1771		.enable_mask = BIT(0),
1772		.hw.init = &(struct clk_init_data){
1773			.name = "gcc_camss_csi2phytimer_clk",
1774			.parent_hws = (const struct clk_hw *[]){
1775				&gcc_camss_csi2phytimer_clk_src.clkr.hw,
1776			},
1777			.num_parents = 1,
1778			.flags = CLK_SET_RATE_PARENT,
1779			.ops = &clk_branch2_ops,
1780		},
1781	},
1782};
1783
1784static struct clk_branch gcc_camss_mclk0_clk = {
1785	.halt_reg = 0x51018,
1786	.halt_check = BRANCH_HALT,
1787	.clkr = {
1788		.enable_reg = 0x51018,
1789		.enable_mask = BIT(0),
1790		.hw.init = &(struct clk_init_data){
1791			.name = "gcc_camss_mclk0_clk",
1792			.parent_hws = (const struct clk_hw *[]){
1793				&gcc_camss_mclk0_clk_src.clkr.hw,
1794			},
1795			.num_parents = 1,
1796			.flags = CLK_SET_RATE_PARENT,
1797			.ops = &clk_branch2_ops,
1798		},
1799	},
1800};
1801
1802static struct clk_branch gcc_camss_mclk1_clk = {
1803	.halt_reg = 0x51034,
1804	.halt_check = BRANCH_HALT,
1805	.clkr = {
1806		.enable_reg = 0x51034,
1807		.enable_mask = BIT(0),
1808		.hw.init = &(struct clk_init_data){
1809			.name = "gcc_camss_mclk1_clk",
1810			.parent_hws = (const struct clk_hw *[]){
1811				&gcc_camss_mclk1_clk_src.clkr.hw,
1812			},
1813			.num_parents = 1,
1814			.flags = CLK_SET_RATE_PARENT,
1815			.ops = &clk_branch2_ops,
1816		},
1817	},
1818};
1819
1820static struct clk_branch gcc_camss_mclk2_clk = {
1821	.halt_reg = 0x51050,
1822	.halt_check = BRANCH_HALT,
1823	.clkr = {
1824		.enable_reg = 0x51050,
1825		.enable_mask = BIT(0),
1826		.hw.init = &(struct clk_init_data){
1827			.name = "gcc_camss_mclk2_clk",
1828			.parent_hws = (const struct clk_hw *[]){
1829				&gcc_camss_mclk2_clk_src.clkr.hw,
1830			},
1831			.num_parents = 1,
1832			.flags = CLK_SET_RATE_PARENT,
1833			.ops = &clk_branch2_ops,
1834		},
1835	},
1836};
1837
1838static struct clk_branch gcc_camss_mclk3_clk = {
1839	.halt_reg = 0x5106c,
1840	.halt_check = BRANCH_HALT,
1841	.clkr = {
1842		.enable_reg = 0x5106c,
1843		.enable_mask = BIT(0),
1844		.hw.init = &(struct clk_init_data){
1845			.name = "gcc_camss_mclk3_clk",
1846			.parent_hws = (const struct clk_hw *[]){
1847				&gcc_camss_mclk3_clk_src.clkr.hw,
1848			},
1849			.num_parents = 1,
1850			.flags = CLK_SET_RATE_PARENT,
1851			.ops = &clk_branch2_ops,
1852		},
1853	},
1854};
1855
1856static struct clk_branch gcc_camss_nrt_axi_clk = {
1857	.halt_reg = 0x58054,
1858	.halt_check = BRANCH_HALT,
1859	.clkr = {
1860		.enable_reg = 0x58054,
1861		.enable_mask = BIT(0),
1862		.hw.init = &(struct clk_init_data){
1863			.name = "gcc_camss_nrt_axi_clk",
1864			.ops = &clk_branch2_ops,
1865		},
1866	},
1867};
1868
1869static struct clk_branch gcc_camss_ope_ahb_clk = {
1870	.halt_reg = 0x5503c,
1871	.halt_check = BRANCH_HALT,
1872	.clkr = {
1873		.enable_reg = 0x5503c,
1874		.enable_mask = BIT(0),
1875		.hw.init = &(struct clk_init_data){
1876			.name = "gcc_camss_ope_ahb_clk",
1877			.parent_hws = (const struct clk_hw *[]){
1878				&gcc_camss_ope_ahb_clk_src.clkr.hw,
1879			},
1880			.num_parents = 1,
1881			.flags = CLK_SET_RATE_PARENT,
1882			.ops = &clk_branch2_ops,
1883		},
1884	},
1885};
1886
1887static struct clk_branch gcc_camss_ope_clk = {
1888	.halt_reg = 0x5501c,
1889	.halt_check = BRANCH_HALT,
1890	.clkr = {
1891		.enable_reg = 0x5501c,
1892		.enable_mask = BIT(0),
1893		.hw.init = &(struct clk_init_data){
1894			.name = "gcc_camss_ope_clk",
1895			.parent_hws = (const struct clk_hw *[]){
1896				&gcc_camss_ope_clk_src.clkr.hw,
1897			},
1898			.num_parents = 1,
1899			.flags = CLK_SET_RATE_PARENT,
1900			.ops = &clk_branch2_ops,
1901		},
1902	},
1903};
1904
1905static struct clk_branch gcc_camss_rt_axi_clk = {
1906	.halt_reg = 0x5805c,
1907	.halt_check = BRANCH_HALT,
1908	.clkr = {
1909		.enable_reg = 0x5805c,
1910		.enable_mask = BIT(0),
1911		.hw.init = &(struct clk_init_data){
1912			.name = "gcc_camss_rt_axi_clk",
1913			.ops = &clk_branch2_ops,
1914		},
1915	},
1916};
1917
1918static struct clk_branch gcc_camss_tfe_0_clk = {
1919	.halt_reg = 0x5201c,
1920	.halt_check = BRANCH_HALT,
1921	.clkr = {
1922		.enable_reg = 0x5201c,
1923		.enable_mask = BIT(0),
1924		.hw.init = &(struct clk_init_data){
1925			.name = "gcc_camss_tfe_0_clk",
1926			.parent_hws = (const struct clk_hw *[]){
1927				&gcc_camss_tfe_0_clk_src.clkr.hw,
1928			},
1929			.num_parents = 1,
1930			.flags = CLK_SET_RATE_PARENT,
1931			.ops = &clk_branch2_ops,
1932		},
1933	},
1934};
1935
1936static struct clk_branch gcc_camss_tfe_0_cphy_rx_clk = {
1937	.halt_reg = 0x5207c,
1938	.halt_check = BRANCH_HALT,
1939	.clkr = {
1940		.enable_reg = 0x5207c,
1941		.enable_mask = BIT(0),
1942		.hw.init = &(struct clk_init_data){
1943			.name = "gcc_camss_tfe_0_cphy_rx_clk",
1944			.parent_hws = (const struct clk_hw *[]){
1945				&gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
1946			},
1947			.num_parents = 1,
1948			.flags = CLK_SET_RATE_PARENT,
1949			.ops = &clk_branch2_ops,
1950		},
1951	},
1952};
1953
1954static struct clk_branch gcc_camss_tfe_0_csid_clk = {
1955	.halt_reg = 0x520ac,
1956	.halt_check = BRANCH_HALT,
1957	.clkr = {
1958		.enable_reg = 0x520ac,
1959		.enable_mask = BIT(0),
1960		.hw.init = &(struct clk_init_data){
1961			.name = "gcc_camss_tfe_0_csid_clk",
1962			.parent_hws = (const struct clk_hw *[]){
1963				&gcc_camss_tfe_0_csid_clk_src.clkr.hw,
1964			},
1965			.num_parents = 1,
1966			.flags = CLK_SET_RATE_PARENT,
1967			.ops = &clk_branch2_ops,
1968		},
1969	},
1970};
1971
1972static struct clk_branch gcc_camss_tfe_1_clk = {
1973	.halt_reg = 0x5203c,
1974	.halt_check = BRANCH_HALT,
1975	.clkr = {
1976		.enable_reg = 0x5203c,
1977		.enable_mask = BIT(0),
1978		.hw.init = &(struct clk_init_data){
1979			.name = "gcc_camss_tfe_1_clk",
1980			.parent_hws = (const struct clk_hw *[]){
1981				&gcc_camss_tfe_1_clk_src.clkr.hw,
1982			},
1983			.num_parents = 1,
1984			.flags = CLK_SET_RATE_PARENT,
1985			.ops = &clk_branch2_ops,
1986		},
1987	},
1988};
1989
1990static struct clk_branch gcc_camss_tfe_1_cphy_rx_clk = {
1991	.halt_reg = 0x52080,
1992	.halt_check = BRANCH_HALT,
1993	.clkr = {
1994		.enable_reg = 0x52080,
1995		.enable_mask = BIT(0),
1996		.hw.init = &(struct clk_init_data){
1997			.name = "gcc_camss_tfe_1_cphy_rx_clk",
1998			.parent_hws = (const struct clk_hw *[]){
1999				&gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
2000			},
2001			.num_parents = 1,
2002			.flags = CLK_SET_RATE_PARENT,
2003			.ops = &clk_branch2_ops,
2004		},
2005	},
2006};
2007
2008static struct clk_branch gcc_camss_tfe_1_csid_clk = {
2009	.halt_reg = 0x520cc,
2010	.halt_check = BRANCH_HALT,
2011	.clkr = {
2012		.enable_reg = 0x520cc,
2013		.enable_mask = BIT(0),
2014		.hw.init = &(struct clk_init_data){
2015			.name = "gcc_camss_tfe_1_csid_clk",
2016			.parent_hws = (const struct clk_hw *[]){
2017				&gcc_camss_tfe_1_csid_clk_src.clkr.hw,
2018			},
2019			.num_parents = 1,
2020			.flags = CLK_SET_RATE_PARENT,
2021			.ops = &clk_branch2_ops,
2022		},
2023	},
2024};
2025
2026static struct clk_branch gcc_camss_tfe_2_clk = {
2027	.halt_reg = 0x5205c,
2028	.halt_check = BRANCH_HALT,
2029	.clkr = {
2030		.enable_reg = 0x5205c,
2031		.enable_mask = BIT(0),
2032		.hw.init = &(struct clk_init_data){
2033			.name = "gcc_camss_tfe_2_clk",
2034			.parent_hws = (const struct clk_hw *[]){
2035				&gcc_camss_tfe_2_clk_src.clkr.hw,
2036			},
2037			.num_parents = 1,
2038			.flags = CLK_SET_RATE_PARENT,
2039			.ops = &clk_branch2_ops,
2040		},
2041	},
2042};
2043
2044static struct clk_branch gcc_camss_tfe_2_cphy_rx_clk = {
2045	.halt_reg = 0x52084,
2046	.halt_check = BRANCH_HALT,
2047	.clkr = {
2048		.enable_reg = 0x52084,
2049		.enable_mask = BIT(0),
2050		.hw.init = &(struct clk_init_data){
2051			.name = "gcc_camss_tfe_2_cphy_rx_clk",
2052			.parent_hws = (const struct clk_hw *[]){
2053				&gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
2054			},
2055			.num_parents = 1,
2056			.flags = CLK_SET_RATE_PARENT,
2057			.ops = &clk_branch2_ops,
2058		},
2059	},
2060};
2061
2062static struct clk_branch gcc_camss_tfe_2_csid_clk = {
2063	.halt_reg = 0x520ec,
2064	.halt_check = BRANCH_HALT,
2065	.clkr = {
2066		.enable_reg = 0x520ec,
2067		.enable_mask = BIT(0),
2068		.hw.init = &(struct clk_init_data){
2069			.name = "gcc_camss_tfe_2_csid_clk",
2070			.parent_hws = (const struct clk_hw *[]){
2071				&gcc_camss_tfe_2_csid_clk_src.clkr.hw,
2072			},
2073			.num_parents = 1,
2074			.flags = CLK_SET_RATE_PARENT,
2075			.ops = &clk_branch2_ops,
2076		},
2077	},
2078};
2079
2080static struct clk_branch gcc_camss_top_ahb_clk = {
2081	.halt_reg = 0x58028,
2082	.halt_check = BRANCH_HALT,
2083	.clkr = {
2084		.enable_reg = 0x58028,
2085		.enable_mask = BIT(0),
2086		.hw.init = &(struct clk_init_data){
2087			.name = "gcc_camss_top_ahb_clk",
2088			.parent_hws = (const struct clk_hw *[]){
2089				&gcc_camss_top_ahb_clk_src.clkr.hw,
2090			},
2091			.num_parents = 1,
2092			.flags = CLK_SET_RATE_PARENT,
2093			.ops = &clk_branch2_ops,
2094		},
2095	},
2096};
2097
2098static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
2099	.halt_reg = 0x1a084,
2100	.halt_check = BRANCH_HALT,
2101	.hwcg_reg = 0x1a084,
2102	.hwcg_bit = 1,
2103	.clkr = {
2104		.enable_reg = 0x1a084,
2105		.enable_mask = BIT(0),
2106		.hw.init = &(struct clk_init_data){
2107			.name = "gcc_cfg_noc_usb3_prim_axi_clk",
2108			.parent_hws = (const struct clk_hw *[]){
2109				&gcc_usb30_prim_master_clk_src.clkr.hw,
2110			},
2111			.num_parents = 1,
2112			.flags = CLK_SET_RATE_PARENT,
2113			.ops = &clk_branch2_ops,
2114		},
2115	},
2116};
2117
2118static struct clk_branch gcc_cpuss_gnoc_clk = {
2119	.halt_reg = 0x2b004,
2120	.halt_check = BRANCH_HALT_VOTED,
2121	.hwcg_reg = 0x2b004,
2122	.hwcg_bit = 1,
2123	.clkr = {
2124		.enable_reg = 0x79004,
2125		.enable_mask = BIT(22),
2126		.hw.init = &(struct clk_init_data){
2127			.name = "gcc_cpuss_gnoc_clk",
2128			.flags = CLK_IS_CRITICAL,
2129			.ops = &clk_branch2_ops,
2130		},
2131	},
2132};
2133
2134static struct clk_branch gcc_disp_ahb_clk = {
2135	.halt_reg = 0x1700c,
2136	.halt_check = BRANCH_HALT,
2137	.hwcg_reg = 0x1700c,
2138	.hwcg_bit = 1,
2139	.clkr = {
2140		.enable_reg = 0x1700c,
2141		.enable_mask = BIT(0),
2142		.hw.init = &(struct clk_init_data){
2143			.name = "gcc_disp_ahb_clk",
2144			.flags = CLK_IS_CRITICAL,
2145			.ops = &clk_branch2_ops,
2146		},
2147	},
2148};
2149
2150static struct clk_regmap_div gcc_disp_gpll0_clk_src = {
2151	.reg = 0x17058,
2152	.shift = 0,
2153	.width = 2,
2154	.clkr.hw.init = &(struct clk_init_data) {
2155		.name = "gcc_disp_gpll0_clk_src",
2156		.parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
2157		.num_parents = 1,
2158		.ops = &clk_regmap_div_ops,
2159	},
2160};
2161
2162static struct clk_branch gcc_disp_gpll0_div_clk_src = {
2163	.halt_check = BRANCH_HALT_DELAY,
2164	.clkr = {
2165		.enable_reg = 0x79004,
2166		.enable_mask = BIT(20),
2167		.hw.init = &(struct clk_init_data){
2168			.name = "gcc_disp_gpll0_div_clk_src",
2169			.parent_hws = (const struct clk_hw *[]){
2170				&gcc_disp_gpll0_clk_src.clkr.hw,
2171			},
2172			.num_parents = 1,
2173			.flags = CLK_SET_RATE_PARENT,
2174			.ops = &clk_branch2_ops,
2175		},
2176	},
2177};
2178
2179static struct clk_branch gcc_disp_hf_axi_clk = {
2180	.halt_reg = 0x17020,
2181	.halt_check = BRANCH_HALT,
2182	.hwcg_reg = 0x17020,
2183	.hwcg_bit = 1,
2184	.clkr = {
2185		.enable_reg = 0x17020,
2186		.enable_mask = BIT(0),
2187		.hw.init = &(struct clk_init_data){
2188			.name = "gcc_disp_hf_axi_clk",
2189			.ops = &clk_branch2_ops,
2190		},
2191	},
2192};
2193
2194static struct clk_branch gcc_disp_throttle_core_clk = {
2195	.halt_reg = 0x17064,
2196	.halt_check = BRANCH_HALT_VOTED,
2197	.hwcg_reg = 0x17064,
2198	.hwcg_bit = 1,
2199	.clkr = {
2200		.enable_reg = 0x7900c,
2201		.enable_mask = BIT(5),
2202		.hw.init = &(struct clk_init_data){
2203			.name = "gcc_disp_throttle_core_clk",
2204			.ops = &clk_branch2_ops,
2205		},
2206	},
2207};
2208
2209static struct clk_branch gcc_disp_xo_clk = {
2210	.halt_reg = 0x1702c,
2211	.halt_check = BRANCH_HALT,
2212	.clkr = {
2213		.enable_reg = 0x1702c,
2214		.enable_mask = BIT(0),
2215		.hw.init = &(struct clk_init_data){
2216			.name = "gcc_disp_xo_clk",
2217			.flags = CLK_IS_CRITICAL,
2218			.ops = &clk_branch2_ops,
2219		},
2220	},
2221};
2222
2223static struct clk_branch gcc_gp1_clk = {
2224	.halt_reg = 0x4d000,
2225	.halt_check = BRANCH_HALT,
2226	.clkr = {
2227		.enable_reg = 0x4d000,
2228		.enable_mask = BIT(0),
2229		.hw.init = &(struct clk_init_data){
2230			.name = "gcc_gp1_clk",
2231			.parent_hws = (const struct clk_hw *[]){
2232				&gcc_gp1_clk_src.clkr.hw,
2233			},
2234			.num_parents = 1,
2235			.flags = CLK_SET_RATE_PARENT,
2236			.ops = &clk_branch2_ops,
2237		},
2238	},
2239};
2240
2241static struct clk_branch gcc_gp2_clk = {
2242	.halt_reg = 0x4e000,
2243	.halt_check = BRANCH_HALT,
2244	.clkr = {
2245		.enable_reg = 0x4e000,
2246		.enable_mask = BIT(0),
2247		.hw.init = &(struct clk_init_data){
2248			.name = "gcc_gp2_clk",
2249			.parent_hws = (const struct clk_hw *[]){
2250				&gcc_gp2_clk_src.clkr.hw,
2251			},
2252			.num_parents = 1,
2253			.flags = CLK_SET_RATE_PARENT,
2254			.ops = &clk_branch2_ops,
2255		},
2256	},
2257};
2258
2259static struct clk_branch gcc_gp3_clk = {
2260	.halt_reg = 0x4f000,
2261	.halt_check = BRANCH_HALT,
2262	.clkr = {
2263		.enable_reg = 0x4f000,
2264		.enable_mask = BIT(0),
2265		.hw.init = &(struct clk_init_data){
2266			.name = "gcc_gp3_clk",
2267			.parent_hws = (const struct clk_hw *[]){
2268				&gcc_gp3_clk_src.clkr.hw,
2269			},
2270			.num_parents = 1,
2271			.flags = CLK_SET_RATE_PARENT,
2272			.ops = &clk_branch2_ops,
2273		},
2274	},
2275};
2276
2277static struct clk_branch gcc_gpu_cfg_ahb_clk = {
2278	.halt_reg = 0x36004,
2279	.halt_check = BRANCH_HALT,
2280	.hwcg_reg = 0x36004,
2281	.hwcg_bit = 1,
2282	.clkr = {
2283		.enable_reg = 0x36004,
2284		.enable_mask = BIT(0),
2285		.hw.init = &(struct clk_init_data){
2286			.name = "gcc_gpu_cfg_ahb_clk",
2287			.flags = CLK_IS_CRITICAL,
2288			.ops = &clk_branch2_ops,
2289		},
2290	},
2291};
2292
2293static struct clk_branch gcc_gpu_gpll0_clk_src = {
2294	.halt_check = BRANCH_HALT_DELAY,
2295	.clkr = {
2296		.enable_reg = 0x79004,
2297		.enable_mask = BIT(15),
2298		.hw.init = &(struct clk_init_data){
2299			.name = "gcc_gpu_gpll0_clk_src",
2300			.parent_hws = (const struct clk_hw *[]){
2301				&gpll0.clkr.hw,
2302			},
2303			.num_parents = 1,
2304			.flags = CLK_SET_RATE_PARENT,
2305			.ops = &clk_branch2_ops,
2306		},
2307	},
2308};
2309
2310static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
2311	.halt_check = BRANCH_HALT_DELAY,
2312	.clkr = {
2313		.enable_reg = 0x79004,
2314		.enable_mask = BIT(16),
2315		.hw.init = &(struct clk_init_data){
2316			.name = "gcc_gpu_gpll0_div_clk_src",
2317			.parent_hws = (const struct clk_hw *[]){
2318				&gpll0_out_aux2.clkr.hw,
2319			},
2320			.num_parents = 1,
2321			.flags = CLK_SET_RATE_PARENT,
2322			.ops = &clk_branch2_ops,
2323		},
2324	},
2325};
2326
2327static struct clk_branch gcc_gpu_iref_clk = {
2328	.halt_reg = 0x36100,
2329	.halt_check = BRANCH_HALT_DELAY,
2330	.clkr = {
2331		.enable_reg = 0x36100,
2332		.enable_mask = BIT(0),
2333		.hw.init = &(struct clk_init_data){
2334			.name = "gcc_gpu_iref_clk",
2335			.ops = &clk_branch2_ops,
2336		},
2337	},
2338};
2339
2340static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
2341	.halt_reg = 0x3600c,
2342	.halt_check = BRANCH_VOTED,
2343	.hwcg_reg = 0x3600c,
2344	.hwcg_bit = 1,
2345	.clkr = {
2346		.enable_reg = 0x3600c,
2347		.enable_mask = BIT(0),
2348		.hw.init = &(struct clk_init_data){
2349			.name = "gcc_gpu_memnoc_gfx_clk",
2350			.ops = &clk_branch2_ops,
2351		},
2352	},
2353};
2354
2355static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
2356	.halt_reg = 0x36018,
2357	.halt_check = BRANCH_HALT,
2358	.clkr = {
2359		.enable_reg = 0x36018,
2360		.enable_mask = BIT(0),
2361		.hw.init = &(struct clk_init_data){
2362			.name = "gcc_gpu_snoc_dvm_gfx_clk",
2363			.ops = &clk_branch2_ops,
2364		},
2365	},
2366};
2367
2368static struct clk_branch gcc_gpu_throttle_core_clk = {
2369	.halt_reg = 0x36048,
2370	.halt_check = BRANCH_HALT_VOTED,
2371	.hwcg_reg = 0x36048,
2372	.hwcg_bit = 1,
2373	.clkr = {
2374		.enable_reg = 0x79004,
2375		.enable_mask = BIT(31),
2376		.hw.init = &(struct clk_init_data){
2377			.name = "gcc_gpu_throttle_core_clk",
2378			.ops = &clk_branch2_ops,
2379		},
2380	},
2381};
2382
2383static struct clk_branch gcc_pdm2_clk = {
2384	.halt_reg = 0x2000c,
2385	.halt_check = BRANCH_HALT,
2386	.clkr = {
2387		.enable_reg = 0x2000c,
2388		.enable_mask = BIT(0),
2389		.hw.init = &(struct clk_init_data){
2390			.name = "gcc_pdm2_clk",
2391			.parent_hws = (const struct clk_hw *[]){
2392				&gcc_pdm2_clk_src.clkr.hw,
2393			},
2394			.num_parents = 1,
2395			.flags = CLK_SET_RATE_PARENT,
2396			.ops = &clk_branch2_ops,
2397		},
2398	},
2399};
2400
2401static struct clk_branch gcc_pdm_ahb_clk = {
2402	.halt_reg = 0x20004,
2403	.halt_check = BRANCH_HALT,
2404	.hwcg_reg = 0x20004,
2405	.hwcg_bit = 1,
2406	.clkr = {
2407		.enable_reg = 0x20004,
2408		.enable_mask = BIT(0),
2409		.hw.init = &(struct clk_init_data){
2410			.name = "gcc_pdm_ahb_clk",
2411			.ops = &clk_branch2_ops,
2412		},
2413	},
2414};
2415
2416static struct clk_branch gcc_pdm_xo4_clk = {
2417	.halt_reg = 0x20008,
2418	.halt_check = BRANCH_HALT,
2419	.clkr = {
2420		.enable_reg = 0x20008,
2421		.enable_mask = BIT(0),
2422		.hw.init = &(struct clk_init_data){
2423			.name = "gcc_pdm_xo4_clk",
2424			.ops = &clk_branch2_ops,
2425		},
2426	},
2427};
2428
2429static struct clk_branch gcc_prng_ahb_clk = {
2430	.halt_reg = 0x21004,
2431	.halt_check = BRANCH_HALT_VOTED,
2432	.hwcg_reg = 0x21004,
2433	.hwcg_bit = 1,
2434	.clkr = {
2435		.enable_reg = 0x79004,
2436		.enable_mask = BIT(13),
2437		.hw.init = &(struct clk_init_data){
2438			.name = "gcc_prng_ahb_clk",
2439			.ops = &clk_branch2_ops,
2440		},
2441	},
2442};
2443
2444static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
2445	.halt_reg = 0x17014,
2446	.halt_check = BRANCH_HALT_VOTED,
2447	.hwcg_reg = 0x17014,
2448	.hwcg_bit = 1,
2449	.clkr = {
2450		.enable_reg = 0x7900c,
2451		.enable_mask = BIT(0),
2452		.hw.init = &(struct clk_init_data){
2453			.name = "gcc_qmip_camera_nrt_ahb_clk",
2454			.ops = &clk_branch2_ops,
2455		},
2456	},
2457};
2458
2459static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
2460	.halt_reg = 0x17060,
2461	.halt_check = BRANCH_HALT_VOTED,
2462	.hwcg_reg = 0x17060,
2463	.hwcg_bit = 1,
2464	.clkr = {
2465		.enable_reg = 0x7900c,
2466		.enable_mask = BIT(2),
2467		.hw.init = &(struct clk_init_data){
2468			.name = "gcc_qmip_camera_rt_ahb_clk",
2469			.ops = &clk_branch2_ops,
2470		},
2471	},
2472};
2473
2474static struct clk_branch gcc_qmip_disp_ahb_clk = {
2475	.halt_reg = 0x17018,
2476	.halt_check = BRANCH_HALT_VOTED,
2477	.hwcg_reg = 0x17018,
2478	.hwcg_bit = 1,
2479	.clkr = {
2480		.enable_reg = 0x7900c,
2481		.enable_mask = BIT(1),
2482		.hw.init = &(struct clk_init_data){
2483			.name = "gcc_qmip_disp_ahb_clk",
2484			.ops = &clk_branch2_ops,
2485		},
2486	},
2487};
2488
2489static struct clk_branch gcc_qmip_gpu_cfg_ahb_clk = {
2490	.halt_reg = 0x36040,
2491	.halt_check = BRANCH_HALT_VOTED,
2492	.hwcg_reg = 0x36040,
2493	.hwcg_bit = 1,
2494	.clkr = {
2495		.enable_reg = 0x7900c,
2496		.enable_mask = BIT(4),
2497		.hw.init = &(struct clk_init_data){
2498			.name = "gcc_qmip_gpu_cfg_ahb_clk",
2499			.ops = &clk_branch2_ops,
2500		},
2501	},
2502};
2503
2504static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
2505	.halt_reg = 0x17010,
2506	.halt_check = BRANCH_HALT_VOTED,
2507	.hwcg_reg = 0x17010,
2508	.hwcg_bit = 1,
2509	.clkr = {
2510		.enable_reg = 0x79004,
2511		.enable_mask = BIT(25),
2512		.hw.init = &(struct clk_init_data){
2513			.name = "gcc_qmip_video_vcodec_ahb_clk",
2514			.ops = &clk_branch2_ops,
2515		},
2516	},
2517};
2518
2519static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
2520	.halt_reg = 0x1f014,
2521	.halt_check = BRANCH_HALT_VOTED,
2522	.clkr = {
2523		.enable_reg = 0x7900c,
2524		.enable_mask = BIT(9),
2525		.hw.init = &(struct clk_init_data){
2526			.name = "gcc_qupv3_wrap0_core_2x_clk",
2527			.ops = &clk_branch2_ops,
2528		},
2529	},
2530};
2531
2532static struct clk_branch gcc_qupv3_wrap0_core_clk = {
2533	.halt_reg = 0x1f00c,
2534	.halt_check = BRANCH_HALT_VOTED,
2535	.clkr = {
2536		.enable_reg = 0x7900c,
2537		.enable_mask = BIT(8),
2538		.hw.init = &(struct clk_init_data){
2539			.name = "gcc_qupv3_wrap0_core_clk",
2540			.ops = &clk_branch2_ops,
2541		},
2542	},
2543};
2544
2545static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
2546	.halt_reg = 0x1f144,
2547	.halt_check = BRANCH_HALT_VOTED,
2548	.clkr = {
2549		.enable_reg = 0x7900c,
2550		.enable_mask = BIT(10),
2551		.hw.init = &(struct clk_init_data){
2552			.name = "gcc_qupv3_wrap0_s0_clk",
2553			.parent_hws = (const struct clk_hw *[]){
2554				&gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
2555			},
2556			.num_parents = 1,
2557			.flags = CLK_SET_RATE_PARENT,
2558			.ops = &clk_branch2_ops,
2559		},
2560	},
2561};
2562
2563static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
2564	.halt_reg = 0x1f274,
2565	.halt_check = BRANCH_HALT_VOTED,
2566	.clkr = {
2567		.enable_reg = 0x7900c,
2568		.enable_mask = BIT(11),
2569		.hw.init = &(struct clk_init_data){
2570			.name = "gcc_qupv3_wrap0_s1_clk",
2571			.parent_hws = (const struct clk_hw *[]){
2572				&gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
2573			},
2574			.num_parents = 1,
2575			.flags = CLK_SET_RATE_PARENT,
2576			.ops = &clk_branch2_ops,
2577		},
2578	},
2579};
2580
2581static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
2582	.halt_reg = 0x1f3a4,
2583	.halt_check = BRANCH_HALT_VOTED,
2584	.clkr = {
2585		.enable_reg = 0x7900c,
2586		.enable_mask = BIT(12),
2587		.hw.init = &(struct clk_init_data){
2588			.name = "gcc_qupv3_wrap0_s2_clk",
2589			.parent_hws = (const struct clk_hw *[]){
2590				&gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
2591			},
2592			.num_parents = 1,
2593			.flags = CLK_SET_RATE_PARENT,
2594			.ops = &clk_branch2_ops,
2595		},
2596	},
2597};
2598
2599static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
2600	.halt_reg = 0x1f4d4,
2601	.halt_check = BRANCH_HALT_VOTED,
2602	.clkr = {
2603		.enable_reg = 0x7900c,
2604		.enable_mask = BIT(13),
2605		.hw.init = &(struct clk_init_data){
2606			.name = "gcc_qupv3_wrap0_s3_clk",
2607			.parent_hws = (const struct clk_hw *[]){
2608				&gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
2609			},
2610			.num_parents = 1,
2611			.flags = CLK_SET_RATE_PARENT,
2612			.ops = &clk_branch2_ops,
2613		},
2614	},
2615};
2616
2617static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2618	.halt_reg = 0x1f604,
2619	.halt_check = BRANCH_HALT_VOTED,
2620	.clkr = {
2621		.enable_reg = 0x7900c,
2622		.enable_mask = BIT(14),
2623		.hw.init = &(struct clk_init_data){
2624			.name = "gcc_qupv3_wrap0_s4_clk",
2625			.parent_hws = (const struct clk_hw *[]){
2626				&gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
2627			},
2628			.num_parents = 1,
2629			.flags = CLK_SET_RATE_PARENT,
2630			.ops = &clk_branch2_ops,
2631		},
2632	},
2633};
2634
2635static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2636	.halt_reg = 0x1f734,
2637	.halt_check = BRANCH_HALT_VOTED,
2638	.clkr = {
2639		.enable_reg = 0x7900c,
2640		.enable_mask = BIT(15),
2641		.hw.init = &(struct clk_init_data){
2642			.name = "gcc_qupv3_wrap0_s5_clk",
2643			.parent_hws = (const struct clk_hw *[]){
2644				&gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
2645			},
2646			.num_parents = 1,
2647			.flags = CLK_SET_RATE_PARENT,
2648			.ops = &clk_branch2_ops,
2649		},
2650	},
2651};
2652
2653static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
2654	.halt_reg = 0x1f004,
2655	.halt_check = BRANCH_HALT_VOTED,
2656	.hwcg_reg = 0x1f004,
2657	.hwcg_bit = 1,
2658	.clkr = {
2659		.enable_reg = 0x7900c,
2660		.enable_mask = BIT(6),
2661		.hw.init = &(struct clk_init_data){
2662			.name = "gcc_qupv3_wrap_0_m_ahb_clk",
2663			.ops = &clk_branch2_ops,
2664		},
2665	},
2666};
2667
2668static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
2669	.halt_reg = 0x1f008,
2670	.halt_check = BRANCH_HALT_VOTED,
2671	.hwcg_reg = 0x1f008,
2672	.hwcg_bit = 1,
2673	.clkr = {
2674		.enable_reg = 0x7900c,
2675		.enable_mask = BIT(7),
2676		.hw.init = &(struct clk_init_data){
2677			.name = "gcc_qupv3_wrap_0_s_ahb_clk",
2678			.ops = &clk_branch2_ops,
2679		},
2680	},
2681};
2682
2683static struct clk_branch gcc_sdcc1_ahb_clk = {
2684	.halt_reg = 0x38008,
2685	.halt_check = BRANCH_HALT,
2686	.clkr = {
2687		.enable_reg = 0x38008,
2688		.enable_mask = BIT(0),
2689		.hw.init = &(struct clk_init_data){
2690			.name = "gcc_sdcc1_ahb_clk",
2691			.ops = &clk_branch2_ops,
2692		},
2693	},
2694};
2695
2696static struct clk_branch gcc_sdcc1_apps_clk = {
2697	.halt_reg = 0x38004,
2698	.halt_check = BRANCH_HALT,
2699	.clkr = {
2700		.enable_reg = 0x38004,
2701		.enable_mask = BIT(0),
2702		.hw.init = &(struct clk_init_data){
2703			.name = "gcc_sdcc1_apps_clk",
2704			.parent_hws = (const struct clk_hw *[]){
2705				&gcc_sdcc1_apps_clk_src.clkr.hw,
2706			},
2707			.num_parents = 1,
2708			.flags = CLK_SET_RATE_PARENT /* | CLK_ENABLE_HAND_OFF */,
2709			.ops = &clk_branch2_ops,
2710		},
2711	},
2712};
2713
2714static struct clk_branch gcc_sdcc1_ice_core_clk = {
2715	.halt_reg = 0x3800c,
2716	.halt_check = BRANCH_HALT,
2717	.hwcg_reg = 0x3800c,
2718	.hwcg_bit = 1,
2719	.clkr = {
2720		.enable_reg = 0x3800c,
2721		.enable_mask = BIT(0),
2722		.hw.init = &(struct clk_init_data){
2723			.name = "gcc_sdcc1_ice_core_clk",
2724			.parent_hws = (const struct clk_hw *[]){
2725				&gcc_sdcc1_ice_core_clk_src.clkr.hw,
2726			},
2727			.num_parents = 1,
2728			.flags = CLK_SET_RATE_PARENT,
2729			.ops = &clk_branch2_ops,
2730		},
2731	},
2732};
2733
2734static struct clk_branch gcc_sdcc2_ahb_clk = {
2735	.halt_reg = 0x1e008,
2736	.halt_check = BRANCH_HALT,
2737	.clkr = {
2738		.enable_reg = 0x1e008,
2739		.enable_mask = BIT(0),
2740		.hw.init = &(struct clk_init_data){
2741			.name = "gcc_sdcc2_ahb_clk",
2742			.ops = &clk_branch2_ops,
2743		},
2744	},
2745};
2746
2747static struct clk_branch gcc_sdcc2_apps_clk = {
2748	.halt_reg = 0x1e004,
2749	.halt_check = BRANCH_HALT,
2750	.clkr = {
2751		.enable_reg = 0x1e004,
2752		.enable_mask = BIT(0),
2753		.hw.init = &(struct clk_init_data){
2754			.name = "gcc_sdcc2_apps_clk",
2755			.parent_hws = (const struct clk_hw *[]){
2756				&gcc_sdcc2_apps_clk_src.clkr.hw,
2757			},
2758			.num_parents = 1,
2759			.flags = CLK_SET_RATE_PARENT,
2760			.ops = &clk_branch2_ops,
2761		},
2762	},
2763};
2764
2765static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
2766	.halt_reg = 0x2b06c,
2767	.halt_check = BRANCH_HALT_VOTED,
2768	.hwcg_reg = 0x2b06c,
2769	.hwcg_bit = 1,
2770	.clkr = {
2771		.enable_reg = 0x79004,
2772		.enable_mask = BIT(0),
2773		.hw.init = &(struct clk_init_data){
2774			.name = "gcc_sys_noc_cpuss_ahb_clk",
2775			.flags = CLK_IS_CRITICAL,
2776			.ops = &clk_branch2_ops,
2777		},
2778	},
2779};
2780
2781static struct clk_branch gcc_sys_noc_ufs_phy_axi_clk = {
2782	.halt_reg = 0x45098,
2783	.halt_check = BRANCH_HALT,
2784	.clkr = {
2785		.enable_reg = 0x45098,
2786		.enable_mask = BIT(0),
2787		.hw.init = &(struct clk_init_data){
2788			.name = "gcc_sys_noc_ufs_phy_axi_clk",
2789			.parent_hws = (const struct clk_hw *[]){
2790				&gcc_ufs_phy_axi_clk_src.clkr.hw,
2791			},
2792			.num_parents = 1,
2793			.flags = CLK_SET_RATE_PARENT,
2794			.ops = &clk_branch2_ops,
2795		},
2796	},
2797};
2798
2799static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk = {
2800	.halt_reg = 0x1a080,
2801	.halt_check = BRANCH_HALT,
2802	.hwcg_reg = 0x1a080,
2803	.hwcg_bit = 1,
2804	.clkr = {
2805		.enable_reg = 0x1a080,
2806		.enable_mask = BIT(0),
2807		.hw.init = &(struct clk_init_data){
2808			.name = "gcc_sys_noc_usb3_prim_axi_clk",
2809			.parent_hws = (const struct clk_hw *[]){
2810				&gcc_usb30_prim_master_clk_src.clkr.hw,
2811			},
2812			.num_parents = 1,
2813			.flags = CLK_SET_RATE_PARENT,
2814			.ops = &clk_branch2_ops,
2815		},
2816	},
2817};
2818
2819static struct clk_branch gcc_ufs_clkref_clk = {
2820	.halt_reg = 0x8c000,
2821	.halt_check = BRANCH_HALT,
2822	.clkr = {
2823		.enable_reg = 0x8c000,
2824		.enable_mask = BIT(0),
2825		.hw.init = &(struct clk_init_data){
2826			.name = "gcc_ufs_clkref_clk",
2827			.ops = &clk_branch2_ops,
2828		},
2829	},
2830};
2831
2832static struct clk_branch gcc_ufs_phy_ahb_clk = {
2833	.halt_reg = 0x45014,
2834	.halt_check = BRANCH_HALT,
2835	.hwcg_reg = 0x45014,
2836	.hwcg_bit = 1,
2837	.clkr = {
2838		.enable_reg = 0x45014,
2839		.enable_mask = BIT(0),
2840		.hw.init = &(struct clk_init_data){
2841			.name = "gcc_ufs_phy_ahb_clk",
2842			.ops = &clk_branch2_ops,
2843		},
2844	},
2845};
2846
2847static struct clk_branch gcc_ufs_phy_axi_clk = {
2848	.halt_reg = 0x45010,
2849	.halt_check = BRANCH_HALT,
2850	.hwcg_reg = 0x45010,
2851	.hwcg_bit = 1,
2852	.clkr = {
2853		.enable_reg = 0x45010,
2854		.enable_mask = BIT(0),
2855		.hw.init = &(struct clk_init_data){
2856			.name = "gcc_ufs_phy_axi_clk",
2857			.parent_hws = (const struct clk_hw *[]){
2858				&gcc_ufs_phy_axi_clk_src.clkr.hw,
2859			},
2860			.num_parents = 1,
2861			.flags = CLK_SET_RATE_PARENT,
2862			.ops = &clk_branch2_ops,
2863		},
2864	},
2865};
2866
2867static struct clk_branch gcc_ufs_phy_ice_core_clk = {
2868	.halt_reg = 0x45044,
2869	.halt_check = BRANCH_HALT,
2870	.hwcg_reg = 0x45044,
2871	.hwcg_bit = 1,
2872	.clkr = {
2873		.enable_reg = 0x45044,
2874		.enable_mask = BIT(0),
2875		.hw.init = &(struct clk_init_data){
2876			.name = "gcc_ufs_phy_ice_core_clk",
2877			.parent_hws = (const struct clk_hw *[]){
2878				&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
2879			},
2880			.num_parents = 1,
2881			.flags = CLK_SET_RATE_PARENT,
2882			.ops = &clk_branch2_ops,
2883		},
2884	},
2885};
2886
2887static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
2888	.halt_reg = 0x45078,
2889	.halt_check = BRANCH_HALT,
2890	.hwcg_reg = 0x45078,
2891	.hwcg_bit = 1,
2892	.clkr = {
2893		.enable_reg = 0x45078,
2894		.enable_mask = BIT(0),
2895		.hw.init = &(struct clk_init_data){
2896			.name = "gcc_ufs_phy_phy_aux_clk",
2897			.parent_hws = (const struct clk_hw *[]){
2898				&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
2899			},
2900			.num_parents = 1,
2901			.flags = CLK_SET_RATE_PARENT,
2902			.ops = &clk_branch2_ops,
2903		},
2904	},
2905};
2906
2907static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
2908	.halt_reg = 0x4501c,
2909	.halt_check = BRANCH_HALT_SKIP,
2910	.clkr = {
2911		.enable_reg = 0x4501c,
2912		.enable_mask = BIT(0),
2913		.hw.init = &(struct clk_init_data){
2914			.name = "gcc_ufs_phy_rx_symbol_0_clk",
2915			.ops = &clk_branch2_ops,
2916		},
2917	},
2918};
2919
2920static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
2921	.halt_reg = 0x45018,
2922	.halt_check = BRANCH_HALT_SKIP,
2923	.clkr = {
2924		.enable_reg = 0x45018,
2925		.enable_mask = BIT(0),
2926		.hw.init = &(struct clk_init_data){
2927			.name = "gcc_ufs_phy_tx_symbol_0_clk",
2928			.ops = &clk_branch2_ops,
2929		},
2930	},
2931};
2932
2933static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
2934	.halt_reg = 0x45040,
2935	.halt_check = BRANCH_HALT,
2936	.hwcg_reg = 0x45040,
2937	.hwcg_bit = 1,
2938	.clkr = {
2939		.enable_reg = 0x45040,
2940		.enable_mask = BIT(0),
2941		.hw.init = &(struct clk_init_data){
2942			.name = "gcc_ufs_phy_unipro_core_clk",
2943			.parent_hws = (const struct clk_hw *[]){
2944				&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
2945			},
2946			.num_parents = 1,
2947			.flags = CLK_SET_RATE_PARENT,
2948			.ops = &clk_branch2_ops,
2949		},
2950	},
2951};
2952
2953static struct clk_branch gcc_usb30_prim_master_clk = {
2954	.halt_reg = 0x1a010,
2955	.halt_check = BRANCH_HALT,
2956	.clkr = {
2957		.enable_reg = 0x1a010,
2958		.enable_mask = BIT(0),
2959		.hw.init = &(struct clk_init_data){
2960			.name = "gcc_usb30_prim_master_clk",
2961			.parent_hws = (const struct clk_hw *[]){
2962				&gcc_usb30_prim_master_clk_src.clkr.hw,
2963			},
2964			.num_parents = 1,
2965			.flags = CLK_SET_RATE_PARENT,
2966			.ops = &clk_branch2_ops,
2967		},
2968	},
2969};
2970
2971static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
2972	.halt_reg = 0x1a018,
2973	.halt_check = BRANCH_HALT,
2974	.clkr = {
2975		.enable_reg = 0x1a018,
2976		.enable_mask = BIT(0),
2977		.hw.init = &(struct clk_init_data){
2978			.name = "gcc_usb30_prim_mock_utmi_clk",
2979			.parent_hws = (const struct clk_hw *[]){
2980				&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
2981			},
2982			.num_parents = 1,
2983			.flags = CLK_SET_RATE_PARENT,
2984			.ops = &clk_branch2_ops,
2985		},
2986	},
2987};
2988
2989static struct clk_branch gcc_usb30_prim_sleep_clk = {
2990	.halt_reg = 0x1a014,
2991	.halt_check = BRANCH_HALT,
2992	.clkr = {
2993		.enable_reg = 0x1a014,
2994		.enable_mask = BIT(0),
2995		.hw.init = &(struct clk_init_data){
2996			.name = "gcc_usb30_prim_sleep_clk",
2997			.ops = &clk_branch2_ops,
2998		},
2999	},
3000};
3001
3002static struct clk_branch gcc_usb3_prim_clkref_clk = {
3003	.halt_reg = 0x9f000,
3004	.halt_check = BRANCH_HALT,
3005	.clkr = {
3006		.enable_reg = 0x9f000,
3007		.enable_mask = BIT(0),
3008		.hw.init = &(struct clk_init_data){
3009			.name = "gcc_usb3_prim_clkref_clk",
3010			.ops = &clk_branch2_ops,
3011		},
3012	},
3013};
3014
3015static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
3016	.halt_reg = 0x1a054,
3017	.halt_check = BRANCH_HALT,
3018	.clkr = {
3019		.enable_reg = 0x1a054,
3020		.enable_mask = BIT(0),
3021		.hw.init = &(struct clk_init_data){
3022			.name = "gcc_usb3_prim_phy_com_aux_clk",
3023			.parent_hws = (const struct clk_hw *[]){
3024				&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
3025			},
3026			.num_parents = 1,
3027			.flags = CLK_SET_RATE_PARENT,
3028			.ops = &clk_branch2_ops,
3029		},
3030	},
3031};
3032
3033static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
3034	.halt_reg = 0x1a058,
3035	.halt_check = BRANCH_HALT_SKIP,
3036	.hwcg_reg = 0x1a058,
3037	.hwcg_bit = 1,
3038	.clkr = {
3039		.enable_reg = 0x1a058,
3040		.enable_mask = BIT(0),
3041		.hw.init = &(struct clk_init_data){
3042			.name = "gcc_usb3_prim_phy_pipe_clk",
3043			.ops = &clk_branch2_ops,
3044		},
3045	},
3046};
3047
3048static struct clk_branch gcc_vcodec0_axi_clk = {
3049	.halt_reg = 0x6e008,
3050	.halt_check = BRANCH_HALT,
3051	.clkr = {
3052		.enable_reg = 0x6e008,
3053		.enable_mask = BIT(0),
3054		.hw.init = &(struct clk_init_data){
3055			.name = "gcc_vcodec0_axi_clk",
3056			.ops = &clk_branch2_ops,
3057		},
3058	},
3059};
3060
3061static struct clk_branch gcc_venus_ahb_clk = {
3062	.halt_reg = 0x6e010,
3063	.halt_check = BRANCH_HALT,
3064	.clkr = {
3065		.enable_reg = 0x6e010,
3066		.enable_mask = BIT(0),
3067		.hw.init = &(struct clk_init_data){
3068			.name = "gcc_venus_ahb_clk",
3069			.ops = &clk_branch2_ops,
3070		},
3071	},
3072};
3073
3074static struct clk_branch gcc_venus_ctl_axi_clk = {
3075	.halt_reg = 0x6e004,
3076	.halt_check = BRANCH_HALT,
3077	.clkr = {
3078		.enable_reg = 0x6e004,
3079		.enable_mask = BIT(0),
3080		.hw.init = &(struct clk_init_data){
3081			.name = "gcc_venus_ctl_axi_clk",
3082			.ops = &clk_branch2_ops,
3083		},
3084	},
3085};
3086
3087static struct clk_branch gcc_video_ahb_clk = {
3088	.halt_reg = 0x17004,
3089	.halt_check = BRANCH_HALT,
3090	.hwcg_reg = 0x17004,
3091	.hwcg_bit = 1,
3092	.clkr = {
3093		.enable_reg = 0x17004,
3094		.enable_mask = BIT(0),
3095		.hw.init = &(struct clk_init_data){
3096			.name = "gcc_video_ahb_clk",
3097			.ops = &clk_branch2_ops,
3098		},
3099	},
3100};
3101
3102static struct clk_branch gcc_video_axi0_clk = {
3103	.halt_reg = 0x1701c,
3104	.halt_check = BRANCH_HALT,
3105	.hwcg_reg = 0x1701c,
3106	.hwcg_bit = 1,
3107	.clkr = {
3108		.enable_reg = 0x1701c,
3109		.enable_mask = BIT(0),
3110		.hw.init = &(struct clk_init_data){
3111			.name = "gcc_video_axi0_clk",
3112			.ops = &clk_branch2_ops,
3113		},
3114	},
3115};
3116
3117static struct clk_branch gcc_video_throttle_core_clk = {
3118	.halt_reg = 0x17068,
3119	.halt_check = BRANCH_HALT_VOTED,
3120	.hwcg_reg = 0x17068,
3121	.hwcg_bit = 1,
3122	.clkr = {
3123		.enable_reg = 0x79004,
3124		.enable_mask = BIT(28),
3125		.hw.init = &(struct clk_init_data){
3126			.name = "gcc_video_throttle_core_clk",
3127			.ops = &clk_branch2_ops,
3128		},
3129	},
3130};
3131
3132static struct clk_branch gcc_video_vcodec0_sys_clk = {
3133	.halt_reg = 0x580a4,
3134	.halt_check = BRANCH_HALT_DELAY,
3135	.hwcg_reg = 0x580a4,
3136	.hwcg_bit = 1,
3137	.clkr = {
3138		.enable_reg = 0x580a4,
3139		.enable_mask = BIT(0),
3140		.hw.init = &(struct clk_init_data){
3141			.name = "gcc_video_vcodec0_sys_clk",
3142			.parent_hws = (const struct clk_hw *[]){
3143				&gcc_video_venus_clk_src.clkr.hw,
3144			},
3145			.num_parents = 1,
3146			.flags = CLK_SET_RATE_PARENT,
3147			.ops = &clk_branch2_ops,
3148		},
3149	},
3150};
3151
3152static struct clk_branch gcc_video_venus_ctl_clk = {
3153	.halt_reg = 0x5808c,
3154	.halt_check = BRANCH_HALT,
3155	.clkr = {
3156		.enable_reg = 0x5808c,
3157		.enable_mask = BIT(0),
3158		.hw.init = &(struct clk_init_data){
3159			.name = "gcc_video_venus_ctl_clk",
3160			.parent_hws = (const struct clk_hw *[]){
3161				&gcc_video_venus_clk_src.clkr.hw,
3162			},
3163			.num_parents = 1,
3164			.flags = CLK_SET_RATE_PARENT,
3165			.ops = &clk_branch2_ops,
3166		},
3167	},
3168};
3169
3170static struct clk_branch gcc_video_xo_clk = {
3171	.halt_reg = 0x17024,
3172	.halt_check = BRANCH_HALT,
3173	.clkr = {
3174		.enable_reg = 0x17024,
3175		.enable_mask = BIT(0),
3176		.hw.init = &(struct clk_init_data){
3177			.name = "gcc_video_xo_clk",
3178			.ops = &clk_branch2_ops,
3179		},
3180	},
3181};
3182
3183static struct gdsc gcc_camss_top_gdsc = {
3184	.gdscr = 0x58004,
3185	.pd = {
3186		.name = "gcc_camss_top",
3187	},
3188	.pwrsts = PWRSTS_OFF_ON,
3189};
3190
3191static struct gdsc gcc_ufs_phy_gdsc = {
3192	.gdscr = 0x45004,
3193	.pd = {
3194		.name = "gcc_ufs_phy",
3195	},
3196	.pwrsts = PWRSTS_OFF_ON,
3197};
3198
3199static struct gdsc gcc_usb30_prim_gdsc = {
3200	.gdscr = 0x1a004,
3201	.pd = {
3202		.name = "gcc_usb30_prim",
3203	},
3204	.pwrsts = PWRSTS_OFF_ON,
3205};
3206
3207static struct gdsc gcc_vcodec0_gdsc = {
3208	.gdscr = 0x58098,
3209	.pd = {
3210		.name = "gcc_vcodec0",
3211	},
3212	.pwrsts = PWRSTS_OFF_ON,
3213};
3214
3215static struct gdsc gcc_venus_gdsc = {
3216	.gdscr = 0x5807c,
3217	.pd = {
3218		.name = "gcc_venus",
3219	},
3220	.pwrsts = PWRSTS_OFF_ON,
3221};
3222
3223static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = {
3224	.gdscr = 0x7d060,
3225	.pd = {
3226		.name = "hlos1_vote_turing_mmu_tbu1",
3227	},
3228	.pwrsts = PWRSTS_OFF_ON,
3229	.flags = VOTABLE,
3230};
3231
3232static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = {
3233	.gdscr = 0x7d07c,
3234	.pd = {
3235		.name = "hlos1_vote_turing_mmu_tbu0",
3236	},
3237	.pwrsts = PWRSTS_OFF_ON,
3238	.flags = VOTABLE,
3239};
3240
3241static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc = {
3242	.gdscr = 0x7d074,
3243	.pd = {
3244		.name = "hlos1_vote_mm_snoc_mmu_tbu_rt",
3245	},
3246	.pwrsts = PWRSTS_OFF_ON,
3247	.flags = VOTABLE,
3248};
3249
3250static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc = {
3251	.gdscr = 0x7d078,
3252	.pd = {
3253		.name = "hlos1_vote_mm_snoc_mmu_tbu_nrt",
3254	},
3255	.pwrsts = PWRSTS_OFF_ON,
3256	.flags = VOTABLE,
3257};
3258
3259static struct clk_regmap *gcc_sm6115_clocks[] = {
3260	[GCC_AHB2PHY_CSI_CLK] = &gcc_ahb2phy_csi_clk.clkr,
3261	[GCC_AHB2PHY_USB_CLK] = &gcc_ahb2phy_usb_clk.clkr,
3262	[GCC_BIMC_GPU_AXI_CLK] = &gcc_bimc_gpu_axi_clk.clkr,
3263	[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3264	[GCC_CAM_THROTTLE_NRT_CLK] = &gcc_cam_throttle_nrt_clk.clkr,
3265	[GCC_CAM_THROTTLE_RT_CLK] = &gcc_cam_throttle_rt_clk.clkr,
3266	[GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
3267	[GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
3268	[GCC_CAMSS_AXI_CLK] = &gcc_camss_axi_clk.clkr,
3269	[GCC_CAMSS_AXI_CLK_SRC] = &gcc_camss_axi_clk_src.clkr,
3270	[GCC_CAMSS_CAMNOC_ATB_CLK] = &gcc_camss_camnoc_atb_clk.clkr,
3271	[GCC_CAMSS_CAMNOC_NTS_XO_CLK] = &gcc_camss_camnoc_nts_xo_clk.clkr,
3272	[GCC_CAMSS_CCI_0_CLK] = &gcc_camss_cci_0_clk.clkr,
3273	[GCC_CAMSS_CCI_CLK_SRC] = &gcc_camss_cci_clk_src.clkr,
3274	[GCC_CAMSS_CPHY_0_CLK] = &gcc_camss_cphy_0_clk.clkr,
3275	[GCC_CAMSS_CPHY_1_CLK] = &gcc_camss_cphy_1_clk.clkr,
3276	[GCC_CAMSS_CPHY_2_CLK] = &gcc_camss_cphy_2_clk.clkr,
3277	[GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
3278	[GCC_CAMSS_CSI0PHYTIMER_CLK_SRC] = &gcc_camss_csi0phytimer_clk_src.clkr,
3279	[GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
3280	[GCC_CAMSS_CSI1PHYTIMER_CLK_SRC] = &gcc_camss_csi1phytimer_clk_src.clkr,
3281	[GCC_CAMSS_CSI2PHYTIMER_CLK] = &gcc_camss_csi2phytimer_clk.clkr,
3282	[GCC_CAMSS_CSI2PHYTIMER_CLK_SRC] = &gcc_camss_csi2phytimer_clk_src.clkr,
3283	[GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
3284	[GCC_CAMSS_MCLK0_CLK_SRC] = &gcc_camss_mclk0_clk_src.clkr,
3285	[GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
3286	[GCC_CAMSS_MCLK1_CLK_SRC] = &gcc_camss_mclk1_clk_src.clkr,
3287	[GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr,
3288	[GCC_CAMSS_MCLK2_CLK_SRC] = &gcc_camss_mclk2_clk_src.clkr,
3289	[GCC_CAMSS_MCLK3_CLK] = &gcc_camss_mclk3_clk.clkr,
3290	[GCC_CAMSS_MCLK3_CLK_SRC] = &gcc_camss_mclk3_clk_src.clkr,
3291	[GCC_CAMSS_NRT_AXI_CLK] = &gcc_camss_nrt_axi_clk.clkr,
3292	[GCC_CAMSS_OPE_AHB_CLK] = &gcc_camss_ope_ahb_clk.clkr,
3293	[GCC_CAMSS_OPE_AHB_CLK_SRC] = &gcc_camss_ope_ahb_clk_src.clkr,
3294	[GCC_CAMSS_OPE_CLK] = &gcc_camss_ope_clk.clkr,
3295	[GCC_CAMSS_OPE_CLK_SRC] = &gcc_camss_ope_clk_src.clkr,
3296	[GCC_CAMSS_RT_AXI_CLK] = &gcc_camss_rt_axi_clk.clkr,
3297	[GCC_CAMSS_TFE_0_CLK] = &gcc_camss_tfe_0_clk.clkr,
3298	[GCC_CAMSS_TFE_0_CLK_SRC] = &gcc_camss_tfe_0_clk_src.clkr,
3299	[GCC_CAMSS_TFE_0_CPHY_RX_CLK] = &gcc_camss_tfe_0_cphy_rx_clk.clkr,
3300	[GCC_CAMSS_TFE_0_CSID_CLK] = &gcc_camss_tfe_0_csid_clk.clkr,
3301	[GCC_CAMSS_TFE_0_CSID_CLK_SRC] = &gcc_camss_tfe_0_csid_clk_src.clkr,
3302	[GCC_CAMSS_TFE_1_CLK] = &gcc_camss_tfe_1_clk.clkr,
3303	[GCC_CAMSS_TFE_1_CLK_SRC] = &gcc_camss_tfe_1_clk_src.clkr,
3304	[GCC_CAMSS_TFE_1_CPHY_RX_CLK] = &gcc_camss_tfe_1_cphy_rx_clk.clkr,
3305	[GCC_CAMSS_TFE_1_CSID_CLK] = &gcc_camss_tfe_1_csid_clk.clkr,
3306	[GCC_CAMSS_TFE_1_CSID_CLK_SRC] = &gcc_camss_tfe_1_csid_clk_src.clkr,
3307	[GCC_CAMSS_TFE_2_CLK] = &gcc_camss_tfe_2_clk.clkr,
3308	[GCC_CAMSS_TFE_2_CLK_SRC] = &gcc_camss_tfe_2_clk_src.clkr,
3309	[GCC_CAMSS_TFE_2_CPHY_RX_CLK] = &gcc_camss_tfe_2_cphy_rx_clk.clkr,
3310	[GCC_CAMSS_TFE_2_CSID_CLK] = &gcc_camss_tfe_2_csid_clk.clkr,
3311	[GCC_CAMSS_TFE_2_CSID_CLK_SRC] = &gcc_camss_tfe_2_csid_clk_src.clkr,
3312	[GCC_CAMSS_TFE_CPHY_RX_CLK_SRC] = &gcc_camss_tfe_cphy_rx_clk_src.clkr,
3313	[GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
3314	[GCC_CAMSS_TOP_AHB_CLK_SRC] = &gcc_camss_top_ahb_clk_src.clkr,
3315	[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
3316	[GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
3317	[GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
3318	[GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
3319	[GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
3320	[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
3321	[GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr,
3322	[GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
3323	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3324	[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3325	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3326	[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3327	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3328	[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
3329	[GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
3330	[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
3331	[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
3332	[GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,
3333	[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
3334	[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
3335	[GCC_GPU_THROTTLE_CORE_CLK] = &gcc_gpu_throttle_core_clk.clkr,
3336	[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3337	[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3338	[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3339	[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3340	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3341	[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
3342	[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
3343	[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3344	[GCC_QMIP_GPU_CFG_AHB_CLK] = &gcc_qmip_gpu_cfg_ahb_clk.clkr,
3345	[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
3346	[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
3347	[GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
3348	[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
3349	[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
3350	[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
3351	[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
3352	[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
3353	[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
3354	[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
3355	[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
3356	[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
3357	[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
3358	[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
3359	[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
3360	[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
3361	[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
3362	[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3363	[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3364	[GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
3365	[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
3366	[GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
3367	[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3368	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3369	[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
3370	[GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
3371	[GCC_SYS_NOC_UFS_PHY_AXI_CLK] = &gcc_sys_noc_ufs_phy_axi_clk.clkr,
3372	[GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr,
3373	[GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
3374	[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
3375	[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
3376	[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
3377	[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
3378	[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
3379	[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
3380	[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
3381	[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
3382	[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
3383	[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
3384	[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
3385		&gcc_ufs_phy_unipro_core_clk_src.clkr,
3386	[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
3387	[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
3388	[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
3389	[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
3390		&gcc_usb30_prim_mock_utmi_clk_src.clkr,
3391	[GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] =
3392		&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
3393	[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
3394	[GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
3395	[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
3396	[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
3397	[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
3398	[GCC_VCODEC0_AXI_CLK] = &gcc_vcodec0_axi_clk.clkr,
3399	[GCC_VENUS_AHB_CLK] = &gcc_venus_ahb_clk.clkr,
3400	[GCC_VENUS_CTL_AXI_CLK] = &gcc_venus_ctl_axi_clk.clkr,
3401	[GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
3402	[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
3403	[GCC_VIDEO_THROTTLE_CORE_CLK] = &gcc_video_throttle_core_clk.clkr,
3404	[GCC_VIDEO_VCODEC0_SYS_CLK] = &gcc_video_vcodec0_sys_clk.clkr,
3405	[GCC_VIDEO_VENUS_CLK_SRC] = &gcc_video_venus_clk_src.clkr,
3406	[GCC_VIDEO_VENUS_CTL_CLK] = &gcc_video_venus_ctl_clk.clkr,
3407	[GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
3408	[GPLL0] = &gpll0.clkr,
3409	[GPLL0_OUT_AUX2] = &gpll0_out_aux2.clkr,
3410	[GPLL0_OUT_MAIN] = &gpll0_out_main.clkr,
3411	[GPLL10] = &gpll10.clkr,
3412	[GPLL10_OUT_MAIN] = &gpll10_out_main.clkr,
3413	[GPLL11] = &gpll11.clkr,
3414	[GPLL11_OUT_MAIN] = &gpll11_out_main.clkr,
3415	[GPLL3] = &gpll3.clkr,
3416	[GPLL4] = &gpll4.clkr,
3417	[GPLL4_OUT_MAIN] = &gpll4_out_main.clkr,
3418	[GPLL6] = &gpll6.clkr,
3419	[GPLL6_OUT_MAIN] = &gpll6_out_main.clkr,
3420	[GPLL7] = &gpll7.clkr,
3421	[GPLL7_OUT_MAIN] = &gpll7_out_main.clkr,
3422	[GPLL8] = &gpll8.clkr,
3423	[GPLL8_OUT_MAIN] = &gpll8_out_main.clkr,
3424	[GPLL9] = &gpll9.clkr,
3425	[GPLL9_OUT_MAIN] = &gpll9_out_main.clkr,
3426};
3427
3428static const struct qcom_reset_map gcc_sm6115_resets[] = {
3429	[GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 },
3430	[GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 },
3431	[GCC_SDCC1_BCR] = { 0x38000 },
3432	[GCC_SDCC2_BCR] = { 0x1e000 },
3433	[GCC_UFS_PHY_BCR] = { 0x45000 },
3434	[GCC_USB30_PRIM_BCR] = { 0x1a000 },
3435	[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 },
3436	[GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 },
3437	[GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 },
3438	[GCC_VCODEC0_BCR] = { 0x58094 },
3439	[GCC_VENUS_BCR] = { 0x58078 },
3440	[GCC_VIDEO_INTERFACE_BCR] = { 0x6e000 },
3441};
3442
3443static struct gdsc *gcc_sm6115_gdscs[] = {
3444	[GCC_CAMSS_TOP_GDSC] = &gcc_camss_top_gdsc,
3445	[GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc,
3446	[GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc,
3447	[GCC_VCODEC0_GDSC] = &gcc_vcodec0_gdsc,
3448	[GCC_VENUS_GDSC] = &gcc_venus_gdsc,
3449	[HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc,
3450	[HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc,
3451	[HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc,
3452	[HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc,
3453};
3454
3455static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
3456	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
3457	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
3458	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
3459	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
3460	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
3461	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
3462};
3463
3464static const struct regmap_config gcc_sm6115_regmap_config = {
3465	.reg_bits = 32,
3466	.reg_stride = 4,
3467	.val_bits = 32,
3468	.max_register = 0xc7000,
3469	.fast_io = true,
3470};
3471
3472static const struct qcom_cc_desc gcc_sm6115_desc = {
3473	.config = &gcc_sm6115_regmap_config,
3474	.clks = gcc_sm6115_clocks,
3475	.num_clks = ARRAY_SIZE(gcc_sm6115_clocks),
3476	.resets = gcc_sm6115_resets,
3477	.num_resets = ARRAY_SIZE(gcc_sm6115_resets),
3478	.gdscs = gcc_sm6115_gdscs,
3479	.num_gdscs = ARRAY_SIZE(gcc_sm6115_gdscs),
3480};
3481
3482static const struct of_device_id gcc_sm6115_match_table[] = {
3483	{ .compatible = "qcom,gcc-sm6115" },
3484	{ }
3485};
3486MODULE_DEVICE_TABLE(of, gcc_sm6115_match_table);
3487
3488static int gcc_sm6115_probe(struct platform_device *pdev)
3489{
3490	struct regmap *regmap;
3491	int ret;
3492
3493	regmap = qcom_cc_map(pdev, &gcc_sm6115_desc);
3494	if (IS_ERR(regmap))
3495		return PTR_ERR(regmap);
3496
3497	ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
3498			ARRAY_SIZE(gcc_dfs_clocks));
3499	if (ret)
3500		return ret;
3501
3502	clk_alpha_pll_configure(&gpll8, regmap, &gpll8_config);
3503	clk_alpha_pll_configure(&gpll9, regmap, &gpll9_config);
3504	clk_alpha_pll_configure(&gpll10, regmap, &gpll10_config);
3505	clk_alpha_pll_configure(&gpll11, regmap, &gpll11_config);
3506
3507	return qcom_cc_really_probe(pdev, &gcc_sm6115_desc, regmap);
3508}
3509
3510static struct platform_driver gcc_sm6115_driver = {
3511	.probe = gcc_sm6115_probe,
3512	.driver = {
3513		.name = "gcc-sm6115",
3514		.of_match_table = gcc_sm6115_match_table,
3515	},
3516};
3517
3518static int __init gcc_sm6115_init(void)
3519{
3520	return platform_driver_register(&gcc_sm6115_driver);
3521}
3522subsys_initcall(gcc_sm6115_init);
3523
3524static void __exit gcc_sm6115_exit(void)
3525{
3526	platform_driver_unregister(&gcc_sm6115_driver);
3527}
3528module_exit(gcc_sm6115_exit);
3529
3530MODULE_DESCRIPTION("QTI GCC SM6115 and SM4250 Driver");
3531MODULE_LICENSE("GPL v2");
3532MODULE_ALIAS("platform:gcc-sm6115");