1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
   4 * Copyright (c) 2020-2021, Linaro Ltd.
   5 */
   6
   7#include <linux/bitops.h>
   8#include <linux/clk-provider.h>
   9#include <linux/err.h>
  10#include <linux/kernel.h>
  11#include <linux/module.h>
  12#include <linux/of.h>
  13#include <linux/of_device.h>
  14#include <linux/platform_device.h>
  15#include <linux/regmap.h>
  16#include <linux/reset-controller.h>
  17
  18#include <dt-bindings/clock/qcom,gcc-sc8180x.h>
  19
  20#include "common.h"
  21#include "clk-alpha-pll.h"
  22#include "clk-branch.h"
  23#include "clk-pll.h"
  24#include "clk-rcg.h"
  25#include "clk-regmap.h"
  26#include "gdsc.h"
  27#include "reset.h"
  28
  29enum {
  30	P_AUD_REF_CLK,
  31	P_BI_TCXO,
  32	P_GPLL0_OUT_EVEN,
  33	P_GPLL0_OUT_MAIN,
  34	P_GPLL1_OUT_MAIN,
  35	P_GPLL2_OUT_MAIN,
  36	P_GPLL4_OUT_MAIN,
  37	P_GPLL5_OUT_MAIN,
  38	P_GPLL7_OUT_MAIN,
  39	P_GPLL9_OUT_MAIN,
  40	P_SLEEP_CLK,
  41};
  42
  43static struct pll_vco trion_vco[] = {
  44	{ 249600000, 2000000000, 0 },
  45};
  46
  47static struct clk_alpha_pll gpll0 = {
  48	.offset = 0x0,
  49	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
  50	.vco_table = trion_vco,
  51	.num_vco = ARRAY_SIZE(trion_vco),
  52	.clkr = {
  53		.enable_reg = 0x52000,
  54		.enable_mask = BIT(0),
  55		.hw.init = &(struct clk_init_data){
  56			.name = "gpll0",
  57			.parent_data = &(const struct clk_parent_data){
  58				.fw_name = "bi_tcxo",
  59			},
  60			.num_parents = 1,
  61			.ops = &clk_alpha_pll_fixed_trion_ops,
  62		},
  63	},
  64};
  65
  66static const struct clk_div_table post_div_table_trion_even[] = {
  67	{ 0x0, 1 },
  68	{ 0x1, 2 },
  69	{ 0x3, 4 },
  70	{ 0x7, 8 },
  71	{ }
  72};
  73
  74static struct clk_alpha_pll_postdiv gpll0_out_even = {
  75	.offset = 0x0,
  76	.post_div_shift = 8,
  77	.post_div_table = post_div_table_trion_even,
  78	.num_post_div = ARRAY_SIZE(post_div_table_trion_even),
  79	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
  80	.width = 4,
  81	.clkr.hw.init = &(struct clk_init_data){
  82		.name = "gpll0_out_even",
  83		.parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
  84		.num_parents = 1,
  85		.ops = &clk_alpha_pll_postdiv_trion_ops,
  86	},
  87};
  88
  89static struct clk_alpha_pll gpll1 = {
  90	.offset = 0x1000,
  91	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
  92	.vco_table = trion_vco,
  93	.num_vco = ARRAY_SIZE(trion_vco),
  94	.clkr = {
  95		.enable_reg = 0x52000,
  96		.enable_mask = BIT(1),
  97		.hw.init = &(struct clk_init_data){
  98			.name = "gpll1",
  99			.parent_data = &(const struct clk_parent_data){
 100				.fw_name = "bi_tcxo",
 101			},
 102			.num_parents = 1,
 103			.ops = &clk_alpha_pll_fixed_trion_ops,
 104		},
 105	},
 106};
 107
 108static struct clk_alpha_pll gpll4 = {
 109	.offset = 0x76000,
 110	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
 111	.vco_table = trion_vco,
 112	.num_vco = ARRAY_SIZE(trion_vco),
 113	.clkr = {
 114		.enable_reg = 0x52000,
 115		.enable_mask = BIT(4),
 116		.hw.init = &(struct clk_init_data){
 117			.name = "gpll4",
 118			.parent_data = &(const struct clk_parent_data){
 119				.fw_name = "bi_tcxo",
 120			},
 121			.num_parents = 1,
 122			.ops = &clk_alpha_pll_fixed_trion_ops,
 123		},
 124	},
 125};
 126
 127static struct clk_alpha_pll gpll7 = {
 128	.offset = 0x1a000,
 129	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
 130	.vco_table = trion_vco,
 131	.num_vco = ARRAY_SIZE(trion_vco),
 132	.clkr = {
 133		.enable_reg = 0x52000,
 134		.enable_mask = BIT(7),
 135		.hw.init = &(struct clk_init_data){
 136			.name = "gpll7",
 137			.parent_data = &(const struct clk_parent_data){
 138				.fw_name = "bi_tcxo",
 139			},
 140			.num_parents = 1,
 141			.ops = &clk_alpha_pll_fixed_trion_ops,
 142		},
 143	},
 144};
 145
 146static const struct parent_map gcc_parent_map_0[] = {
 147	{ P_BI_TCXO, 0 },
 148	{ P_GPLL0_OUT_MAIN, 1 },
 149	{ P_GPLL0_OUT_EVEN, 6 },
 150};
 151
 152static const struct clk_parent_data gcc_parents_0[] = {
 153	{ .fw_name = "bi_tcxo" },
 154	{ .hw = &gpll0.clkr.hw },
 155	{ .hw = &gpll0_out_even.clkr.hw },
 156};
 157
 158static const struct parent_map gcc_parent_map_1[] = {
 159	{ P_BI_TCXO, 0 },
 160	{ P_GPLL0_OUT_MAIN, 1 },
 161	{ P_SLEEP_CLK, 5 },
 162	{ P_GPLL0_OUT_EVEN, 6 },
 163};
 164
 165static const struct clk_parent_data gcc_parents_1[] = {
 166	{ .fw_name = "bi_tcxo", },
 167	{ .hw = &gpll0.clkr.hw },
 168	{ .fw_name = "sleep_clk", },
 169	{ .hw = &gpll0_out_even.clkr.hw },
 170};
 171
 172static const struct parent_map gcc_parent_map_2[] = {
 173	{ P_BI_TCXO, 0 },
 174	{ P_SLEEP_CLK, 5 },
 175};
 176
 177static const struct clk_parent_data gcc_parents_2[] = {
 178	{ .fw_name = "bi_tcxo", },
 179	{ .fw_name = "sleep_clk", },
 180};
 181
 182static const struct parent_map gcc_parent_map_3[] = {
 183	{ P_BI_TCXO, 0 },
 184	{ P_GPLL0_OUT_MAIN, 1 },
 185	{ P_GPLL2_OUT_MAIN, 2 },
 186	{ P_GPLL5_OUT_MAIN, 3 },
 187	{ P_GPLL1_OUT_MAIN, 4 },
 188	{ P_GPLL4_OUT_MAIN, 5 },
 189	{ P_GPLL0_OUT_EVEN, 6 },
 190};
 191
 192static const struct clk_parent_data gcc_parents_3[] = {
 193	{ .fw_name = "bi_tcxo", },
 194	{ .hw = &gpll0.clkr.hw },
 195	{ .name = "gpll2" },
 196	{ .name = "gpll5" },
 197	{ .hw = &gpll1.clkr.hw },
 198	{ .hw = &gpll4.clkr.hw },
 199	{ .hw = &gpll0_out_even.clkr.hw },
 200};
 201
 202static const struct parent_map gcc_parent_map_4[] = {
 203	{ P_BI_TCXO, 0 },
 204};
 205
 206static const struct clk_parent_data gcc_parents_4[] = {
 207	{ .fw_name = "bi_tcxo", },
 208};
 209
 210static const struct parent_map gcc_parent_map_5[] = {
 211	{ P_BI_TCXO, 0 },
 212	{ P_GPLL0_OUT_MAIN, 1 },
 213};
 214
 215static const struct clk_parent_data gcc_parents_5[] = {
 216	{ .fw_name = "bi_tcxo", },
 217	{ .hw = &gpll0.clkr.hw },
 218};
 219
 220static const struct parent_map gcc_parent_map_6[] = {
 221	{ P_BI_TCXO, 0 },
 222	{ P_GPLL0_OUT_MAIN, 1 },
 223	{ P_GPLL7_OUT_MAIN, 3 },
 224	{ P_GPLL0_OUT_EVEN, 6 },
 225};
 226
 227static const struct clk_parent_data gcc_parents_6[] = {
 228	{ .fw_name = "bi_tcxo", },
 229	{ .hw = &gpll0.clkr.hw },
 230	{ .hw = &gpll7.clkr.hw },
 231	{ .hw = &gpll0_out_even.clkr.hw },
 232};
 233
 234static const struct parent_map gcc_parent_map_7[] = {
 235	{ P_BI_TCXO, 0 },
 236	{ P_GPLL0_OUT_MAIN, 1 },
 237	{ P_GPLL9_OUT_MAIN, 2 },
 238	{ P_GPLL4_OUT_MAIN, 5 },
 239	{ P_GPLL0_OUT_EVEN, 6 },
 240};
 241
 242static const struct clk_parent_data gcc_parents_7[] = {
 243	{ .fw_name = "bi_tcxo", },
 244	{ .hw = &gpll0.clkr.hw },
 245	{ .name = "gppl9" },
 246	{ .hw = &gpll4.clkr.hw },
 247	{ .hw = &gpll0_out_even.clkr.hw },
 248};
 249
 250static const struct parent_map gcc_parent_map_8[] = {
 251	{ P_BI_TCXO, 0 },
 252	{ P_GPLL0_OUT_MAIN, 1 },
 253	{ P_AUD_REF_CLK, 2 },
 254	{ P_GPLL0_OUT_EVEN, 6 },
 255};
 256
 257static const struct clk_parent_data gcc_parents_8[] = {
 258	{ .fw_name = "bi_tcxo", },
 259	{ .hw = &gpll0.clkr.hw },
 260	{ .name = "aud_ref_clk" },
 261	{ .hw = &gpll0_out_even.clkr.hw },
 262};
 263
 264static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
 265	F(19200000, P_BI_TCXO, 1, 0, 0),
 266	F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
 267	F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 268	{ }
 269};
 270
 271static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
 272	.cmd_rcgr = 0x48014,
 273	.mnd_width = 0,
 274	.hid_width = 5,
 275	.parent_map = gcc_parent_map_0,
 276	.freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
 277	.clkr.hw.init = &(struct clk_init_data){
 278		.name = "gcc_cpuss_ahb_clk_src",
 279		.parent_data = gcc_parents_0,
 280		.num_parents = ARRAY_SIZE(gcc_parents_0),
 281		.flags = CLK_SET_RATE_PARENT,
 282		.ops = &clk_rcg2_ops,
 283	},
 284};
 285
 286static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = {
 287	F(19200000, P_BI_TCXO, 1, 0, 0),
 288	F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
 289	F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
 290	F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
 291	{ }
 292};
 293
 294static struct clk_rcg2 gcc_emac_ptp_clk_src = {
 295	.cmd_rcgr = 0x6038,
 296	.mnd_width = 0,
 297	.hid_width = 5,
 298	.parent_map = gcc_parent_map_6,
 299	.freq_tbl = ftbl_gcc_emac_ptp_clk_src,
 300	.clkr.hw.init = &(struct clk_init_data){
 301		.name = "gcc_emac_ptp_clk_src",
 302		.parent_data = gcc_parents_6,
 303		.num_parents = ARRAY_SIZE(gcc_parents_6),
 304		.flags = CLK_SET_RATE_PARENT,
 305		.ops = &clk_rcg2_ops,
 306	},
 307};
 308
 309static const struct freq_tbl ftbl_gcc_emac_rgmii_clk_src[] = {
 310	F(2500000, P_BI_TCXO, 1, 25, 192),
 311	F(5000000, P_BI_TCXO, 1, 25, 96),
 312	F(19200000, P_BI_TCXO, 1, 0, 0),
 313	F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
 314	F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
 315	F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
 316	F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
 317	{ }
 318};
 319
 320static struct clk_rcg2 gcc_emac_rgmii_clk_src = {
 321	.cmd_rcgr = 0x601c,
 322	.mnd_width = 8,
 323	.hid_width = 5,
 324	.parent_map = gcc_parent_map_6,
 325	.freq_tbl = ftbl_gcc_emac_rgmii_clk_src,
 326	.clkr.hw.init = &(struct clk_init_data){
 327		.name = "gcc_emac_rgmii_clk_src",
 328		.parent_data = gcc_parents_6,
 329		.num_parents = ARRAY_SIZE(gcc_parents_6),
 330		.flags = CLK_SET_RATE_PARENT,
 331		.ops = &clk_rcg2_ops,
 332	},
 333};
 334
 335static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
 336	F(19200000, P_BI_TCXO, 1, 0, 0),
 337	F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
 338	F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
 339	F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 340	F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
 341	{ }
 342};
 343
 344static struct clk_rcg2 gcc_gp1_clk_src = {
 345	.cmd_rcgr = 0x64004,
 346	.mnd_width = 8,
 347	.hid_width = 5,
 348	.parent_map = gcc_parent_map_1,
 349	.freq_tbl = ftbl_gcc_gp1_clk_src,
 350	.clkr.hw.init = &(struct clk_init_data){
 351		.name = "gcc_gp1_clk_src",
 352		.parent_data = gcc_parents_1,
 353		.num_parents = ARRAY_SIZE(gcc_parents_1),
 354		.flags = CLK_SET_RATE_PARENT,
 355		.ops = &clk_rcg2_ops,
 356	},
 357};
 358
 359static struct clk_rcg2 gcc_gp2_clk_src = {
 360	.cmd_rcgr = 0x65004,
 361	.mnd_width = 8,
 362	.hid_width = 5,
 363	.parent_map = gcc_parent_map_1,
 364	.freq_tbl = ftbl_gcc_gp1_clk_src,
 365	.clkr.hw.init = &(struct clk_init_data){
 366		.name = "gcc_gp2_clk_src",
 367		.parent_data = gcc_parents_1,
 368		.num_parents = ARRAY_SIZE(gcc_parents_1),
 369		.flags = CLK_SET_RATE_PARENT,
 370		.ops = &clk_rcg2_ops,
 371	},
 372};
 373
 374static struct clk_rcg2 gcc_gp3_clk_src = {
 375	.cmd_rcgr = 0x66004,
 376	.mnd_width = 8,
 377	.hid_width = 5,
 378	.parent_map = gcc_parent_map_1,
 379	.freq_tbl = ftbl_gcc_gp1_clk_src,
 380	.clkr.hw.init = &(struct clk_init_data){
 381		.name = "gcc_gp3_clk_src",
 382		.parent_data = gcc_parents_1,
 383		.num_parents = ARRAY_SIZE(gcc_parents_1),
 384		.flags = CLK_SET_RATE_PARENT,
 385		.ops = &clk_rcg2_ops,
 386	},
 387};
 388
 389static struct clk_rcg2 gcc_gp4_clk_src = {
 390	.cmd_rcgr = 0xbe004,
 391	.mnd_width = 8,
 392	.hid_width = 5,
 393	.parent_map = gcc_parent_map_1,
 394	.freq_tbl = ftbl_gcc_gp1_clk_src,
 395	.clkr.hw.init = &(struct clk_init_data){
 396		.name = "gcc_gp4_clk_src",
 397		.parent_data = gcc_parents_1,
 398		.num_parents = ARRAY_SIZE(gcc_parents_1),
 399		.flags = CLK_SET_RATE_PARENT,
 400		.ops = &clk_rcg2_ops,
 401	},
 402};
 403
 404static struct clk_rcg2 gcc_gp5_clk_src = {
 405	.cmd_rcgr = 0xbf004,
 406	.mnd_width = 8,
 407	.hid_width = 5,
 408	.parent_map = gcc_parent_map_1,
 409	.freq_tbl = ftbl_gcc_gp1_clk_src,
 410	.clkr.hw.init = &(struct clk_init_data){
 411		.name = "gcc_gp5_clk_src",
 412		.parent_data = gcc_parents_1,
 413		.num_parents = ARRAY_SIZE(gcc_parents_1),
 414		.flags = CLK_SET_RATE_PARENT,
 415		.ops = &clk_rcg2_ops,
 416	},
 417};
 418
 419static const struct freq_tbl ftbl_gcc_npu_axi_clk_src[] = {
 420	F(19200000, P_BI_TCXO, 1, 0, 0),
 421	F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
 422	F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
 423	F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
 424	F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
 425	F(403000000, P_GPLL4_OUT_MAIN, 2, 0, 0),
 426	F(533000000, P_GPLL1_OUT_MAIN, 2, 0, 0),
 427	{ }
 428};
 429
 430static struct clk_rcg2 gcc_npu_axi_clk_src = {
 431	.cmd_rcgr = 0x4d014,
 432	.mnd_width = 0,
 433	.hid_width = 5,
 434	.parent_map = gcc_parent_map_3,
 435	.freq_tbl = ftbl_gcc_npu_axi_clk_src,
 436	.clkr.hw.init = &(struct clk_init_data){
 437		.name = "gcc_npu_axi_clk_src",
 438		.parent_data = gcc_parents_3,
 439		.num_parents = ARRAY_SIZE(gcc_parents_3),
 440		.flags = CLK_SET_RATE_PARENT,
 441		.ops = &clk_rcg2_ops,
 442	},
 443};
 444
 445static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
 446	F(9600000, P_BI_TCXO, 2, 0, 0),
 447	F(19200000, P_BI_TCXO, 1, 0, 0),
 448	{ }
 449};
 450
 451static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
 452	.cmd_rcgr = 0x6b02c,
 453	.mnd_width = 16,
 454	.hid_width = 5,
 455	.parent_map = gcc_parent_map_2,
 456	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 457	.clkr.hw.init = &(struct clk_init_data){
 458		.name = "gcc_pcie_0_aux_clk_src",
 459		.parent_data = gcc_parents_2,
 460		.num_parents = ARRAY_SIZE(gcc_parents_2),
 461		.flags = CLK_SET_RATE_PARENT,
 462		.ops = &clk_rcg2_ops,
 463	},
 464};
 465
 466static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
 467	.cmd_rcgr = 0x8d02c,
 468	.mnd_width = 16,
 469	.hid_width = 5,
 470	.parent_map = gcc_parent_map_2,
 471	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 472	.clkr.hw.init = &(struct clk_init_data){
 473		.name = "gcc_pcie_1_aux_clk_src",
 474		.parent_data = gcc_parents_2,
 475		.num_parents = ARRAY_SIZE(gcc_parents_2),
 476		.flags = CLK_SET_RATE_PARENT,
 477		.ops = &clk_rcg2_ops,
 478	},
 479};
 480
 481static struct clk_rcg2 gcc_pcie_2_aux_clk_src = {
 482	.cmd_rcgr = 0x9d02c,
 483	.mnd_width = 16,
 484	.hid_width = 5,
 485	.parent_map = gcc_parent_map_2,
 486	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 487	.clkr.hw.init = &(struct clk_init_data){
 488		.name = "gcc_pcie_2_aux_clk_src",
 489		.parent_data = gcc_parents_2,
 490		.num_parents = ARRAY_SIZE(gcc_parents_2),
 491		.flags = CLK_SET_RATE_PARENT,
 492		.ops = &clk_rcg2_ops,
 493	},
 494};
 495
 496static struct clk_rcg2 gcc_pcie_3_aux_clk_src = {
 497	.cmd_rcgr = 0xa302c,
 498	.mnd_width = 16,
 499	.hid_width = 5,
 500	.parent_map = gcc_parent_map_2,
 501	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 502	.clkr.hw.init = &(struct clk_init_data){
 503		.name = "gcc_pcie_3_aux_clk_src",
 504		.parent_data = gcc_parents_2,
 505		.num_parents = ARRAY_SIZE(gcc_parents_2),
 506		.flags = CLK_SET_RATE_PARENT,
 507		.ops = &clk_rcg2_ops,
 508	},
 509};
 510
 511static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = {
 512	F(19200000, P_BI_TCXO, 1, 0, 0),
 513	F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 514	{ }
 515};
 516
 517static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = {
 518	.cmd_rcgr = 0x6f014,
 519	.mnd_width = 0,
 520	.hid_width = 5,
 521	.parent_map = gcc_parent_map_0,
 522	.freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src,
 523	.clkr.hw.init = &(struct clk_init_data){
 524		.name = "gcc_pcie_phy_refgen_clk_src",
 525		.parent_data = gcc_parents_0,
 526		.num_parents = ARRAY_SIZE(gcc_parents_0),
 527		.flags = CLK_SET_RATE_PARENT,
 528		.ops = &clk_rcg2_ops,
 529	},
 530};
 531
 532static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
 533	F(9600000, P_BI_TCXO, 2, 0, 0),
 534	F(19200000, P_BI_TCXO, 1, 0, 0),
 535	F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
 536	{ }
 537};
 538
 539static struct clk_rcg2 gcc_pdm2_clk_src = {
 540	.cmd_rcgr = 0x33010,
 541	.mnd_width = 0,
 542	.hid_width = 5,
 543	.parent_map = gcc_parent_map_0,
 544	.freq_tbl = ftbl_gcc_pdm2_clk_src,
 545	.clkr.hw.init = &(struct clk_init_data){
 546		.name = "gcc_pdm2_clk_src",
 547		.parent_data = gcc_parents_0,
 548		.num_parents = ARRAY_SIZE(gcc_parents_0),
 549		.flags = CLK_SET_RATE_PARENT,
 550		.ops = &clk_rcg2_ops,
 551	},
 552};
 553
 554static const struct freq_tbl ftbl_gcc_qspi_1_core_clk_src[] = {
 555	F(19200000, P_BI_TCXO, 1, 0, 0),
 556	F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
 557	F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
 558	F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
 559	{ }
 560};
 561
 562static struct clk_rcg2 gcc_qspi_1_core_clk_src = {
 563	.cmd_rcgr = 0x4a00c,
 564	.mnd_width = 0,
 565	.hid_width = 5,
 566	.parent_map = gcc_parent_map_0,
 567	.freq_tbl = ftbl_gcc_qspi_1_core_clk_src,
 568	.clkr.hw.init = &(struct clk_init_data){
 569		.name = "gcc_qspi_1_core_clk_src",
 570		.parent_data = gcc_parents_0,
 571		.num_parents = ARRAY_SIZE(gcc_parents_0),
 572		.flags = CLK_SET_RATE_PARENT,
 573		.ops = &clk_rcg2_ops,
 574	},
 575};
 576
 577static struct clk_rcg2 gcc_qspi_core_clk_src = {
 578	.cmd_rcgr = 0x4b008,
 579	.mnd_width = 0,
 580	.hid_width = 5,
 581	.parent_map = gcc_parent_map_0,
 582	.freq_tbl = ftbl_gcc_qspi_1_core_clk_src,
 583	.clkr.hw.init = &(struct clk_init_data){
 584		.name = "gcc_qspi_core_clk_src",
 585		.parent_data = gcc_parents_0,
 586		.num_parents = ARRAY_SIZE(gcc_parents_0),
 587		.flags = CLK_SET_RATE_PARENT,
 588		.ops = &clk_rcg2_ops,
 589	},
 590};
 591
 592static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
 593	F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
 594	F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
 595	F(19200000, P_BI_TCXO, 1, 0, 0),
 596	F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
 597	F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
 598	F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
 599	F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
 600	F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
 601	F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
 602	F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
 603	F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
 604	F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 605	F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
 606	F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
 607	F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
 608	F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
 609	F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75),
 610	{ }
 611};
 612
 613static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
 614	.cmd_rcgr = 0x17148,
 615	.mnd_width = 16,
 616	.hid_width = 5,
 617	.parent_map = gcc_parent_map_0,
 618	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 619	.clkr.hw.init = &(struct clk_init_data){
 620		.name = "gcc_qupv3_wrap0_s0_clk_src",
 621		.parent_data = gcc_parents_0,
 622		.num_parents = ARRAY_SIZE(gcc_parents_0),
 623		.flags = CLK_SET_RATE_PARENT,
 624		.ops = &clk_rcg2_ops,
 625	},
 626};
 627
 628static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
 629	.cmd_rcgr = 0x17278,
 630	.mnd_width = 16,
 631	.hid_width = 5,
 632	.parent_map = gcc_parent_map_0,
 633	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 634	.clkr.hw.init = &(struct clk_init_data){
 635		.name = "gcc_qupv3_wrap0_s1_clk_src",
 636		.parent_data = gcc_parents_0,
 637		.num_parents = ARRAY_SIZE(gcc_parents_0),
 638		.flags = CLK_SET_RATE_PARENT,
 639		.ops = &clk_rcg2_ops,
 640	},
 641};
 642
 643static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
 644	.cmd_rcgr = 0x173a8,
 645	.mnd_width = 16,
 646	.hid_width = 5,
 647	.parent_map = gcc_parent_map_0,
 648	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 649	.clkr.hw.init = &(struct clk_init_data){
 650		.name = "gcc_qupv3_wrap0_s2_clk_src",
 651		.parent_data = gcc_parents_0,
 652		.num_parents = ARRAY_SIZE(gcc_parents_0),
 653		.flags = CLK_SET_RATE_PARENT,
 654		.ops = &clk_rcg2_ops,
 655	},
 656};
 657
 658static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
 659	.cmd_rcgr = 0x174d8,
 660	.mnd_width = 16,
 661	.hid_width = 5,
 662	.parent_map = gcc_parent_map_0,
 663	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 664	.clkr.hw.init = &(struct clk_init_data){
 665		.name = "gcc_qupv3_wrap0_s3_clk_src",
 666		.parent_data = gcc_parents_0,
 667		.num_parents = ARRAY_SIZE(gcc_parents_0),
 668		.flags = CLK_SET_RATE_PARENT,
 669		.ops = &clk_rcg2_ops,
 670	},
 671};
 672
 673static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
 674	.cmd_rcgr = 0x17608,
 675	.mnd_width = 16,
 676	.hid_width = 5,
 677	.parent_map = gcc_parent_map_0,
 678	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 679	.clkr.hw.init = &(struct clk_init_data){
 680		.name = "gcc_qupv3_wrap0_s4_clk_src",
 681		.parent_data = gcc_parents_0,
 682		.num_parents = ARRAY_SIZE(gcc_parents_0),
 683		.flags = CLK_SET_RATE_PARENT,
 684		.ops = &clk_rcg2_ops,
 685	},
 686};
 687
 688static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
 689	.cmd_rcgr = 0x17738,
 690	.mnd_width = 16,
 691	.hid_width = 5,
 692	.parent_map = gcc_parent_map_0,
 693	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 694	.clkr.hw.init = &(struct clk_init_data){
 695		.name = "gcc_qupv3_wrap0_s5_clk_src",
 696		.parent_data = gcc_parents_0,
 697		.num_parents = ARRAY_SIZE(gcc_parents_0),
 698		.flags = CLK_SET_RATE_PARENT,
 699		.ops = &clk_rcg2_ops,
 700	},
 701};
 702
 703static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
 704	.cmd_rcgr = 0x17868,
 705	.mnd_width = 16,
 706	.hid_width = 5,
 707	.parent_map = gcc_parent_map_0,
 708	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 709	.clkr.hw.init = &(struct clk_init_data){
 710		.name = "gcc_qupv3_wrap0_s6_clk_src",
 711		.parent_data = gcc_parents_0,
 712		.num_parents = ARRAY_SIZE(gcc_parents_0),
 713		.flags = CLK_SET_RATE_PARENT,
 714		.ops = &clk_rcg2_ops,
 715	},
 716};
 717
 718static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
 719	.cmd_rcgr = 0x17998,
 720	.mnd_width = 16,
 721	.hid_width = 5,
 722	.parent_map = gcc_parent_map_0,
 723	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 724	.clkr.hw.init = &(struct clk_init_data){
 725		.name = "gcc_qupv3_wrap0_s7_clk_src",
 726		.parent_data = gcc_parents_0,
 727		.num_parents = ARRAY_SIZE(gcc_parents_0),
 728		.flags = CLK_SET_RATE_PARENT,
 729		.ops = &clk_rcg2_ops,
 730	},
 731};
 732
 733static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
 734	.cmd_rcgr = 0x18148,
 735	.mnd_width = 16,
 736	.hid_width = 5,
 737	.parent_map = gcc_parent_map_0,
 738	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 739	.clkr.hw.init = &(struct clk_init_data){
 740		.name = "gcc_qupv3_wrap1_s0_clk_src",
 741		.parent_data = gcc_parents_0,
 742		.num_parents = ARRAY_SIZE(gcc_parents_0),
 743		.flags = CLK_SET_RATE_PARENT,
 744		.ops = &clk_rcg2_ops,
 745	},
 746};
 747
 748static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
 749	.cmd_rcgr = 0x18278,
 750	.mnd_width = 16,
 751	.hid_width = 5,
 752	.parent_map = gcc_parent_map_0,
 753	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 754	.clkr.hw.init = &(struct clk_init_data){
 755		.name = "gcc_qupv3_wrap1_s1_clk_src",
 756		.parent_data = gcc_parents_0,
 757		.num_parents = ARRAY_SIZE(gcc_parents_0),
 758		.flags = CLK_SET_RATE_PARENT,
 759		.ops = &clk_rcg2_ops,
 760	},
 761};
 762
 763static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
 764	.cmd_rcgr = 0x183a8,
 765	.mnd_width = 16,
 766	.hid_width = 5,
 767	.parent_map = gcc_parent_map_0,
 768	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 769	.clkr.hw.init = &(struct clk_init_data){
 770		.name = "gcc_qupv3_wrap1_s2_clk_src",
 771		.parent_data = gcc_parents_0,
 772		.num_parents = ARRAY_SIZE(gcc_parents_0),
 773		.flags = CLK_SET_RATE_PARENT,
 774		.ops = &clk_rcg2_ops,
 775	},
 776};
 777
 778static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
 779	.cmd_rcgr = 0x184d8,
 780	.mnd_width = 16,
 781	.hid_width = 5,
 782	.parent_map = gcc_parent_map_0,
 783	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 784	.clkr.hw.init = &(struct clk_init_data){
 785		.name = "gcc_qupv3_wrap1_s3_clk_src",
 786		.parent_data = gcc_parents_0,
 787		.num_parents = ARRAY_SIZE(gcc_parents_0),
 788		.flags = CLK_SET_RATE_PARENT,
 789		.ops = &clk_rcg2_ops,
 790	},
 791};
 792
 793static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
 794	.cmd_rcgr = 0x18608,
 795	.mnd_width = 16,
 796	.hid_width = 5,
 797	.parent_map = gcc_parent_map_0,
 798	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 799	.clkr.hw.init = &(struct clk_init_data){
 800		.name = "gcc_qupv3_wrap1_s4_clk_src",
 801		.parent_data = gcc_parents_0,
 802		.num_parents = ARRAY_SIZE(gcc_parents_0),
 803		.flags = CLK_SET_RATE_PARENT,
 804		.ops = &clk_rcg2_ops,
 805	},
 806};
 807
 808static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
 809	.cmd_rcgr = 0x18738,
 810	.mnd_width = 16,
 811	.hid_width = 5,
 812	.parent_map = gcc_parent_map_0,
 813	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 814	.clkr.hw.init = &(struct clk_init_data){
 815		.name = "gcc_qupv3_wrap1_s5_clk_src",
 816		.parent_data = gcc_parents_0,
 817		.num_parents = ARRAY_SIZE(gcc_parents_0),
 818		.flags = CLK_SET_RATE_PARENT,
 819		.ops = &clk_rcg2_ops,
 820	},
 821};
 822
 823static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
 824	.cmd_rcgr = 0x1e148,
 825	.mnd_width = 16,
 826	.hid_width = 5,
 827	.parent_map = gcc_parent_map_0,
 828	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 829	.clkr.hw.init = &(struct clk_init_data){
 830		.name = "gcc_qupv3_wrap2_s0_clk_src",
 831		.parent_data = gcc_parents_0,
 832		.num_parents = ARRAY_SIZE(gcc_parents_0),
 833		.flags = CLK_SET_RATE_PARENT,
 834		.ops = &clk_rcg2_ops,
 835	},
 836};
 837
 838static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
 839	.cmd_rcgr = 0x1e278,
 840	.mnd_width = 16,
 841	.hid_width = 5,
 842	.parent_map = gcc_parent_map_0,
 843	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 844	.clkr.hw.init = &(struct clk_init_data){
 845		.name = "gcc_qupv3_wrap2_s1_clk_src",
 846		.parent_data = gcc_parents_0,
 847		.num_parents = ARRAY_SIZE(gcc_parents_0),
 848		.flags = CLK_SET_RATE_PARENT,
 849		.ops = &clk_rcg2_ops,
 850	},
 851};
 852
 853static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
 854	.cmd_rcgr = 0x1e3a8,
 855	.mnd_width = 16,
 856	.hid_width = 5,
 857	.parent_map = gcc_parent_map_0,
 858	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 859	.clkr.hw.init = &(struct clk_init_data){
 860		.name = "gcc_qupv3_wrap2_s2_clk_src",
 861		.parent_data = gcc_parents_0,
 862		.num_parents = ARRAY_SIZE(gcc_parents_0),
 863		.flags = CLK_SET_RATE_PARENT,
 864		.ops = &clk_rcg2_ops,
 865	},
 866};
 867
 868static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
 869	.cmd_rcgr = 0x1e4d8,
 870	.mnd_width = 16,
 871	.hid_width = 5,
 872	.parent_map = gcc_parent_map_0,
 873	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 874	.clkr.hw.init = &(struct clk_init_data){
 875		.name = "gcc_qupv3_wrap2_s3_clk_src",
 876		.parent_data = gcc_parents_0,
 877		.num_parents = ARRAY_SIZE(gcc_parents_0),
 878		.flags = CLK_SET_RATE_PARENT,
 879		.ops = &clk_rcg2_ops,
 880	},
 881};
 882
 883static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
 884	.cmd_rcgr = 0x1e608,
 885	.mnd_width = 16,
 886	.hid_width = 5,
 887	.parent_map = gcc_parent_map_0,
 888	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 889	.clkr.hw.init = &(struct clk_init_data){
 890		.name = "gcc_qupv3_wrap2_s4_clk_src",
 891		.parent_data = gcc_parents_0,
 892		.num_parents = ARRAY_SIZE(gcc_parents_0),
 893		.flags = CLK_SET_RATE_PARENT,
 894		.ops = &clk_rcg2_ops,
 895	},
 896};
 897
 898static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
 899	.cmd_rcgr = 0x1e738,
 900	.mnd_width = 16,
 901	.hid_width = 5,
 902	.parent_map = gcc_parent_map_0,
 903	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 904	.clkr.hw.init = &(struct clk_init_data){
 905		.name = "gcc_qupv3_wrap2_s5_clk_src",
 906		.parent_data = gcc_parents_0,
 907		.num_parents = ARRAY_SIZE(gcc_parents_0),
 908		.flags = CLK_SET_RATE_PARENT,
 909		.ops = &clk_rcg2_ops,
 910	},
 911};
 912
 913static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
 914	F(400000, P_BI_TCXO, 12, 1, 4),
 915	F(9600000, P_BI_TCXO, 2, 0, 0),
 916	F(19200000, P_BI_TCXO, 1, 0, 0),
 917	F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
 918	F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
 919	F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 920	F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
 921	{ }
 922};
 923
 924static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
 925	.cmd_rcgr = 0x1400c,
 926	.mnd_width = 8,
 927	.hid_width = 5,
 928	.parent_map = gcc_parent_map_7,
 929	.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
 930	.clkr.hw.init = &(struct clk_init_data){
 931		.name = "gcc_sdcc2_apps_clk_src",
 932		.parent_data = gcc_parents_7,
 933		.num_parents = ARRAY_SIZE(gcc_parents_7),
 934		.flags = CLK_SET_RATE_PARENT,
 935		.ops = &clk_rcg2_floor_ops,
 936	},
 937};
 938
 939static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
 940	F(400000, P_BI_TCXO, 12, 1, 4),
 941	F(9600000, P_BI_TCXO, 2, 0, 0),
 942	F(19200000, P_BI_TCXO, 1, 0, 0),
 943	F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
 944	F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
 945	F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
 946	{ }
 947};
 948
 949static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
 950	.cmd_rcgr = 0x1600c,
 951	.mnd_width = 8,
 952	.hid_width = 5,
 953	.parent_map = gcc_parent_map_5,
 954	.freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
 955	.clkr.hw.init = &(struct clk_init_data){
 956		.name = "gcc_sdcc4_apps_clk_src",
 957		.parent_data = gcc_parents_5,
 958		.num_parents = ARRAY_SIZE(gcc_parents_5),
 959		.flags = CLK_SET_RATE_PARENT,
 960		.ops = &clk_rcg2_floor_ops,
 961	},
 962};
 963
 964static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = {
 965	F(105495, P_BI_TCXO, 2, 1, 91),
 966	{ }
 967};
 968
 969static struct clk_rcg2 gcc_tsif_ref_clk_src = {
 970	.cmd_rcgr = 0x36010,
 971	.mnd_width = 8,
 972	.hid_width = 5,
 973	.parent_map = gcc_parent_map_8,
 974	.freq_tbl = ftbl_gcc_tsif_ref_clk_src,
 975	.clkr.hw.init = &(struct clk_init_data){
 976		.name = "gcc_tsif_ref_clk_src",
 977		.parent_data = gcc_parents_8,
 978		.num_parents = ARRAY_SIZE(gcc_parents_8),
 979		.flags = CLK_SET_RATE_PARENT,
 980		.ops = &clk_rcg2_ops,
 981	},
 982};
 983
 984static const struct freq_tbl ftbl_gcc_ufs_card_2_axi_clk_src[] = {
 985	F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
 986	F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
 987	F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
 988	F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
 989	{ }
 990};
 991
 992static struct clk_rcg2 gcc_ufs_card_2_axi_clk_src = {
 993	.cmd_rcgr = 0xa2020,
 994	.mnd_width = 8,
 995	.hid_width = 5,
 996	.parent_map = gcc_parent_map_0,
 997	.freq_tbl = ftbl_gcc_ufs_card_2_axi_clk_src,
 998	.clkr.hw.init = &(struct clk_init_data){
 999		.name = "gcc_ufs_card_2_axi_clk_src",
1000		.parent_data = gcc_parents_0,
1001		.num_parents = ARRAY_SIZE(gcc_parents_0),
1002		.flags = CLK_SET_RATE_PARENT,
1003		.ops = &clk_rcg2_ops,
1004	},
1005};
1006
1007static struct clk_rcg2 gcc_ufs_card_2_ice_core_clk_src = {
1008	.cmd_rcgr = 0xa2060,
1009	.mnd_width = 0,
1010	.hid_width = 5,
1011	.parent_map = gcc_parent_map_0,
1012	.freq_tbl = ftbl_gcc_ufs_card_2_axi_clk_src,
1013	.clkr.hw.init = &(struct clk_init_data){
1014		.name = "gcc_ufs_card_2_ice_core_clk_src",
1015		.parent_data = gcc_parents_0,
1016		.num_parents = ARRAY_SIZE(gcc_parents_0),
1017		.flags = CLK_SET_RATE_PARENT,
1018		.ops = &clk_rcg2_ops,
1019	},
1020};
1021
1022static const struct freq_tbl ftbl_gcc_ufs_card_2_phy_aux_clk_src[] = {
1023	F(19200000, P_BI_TCXO, 1, 0, 0),
1024	{ }
1025};
1026
1027static struct clk_rcg2 gcc_ufs_card_2_phy_aux_clk_src = {
1028	.cmd_rcgr = 0xa2094,
1029	.mnd_width = 0,
1030	.hid_width = 5,
1031	.parent_map = gcc_parent_map_4,
1032	.freq_tbl = ftbl_gcc_ufs_card_2_phy_aux_clk_src,
1033	.clkr.hw.init = &(struct clk_init_data){
1034		.name = "gcc_ufs_card_2_phy_aux_clk_src",
1035		.parent_data = gcc_parents_4,
1036		.num_parents = ARRAY_SIZE(gcc_parents_4),
1037		.flags = CLK_SET_RATE_PARENT,
1038		.ops = &clk_rcg2_ops,
1039	},
1040};
1041
1042static struct clk_rcg2 gcc_ufs_card_2_unipro_core_clk_src = {
1043	.cmd_rcgr = 0xa2078,
1044	.mnd_width = 0,
1045	.hid_width = 5,
1046	.parent_map = gcc_parent_map_0,
1047	.freq_tbl = ftbl_gcc_ufs_card_2_axi_clk_src,
1048	.clkr.hw.init = &(struct clk_init_data){
1049		.name = "gcc_ufs_card_2_unipro_core_clk_src",
1050		.parent_data = gcc_parents_0,
1051		.num_parents = ARRAY_SIZE(gcc_parents_0),
1052		.flags = CLK_SET_RATE_PARENT,
1053		.ops = &clk_rcg2_ops,
1054	},
1055};
1056
1057static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {
1058	F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
1059	F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
1060	F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
1061	F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1062	F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1063	{ }
1064};
1065
1066static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
1067	.cmd_rcgr = 0x75020,
1068	.mnd_width = 8,
1069	.hid_width = 5,
1070	.parent_map = gcc_parent_map_0,
1071	.freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
1072	.clkr.hw.init = &(struct clk_init_data){
1073		.name = "gcc_ufs_card_axi_clk_src",
1074		.parent_data = gcc_parents_0,
1075		.num_parents = ARRAY_SIZE(gcc_parents_0),
1076		.flags = CLK_SET_RATE_PARENT,
1077		.ops = &clk_rcg2_ops,
1078	},
1079};
1080
1081static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {
1082	F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
1083	F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1084	F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
1085	{ }
1086};
1087
1088static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
1089	.cmd_rcgr = 0x75060,
1090	.mnd_width = 0,
1091	.hid_width = 5,
1092	.parent_map = gcc_parent_map_0,
1093	.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
1094	.clkr.hw.init = &(struct clk_init_data){
1095		.name = "gcc_ufs_card_ice_core_clk_src",
1096		.parent_data = gcc_parents_0,
1097		.num_parents = ARRAY_SIZE(gcc_parents_0),
1098		.flags = CLK_SET_RATE_PARENT,
1099		.ops = &clk_rcg2_ops,
1100	},
1101};
1102
1103static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
1104	.cmd_rcgr = 0x75094,
1105	.mnd_width = 0,
1106	.hid_width = 5,
1107	.parent_map = gcc_parent_map_4,
1108	.freq_tbl = ftbl_gcc_ufs_card_2_phy_aux_clk_src,
1109	.clkr.hw.init = &(struct clk_init_data){
1110		.name = "gcc_ufs_card_phy_aux_clk_src",
1111		.parent_data = gcc_parents_4,
1112		.num_parents = ARRAY_SIZE(gcc_parents_4),
1113		.flags = CLK_SET_RATE_PARENT,
1114		.ops = &clk_rcg2_ops,
1115	},
1116};
1117
1118static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = {
1119	F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
1120	F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1121	F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1122	{ }
1123};
1124
1125static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
1126	.cmd_rcgr = 0x75078,
1127	.mnd_width = 0,
1128	.hid_width = 5,
1129	.parent_map = gcc_parent_map_0,
1130	.freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src,
1131	.clkr.hw.init = &(struct clk_init_data){
1132		.name = "gcc_ufs_card_unipro_core_clk_src",
1133		.parent_data = gcc_parents_0,
1134		.num_parents = ARRAY_SIZE(gcc_parents_0),
1135		.flags = CLK_SET_RATE_PARENT,
1136		.ops = &clk_rcg2_ops,
1137	},
1138};
1139
1140static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
1141	F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
1142	F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
1143	F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
1144	F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1145	F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
1146	{ }
1147};
1148
1149static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
1150	.cmd_rcgr = 0x77020,
1151	.mnd_width = 8,
1152	.hid_width = 5,
1153	.parent_map = gcc_parent_map_0,
1154	.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
1155	.clkr.hw.init = &(struct clk_init_data){
1156		.name = "gcc_ufs_phy_axi_clk_src",
1157		.parent_data = gcc_parents_0,
1158		.num_parents = ARRAY_SIZE(gcc_parents_0),
1159		.flags = CLK_SET_RATE_PARENT,
1160		.ops = &clk_rcg2_ops,
1161	},
1162};
1163
1164static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
1165	.cmd_rcgr = 0x77060,
1166	.mnd_width = 0,
1167	.hid_width = 5,
1168	.parent_map = gcc_parent_map_0,
1169	.freq_tbl = ftbl_gcc_ufs_card_2_axi_clk_src,
1170	.clkr.hw.init = &(struct clk_init_data){
1171		.name = "gcc_ufs_phy_ice_core_clk_src",
1172		.parent_data = gcc_parents_0,
1173		.num_parents = ARRAY_SIZE(gcc_parents_0),
1174		.flags = CLK_SET_RATE_PARENT,
1175		.ops = &clk_rcg2_ops,
1176	},
1177};
1178
1179static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
1180	.cmd_rcgr = 0x77094,
1181	.mnd_width = 0,
1182	.hid_width = 5,
1183	.parent_map = gcc_parent_map_4,
1184	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1185	.clkr.hw.init = &(struct clk_init_data){
1186		.name = "gcc_ufs_phy_phy_aux_clk_src",
1187		.parent_data = gcc_parents_4,
1188		.num_parents = ARRAY_SIZE(gcc_parents_4),
1189		.flags = CLK_SET_RATE_PARENT,
1190		.ops = &clk_rcg2_ops,
1191	},
1192};
1193
1194static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
1195	.cmd_rcgr = 0x77078,
1196	.mnd_width = 0,
1197	.hid_width = 5,
1198	.parent_map = gcc_parent_map_0,
1199	.freq_tbl = ftbl_gcc_ufs_card_2_axi_clk_src,
1200	.clkr.hw.init = &(struct clk_init_data){
1201		.name = "gcc_ufs_phy_unipro_core_clk_src",
1202		.parent_data = gcc_parents_0,
1203		.num_parents = ARRAY_SIZE(gcc_parents_0),
1204		.flags = CLK_SET_RATE_PARENT,
1205		.ops = &clk_rcg2_ops,
1206	},
1207};
1208
1209static const struct freq_tbl ftbl_gcc_usb30_mp_master_clk_src[] = {
1210	F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
1211	F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
1212	F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1213	F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1214	F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1215	{ }
1216};
1217
1218static struct clk_rcg2 gcc_usb30_mp_master_clk_src = {
1219	.cmd_rcgr = 0xa601c,
1220	.mnd_width = 8,
1221	.hid_width = 5,
1222	.parent_map = gcc_parent_map_0,
1223	.freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
1224	.clkr.hw.init = &(struct clk_init_data){
1225		.name = "gcc_usb30_mp_master_clk_src",
1226		.parent_data = gcc_parents_0,
1227		.num_parents = ARRAY_SIZE(gcc_parents_0),
1228		.flags = CLK_SET_RATE_PARENT,
1229		.ops = &clk_rcg2_ops,
1230	},
1231};
1232
1233static const struct freq_tbl ftbl_gcc_usb30_mp_mock_utmi_clk_src[] = {
1234	F(19200000, P_BI_TCXO, 1, 0, 0),
1235	F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
1236	F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0),
1237	F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1238	{ }
1239};
1240
1241static struct clk_rcg2 gcc_usb30_mp_mock_utmi_clk_src = {
1242	.cmd_rcgr = 0xa6034,
1243	.mnd_width = 0,
1244	.hid_width = 5,
1245	.parent_map = gcc_parent_map_0,
1246	.freq_tbl = ftbl_gcc_usb30_mp_mock_utmi_clk_src,
1247	.clkr.hw.init = &(struct clk_init_data){
1248		.name = "gcc_usb30_mp_mock_utmi_clk_src",
1249		.parent_data = gcc_parents_0,
1250		.num_parents = ARRAY_SIZE(gcc_parents_0),
1251		.flags = CLK_SET_RATE_PARENT,
1252		.ops = &clk_rcg2_ops,
1253	},
1254};
1255
1256static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1257	.cmd_rcgr = 0xf01c,
1258	.mnd_width = 8,
1259	.hid_width = 5,
1260	.parent_map = gcc_parent_map_0,
1261	.freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
1262	.clkr.hw.init = &(struct clk_init_data){
1263		.name = "gcc_usb30_prim_master_clk_src",
1264		.parent_data = gcc_parents_0,
1265		.num_parents = ARRAY_SIZE(gcc_parents_0),
1266		.flags = CLK_SET_RATE_PARENT,
1267		.ops = &clk_rcg2_ops,
1268	},
1269};
1270
1271static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1272	.cmd_rcgr = 0xf034,
1273	.mnd_width = 0,
1274	.hid_width = 5,
1275	.parent_map = gcc_parent_map_0,
1276	.freq_tbl = ftbl_gcc_usb30_mp_mock_utmi_clk_src,
1277	.clkr.hw.init = &(struct clk_init_data){
1278		.name = "gcc_usb30_prim_mock_utmi_clk_src",
1279		.parent_data = gcc_parents_0,
1280		.num_parents = ARRAY_SIZE(gcc_parents_0),
1281		.flags = CLK_SET_RATE_PARENT,
1282		.ops = &clk_rcg2_ops,
1283	},
1284};
1285
1286static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
1287	.cmd_rcgr = 0x1001c,
1288	.mnd_width = 8,
1289	.hid_width = 5,
1290	.parent_map = gcc_parent_map_0,
1291	.freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
1292	.clkr.hw.init = &(struct clk_init_data){
1293		.name = "gcc_usb30_sec_master_clk_src",
1294		.parent_data = gcc_parents_0,
1295		.num_parents = ARRAY_SIZE(gcc_parents_0),
1296		.flags = CLK_SET_RATE_PARENT,
1297		.ops = &clk_rcg2_ops,
1298	},
1299};
1300
1301static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
1302	.cmd_rcgr = 0x10034,
1303	.mnd_width = 0,
1304	.hid_width = 5,
1305	.parent_map = gcc_parent_map_0,
1306	.freq_tbl = ftbl_gcc_usb30_mp_mock_utmi_clk_src,
1307	.clkr.hw.init = &(struct clk_init_data){
1308		.name = "gcc_usb30_sec_mock_utmi_clk_src",
1309		.parent_data = gcc_parents_0,
1310		.num_parents = ARRAY_SIZE(gcc_parents_0),
1311		.flags = CLK_SET_RATE_PARENT,
1312		.ops = &clk_rcg2_ops,
1313	},
1314};
1315
1316static struct clk_rcg2 gcc_usb3_mp_phy_aux_clk_src = {
1317	.cmd_rcgr = 0xa6068,
1318	.mnd_width = 0,
1319	.hid_width = 5,
1320	.parent_map = gcc_parent_map_2,
1321	.freq_tbl = ftbl_gcc_ufs_card_2_phy_aux_clk_src,
1322	.clkr.hw.init = &(struct clk_init_data){
1323		.name = "gcc_usb3_mp_phy_aux_clk_src",
1324		.parent_data = gcc_parents_2,
1325		.num_parents = ARRAY_SIZE(gcc_parents_2),
1326		.flags = CLK_SET_RATE_PARENT,
1327		.ops = &clk_rcg2_ops,
1328	},
1329};
1330
1331static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1332	.cmd_rcgr = 0xf060,
1333	.mnd_width = 0,
1334	.hid_width = 5,
1335	.parent_map = gcc_parent_map_2,
1336	.freq_tbl = ftbl_gcc_ufs_card_2_phy_aux_clk_src,
1337	.clkr.hw.init = &(struct clk_init_data){
1338		.name = "gcc_usb3_prim_phy_aux_clk_src",
1339		.parent_data = gcc_parents_2,
1340		.num_parents = ARRAY_SIZE(gcc_parents_2),
1341		.flags = CLK_SET_RATE_PARENT,
1342		.ops = &clk_rcg2_ops,
1343	},
1344};
1345
1346static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
1347	.cmd_rcgr = 0x10060,
1348	.mnd_width = 0,
1349	.hid_width = 5,
1350	.parent_map = gcc_parent_map_2,
1351	.freq_tbl = ftbl_gcc_ufs_card_2_phy_aux_clk_src,
1352	.clkr.hw.init = &(struct clk_init_data){
1353		.name = "gcc_usb3_sec_phy_aux_clk_src",
1354		.parent_data = gcc_parents_2,
1355		.num_parents = ARRAY_SIZE(gcc_parents_2),
1356		.flags = CLK_SET_RATE_PARENT,
1357		.ops = &clk_rcg2_ops,
1358	},
1359};
1360
1361static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
1362	.halt_reg = 0x90018,
1363	.halt_check = BRANCH_HALT,
1364	.clkr = {
1365		.enable_reg = 0x90018,
1366		.enable_mask = BIT(0),
1367		.hw.init = &(struct clk_init_data){
1368			.name = "gcc_aggre_noc_pcie_tbu_clk",
1369			.ops = &clk_branch2_ops,
1370		},
1371	},
1372};
1373
1374static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
1375	.halt_reg = 0x750c0,
1376	.halt_check = BRANCH_HALT,
1377	.hwcg_reg = 0x750c0,
1378	.hwcg_bit = 1,
1379	.clkr = {
1380		.enable_reg = 0x750c0,
1381		.enable_mask = BIT(0),
1382		.hw.init = &(struct clk_init_data){
1383			.name = "gcc_aggre_ufs_card_axi_clk",
1384			.parent_hws = (const struct clk_hw *[]){
1385				      &gcc_ufs_card_axi_clk_src.clkr.hw
1386			},
1387			.num_parents = 1,
1388			.flags = CLK_SET_RATE_PARENT,
1389			.ops = &clk_branch2_ops,
1390		},
1391	},
1392};
1393
1394static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = {
1395	.halt_reg = 0x750c0,
1396	.halt_check = BRANCH_HALT,
1397	.hwcg_reg = 0x750c0,
1398	.hwcg_bit = 1,
1399	.clkr = {
1400		.enable_reg = 0x750c0,
1401		.enable_mask = BIT(1),
1402		.hw.init = &(struct clk_init_data){
1403			.name = "gcc_aggre_ufs_card_axi_hw_ctl_clk",
1404			.parent_hws = (const struct clk_hw *[]){
1405				      &gcc_aggre_ufs_card_axi_clk.clkr.hw
1406			},
1407			.num_parents = 1,
1408			.flags = CLK_SET_RATE_PARENT,
1409			.ops = &clk_branch_simple_ops,
1410		},
1411	},
1412};
1413
1414static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1415	.halt_reg = 0x770c0,
1416	.halt_check = BRANCH_HALT,
1417	.hwcg_reg = 0x770c0,
1418	.hwcg_bit = 1,
1419	.clkr = {
1420		.enable_reg = 0x770c0,
1421		.enable_mask = BIT(0),
1422		.hw.init = &(struct clk_init_data){
1423			.name = "gcc_aggre_ufs_phy_axi_clk",
1424			.parent_hws = (const struct clk_hw *[]){
1425				      &gcc_ufs_phy_axi_clk_src.clkr.hw
1426			},
1427			.num_parents = 1,
1428			.flags = CLK_SET_RATE_PARENT,
1429			.ops = &clk_branch2_ops,
1430		},
1431	},
1432};
1433
1434static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
1435	.halt_reg = 0x770c0,
1436	.halt_check = BRANCH_HALT,
1437	.hwcg_reg = 0x770c0,
1438	.hwcg_bit = 1,
1439	.clkr = {
1440		.enable_reg = 0x770c0,
1441		.enable_mask = BIT(1),
1442		.hw.init = &(struct clk_init_data){
1443			.name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
1444			.parent_hws = (const struct clk_hw *[]){
1445				      &gcc_aggre_ufs_phy_axi_clk.clkr.hw
1446			},
1447			.num_parents = 1,
1448			.flags = CLK_SET_RATE_PARENT,
1449			.ops = &clk_branch_simple_ops,
1450		},
1451	},
1452};
1453
1454static struct clk_branch gcc_aggre_usb3_mp_axi_clk = {
1455	.halt_reg = 0xa6084,
1456	.halt_check = BRANCH_HALT,
1457	.clkr = {
1458		.enable_reg = 0xa6084,
1459		.enable_mask = BIT(0),
1460		.hw.init = &(struct clk_init_data){
1461			.name = "gcc_aggre_usb3_mp_axi_clk",
1462			.parent_hws = (const struct clk_hw *[]){
1463				      &gcc_usb30_mp_master_clk_src.clkr.hw
1464			},
1465			.num_parents = 1,
1466			.flags = CLK_SET_RATE_PARENT,
1467			.ops = &clk_branch2_ops,
1468		},
1469	},
1470};
1471
1472static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1473	.halt_reg = 0xf07c,
1474	.halt_check = BRANCH_HALT,
1475	.clkr = {
1476		.enable_reg = 0xf07c,
1477		.enable_mask = BIT(0),
1478		.hw.init = &(struct clk_init_data){
1479			.name = "gcc_aggre_usb3_prim_axi_clk",
1480			.parent_hws = (const struct clk_hw *[]){
1481				      &gcc_usb30_prim_master_clk_src.clkr.hw
1482			},
1483			.num_parents = 1,
1484			.flags = CLK_SET_RATE_PARENT,
1485			.ops = &clk_branch2_ops,
1486		},
1487	},
1488};
1489
1490static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
1491	.halt_reg = 0x1007c,
1492	.halt_check = BRANCH_HALT,
1493	.clkr = {
1494		.enable_reg = 0x1007c,
1495		.enable_mask = BIT(0),
1496		.hw.init = &(struct clk_init_data){
1497			.name = "gcc_aggre_usb3_sec_axi_clk",
1498			.parent_hws = (const struct clk_hw *[]){
1499				      &gcc_usb30_sec_master_clk_src.clkr.hw
1500			},
1501			.num_parents = 1,
1502			.flags = CLK_SET_RATE_PARENT,
1503			.ops = &clk_branch2_ops,
1504		},
1505	},
1506};
1507
1508static struct clk_branch gcc_boot_rom_ahb_clk = {
1509	.halt_reg = 0x38004,
1510	.halt_check = BRANCH_HALT_VOTED,
1511	.hwcg_reg = 0x38004,
1512	.hwcg_bit = 1,
1513	.clkr = {
1514		.enable_reg = 0x52004,
1515		.enable_mask = BIT(10),
1516		.hw.init = &(struct clk_init_data){
1517			.name = "gcc_boot_rom_ahb_clk",
1518			.ops = &clk_branch2_ops,
1519		},
1520	},
1521};
1522
1523static struct clk_branch gcc_camera_hf_axi_clk = {
1524	.halt_reg = 0xb030,
1525	.halt_check = BRANCH_HALT,
1526	.clkr = {
1527		.enable_reg = 0xb030,
1528		.enable_mask = BIT(0),
1529		.hw.init = &(struct clk_init_data){
1530			.name = "gcc_camera_hf_axi_clk",
1531			.ops = &clk_branch2_ops,
1532		},
1533	},
1534};
1535
1536static struct clk_branch gcc_camera_sf_axi_clk = {
1537	.halt_reg = 0xb034,
1538	.halt_check = BRANCH_HALT,
1539	.clkr = {
1540		.enable_reg = 0xb034,
1541		.enable_mask = BIT(0),
1542		.hw.init = &(struct clk_init_data){
1543			.name = "gcc_camera_sf_axi_clk",
1544			.ops = &clk_branch2_ops,
1545		},
1546	},
1547};
1548
1549static struct clk_branch gcc_cfg_noc_usb3_mp_axi_clk = {
1550	.halt_reg = 0xa609c,
1551	.halt_check = BRANCH_HALT,
1552	.clkr = {
1553		.enable_reg = 0xa609c,
1554		.enable_mask = BIT(0),
1555		.hw.init = &(struct clk_init_data){
1556			.name = "gcc_cfg_noc_usb3_mp_axi_clk",
1557			.parent_hws = (const struct clk_hw *[]){
1558				      &gcc_usb30_mp_master_clk_src.clkr.hw
1559			},
1560			.num_parents = 1,
1561			.flags = CLK_SET_RATE_PARENT,
1562			.ops = &clk_branch2_ops,
1563		},
1564	},
1565};
1566
1567static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1568	.halt_reg = 0xf078,
1569	.halt_check = BRANCH_HALT,
1570	.clkr = {
1571		.enable_reg = 0xf078,
1572		.enable_mask = BIT(0),
1573		.hw.init = &(struct clk_init_data){
1574			.name = "gcc_cfg_noc_usb3_prim_axi_clk",
1575			.parent_hws = (const struct clk_hw *[]){
1576				      &gcc_usb30_prim_master_clk_src.clkr.hw
1577			},
1578			.num_parents = 1,
1579			.flags = CLK_SET_RATE_PARENT,
1580			.ops = &clk_branch2_ops,
1581		},
1582	},
1583};
1584
1585static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
1586	.halt_reg = 0x10078,
1587	.halt_check = BRANCH_HALT,
1588	.clkr = {
1589		.enable_reg = 0x10078,
1590		.enable_mask = BIT(0),
1591		.hw.init = &(struct clk_init_data){
1592			.name = "gcc_cfg_noc_usb3_sec_axi_clk",
1593			.parent_hws = (const struct clk_hw *[]){
1594				      &gcc_usb30_sec_master_clk_src.clkr.hw
1595			},
1596			.num_parents = 1,
1597			.flags = CLK_SET_RATE_PARENT,
1598			.ops = &clk_branch2_ops,
1599		},
1600	},
1601};
1602
1603/* For CPUSS functionality the AHB clock needs to be left enabled */
1604static struct clk_branch gcc_cpuss_ahb_clk = {
1605	.halt_reg = 0x48000,
1606	.halt_check = BRANCH_HALT_VOTED,
1607	.clkr = {
1608		.enable_reg = 0x52004,
1609		.enable_mask = BIT(21),
1610		.hw.init = &(struct clk_init_data){
1611			.name = "gcc_cpuss_ahb_clk",
1612			.parent_hws = (const struct clk_hw *[]){
1613				      &gcc_cpuss_ahb_clk_src.clkr.hw
1614			},
1615			.num_parents = 1,
1616			.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1617			.ops = &clk_branch2_ops,
1618		},
1619	},
1620};
1621
1622static struct clk_branch gcc_cpuss_rbcpr_clk = {
1623	.halt_reg = 0x48008,
1624	.halt_check = BRANCH_HALT,
1625	.clkr = {
1626		.enable_reg = 0x48008,
1627		.enable_mask = BIT(0),
1628		.hw.init = &(struct clk_init_data){
1629			.name = "gcc_cpuss_rbcpr_clk",
1630			.ops = &clk_branch2_ops,
1631		},
1632	},
1633};
1634
1635static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1636	.halt_reg = 0x71154,
1637	.halt_check = BRANCH_VOTED,
1638	.clkr = {
1639		.enable_reg = 0x71154,
1640		.enable_mask = BIT(0),
1641		.hw.init = &(struct clk_init_data){
1642			.name = "gcc_ddrss_gpu_axi_clk",
1643			.ops = &clk_branch2_ops,
1644		},
1645	},
1646};
1647
1648static struct clk_branch gcc_disp_hf_axi_clk = {
1649	.halt_reg = 0xb038,
1650	.halt_check = BRANCH_HALT,
1651	.clkr = {
1652		.enable_reg = 0xb038,
1653		.enable_mask = BIT(0),
1654		.hw.init = &(struct clk_init_data){
1655			.name = "gcc_disp_hf_axi_clk",
1656			.ops = &clk_branch2_ops,
1657		},
1658	},
1659};
1660
1661static struct clk_branch gcc_disp_sf_axi_clk = {
1662	.halt_reg = 0xb03c,
1663	.halt_check = BRANCH_HALT,
1664	.clkr = {
1665		.enable_reg = 0xb03c,
1666		.enable_mask = BIT(0),
1667		.hw.init = &(struct clk_init_data){
1668			.name = "gcc_disp_sf_axi_clk",
1669			.ops = &clk_branch2_ops,
1670		},
1671	},
1672};
1673
1674static struct clk_branch gcc_emac_axi_clk = {
1675	.halt_reg = 0x6010,
1676	.halt_check = BRANCH_HALT,
1677	.clkr = {
1678		.enable_reg = 0x6010,
1679		.enable_mask = BIT(0),
1680		.hw.init = &(struct clk_init_data){
1681			.name = "gcc_emac_axi_clk",
1682			.ops = &clk_branch2_ops,
1683		},
1684	},
1685};
1686
1687static struct clk_branch gcc_emac_ptp_clk = {
1688	.halt_reg = 0x6034,
1689	.halt_check = BRANCH_HALT,
1690	.clkr = {
1691		.enable_reg = 0x6034,
1692		.enable_mask = BIT(0),
1693		.hw.init = &(struct clk_init_data){
1694			.name = "gcc_emac_ptp_clk",
1695			.parent_hws = (const struct clk_hw *[]){
1696				      &gcc_emac_ptp_clk_src.clkr.hw
1697			},
1698			.num_parents = 1,
1699			.flags = CLK_SET_RATE_PARENT,
1700			.ops = &clk_branch2_ops,
1701		},
1702	},
1703};
1704
1705static struct clk_branch gcc_emac_rgmii_clk = {
1706	.halt_reg = 0x6018,
1707	.halt_check = BRANCH_HALT,
1708	.clkr = {
1709		.enable_reg = 0x6018,
1710		.enable_mask = BIT(0),
1711		.hw.init = &(struct clk_init_data){
1712			.name = "gcc_emac_rgmii_clk",
1713			.parent_hws = (const struct clk_hw *[]){
1714				      &gcc_emac_rgmii_clk_src.clkr.hw
1715			},
1716			.num_parents = 1,
1717			.flags = CLK_SET_RATE_PARENT,
1718			.ops = &clk_branch2_ops,
1719		},
1720	},
1721};
1722
1723static struct clk_branch gcc_emac_slv_ahb_clk = {
1724	.halt_reg = 0x6014,
1725	.halt_check = BRANCH_HALT,
1726	.hwcg_reg = 0x6014,
1727	.hwcg_bit = 1,
1728	.clkr = {
1729		.enable_reg = 0x6014,
1730		.enable_mask = BIT(0),
1731		.hw.init = &(struct clk_init_data){
1732			.name = "gcc_emac_slv_ahb_clk",
1733			.ops = &clk_branch2_ops,
1734		},
1735	},
1736};
1737
1738static struct clk_branch gcc_gp1_clk = {
1739	.halt_reg = 0x64000,
1740	.halt_check = BRANCH_HALT,
1741	.clkr = {
1742		.enable_reg = 0x64000,
1743		.enable_mask = BIT(0),
1744		.hw.init = &(struct clk_init_data){
1745			.name = "gcc_gp1_clk",
1746			.parent_hws = (const struct clk_hw *[]){
1747				      &gcc_gp1_clk_src.clkr.hw
1748			},
1749			.num_parents = 1,
1750			.flags = CLK_SET_RATE_PARENT,
1751			.ops = &clk_branch2_ops,
1752		},
1753	},
1754};
1755
1756static struct clk_branch gcc_gp2_clk = {
1757	.halt_reg = 0x65000,
1758	.halt_check = BRANCH_HALT,
1759	.clkr = {
1760		.enable_reg = 0x65000,
1761		.enable_mask = BIT(0),
1762		.hw.init = &(struct clk_init_data){
1763			.name = "gcc_gp2_clk",
1764			.parent_hws = (const struct clk_hw *[]){
1765				      &gcc_gp2_clk_src.clkr.hw
1766			},
1767			.num_parents = 1,
1768			.flags = CLK_SET_RATE_PARENT,
1769			.ops = &clk_branch2_ops,
1770		},
1771	},
1772};
1773
1774static struct clk_branch gcc_gp3_clk = {
1775	.halt_reg = 0x66000,
1776	.halt_check = BRANCH_HALT,
1777	.clkr = {
1778		.enable_reg = 0x66000,
1779		.enable_mask = BIT(0),
1780		.hw.init = &(struct clk_init_data){
1781			.name = "gcc_gp3_clk",
1782			.parent_hws = (const struct clk_hw *[]){
1783				      &gcc_gp3_clk_src.clkr.hw
1784			},
1785			.num_parents = 1,
1786			.flags = CLK_SET_RATE_PARENT,
1787			.ops = &clk_branch2_ops,
1788		},
1789	},
1790};
1791
1792static struct clk_branch gcc_gp4_clk = {
1793	.halt_reg = 0xbe000,
1794	.halt_check = BRANCH_HALT,
1795	.clkr = {
1796		.enable_reg = 0xbe000,
1797		.enable_mask = BIT(0),
1798		.hw.init = &(struct clk_init_data){
1799			.name = "gcc_gp4_clk",
1800			.parent_hws = (const struct clk_hw *[]){
1801				      &gcc_gp4_clk_src.clkr.hw
1802			},
1803			.num_parents = 1,
1804			.flags = CLK_SET_RATE_PARENT,
1805			.ops = &clk_branch2_ops,
1806		},
1807	},
1808};
1809
1810static struct clk_branch gcc_gp5_clk = {
1811	.halt_reg = 0xbf000,
1812	.halt_check = BRANCH_HALT,
1813	.clkr = {
1814		.enable_reg = 0xbf000,
1815		.enable_mask = BIT(0),
1816		.hw.init = &(struct clk_init_data){
1817			.name = "gcc_gp5_clk",
1818			.parent_hws = (const struct clk_hw *[]){
1819				      &gcc_gp5_clk_src.clkr.hw
1820			},
1821			.num_parents = 1,
1822			.flags = CLK_SET_RATE_PARENT,
1823			.ops = &clk_branch2_ops,
1824		},
1825	},
1826};
1827
1828static struct clk_branch gcc_gpu_gpll0_clk_src = {
1829	.halt_check = BRANCH_HALT_DELAY,
1830	.clkr = {
1831		.enable_reg = 0x52004,
1832		.enable_mask = BIT(15),
1833		.hw.init = &(struct clk_init_data){
1834			.name = "gcc_gpu_gpll0_clk_src",
1835			.parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
1836			.num_parents = 1,
1837			.flags = CLK_SET_RATE_PARENT,
1838			.ops = &clk_branch2_ops,
1839		},
1840	},
1841};
1842
1843static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1844	.halt_check = BRANCH_HALT_DELAY,
1845	.clkr = {
1846		.enable_reg = 0x52004,
1847		.enable_mask = BIT(16),
1848		.hw.init = &(struct clk_init_data){
1849			.name = "gcc_gpu_gpll0_div_clk_src",
1850			.parent_hws = (const struct clk_hw *[]){
1851				      &gpll0_out_even.clkr.hw
1852			},
1853			.num_parents = 1,
1854			.flags = CLK_SET_RATE_PARENT,
1855			.ops = &clk_branch2_ops,
1856		},
1857	},
1858};
1859
1860static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1861	.halt_reg = 0x7100c,
1862	.halt_check = BRANCH_VOTED,
1863	.clkr = {
1864		.enable_reg = 0x7100c,
1865		.enable_mask = BIT(0),
1866		.hw.init = &(struct clk_init_data){
1867			.name = "gcc_gpu_memnoc_gfx_clk",
1868			.ops = &clk_branch2_ops,
1869		},
1870	},
1871};
1872
1873static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1874	.halt_reg = 0x71018,
1875	.halt_check = BRANCH_HALT,
1876	.clkr = {
1877		.enable_reg = 0x71018,
1878		.enable_mask = BIT(0),
1879		.hw.init = &(struct clk_init_data){
1880			.name = "gcc_gpu_snoc_dvm_gfx_clk",
1881			.ops = &clk_branch2_ops,
1882		},
1883	},
1884};
1885
1886static struct clk_branch gcc_npu_at_clk = {
1887	.halt_reg = 0x4d010,
1888	.halt_check = BRANCH_VOTED,
1889	.clkr = {
1890		.enable_reg = 0x4d010,
1891		.enable_mask = BIT(0),
1892		.hw.init = &(struct clk_init_data){
1893			.name = "gcc_npu_at_clk",
1894			.ops = &clk_branch2_ops,
1895		},
1896	},
1897};
1898
1899static struct clk_branch gcc_npu_axi_clk = {
1900	.halt_reg = 0x4d008,
1901	.halt_check = BRANCH_VOTED,
1902	.clkr = {
1903		.enable_reg = 0x4d008,
1904		.enable_mask = BIT(0),
1905		.hw.init = &(struct clk_init_data){
1906			.name = "gcc_npu_axi_clk",
1907			.parent_hws = (const struct clk_hw *[]){
1908				      &gcc_npu_axi_clk_src.clkr.hw
1909			},
1910			.num_parents = 1,
1911			.flags = CLK_SET_RATE_PARENT,
1912			.ops = &clk_branch2_ops,
1913		},
1914	},
1915};
1916
1917static struct clk_branch gcc_npu_gpll0_clk_src = {
1918	.halt_check = BRANCH_HALT_DELAY,
1919	.clkr = {
1920		.enable_reg = 0x52004,
1921		.enable_mask = BIT(18),
1922		.hw.init = &(struct clk_init_data){
1923			.name = "gcc_npu_gpll0_clk_src",
1924			.parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
1925			.num_parents = 1,
1926			.flags = CLK_SET_RATE_PARENT,
1927			.ops = &clk_branch2_ops,
1928		},
1929	},
1930};
1931
1932static struct clk_branch gcc_npu_gpll0_div_clk_src = {
1933	.halt_check = BRANCH_HALT_DELAY,
1934	.clkr = {
1935		.enable_reg = 0x52004,
1936		.enable_mask = BIT(19),
1937		.hw.init = &(struct clk_init_data){
1938			.name = "gcc_npu_gpll0_div_clk_src",
1939			.parent_hws = (const struct clk_hw *[]){
1940				      &gpll0_out_even.clkr.hw
1941			},
1942			.num_parents = 1,
1943			.flags = CLK_SET_RATE_PARENT,
1944			.ops = &clk_branch2_ops,
1945		},
1946	},
1947};
1948
1949static struct clk_branch gcc_npu_trig_clk = {
1950	.halt_reg = 0x4d00c,
1951	.halt_check = BRANCH_VOTED,
1952	.clkr = {
1953		.enable_reg = 0x4d00c,
1954		.enable_mask = BIT(0),
1955		.hw.init = &(struct clk_init_data){
1956			.name = "gcc_npu_trig_clk",
1957			.ops = &clk_branch2_ops,
1958		},
1959	},
1960};
1961
1962static struct clk_branch gcc_pcie0_phy_refgen_clk = {
1963	.halt_reg = 0x6f02c,
1964	.halt_check = BRANCH_HALT,
1965	.clkr = {
1966		.enable_reg = 0x6f02c,
1967		.enable_mask = BIT(0),
1968		.hw.init = &(struct clk_init_data){
1969			.name = "gcc_pcie0_phy_refgen_clk",
1970			.parent_hws = (const struct clk_hw *[]){
1971				      &gcc_pcie_phy_refgen_clk_src.clkr.hw
1972			},
1973			.num_parents = 1,
1974			.flags = CLK_SET_RATE_PARENT,
1975			.ops = &clk_branch2_ops,
1976		},
1977	},
1978};
1979
1980static struct clk_branch gcc_pcie1_phy_refgen_clk = {
1981	.halt_reg = 0x6f030,
1982	.halt_check = BRANCH_HALT,
1983	.clkr = {
1984		.enable_reg = 0x6f030,
1985		.enable_mask = BIT(0),
1986		.hw.init = &(struct clk_init_data){
1987			.name = "gcc_pcie1_phy_refgen_clk",
1988			.parent_hws = (const struct clk_hw *[]){
1989				      &gcc_pcie_phy_refgen_clk_src.clkr.hw
1990			},
1991			.num_parents = 1,
1992			.flags = CLK_SET_RATE_PARENT,
1993			.ops = &clk_branch2_ops,
1994		},
1995	},
1996};
1997
1998static struct clk_branch gcc_pcie2_phy_refgen_clk = {
1999	.halt_reg = 0x6f034,
2000	.halt_check = BRANCH_HALT,
2001	.clkr = {
2002		.enable_reg = 0x6f034,
2003		.enable_mask = BIT(0),
2004		.hw.init = &(struct clk_init_data){
2005			.name = "gcc_pcie2_phy_refgen_clk",
2006			.parent_hws = (const struct clk_hw *[]){
2007				      &gcc_pcie_phy_refgen_clk_src.clkr.hw
2008			},
2009			.num_parents = 1,
2010			.flags = CLK_SET_RATE_PARENT,
2011			.ops = &clk_branch2_ops,
2012		},
2013	},
2014};
2015
2016static struct clk_branch gcc_pcie3_phy_refgen_clk = {
2017	.halt_reg = 0x6f038,
2018	.halt_check = BRANCH_HALT,
2019	.clkr = {
2020		.enable_reg = 0x6f038,
2021		.enable_mask = BIT(0),
2022		.hw.init = &(struct clk_init_data){
2023			.name = "gcc_pcie3_phy_refgen_clk",
2024			.parent_hws = (const struct clk_hw *[]){
2025				      &gcc_pcie_phy_refgen_clk_src.clkr.hw
2026			},
2027			.num_parents = 1,
2028			.flags = CLK_SET_RATE_PARENT,
2029			.ops = &clk_branch2_ops,
2030		},
2031	},
2032};
2033
2034static struct clk_branch gcc_pcie_0_aux_clk = {
2035	.halt_reg = 0x6b020,
2036	.halt_check = BRANCH_HALT_VOTED,
2037	.clkr = {
2038		.enable_reg = 0x5200c,
2039		.enable_mask = BIT(3),
2040		.hw.init = &(struct clk_init_data){
2041			.name = "gcc_pcie_0_aux_clk",
2042			.parent_hws = (const struct clk_hw *[]){
2043				      &gcc_pcie_0_aux_clk_src.clkr.hw
2044			},
2045			.num_parents = 1,
2046			.flags = CLK_SET_RATE_PARENT,
2047			.ops = &clk_branch2_ops,
2048		},
2049	},
2050};
2051
2052static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
2053	.halt_reg = 0x6b01c,
2054	.halt_check = BRANCH_HALT_VOTED,
2055	.hwcg_reg = 0x6b01c,
2056	.hwcg_bit = 1,
2057	.clkr = {
2058		.enable_reg = 0x5200c,
2059		.enable_mask = BIT(2),
2060		.hw.init = &(struct clk_init_data){
2061			.name = "gcc_pcie_0_cfg_ahb_clk",
2062			.ops = &clk_branch2_ops,
2063		},
2064	},
2065};
2066
2067static struct clk_branch gcc_pcie_0_clkref_clk = {
2068	.halt_reg = 0x8c00c,
2069	.halt_check = BRANCH_HALT,
2070	.clkr = {
2071		.enable_reg = 0x8c00c,
2072		.enable_mask = BIT(0),
2073		.hw.init = &(struct clk_init_data){
2074			.name = "gcc_pcie_0_clkref_clk",
2075			.ops = &clk_branch2_ops,
2076		},
2077	},
2078};
2079
2080static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
2081	.halt_reg = 0x6b018,
2082	.halt_check = BRANCH_HALT_VOTED,
2083	.clkr = {
2084		.enable_reg = 0x5200c,
2085		.enable_mask = BIT(1),
2086		.hw.init = &(struct clk_init_data){
2087			.name = "gcc_pcie_0_mstr_axi_clk",
2088			.ops = &clk_branch2_ops,
2089		},
2090	},
2091};
2092
2093static struct clk_branch gcc_pcie_0_pipe_clk = {
2094	.halt_reg = 0x6b024,
2095	.halt_check = BRANCH_HALT_SKIP,
2096	.clkr = {
2097		.enable_reg = 0x5200c,
2098		.enable_mask = BIT(4),
2099		.hw.init = &(struct clk_init_data){
2100			.name = "gcc_pcie_0_pipe_clk",
2101			.ops = &clk_branch2_ops,
2102		},
2103	},
2104};
2105
2106static struct clk_branch gcc_pcie_0_slv_axi_clk = {
2107	.halt_reg = 0x6b014,
2108	.halt_check = BRANCH_HALT_VOTED,
2109	.hwcg_reg = 0x6b014,
2110	.hwcg_bit = 1,
2111	.clkr = {
2112		.enable_reg = 0x5200c,
2113		.enable_mask = BIT(0),
2114		.hw.init = &(struct clk_init_data){
2115			.name = "gcc_pcie_0_slv_axi_clk",
2116			.ops = &clk_branch2_ops,
2117		},
2118	},
2119};
2120
2121static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
2122	.halt_reg = 0x6b010,
2123	.halt_check = BRANCH_HALT_VOTED,
2124	.clkr = {
2125		.enable_reg = 0x5200c,
2126		.enable_mask = BIT(5),
2127		.hw.init = &(struct clk_init_data){
2128			.name = "gcc_pcie_0_slv_q2a_axi_clk",
2129			.ops = &clk_branch2_ops,
2130		},
2131	},
2132};
2133
2134static struct clk_branch gcc_pcie_1_aux_clk = {
2135	.halt_reg = 0x8d020,
2136	.halt_check = BRANCH_HALT_VOTED,
2137	.clkr = {
2138		.enable_reg = 0x52004,
2139		.enable_mask = BIT(29),
2140		.hw.init = &(struct clk_init_data){
2141			.name = "gcc_pcie_1_aux_clk",
2142			.parent_hws = (const struct clk_hw *[]){
2143				&gcc_pcie_1_aux_clk_src.clkr.hw
2144			},
2145			.num_parents = 1,
2146			.flags = CLK_SET_RATE_PARENT,
2147			.ops = &clk_branch2_ops,
2148		},
2149	},
2150};
2151
2152static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
2153	.halt_reg = 0x8d01c,
2154	.halt_check = BRANCH_HALT_VOTED,
2155	.hwcg_reg = 0x8d01c,
2156	.hwcg_bit = 1,
2157	.clkr = {
2158		.enable_reg = 0x52004,
2159		.enable_mask = BIT(28),
2160		.hw.init = &(struct clk_init_data){
2161			.name = "gcc_pcie_1_cfg_ahb_clk",
2162			.ops = &clk_branch2_ops,
2163		},
2164	},
2165};
2166
2167static struct clk_branch gcc_pcie_1_clkref_clk = {
2168	.halt_reg = 0x8c02c,
2169	.halt_check = BRANCH_HALT,
2170	.clkr = {
2171		.enable_reg = 0x8c02c,
2172		.enable_mask = BIT(0),
2173		.hw.init = &(struct clk_init_data){
2174			.name = "gcc_pcie_1_clkref_clk",
2175			.ops = &clk_branch2_ops,
2176		},
2177	},
2178};
2179
2180static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
2181	.halt_reg = 0x8d018,
2182	.halt_check = BRANCH_HALT_VOTED,
2183	.clkr = {
2184		.enable_reg = 0x52004,
2185		.enable_mask = BIT(27),
2186		.hw.init = &(struct clk_init_data){
2187			.name = "gcc_pcie_1_mstr_axi_clk",
2188			.ops = &clk_branch2_ops,
2189		},
2190	},
2191};
2192
2193static struct clk_branch gcc_pcie_1_pipe_clk = {
2194	.halt_reg = 0x8d024,
2195	.halt_check = BRANCH_HALT_SKIP,
2196	.clkr = {
2197		.enable_reg = 0x52004,
2198		.enable_mask = BIT(30),
2199		.hw.init = &(struct clk_init_data){
2200			.name = "gcc_pcie_1_pipe_clk",
2201			.ops = &clk_branch2_ops,
2202		},
2203	},
2204};
2205
2206static struct clk_branch gcc_pcie_1_slv_axi_clk = {
2207	.halt_reg = 0x8d014,
2208	.halt_check = BRANCH_HALT_VOTED,
2209	.hwcg_reg = 0x8d014,
2210	.hwcg_bit = 1,
2211	.clkr = {
2212		.enable_reg = 0x52004,
2213		.enable_mask = BIT(26),
2214		.hw.init = &(struct clk_init_data){
2215			.name = "gcc_pcie_1_slv_axi_clk",
2216			.ops = &clk_branch2_ops,
2217		},
2218	},
2219};
2220
2221static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
2222	.halt_reg = 0x8d010,
2223	.halt_check = BRANCH_HALT_VOTED,
2224	.clkr = {
2225		.enable_reg = 0x52004,
2226		.enable_mask = BIT(25),
2227		.hw.init = &(struct clk_init_data){
2228			.name = "gcc_pcie_1_slv_q2a_axi_clk",
2229			.ops = &clk_branch2_ops,
2230		},
2231	},
2232};
2233
2234static struct clk_branch gcc_pcie_2_aux_clk = {
2235	.halt_reg = 0x9d020,
2236	.halt_check = BRANCH_HALT_VOTED,
2237	.clkr = {
2238		.enable_reg = 0x52014,
2239		.enable_mask = BIT(14),
2240		.hw.init = &(struct clk_init_data){
2241			.name = "gcc_pcie_2_aux_clk",
2242			.parent_hws = (const struct clk_hw *[]){
2243				&gcc_pcie_2_aux_clk_src.clkr.hw
2244			},
2245			.num_parents = 1,
2246			.flags = CLK_SET_RATE_PARENT,
2247			.ops = &clk_branch2_ops,
2248		},
2249	},
2250};
2251
2252static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
2253	.halt_reg = 0x9d01c,
2254	.halt_check = BRANCH_HALT_VOTED,
2255	.hwcg_reg = 0x9d01c,
2256	.hwcg_bit = 1,
2257	.clkr = {
2258		.enable_reg = 0x52014,
2259		.enable_mask = BIT(13),
2260		.hw.init = &(struct clk_init_data){
2261			.name = "gcc_pcie_2_cfg_ahb_clk",
2262			.ops = &clk_branch2_ops,
2263		},
2264	},
2265};
2266
2267static struct clk_branch gcc_pcie_2_clkref_clk = {
2268	.halt_reg = 0x8c014,
2269	.halt_check = BRANCH_HALT,
2270	.clkr = {
2271		.enable_reg = 0x8c014,
2272		.enable_mask = BIT(0),
2273		.hw.init = &(struct clk_init_data){
2274			.name = "gcc_pcie_2_clkref_clk",
2275			.ops = &clk_branch2_ops,
2276		},
2277	},
2278};
2279
2280static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
2281	.halt_reg = 0x9d018,
2282	.halt_check = BRANCH_HALT_VOTED,
2283	.clkr = {
2284		.enable_reg = 0x52014,
2285		.enable_mask = BIT(12),
2286		.hw.init = &(struct clk_init_data){
2287			.name = "gcc_pcie_2_mstr_axi_clk",
2288			.ops = &clk_branch2_ops,
2289		},
2290	},
2291};
2292
2293static struct clk_branch gcc_pcie_2_pipe_clk = {
2294	.halt_reg = 0x9d024,
2295	.halt_check = BRANCH_HALT_SKIP,
2296	.clkr = {
2297		.enable_reg = 0x52014,
2298		.enable_mask = BIT(15),
2299		.hw.init = &(struct clk_init_data){
2300			.name = "gcc_pcie_2_pipe_clk",
2301			.ops = &clk_branch2_ops,
2302		},
2303	},
2304};
2305
2306static struct clk_branch gcc_pcie_2_slv_axi_clk = {
2307	.halt_reg = 0x9d014,
2308	.halt_check = BRANCH_HALT_VOTED,
2309	.hwcg_reg = 0x9d014,
2310	.hwcg_bit = 1,
2311	.clkr = {
2312		.enable_reg = 0x52014,
2313		.enable_mask = BIT(11),
2314		.hw.init = &(struct clk_init_data){
2315			.name = "gcc_pcie_2_slv_axi_clk",
2316			.ops = &clk_branch2_ops,
2317		},
2318	},
2319};
2320
2321static struct clk_branch gcc_pcie_2_slv_q2a_axi_clk = {
2322	.halt_reg = 0x9d010,
2323	.halt_check = BRANCH_HALT_VOTED,
2324	.clkr = {
2325		.enable_reg = 0x52014,
2326		.enable_mask = BIT(10),
2327		.hw.init = &(struct clk_init_data){
2328			.name = "gcc_pcie_2_slv_q2a_axi_clk",
2329			.ops = &clk_branch2_ops,
2330		},
2331	},
2332};
2333
2334static struct clk_branch gcc_pcie_3_aux_clk = {
2335	.halt_reg = 0xa3020,
2336	.halt_check = BRANCH_HALT_VOTED,
2337	.clkr = {
2338		.enable_reg = 0x52014,
2339		.enable_mask = BIT(20),
2340		.hw.init = &(struct clk_init_data){
2341			.name = "gcc_pcie_3_aux_clk",
2342			.parent_hws = (const struct clk_hw *[]){
2343				&gcc_pcie_3_aux_clk_src.clkr.hw
2344			},
2345			.num_parents = 1,
2346			.flags = CLK_SET_RATE_PARENT,
2347			.ops = &clk_branch2_ops,
2348		},
2349	},
2350};
2351
2352static struct clk_branch gcc_pcie_3_cfg_ahb_clk = {
2353	.halt_reg = 0xa301c,
2354	.halt_check = BRANCH_HALT_VOTED,
2355	.hwcg_reg = 0xa301c,
2356	.hwcg_bit = 1,
2357	.clkr = {
2358		.enable_reg = 0x52014,
2359		.enable_mask = BIT(19),
2360		.hw.init = &(struct clk_init_data){
2361			.name = "gcc_pcie_3_cfg_ahb_clk",
2362			.ops = &clk_branch2_ops,
2363		},
2364	},
2365};
2366
2367static struct clk_branch gcc_pcie_3_clkref_clk = {
2368	.halt_reg = 0x8c018,
2369	.halt_check = BRANCH_HALT,
2370	.clkr = {
2371		.enable_reg = 0x8c018,
2372		.enable_mask = BIT(0),
2373		.hw.init = &(struct clk_init_data){
2374			.name = "gcc_pcie_3_clkref_clk",
2375			.ops = &clk_branch2_ops,
2376		},
2377	},
2378};
2379
2380static struct clk_branch gcc_pcie_3_mstr_axi_clk = {
2381	.halt_reg = 0xa3018,
2382	.halt_check = BRANCH_HALT_VOTED,
2383	.clkr = {
2384		.enable_reg = 0x52014,
2385		.enable_mask = BIT(18),
2386		.hw.init = &(struct clk_init_data){
2387			.name = "gcc_pcie_3_mstr_axi_clk",
2388			.ops = &clk_branch2_ops,
2389		},
2390	},
2391};
2392
2393static struct clk_branch gcc_pcie_3_pipe_clk = {
2394	.halt_reg = 0xa3024,
2395	.halt_check = BRANCH_HALT_SKIP,
2396	.clkr = {
2397		.enable_reg = 0x52014,
2398		.enable_mask = BIT(21),
2399		.hw.init = &(struct clk_init_data){
2400			.name = "gcc_pcie_3_pipe_clk",
2401			.ops = &clk_branch2_ops,
2402		},
2403	},
2404};
2405
2406static struct clk_branch gcc_pcie_3_slv_axi_clk = {
2407	.halt_reg = 0xa3014,
2408	.halt_check = BRANCH_HALT_VOTED,
2409	.hwcg_reg = 0xa3014,
2410	.hwcg_bit = 1,
2411	.clkr = {
2412		.enable_reg = 0x52014,
2413		.enable_mask = BIT(17),
2414		.hw.init = &(struct clk_init_data){
2415			.name = "gcc_pcie_3_slv_axi_clk",
2416			.ops = &clk_branch2_ops,
2417		},
2418	},
2419};
2420
2421static struct clk_branch gcc_pcie_3_slv_q2a_axi_clk = {
2422	.halt_reg = 0xa3010,
2423	.halt_check = BRANCH_HALT_VOTED,
2424	.clkr = {
2425		.enable_reg = 0x52014,
2426		.enable_mask = BIT(16),
2427		.hw.init = &(struct clk_init_data){
2428			.name = "gcc_pcie_3_slv_q2a_axi_clk",
2429			.ops = &clk_branch2_ops,
2430		},
2431	},
2432};
2433
2434static struct clk_branch gcc_pcie_phy_aux_clk = {
2435	.halt_reg = 0x6f004,
2436	.halt_check = BRANCH_HALT,
2437	.clkr = {
2438		.enable_reg = 0x6f004,
2439		.enable_mask = BIT(0),
2440		.hw.init = &(struct clk_init_data){
2441			.name = "gcc_pcie_phy_aux_clk",
2442			.parent_hws = (const struct clk_hw *[]){
2443				      &gcc_pcie_0_aux_clk_src.clkr.hw
2444			},
2445			.num_parents = 1,
2446			.flags = CLK_SET_RATE_PARENT,
2447			.ops = &clk_branch2_ops,
2448		},
2449	},
2450};
2451
2452static struct clk_branch gcc_pdm2_clk = {
2453	.halt_reg = 0x3300c,
2454	.halt_check = BRANCH_HALT,
2455	.clkr = {
2456		.enable_reg = 0x3300c,
2457		.enable_mask = BIT(0),
2458		.hw.init = &(struct clk_init_data){
2459			.name = "gcc_pdm2_clk",
2460			.parent_hws = (const struct clk_hw *[]){
2461				      &gcc_pdm2_clk_src.clkr.hw
2462			},
2463			.num_parents = 1,
2464			.flags = CLK_SET_RATE_PARENT,
2465			.ops = &clk_branch2_ops,
2466		},
2467	},
2468};
2469
2470static struct clk_branch gcc_pdm_ahb_clk = {
2471	.halt_reg = 0x33004,
2472	.halt_check = BRANCH_HALT,
2473	.hwcg_reg = 0x33004,
2474	.hwcg_bit = 1,
2475	.clkr = {
2476		.enable_reg = 0x33004,
2477		.enable_mask = BIT(0),
2478		.hw.init = &(struct clk_init_data){
2479			.name = "gcc_pdm_ahb_clk",
2480			.ops = &clk_branch2_ops,
2481		},
2482	},
2483};
2484
2485static struct clk_branch gcc_pdm_xo4_clk = {
2486	.halt_reg = 0x33008,
2487	.halt_check = BRANCH_HALT,
2488	.clkr = {
2489		.enable_reg = 0x33008,
2490		.enable_mask = BIT(0),
2491		.hw.init = &(struct clk_init_data){
2492			.name = "gcc_pdm_xo4_clk",
2493			.ops = &clk_branch2_ops,
2494		},
2495	},
2496};
2497
2498static struct clk_branch gcc_prng_ahb_clk = {
2499	.halt_reg = 0x34004,
2500	.halt_check = BRANCH_HALT_VOTED,
2501	.clkr = {
2502		.enable_reg = 0x52004,
2503		.enable_mask = BIT(13),
2504		.hw.init = &(struct clk_init_data){
2505			.name = "gcc_prng_ahb_clk",
2506			.ops = &clk_branch2_ops,
2507		},
2508	},
2509};
2510
2511static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
2512	.halt_reg = 0xb018,
2513	.halt_check = BRANCH_HALT,
2514	.hwcg_reg = 0xb018,
2515	.hwcg_bit = 1,
2516	.clkr = {
2517		.enable_reg = 0xb018,
2518		.enable_mask = BIT(0),
2519		.hw.init = &(struct clk_init_data){
2520			.name = "gcc_qmip_camera_nrt_ahb_clk",
2521			.ops = &clk_branch2_ops,
2522		},
2523	},
2524};
2525
2526static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
2527	.halt_reg = 0xb01c,
2528	.halt_check = BRANCH_HALT,
2529	.hwcg_reg = 0xb01c,
2530	.hwcg_bit = 1,
2531	.clkr = {
2532		.enable_reg = 0xb01c,
2533		.enable_mask = BIT(0),
2534		.hw.init = &(struct clk_init_data){
2535			.name = "gcc_qmip_camera_rt_ahb_clk",
2536			.ops = &clk_branch2_ops,
2537		},
2538	},
2539};
2540
2541static struct clk_branch gcc_qmip_disp_ahb_clk = {
2542	.halt_reg = 0xb020,
2543	.halt_check = BRANCH_HALT,
2544	.hwcg_reg = 0xb020,
2545	.hwcg_bit = 1,
2546	.clkr = {
2547		.enable_reg = 0xb020,
2548		.enable_mask = BIT(0),
2549		.hw.init = &(struct clk_init_data){
2550			.name = "gcc_qmip_disp_ahb_clk",
2551			.ops = &clk_branch2_ops,
2552		},
2553	},
2554};
2555
2556static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
2557	.halt_reg = 0xb010,
2558	.halt_check = BRANCH_HALT,
2559	.hwcg_reg = 0xb010,
2560	.hwcg_bit = 1,
2561	.clkr = {
2562		.enable_reg = 0xb010,
2563		.enable_mask = BIT(0),
2564		.hw.init = &(struct clk_init_data){
2565			.name = "gcc_qmip_video_cvp_ahb_clk",
2566			.ops = &clk_branch2_ops,
2567		},
2568	},
2569};
2570
2571static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
2572	.halt_reg = 0xb014,
2573	.halt_check = BRANCH_HALT,
2574	.hwcg_reg = 0xb014,
2575	.hwcg_bit = 1,
2576	.clkr = {
2577		.enable_reg = 0xb014,
2578		.enable_mask = BIT(0),
2579		.hw.init = &(struct clk_init_data){
2580			.name = "gcc_qmip_video_vcodec_ahb_clk",
2581			.ops = &clk_branch2_ops,
2582		},
2583	},
2584};
2585
2586static struct clk_branch gcc_qspi_1_cnoc_periph_ahb_clk = {
2587	.halt_reg = 0x4a004,
2588	.halt_check = BRANCH_HALT,
2589	.clkr = {
2590		.enable_reg = 0x4a004,
2591		.enable_mask = BIT(0),
2592		.hw.init = &(struct clk_init_data){
2593			.name = "gcc_qspi_1_cnoc_periph_ahb_clk",
2594			.ops = &clk_branch2_ops,
2595		},
2596	},
2597};
2598
2599static struct clk_branch gcc_qspi_1_core_clk = {
2600	.halt_reg = 0x4a008,
2601	.halt_check = BRANCH_HALT,
2602	.clkr = {
2603		.enable_reg = 0x4a008,
2604		.enable_mask = BIT(0),
2605		.hw.init = &(struct clk_init_data){
2606			.name = "gcc_qspi_1_core_clk",
2607			.parent_hws = (const struct clk_hw *[]){
2608				      &gcc_qspi_1_core_clk_src.clkr.hw
2609			},
2610			.num_parents = 1,
2611			.flags = CLK_SET_RATE_PARENT,
2612			.ops = &clk_branch2_ops,
2613		},
2614	},
2615};
2616
2617static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
2618	.halt_reg = 0x4b000,
2619	.halt_check = BRANCH_HALT,
2620	.clkr = {
2621		.enable_reg = 0x4b000,
2622		.enable_mask = BIT(0),
2623		.hw.init = &(struct clk_init_data){
2624			.name = "gcc_qspi_cnoc_periph_ahb_clk",
2625			.ops = &clk_branch2_ops,
2626		},
2627	},
2628};
2629
2630static struct clk_branch gcc_qspi_core_clk = {
2631	.halt_reg = 0x4b004,
2632	.halt_check = BRANCH_HALT,
2633	.clkr = {
2634		.enable_reg = 0x4b004,
2635		.enable_mask = BIT(0),
2636		.hw.init = &(struct clk_init_data){
2637			.name = "gcc_qspi_core_clk",
2638			.parent_hws = (const struct clk_hw *[]){
2639				      &gcc_qspi_core_clk_src.clkr.hw
2640			},
2641			.num_parents = 1,
2642			.flags = CLK_SET_RATE_PARENT,
2643			.ops = &clk_branch2_ops,
2644		},
2645	},
2646};
2647
2648static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
2649	.halt_reg = 0x17144,
2650	.halt_check = BRANCH_HALT_VOTED,
2651	.clkr = {
2652		.enable_reg = 0x5200c,
2653		.enable_mask = BIT(10),
2654		.hw.init = &(struct clk_init_data){
2655			.name = "gcc_qupv3_wrap0_s0_clk",
2656			.parent_hws = (const struct clk_hw *[]){
2657				      &gcc_qupv3_wrap0_s0_clk_src.clkr.hw
2658			},
2659			.num_parents = 1,
2660			.flags = CLK_SET_RATE_PARENT,
2661			.ops = &clk_branch2_ops,
2662		},
2663	},
2664};
2665
2666static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
2667	.halt_reg = 0x17274,
2668	.halt_check = BRANCH_HALT_VOTED,
2669	.clkr = {
2670		.enable_reg = 0x5200c,
2671		.enable_mask = BIT(11),
2672		.hw.init = &(struct clk_init_data){
2673			.name = "gcc_qupv3_wrap0_s1_clk",
2674			.parent_hws = (const struct clk_hw *[]){
2675				&gcc_qupv3_wrap0_s1_clk_src.clkr.hw
2676			},
2677			.num_parents = 1,
2678			.flags = CLK_SET_RATE_PARENT,
2679			.ops = &clk_branch2_ops,
2680		},
2681	},
2682};
2683
2684static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
2685	.halt_reg = 0x173a4,
2686	.halt_check = BRANCH_HALT_VOTED,
2687	.clkr = {
2688		.enable_reg = 0x5200c,
2689		.enable_mask = BIT(12),
2690		.hw.init = &(struct clk_init_data){
2691			.name = "gcc_qupv3_wrap0_s2_clk",
2692			.parent_hws = (const struct clk_hw *[]){
2693				&gcc_qupv3_wrap0_s2_clk_src.clkr.hw
2694			},
2695			.num_parents = 1,
2696			.flags = CLK_SET_RATE_PARENT,
2697			.ops = &clk_branch2_ops,
2698		},
2699	},
2700};
2701
2702static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
2703	.halt_reg = 0x174d4,
2704	.halt_check = BRANCH_HALT_VOTED,
2705	.clkr = {
2706		.enable_reg = 0x5200c,
2707		.enable_mask = BIT(13),
2708		.hw.init = &(struct clk_init_data){
2709			.name = "gcc_qupv3_wrap0_s3_clk",
2710			.parent_hws = (const struct clk_hw *[]){
2711				&gcc_qupv3_wrap0_s3_clk_src.clkr.hw
2712			},
2713			.num_parents = 1,
2714			.flags = CLK_SET_RATE_PARENT,
2715			.ops = &clk_branch2_ops,
2716		},
2717	},
2718};
2719
2720static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2721	.halt_reg = 0x17604,
2722	.halt_check = BRANCH_HALT_VOTED,
2723	.clkr = {
2724		.enable_reg = 0x5200c,
2725		.enable_mask = BIT(14),
2726		.hw.init = &(struct clk_init_data){
2727			.name = "gcc_qupv3_wrap0_s4_clk",
2728			.parent_hws = (const struct clk_hw *[]){
2729				&gcc_qupv3_wrap0_s4_clk_src.clkr.hw
2730			},
2731			.num_parents = 1,
2732			.flags = CLK_SET_RATE_PARENT,
2733			.ops = &clk_branch2_ops,
2734		},
2735	},
2736};
2737
2738static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2739	.halt_reg = 0x17734,
2740	.halt_check = BRANCH_HALT_VOTED,
2741	.clkr = {
2742		.enable_reg = 0x5200c,
2743		.enable_mask = BIT(15),
2744		.hw.init = &(struct clk_init_data){
2745			.name = "gcc_qupv3_wrap0_s5_clk",
2746			.parent_hws = (const struct clk_hw *[]){
2747				&gcc_qupv3_wrap0_s5_clk_src.clkr.hw
2748			},
2749			.num_parents = 1,
2750			.flags = CLK_SET_RATE_PARENT,
2751			.ops = &clk_branch2_ops,
2752		},
2753	},
2754};
2755
2756static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
2757	.halt_reg = 0x17864,
2758	.halt_check = BRANCH_HALT_VOTED,
2759	.clkr = {
2760		.enable_reg = 0x5200c,
2761		.enable_mask = BIT(16),
2762		.hw.init = &(struct clk_init_data){
2763			.name = "gcc_qupv3_wrap0_s6_clk",
2764			.parent_hws = (const struct clk_hw *[]){
2765				&gcc_qupv3_wrap0_s6_clk_src.clkr.hw
2766			},
2767			.num_parents = 1,
2768			.flags = CLK_SET_RATE_PARENT,
2769			.ops = &clk_branch2_ops,
2770		},
2771	},
2772};
2773
2774static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
2775	.halt_reg = 0x17994,
2776	.halt_check = BRANCH_HALT_VOTED,
2777	.clkr = {
2778		.enable_reg = 0x5200c,
2779		.enable_mask = BIT(17),
2780		.hw.init = &(struct clk_init_data){
2781			.name = "gcc_qupv3_wrap0_s7_clk",
2782			.parent_hws = (const struct clk_hw *[]){
2783				&gcc_qupv3_wrap0_s7_clk_src.clkr.hw
2784			},
2785			.num_parents = 1,
2786			.flags = CLK_SET_RATE_PARENT,
2787			.ops = &clk_branch2_ops,
2788		},
2789	},
2790};
2791
2792static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
2793	.halt_reg = 0x18144,
2794	.halt_check = BRANCH_HALT_VOTED,
2795	.clkr = {
2796		.enable_reg = 0x5200c,
2797		.enable_mask = BIT(22),
2798		.hw.init = &(struct clk_init_data){
2799			.name = "gcc_qupv3_wrap1_s0_clk",
2800			.parent_hws = (const struct clk_hw *[]){
2801				&gcc_qupv3_wrap1_s0_clk_src.clkr.hw
2802			},
2803			.num_parents = 1,
2804			.flags = CLK_SET_RATE_PARENT,
2805			.ops = &clk_branch2_ops,
2806		},
2807	},
2808};
2809
2810static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
2811	.halt_reg = 0x18274,
2812	.halt_check = BRANCH_HALT_VOTED,
2813	.clkr = {
2814		.enable_reg = 0x5200c,
2815		.enable_mask = BIT(23),
2816		.hw.init = &(struct clk_init_data){
2817			.name = "gcc_qupv3_wrap1_s1_clk",
2818			.parent_hws = (const struct clk_hw *[]){
2819				&gcc_qupv3_wrap1_s1_clk_src.clkr.hw
2820			},
2821			.num_parents = 1,
2822			.flags = CLK_SET_RATE_PARENT,
2823			.ops = &clk_branch2_ops,
2824		},
2825	},
2826};
2827
2828static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
2829	.halt_reg = 0x183a4,
2830	.halt_check = BRANCH_HALT_VOTED,
2831	.clkr = {
2832		.enable_reg = 0x5200c,
2833		.enable_mask = BIT(24),
2834		.hw.init = &(struct clk_init_data){
2835			.name = "gcc_qupv3_wrap1_s2_clk",
2836			.parent_hws = (const struct clk_hw *[]){
2837				&gcc_qupv3_wrap1_s2_clk_src.clkr.hw
2838			},
2839			.num_parents = 1,
2840			.flags = CLK_SET_RATE_PARENT,
2841			.ops = &clk_branch2_ops,
2842		},
2843	},
2844};
2845
2846static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
2847	.halt_reg = 0x184d4,
2848	.halt_check = BRANCH_HALT_VOTED,
2849	.clkr = {
2850		.enable_reg = 0x5200c,
2851		.enable_mask = BIT(25),
2852		.hw.init = &(struct clk_init_data){
2853			.name = "gcc_qupv3_wrap1_s3_clk",
2854			.parent_hws = (const struct clk_hw *[]){
2855				&gcc_qupv3_wrap1_s3_clk_src.clkr.hw
2856			},
2857			.num_parents = 1,
2858			.flags = CLK_SET_RATE_PARENT,
2859			.ops = &clk_branch2_ops,
2860		},
2861	},
2862};
2863
2864static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
2865	.halt_reg = 0x18604,
2866	.halt_check = BRANCH_HALT_VOTED,
2867	.clkr = {
2868		.enable_reg = 0x5200c,
2869		.enable_mask = BIT(26),
2870		.hw.init = &(struct clk_init_data){
2871			.name = "gcc_qupv3_wrap1_s4_clk",
2872			.parent_hws = (const struct clk_hw *[]){
2873				&gcc_qupv3_wrap1_s4_clk_src.clkr.hw
2874			},
2875			.num_parents = 1,
2876			.flags = CLK_SET_RATE_PARENT,
2877			.ops = &clk_branch2_ops,
2878		},
2879	},
2880};
2881
2882static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
2883	.halt_reg = 0x18734,
2884	.halt_check = BRANCH_HALT_VOTED,
2885	.clkr = {
2886		.enable_reg = 0x5200c,
2887		.enable_mask = BIT(27),
2888		.hw.init = &(struct clk_init_data){
2889			.name = "gcc_qupv3_wrap1_s5_clk",
2890			.parent_hws = (const struct clk_hw *[]){
2891				&gcc_qupv3_wrap1_s5_clk_src.clkr.hw
2892			},
2893			.num_parents = 1,
2894			.flags = CLK_SET_RATE_PARENT,
2895			.ops = &clk_branch2_ops,
2896		},
2897	},
2898};
2899
2900static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
2901	.halt_reg = 0x1e144,
2902	.halt_check = BRANCH_HALT_VOTED,
2903	.clkr = {
2904		.enable_reg = 0x52014,
2905		.enable_mask = BIT(4),
2906		.hw.init = &(struct clk_init_data){
2907			.name = "gcc_qupv3_wrap2_s0_clk",
2908			.parent_hws = (const struct clk_hw *[]){
2909				&gcc_qupv3_wrap2_s0_clk_src.clkr.hw
2910			},
2911			.num_parents = 1,
2912			.flags = CLK_SET_RATE_PARENT,
2913			.ops = &clk_branch2_ops,
2914		},
2915	},
2916};
2917
2918static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
2919	.halt_reg = 0x1e274,
2920	.halt_check = BRANCH_HALT_VOTED,
2921	.clkr = {
2922		.enable_reg = 0x52014,
2923		.enable_mask = BIT(5),
2924		.hw.init = &(struct clk_init_data){
2925			.name = "gcc_qupv3_wrap2_s1_clk",
2926			.parent_hws = (const struct clk_hw *[]){
2927				&gcc_qupv3_wrap2_s1_clk_src.clkr.hw
2928			},
2929			.num_parents = 1,
2930			.flags = CLK_SET_RATE_PARENT,
2931			.ops = &clk_branch2_ops,
2932		},
2933	},
2934};
2935
2936static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
2937	.halt_reg = 0x1e3a4,
2938	.halt_check = BRANCH_HALT_VOTED,
2939	.clkr = {
2940		.enable_reg = 0x52014,
2941		.enable_mask = BIT(6),
2942		.hw.init = &(struct clk_init_data){
2943			.name = "gcc_qupv3_wrap2_s2_clk",
2944			.parent_hws = (const struct clk_hw *[]){
2945				&gcc_qupv3_wrap2_s2_clk_src.clkr.hw
2946			},
2947			.num_parents = 1,
2948			.flags = CLK_SET_RATE_PARENT,
2949			.ops = &clk_branch2_ops,
2950		},
2951	},
2952};
2953
2954static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
2955	.halt_reg = 0x1e4d4,
2956	.halt_check = BRANCH_HALT_VOTED,
2957	.clkr = {
2958		.enable_reg = 0x52014,
2959		.enable_mask = BIT(7),
2960		.hw.init = &(struct clk_init_data){
2961			.name = "gcc_qupv3_wrap2_s3_clk",
2962			.parent_hws = (const struct clk_hw *[]){
2963				&gcc_qupv3_wrap2_s3_clk_src.clkr.hw
2964			},
2965			.num_parents = 1,
2966			.flags = CLK_SET_RATE_PARENT,
2967			.ops = &clk_branch2_ops,
2968		},
2969	},
2970};
2971
2972static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
2973	.halt_reg = 0x1e604,
2974	.halt_check = BRANCH_HALT_VOTED,
2975	.clkr = {
2976		.enable_reg = 0x52014,
2977		.enable_mask = BIT(8),
2978		.hw.init = &(struct clk_init_data){
2979			.name = "gcc_qupv3_wrap2_s4_clk",
2980			.parent_hws = (const struct clk_hw *[]){
2981				&gcc_qupv3_wrap2_s4_clk_src.clkr.hw
2982			},
2983			.num_parents = 1,
2984			.flags = CLK_SET_RATE_PARENT,
2985			.ops = &clk_branch2_ops,
2986		},
2987	},
2988};
2989
2990static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
2991	.halt_reg = 0x1e734,
2992	.halt_check = BRANCH_HALT_VOTED,
2993	.clkr = {
2994		.enable_reg = 0x52014,
2995		.enable_mask = BIT(9),
2996		.hw.init = &(struct clk_init_data){
2997			.name = "gcc_qupv3_wrap2_s5_clk",
2998			.parent_hws = (const struct clk_hw *[]){
2999				&gcc_qupv3_wrap2_s5_clk_src.clkr.hw
3000			},
3001			.num_parents = 1,
3002			.flags = CLK_SET_RATE_PARENT,
3003			.ops = &clk_branch2_ops,
3004		},
3005	},
3006};
3007
3008static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
3009	.halt_reg = 0x17004,
3010	.halt_check = BRANCH_HALT_VOTED,
3011	.clkr = {
3012		.enable_reg = 0x5200c,
3013		.enable_mask = BIT(6),
3014		.hw.init = &(struct clk_init_data){
3015			.name = "gcc_qupv3_wrap_0_m_ahb_clk",
3016			.ops = &clk_branch2_ops,
3017		},
3018	},
3019};
3020
3021static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
3022	.halt_reg = 0x17008,
3023	.halt_check = BRANCH_HALT_VOTED,
3024	.hwcg_reg = 0x17008,
3025	.hwcg_bit = 1,
3026	.clkr = {
3027		.enable_reg = 0x5200c,
3028		.enable_mask = BIT(7),
3029		.hw.init = &(struct clk_init_data){
3030			.name = "gcc_qupv3_wrap_0_s_ahb_clk",
3031			.ops = &clk_branch2_ops,
3032		},
3033	},
3034};
3035
3036static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
3037	.halt_reg = 0x18004,
3038	.halt_check = BRANCH_HALT_VOTED,
3039	.clkr = {
3040		.enable_reg = 0x5200c,
3041		.enable_mask = BIT(20),
3042		.hw.init = &(struct clk_init_data){
3043			.name = "gcc_qupv3_wrap_1_m_ahb_clk",
3044			.ops = &clk_branch2_ops,
3045		},
3046	},
3047};
3048
3049static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
3050	.halt_reg = 0x18008,
3051	.halt_check = BRANCH_HALT_VOTED,
3052	.hwcg_reg = 0x18008,
3053	.hwcg_bit = 1,
3054	.clkr = {
3055		.enable_reg = 0x5200c,
3056		.enable_mask = BIT(21),
3057		.hw.init = &(struct clk_init_data){
3058			.name = "gcc_qupv3_wrap_1_s_ahb_clk",
3059			.ops = &clk_branch2_ops,
3060		},
3061	},
3062};
3063
3064static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
3065	.halt_reg = 0x1e004,
3066	.halt_check = BRANCH_HALT_VOTED,
3067	.clkr = {
3068		.enable_reg = 0x52014,
3069		.enable_mask = BIT(2),
3070		.hw.init = &(struct clk_init_data){
3071			.name = "gcc_qupv3_wrap_2_m_ahb_clk",
3072			.ops = &clk_branch2_ops,
3073		},
3074	},
3075};
3076
3077static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
3078	.halt_reg = 0x1e008,
3079	.halt_check = BRANCH_HALT_VOTED,
3080	.hwcg_reg = 0x1e008,
3081	.hwcg_bit = 1,
3082	.clkr = {
3083		.enable_reg = 0x52014,
3084		.enable_mask = BIT(1),
3085		.hw.init = &(struct clk_init_data){
3086			.name = "gcc_qupv3_wrap_2_s_ahb_clk",
3087			.ops = &clk_branch2_ops,
3088		},
3089	},
3090};
3091
3092static struct clk_branch gcc_sdcc2_ahb_clk = {
3093	.halt_reg = 0x14008,
3094	.halt_check = BRANCH_HALT,
3095	.clkr = {
3096		.enable_reg = 0x14008,
3097		.enable_mask = BIT(0),
3098		.hw.init = &(struct clk_init_data){
3099			.name = "gcc_sdcc2_ahb_clk",
3100			.ops = &clk_branch2_ops,
3101		},
3102	},
3103};
3104
3105static struct clk_branch gcc_sdcc2_apps_clk = {
3106	.halt_reg = 0x14004,
3107	.halt_check = BRANCH_HALT,
3108	.clkr = {
3109		.enable_reg = 0x14004,
3110		.enable_mask = BIT(0),
3111		.hw.init = &(struct clk_init_data){
3112			.name = "gcc_sdcc2_apps_clk",
3113			.parent_hws = (const struct clk_hw *[]){
3114				&gcc_sdcc2_apps_clk_src.clkr.hw
3115			},
3116			.num_parents = 1,
3117			.flags = CLK_SET_RATE_PARENT,
3118			.ops = &clk_branch2_ops,
3119		},
3120	},
3121};
3122
3123static struct clk_branch gcc_sdcc4_ahb_clk = {
3124	.halt_reg = 0x16008,
3125	.halt_check = BRANCH_HALT,
3126	.clkr = {
3127		.enable_reg = 0x16008,
3128		.enable_mask = BIT(0),
3129		.hw.init = &(struct clk_init_data){
3130			.name = "gcc_sdcc4_ahb_clk",
3131			.ops = &clk_branch2_ops,
3132		},
3133	},
3134};
3135
3136static struct clk_branch gcc_sdcc4_apps_clk = {
3137	.halt_reg = 0x16004,
3138	.halt_check = BRANCH_HALT,
3139	.clkr = {
3140		.enable_reg = 0x16004,
3141		.enable_mask = BIT(0),
3142		.hw.init = &(struct clk_init_data){
3143			.name = "gcc_sdcc4_apps_clk",
3144			.parent_hws = (const struct clk_hw *[]){
3145				&gcc_sdcc4_apps_clk_src.clkr.hw
3146			},
3147			.num_parents = 1,
3148			.flags = CLK_SET_RATE_PARENT,
3149			.ops = &clk_branch2_ops,
3150		},
3151	},
3152};
3153
3154/* For CPUSS functionality the SYS NOC clock needs to be left enabled */
3155static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
3156	.halt_reg = 0x4819c,
3157	.halt_check = BRANCH_HALT_VOTED,
3158	.clkr = {
3159		.enable_reg = 0x52004,
3160		.enable_mask = BIT(0),
3161		.hw.init = &(struct clk_init_data){
3162			.name = "gcc_sys_noc_cpuss_ahb_clk",
3163			.parent_hws = (const struct clk_hw *[]){
3164				      &gcc_cpuss_ahb_clk_src.clkr.hw
3165			},
3166			.num_parents = 1,
3167			.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
3168			.ops = &clk_branch2_ops,
3169		},
3170	},
3171};
3172
3173static struct clk_branch gcc_tsif_ahb_clk = {
3174	.halt_reg = 0x36004,
3175	.halt_check = BRANCH_HALT,
3176	.clkr = {
3177		.enable_reg = 0x36004,
3178		.enable_mask = BIT(0),
3179		.hw.init = &(struct clk_init_data){
3180			.name = "gcc_tsif_ahb_clk",
3181			.ops = &clk_branch2_ops,
3182		},
3183	},
3184};
3185
3186static struct clk_branch gcc_tsif_inactivity_timers_clk = {
3187	.halt_reg = 0x3600c,
3188	.halt_check = BRANCH_HALT,
3189	.clkr = {
3190		.enable_reg = 0x3600c,
3191		.enable_mask = BIT(0),
3192		.hw.init = &(struct clk_init_data){
3193			.name = "gcc_tsif_inactivity_timers_clk",
3194			.ops = &clk_branch2_ops,
3195		},
3196	},
3197};
3198
3199static struct clk_branch gcc_tsif_ref_clk = {
3200	.halt_reg = 0x36008,
3201	.halt_check = BRANCH_HALT,
3202	.clkr = {
3203		.enable_reg = 0x36008,
3204		.enable_mask = BIT(0),
3205		.hw.init = &(struct clk_init_data){
3206			.name = "gcc_tsif_ref_clk",
3207			.parent_hws = (const struct clk_hw *[]){
3208				&gcc_tsif_ref_clk_src.clkr.hw
3209			},
3210			.num_parents = 1,
3211			.flags = CLK_SET_RATE_PARENT,
3212			.ops = &clk_branch2_ops,
3213		},
3214	},
3215};
3216
3217static struct clk_branch gcc_ufs_card_2_ahb_clk = {
3218	.halt_reg = 0xa2014,
3219	.halt_check = BRANCH_HALT,
3220	.hwcg_reg = 0xa2014,
3221	.hwcg_bit = 1,
3222	.clkr = {
3223		.enable_reg = 0xa2014,
3224		.enable_mask = BIT(0),
3225		.hw.init = &(struct clk_init_data){
3226			.name = "gcc_ufs_card_2_ahb_clk",
3227			.ops = &clk_branch2_ops,
3228		},
3229	},
3230};
3231
3232static struct clk_branch gcc_ufs_card_2_axi_clk = {
3233	.halt_reg = 0xa2010,
3234	.halt_check = BRANCH_HALT,
3235	.hwcg_reg = 0xa2010,
3236	.hwcg_bit = 1,
3237	.clkr = {
3238		.enable_reg = 0xa2010,
3239		.enable_mask = BIT(0),
3240		.hw.init = &(struct clk_init_data){
3241			.name = "gcc_ufs_card_2_axi_clk",
3242			.parent_hws = (const struct clk_hw *[]){
3243				&gcc_ufs_card_2_axi_clk_src.clkr.hw
3244			},
3245			.num_parents = 1,
3246			.flags = CLK_SET_RATE_PARENT,
3247			.ops = &clk_branch2_ops,
3248		},
3249	},
3250};
3251
3252static struct clk_branch gcc_ufs_card_2_ice_core_clk = {
3253	.halt_reg = 0xa205c,
3254	.halt_check = BRANCH_HALT,
3255	.hwcg_reg = 0xa205c,
3256	.hwcg_bit = 1,
3257	.clkr = {
3258		.enable_reg = 0xa205c,
3259		.enable_mask = BIT(0),
3260		.hw.init = &(struct clk_init_data){
3261			.name = "gcc_ufs_card_2_ice_core_clk",
3262			.parent_hws = (const struct clk_hw *[]){
3263				&gcc_ufs_card_2_ice_core_clk_src.clkr.hw
3264			},
3265			.num_parents = 1,
3266			.flags = CLK_SET_RATE_PARENT,
3267			.ops = &clk_branch2_ops,
3268		},
3269	},
3270};
3271
3272static struct clk_branch gcc_ufs_card_2_phy_aux_clk = {
3273	.halt_reg = 0xa2090,
3274	.halt_check = BRANCH_HALT,
3275	.hwcg_reg = 0xa2090,
3276	.hwcg_bit = 1,
3277	.clkr = {
3278		.enable_reg = 0xa2090,
3279		.enable_mask = BIT(0),
3280		.hw.init = &(struct clk_init_data){
3281			.name = "gcc_ufs_card_2_phy_aux_clk",
3282			.parent_hws = (const struct clk_hw *[]){
3283				&gcc_ufs_card_2_phy_aux_clk_src.clkr.hw
3284			},
3285			.num_parents = 1,
3286			.flags = CLK_SET_RATE_PARENT,
3287			.ops = &clk_branch2_ops,
3288		},
3289	},
3290};
3291
3292static struct clk_branch gcc_ufs_card_2_rx_symbol_0_clk = {
3293	.halt_reg = 0xa201c,
3294	.halt_check = BRANCH_HALT,
3295	.clkr = {
3296		.enable_reg = 0xa201c,
3297		.enable_mask = BIT(0),
3298		.hw.init = &(struct clk_init_data){
3299			.name = "gcc_ufs_card_2_rx_symbol_0_clk",
3300			.ops = &clk_branch2_ops,
3301		},
3302	},
3303};
3304
3305static struct clk_branch gcc_ufs_card_2_rx_symbol_1_clk = {
3306	.halt_reg = 0xa20ac,
3307	.halt_check = BRANCH_HALT,
3308	.clkr = {
3309		.enable_reg = 0xa20ac,
3310		.enable_mask = BIT(0),
3311		.hw.init = &(struct clk_init_data){
3312			.name = "gcc_ufs_card_2_rx_symbol_1_clk",
3313			.ops = &clk_branch2_ops,
3314		},
3315	},
3316};
3317
3318static struct clk_branch gcc_ufs_card_2_tx_symbol_0_clk = {
3319	.halt_reg = 0xa2018,
3320	.halt_check = BRANCH_HALT,
3321	.clkr = {
3322		.enable_reg = 0xa2018,
3323		.enable_mask = BIT(0),
3324		.hw.init = &(struct clk_init_data){
3325			.name = "gcc_ufs_card_2_tx_symbol_0_clk",
3326			.ops = &clk_branch2_ops,
3327		},
3328	},
3329};
3330
3331static struct clk_branch gcc_ufs_card_2_unipro_core_clk = {
3332	.halt_reg = 0xa2058,
3333	.halt_check = BRANCH_HALT,
3334	.hwcg_reg = 0xa2058,
3335	.hwcg_bit = 1,
3336	.clkr = {
3337		.enable_reg = 0xa2058,
3338		.enable_mask = BIT(0),
3339		.hw.init = &(struct clk_init_data){
3340			.name = "gcc_ufs_card_2_unipro_core_clk",
3341			.parent_hws = (const struct clk_hw *[]){
3342				&gcc_ufs_card_2_unipro_core_clk_src.clkr.hw
3343			},
3344			.num_parents = 1,
3345			.flags = CLK_SET_RATE_PARENT,
3346			.ops = &clk_branch2_ops,
3347		},
3348	},
3349};
3350
3351static struct clk_branch gcc_ufs_card_ahb_clk = {
3352	.halt_reg = 0x75014,
3353	.halt_check = BRANCH_HALT,
3354	.hwcg_reg = 0x75014,
3355	.hwcg_bit = 1,
3356	.clkr = {
3357		.enable_reg = 0x75014,
3358		.enable_mask = BIT(0),
3359		.hw.init = &(struct clk_init_data){
3360			.name = "gcc_ufs_card_ahb_clk",
3361			.ops = &clk_branch2_ops,
3362		},
3363	},
3364};
3365
3366static struct clk_branch gcc_ufs_card_axi_clk = {
3367	.halt_reg = 0x75010,
3368	.halt_check = BRANCH_HALT,
3369	.hwcg_reg = 0x75010,
3370	.hwcg_bit = 1,
3371	.clkr = {
3372		.enable_reg = 0x75010,
3373		.enable_mask = BIT(0),
3374		.hw.init = &(struct clk_init_data){
3375			.name = "gcc_ufs_card_axi_clk",
3376			.parent_hws = (const struct clk_hw *[]){
3377				      &gcc_ufs_card_axi_clk_src.clkr.hw
3378			},
3379			.num_parents = 1,
3380			.flags = CLK_SET_RATE_PARENT,
3381			.ops = &clk_branch2_ops,
3382		},
3383	},
3384};
3385
3386static struct clk_branch gcc_ufs_card_axi_hw_ctl_clk = {
3387	.halt_reg = 0x75010,
3388	.halt_check = BRANCH_HALT,
3389	.hwcg_reg = 0x75010,
3390	.hwcg_bit = 1,
3391	.clkr = {
3392		.enable_reg = 0x75010,
3393		.enable_mask = BIT(1),
3394		.hw.init = &(struct clk_init_data){
3395			.name = "gcc_ufs_card_axi_hw_ctl_clk",
3396			.parent_hws = (const struct clk_hw *[]){
3397				      &gcc_ufs_card_axi_clk.clkr.hw
3398			},
3399			.num_parents = 1,
3400			.flags = CLK_SET_RATE_PARENT,
3401			.ops = &clk_branch_simple_ops,
3402		},
3403	},
3404};
3405
3406static struct clk_branch gcc_ufs_card_ice_core_clk = {
3407	.halt_reg = 0x7505c,
3408	.halt_check = BRANCH_HALT,
3409	.hwcg_reg = 0x7505c,
3410	.hwcg_bit = 1,
3411	.clkr = {
3412		.enable_reg = 0x7505c,
3413		.enable_mask = BIT(0),
3414		.hw.init = &(struct clk_init_data){
3415			.name = "gcc_ufs_card_ice_core_clk",
3416			.parent_hws = (const struct clk_hw *[]){
3417				      &gcc_ufs_card_ice_core_clk_src.clkr.hw
3418			},
3419			.num_parents = 1,
3420			.flags = CLK_SET_RATE_PARENT,
3421			.ops = &clk_branch2_ops,
3422		},
3423	},
3424};
3425
3426static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = {
3427	.halt_reg = 0x7505c,
3428	.halt_check = BRANCH_HALT,
3429	.hwcg_reg = 0x7505c,
3430	.hwcg_bit = 1,
3431	.clkr = {
3432		.enable_reg = 0x7505c,
3433		.enable_mask = BIT(1),
3434		.hw.init = &(struct clk_init_data){
3435			.name = "gcc_ufs_card_ice_core_hw_ctl_clk",
3436			.parent_hws = (const struct clk_hw *[]){
3437				      &gcc_ufs_card_ice_core_clk.clkr.hw
3438			},
3439			.num_parents = 1,
3440			.flags = CLK_SET_RATE_PARENT,
3441			.ops = &clk_branch_simple_ops,
3442		},
3443	},
3444};
3445
3446static struct clk_branch gcc_ufs_card_phy_aux_clk = {
3447	.halt_reg = 0x75090,
3448	.halt_check = BRANCH_HALT,
3449	.hwcg_reg = 0x75090,
3450	.hwcg_bit = 1,
3451	.clkr = {
3452		.enable_reg = 0x75090,
3453		.enable_mask = BIT(0),
3454		.hw.init = &(struct clk_init_data){
3455			.name = "gcc_ufs_card_phy_aux_clk",
3456			.parent_hws = (const struct clk_hw *[]){
3457				      &gcc_ufs_card_phy_aux_clk_src.clkr.hw
3458			},
3459			.num_parents = 1,
3460			.flags = CLK_SET_RATE_PARENT,
3461			.ops = &clk_branch2_ops,
3462		},
3463	},
3464};
3465
3466static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = {
3467	.halt_reg = 0x75090,
3468	.halt_check = BRANCH_HALT,
3469	.hwcg_reg = 0x75090,
3470	.hwcg_bit = 1,
3471	.clkr = {
3472		.enable_reg = 0x75090,
3473		.enable_mask = BIT(1),
3474		.hw.init = &(struct clk_init_data){
3475			.name = "gcc_ufs_card_phy_aux_hw_ctl_clk",
3476			.parent_hws = (const struct clk_hw *[]){
3477				      &gcc_ufs_card_phy_aux_clk.clkr.hw
3478			},
3479			.num_parents = 1,
3480			.flags = CLK_SET_RATE_PARENT,
3481			.ops = &clk_branch_simple_ops,
3482		},
3483	},
3484};
3485
3486static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
3487	.halt_reg = 0x7501c,
3488	.halt_check = BRANCH_HALT_DELAY,
3489	.clkr = {
3490		.enable_reg = 0x7501c,
3491		.enable_mask = BIT(0),
3492		.hw.init = &(struct clk_init_data){
3493			.name = "gcc_ufs_card_rx_symbol_0_clk",
3494			.ops = &clk_branch2_ops,
3495		},
3496	},
3497};
3498
3499static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {
3500	.halt_reg = 0x750ac,
3501	.halt_check = BRANCH_HALT_DELAY,
3502	.clkr = {
3503		.enable_reg = 0x750ac,
3504		.enable_mask = BIT(0),
3505		.hw.init = &(struct clk_init_data){
3506			.name = "gcc_ufs_card_rx_symbol_1_clk",
3507			.ops = &clk_branch2_ops,
3508		},
3509	},
3510};
3511
3512static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {
3513	.halt_reg = 0x75018,
3514	.halt_check = BRANCH_HALT_DELAY,
3515	.clkr = {
3516		.enable_reg = 0x75018,
3517		.enable_mask = BIT(0),
3518		.hw.init = &(struct clk_init_data){
3519			.name = "gcc_ufs_card_tx_symbol_0_clk",
3520			.ops = &clk_branch2_ops,
3521		},
3522	},
3523};
3524
3525static struct clk_branch gcc_ufs_card_unipro_core_clk = {
3526	.halt_reg = 0x75058,
3527	.halt_check = BRANCH_HALT,
3528	.hwcg_reg = 0x75058,
3529	.hwcg_bit = 1,
3530	.clkr = {
3531		.enable_reg = 0x75058,
3532		.enable_mask = BIT(0),
3533		.hw.init = &(struct clk_init_data){
3534			.name = "gcc_ufs_card_unipro_core_clk",
3535			.parent_hws = (const struct clk_hw *[]){
3536				      &gcc_ufs_card_unipro_core_clk_src.clkr.hw
3537			},
3538			.num_parents = 1,
3539			.flags = CLK_SET_RATE_PARENT,
3540			.ops = &clk_branch2_ops,
3541		},
3542	},
3543};
3544
3545static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = {
3546	.halt_reg = 0x75058,
3547	.halt_check = BRANCH_HALT,
3548	.hwcg_reg = 0x75058,
3549	.hwcg_bit = 1,
3550	.clkr = {
3551		.enable_reg = 0x75058,
3552		.enable_mask = BIT(1),
3553		.hw.init = &(struct clk_init_data){
3554			.name = "gcc_ufs_card_unipro_core_hw_ctl_clk",
3555			.parent_hws = (const struct clk_hw *[]){
3556				      &gcc_ufs_card_unipro_core_clk.clkr.hw
3557			},
3558			.num_parents = 1,
3559			.flags = CLK_SET_RATE_PARENT,
3560			.ops = &clk_branch_simple_ops,
3561		},
3562	},
3563};
3564
3565static struct clk_branch gcc_ufs_phy_ahb_clk = {
3566	.halt_reg = 0x77014,
3567	.halt_check = BRANCH_HALT,
3568	.hwcg_reg = 0x77014,
3569	.hwcg_bit = 1,
3570	.clkr = {
3571		.enable_reg = 0x77014,
3572		.enable_mask = BIT(0),
3573		.hw.init = &(struct clk_init_data){
3574			.name = "gcc_ufs_phy_ahb_clk",
3575			.ops = &clk_branch2_ops,
3576		},
3577	},
3578};
3579
3580static struct clk_branch gcc_ufs_phy_axi_clk = {
3581	.halt_reg = 0x77010,
3582	.halt_check = BRANCH_HALT,
3583	.hwcg_reg = 0x77010,
3584	.hwcg_bit = 1,
3585	.clkr = {
3586		.enable_reg = 0x77010,
3587		.enable_mask = BIT(0),
3588		.hw.init = &(struct clk_init_data){
3589			.name = "gcc_ufs_phy_axi_clk",
3590			.parent_hws = (const struct clk_hw *[]){
3591				      &gcc_ufs_phy_axi_clk_src.clkr.hw
3592			},
3593			.num_parents = 1,
3594			.flags = CLK_SET_RATE_PARENT,
3595			.ops = &clk_branch2_ops,
3596		},
3597	},
3598};
3599
3600static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
3601	.halt_reg = 0x77010,
3602	.halt_check = BRANCH_HALT,
3603	.hwcg_reg = 0x77010,
3604	.hwcg_bit = 1,
3605	.clkr = {
3606		.enable_reg = 0x77010,
3607		.enable_mask = BIT(1),
3608		.hw.init = &(struct clk_init_data){
3609			.name = "gcc_ufs_phy_axi_hw_ctl_clk",
3610			.parent_hws = (const struct clk_hw *[]){
3611				      &gcc_ufs_phy_axi_clk.clkr.hw
3612			},
3613			.num_parents = 1,
3614			.flags = CLK_SET_RATE_PARENT,
3615			.ops = &clk_branch_simple_ops,
3616		},
3617	},
3618};
3619
3620static struct clk_branch gcc_ufs_phy_ice_core_clk = {
3621	.halt_reg = 0x7705c,
3622	.halt_check = BRANCH_HALT,
3623	.hwcg_reg = 0x7705c,
3624	.hwcg_bit = 1,
3625	.clkr = {
3626		.enable_reg = 0x7705c,
3627		.enable_mask = BIT(0),
3628		.hw.init = &(struct clk_init_data){
3629			.name = "gcc_ufs_phy_ice_core_clk",
3630			.parent_hws = (const struct clk_hw *[]){
3631				      &gcc_ufs_phy_ice_core_clk_src.clkr.hw
3632			},
3633			.num_parents = 1,
3634			.flags = CLK_SET_RATE_PARENT,
3635			.ops = &clk_branch2_ops,
3636		},
3637	},
3638};
3639
3640static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
3641	.halt_reg = 0x7705c,
3642	.halt_check = BRANCH_HALT,
3643	.hwcg_reg = 0x7705c,
3644	.hwcg_bit = 1,
3645	.clkr = {
3646		.enable_reg = 0x7705c,
3647		.enable_mask = BIT(1),
3648		.hw.init = &(struct clk_init_data){
3649			.name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
3650			.parent_hws = (const struct clk_hw *[]){
3651				      &gcc_ufs_phy_ice_core_clk.clkr.hw
3652			},
3653			.num_parents = 1,
3654			.flags = CLK_SET_RATE_PARENT,
3655			.ops = &clk_branch_simple_ops,
3656		},
3657	},
3658};
3659
3660static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
3661	.halt_reg = 0x77090,
3662	.halt_check = BRANCH_HALT,
3663	.hwcg_reg = 0x77090,
3664	.hwcg_bit = 1,
3665	.clkr = {
3666		.enable_reg = 0x77090,
3667		.enable_mask = BIT(0),
3668		.hw.init = &(struct clk_init_data){
3669			.name = "gcc_ufs_phy_phy_aux_clk",
3670			.parent_hws = (const struct clk_hw *[]){
3671				      &gcc_ufs_phy_phy_aux_clk_src.clkr.hw
3672			},
3673			.num_parents = 1,
3674			.flags = CLK_SET_RATE_PARENT,
3675			.ops = &clk_branch2_ops,
3676		},
3677	},
3678};
3679
3680static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
3681	.halt_reg = 0x77090,
3682	.halt_check = BRANCH_HALT,
3683	.hwcg_reg = 0x77090,
3684	.hwcg_bit = 1,
3685	.clkr = {
3686		.enable_reg = 0x77090,
3687		.enable_mask = BIT(1),
3688		.hw.init = &(struct clk_init_data){
3689			.name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
3690			.parent_hws = (const struct clk_hw *[]){
3691				      &gcc_ufs_phy_phy_aux_clk.clkr.hw
3692			},
3693			.num_parents = 1,
3694			.flags = CLK_SET_RATE_PARENT,
3695			.ops = &clk_branch_simple_ops,
3696		},
3697	},
3698};
3699
3700static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
3701	.halt_reg = 0x7701c,
3702	.halt_check = BRANCH_HALT_SKIP,
3703	.clkr = {
3704		.enable_reg = 0x7701c,
3705		.enable_mask = BIT(0),
3706		.hw.init = &(struct clk_init_data){
3707			.name = "gcc_ufs_phy_rx_symbol_0_clk",
3708			.ops = &clk_branch2_ops,
3709		},
3710	},
3711};
3712
3713static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
3714	.halt_reg = 0x770ac,
3715	.halt_check = BRANCH_HALT_SKIP,
3716	.clkr = {
3717		.enable_reg = 0x770ac,
3718		.enable_mask = BIT(0),
3719		.hw.init = &(struct clk_init_data){
3720			.name = "gcc_ufs_phy_rx_symbol_1_clk",
3721			.ops = &clk_branch2_ops,
3722		},
3723	},
3724};
3725
3726static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
3727	.halt_reg = 0x77018,
3728	.halt_check = BRANCH_HALT_SKIP,
3729	.clkr = {
3730		.enable_reg = 0x77018,
3731		.enable_mask = BIT(0),
3732		.hw.init = &(struct clk_init_data){
3733			.name = "gcc_ufs_phy_tx_symbol_0_clk",
3734			.ops = &clk_branch2_ops,
3735		},
3736	},
3737};
3738
3739static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
3740	.halt_reg = 0x77058,
3741	.halt_check = BRANCH_HALT,
3742	.hwcg_reg = 0x77058,
3743	.hwcg_bit = 1,
3744	.clkr = {
3745		.enable_reg = 0x77058,
3746		.enable_mask = BIT(0),
3747		.hw.init = &(struct clk_init_data){
3748			.name = "gcc_ufs_phy_unipro_core_clk",
3749			.parent_hws = (const struct clk_hw *[]){
3750				      &gcc_ufs_phy_unipro_core_clk_src.clkr.hw
3751			},
3752			.num_parents = 1,
3753			.flags = CLK_SET_RATE_PARENT,
3754			.ops = &clk_branch2_ops,
3755		},
3756	},
3757};
3758
3759static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
3760	.halt_reg = 0x77058,
3761	.halt_check = BRANCH_HALT,
3762	.hwcg_reg = 0x77058,
3763	.hwcg_bit = 1,
3764	.clkr = {
3765		.enable_reg = 0x77058,
3766		.enable_mask = BIT(1),
3767		.hw.init = &(struct clk_init_data){
3768			.name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
3769			.parent_hws = (const struct clk_hw *[]){
3770				      &gcc_ufs_phy_unipro_core_clk.clkr.hw
3771			},
3772			.num_parents = 1,
3773			.flags = CLK_SET_RATE_PARENT,
3774			.ops = &clk_branch_simple_ops,
3775		},
3776	},
3777};
3778
3779static struct clk_branch gcc_usb30_mp_master_clk = {
3780	.halt_reg = 0xa6010,
3781	.halt_check = BRANCH_HALT,
3782	.clkr = {
3783		.enable_reg = 0xa6010,
3784		.enable_mask = BIT(0),
3785		.hw.init = &(struct clk_init_data){
3786			.name = "gcc_usb30_mp_master_clk",
3787			.parent_hws = (const struct clk_hw *[]){
3788				      &gcc_usb30_mp_master_clk_src.clkr.hw },
3789			.num_parents = 1,
3790			.flags = CLK_SET_RATE_PARENT,
3791			.ops = &clk_branch2_ops,
3792		},
3793	},
3794};
3795
3796static struct clk_branch gcc_usb30_mp_mock_utmi_clk = {
3797	.halt_reg = 0xa6018,
3798	.halt_check = BRANCH_HALT,
3799	.clkr = {
3800		.enable_reg = 0xa6018,
3801		.enable_mask = BIT(0),
3802		.hw.init = &(struct clk_init_data){
3803			.name = "gcc_usb30_mp_mock_utmi_clk",
3804			.parent_hws = (const struct clk_hw *[]){
3805				      &gcc_usb30_mp_mock_utmi_clk_src.clkr.hw
3806			},
3807			.num_parents = 1,
3808			.flags = CLK_SET_RATE_PARENT,
3809			.ops = &clk_branch2_ops,
3810		},
3811	},
3812};
3813
3814static struct clk_branch gcc_usb30_mp_sleep_clk = {
3815	.halt_reg = 0xa6014,
3816	.halt_check = BRANCH_HALT,
3817	.clkr = {
3818		.enable_reg = 0xa6014,
3819		.enable_mask = BIT(0),
3820		.hw.init = &(struct clk_init_data){
3821			.name = "gcc_usb30_mp_sleep_clk",
3822			.ops = &clk_branch2_ops,
3823		},
3824	},
3825};
3826
3827static struct clk_branch gcc_usb30_prim_master_clk = {
3828	.halt_reg = 0xf010,
3829	.halt_check = BRANCH_HALT,
3830	.clkr = {
3831		.enable_reg = 0xf010,
3832		.enable_mask = BIT(0),
3833		.hw.init = &(struct clk_init_data){
3834			.name = "gcc_usb30_prim_master_clk",
3835			.parent_hws = (const struct clk_hw *[]){
3836				      &gcc_usb30_prim_master_clk_src.clkr.hw },
3837			.num_parents = 1,
3838			.flags = CLK_SET_RATE_PARENT,
3839			.ops = &clk_branch2_ops,
3840		},
3841	},
3842};
3843
3844static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
3845	.halt_reg = 0xf018,
3846	.halt_check = BRANCH_HALT,
3847	.clkr = {
3848		.enable_reg = 0xf018,
3849		.enable_mask = BIT(0),
3850		.hw.init = &(struct clk_init_data){
3851			.name = "gcc_usb30_prim_mock_utmi_clk",
3852			.parent_hws = (const struct clk_hw *[]){
3853				      &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw
3854			},
3855			.num_parents = 1,
3856			.flags = CLK_SET_RATE_PARENT,
3857			.ops = &clk_branch2_ops,
3858		},
3859	},
3860};
3861
3862static struct clk_branch gcc_usb30_prim_sleep_clk = {
3863	.halt_reg = 0xf014,
3864	.halt_check = BRANCH_HALT,
3865	.clkr = {
3866		.enable_reg = 0xf014,
3867		.enable_mask = BIT(0),
3868		.hw.init = &(struct clk_init_data){
3869			.name = "gcc_usb30_prim_sleep_clk",
3870			.ops = &clk_branch2_ops,
3871		},
3872	},
3873};
3874
3875static struct clk_branch gcc_usb30_sec_master_clk = {
3876	.halt_reg = 0x10010,
3877	.halt_check = BRANCH_HALT,
3878	.clkr = {
3879		.enable_reg = 0x10010,
3880		.enable_mask = BIT(0),
3881		.hw.init = &(struct clk_init_data){
3882			.name = "gcc_usb30_sec_master_clk",
3883			.parent_hws = (const struct clk_hw *[]){
3884				      &gcc_usb30_sec_master_clk_src.clkr.hw },
3885			.num_parents = 1,
3886			.flags = CLK_SET_RATE_PARENT,
3887			.ops = &clk_branch2_ops,
3888		},
3889	},
3890};
3891
3892static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
3893	.halt_reg = 0x10018,
3894	.halt_check = BRANCH_HALT,
3895	.clkr = {
3896		.enable_reg = 0x10018,
3897		.enable_mask = BIT(0),
3898		.hw.init = &(struct clk_init_data){
3899			.name = "gcc_usb30_sec_mock_utmi_clk",
3900			.parent_hws = (const struct clk_hw *[]){
3901				      &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw
3902			},
3903			.num_parents = 1,
3904			.flags = CLK_SET_RATE_PARENT,
3905			.ops = &clk_branch2_ops,
3906		},
3907	},
3908};
3909
3910static struct clk_branch gcc_usb30_sec_sleep_clk = {
3911	.halt_reg = 0x10014,
3912	.halt_check = BRANCH_HALT,
3913	.clkr = {
3914		.enable_reg = 0x10014,
3915		.enable_mask = BIT(0),
3916		.hw.init = &(struct clk_init_data){
3917			.name = "gcc_usb30_sec_sleep_clk",
3918			.ops = &clk_branch2_ops,
3919		},
3920	},
3921};
3922
3923static struct clk_branch gcc_usb3_mp_phy_aux_clk = {
3924	.halt_reg = 0xa6050,
3925	.halt_check = BRANCH_HALT,
3926	.clkr = {
3927		.enable_reg = 0xa6050,
3928		.enable_mask = BIT(0),
3929		.hw.init = &(struct clk_init_data){
3930			.name = "gcc_usb3_mp_phy_aux_clk",
3931			.parent_hws = (const struct clk_hw *[]){
3932				      &gcc_usb3_mp_phy_aux_clk_src.clkr.hw
3933			},
3934			.num_parents = 1,
3935			.flags = CLK_SET_RATE_PARENT,
3936			.ops = &clk_branch2_ops,
3937		},
3938	},
3939};
3940
3941static struct clk_branch gcc_usb3_mp_phy_com_aux_clk = {
3942	.halt_reg = 0xa6054,
3943	.halt_check = BRANCH_HALT,
3944	.clkr = {
3945		.enable_reg = 0xa6054,
3946		.enable_mask = BIT(0),
3947		.hw.init = &(struct clk_init_data){
3948			.name = "gcc_usb3_mp_phy_com_aux_clk",
3949			.parent_hws = (const struct clk_hw *[]){
3950				      &gcc_usb3_mp_phy_aux_clk_src.clkr.hw
3951			},
3952			.num_parents = 1,
3953			.flags = CLK_SET_RATE_PARENT,
3954			.ops = &clk_branch2_ops,
3955		},
3956	},
3957};
3958
3959static struct clk_branch gcc_usb3_mp_phy_pipe_0_clk = {
3960	.halt_reg = 0xa6058,
3961	.halt_check = BRANCH_HALT_SKIP,
3962	.clkr = {
3963		.enable_reg = 0xa6058,
3964		.enable_mask = BIT(0),
3965		.hw.init = &(struct clk_init_data){
3966			.name = "gcc_usb3_mp_phy_pipe_0_clk",
3967			.ops = &clk_branch2_ops,
3968		},
3969	},
3970};
3971
3972static struct clk_branch gcc_usb3_mp_phy_pipe_1_clk = {
3973	.halt_reg = 0xa605c,
3974	.halt_check = BRANCH_HALT_SKIP,
3975	.clkr = {
3976		.enable_reg = 0xa605c,
3977		.enable_mask = BIT(0),
3978		.hw.init = &(struct clk_init_data){
3979			.name = "gcc_usb3_mp_phy_pipe_1_clk",
3980			.ops = &clk_branch2_ops,
3981		},
3982	},
3983};
3984
3985static struct clk_branch gcc_usb3_prim_clkref_clk = {
3986	.halt_reg = 0x8c008,
3987	.halt_check = BRANCH_HALT,
3988	.clkr = {
3989		.enable_reg = 0x8c008,
3990		.enable_mask = BIT(0),
3991		.hw.init = &(struct clk_init_data){
3992			.name = "gcc_usb3_prim_clkref_clk",
3993			.ops = &clk_branch2_ops,
3994		},
3995	},
3996};
3997
3998static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
3999	.halt_reg = 0xf050,
4000	.halt_check = BRANCH_HALT,
4001	.clkr = {
4002		.enable_reg = 0xf050,
4003		.enable_mask = BIT(0),
4004		.hw.init = &(struct clk_init_data){
4005			.name = "gcc_usb3_prim_phy_aux_clk",
4006			.parent_hws = (const struct clk_hw *[]){
4007				      &gcc_usb3_prim_phy_aux_clk_src.clkr.hw
4008			},
4009			.num_parents = 1,
4010			.flags = CLK_SET_RATE_PARENT,
4011			.ops = &clk_branch2_ops,
4012		},
4013	},
4014};
4015
4016static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
4017	.halt_reg = 0xf054,
4018	.halt_check = BRANCH_HALT,
4019	.clkr = {
4020		.enable_reg = 0xf054,
4021		.enable_mask = BIT(0),
4022		.hw.init = &(struct clk_init_data){
4023			.name = "gcc_usb3_prim_phy_com_aux_clk",
4024			.parent_hws = (const struct clk_hw *[]){
4025				      &gcc_usb3_prim_phy_aux_clk_src.clkr.hw
4026			},
4027			.num_parents = 1,
4028			.flags = CLK_SET_RATE_PARENT,
4029			.ops = &clk_branch2_ops,
4030		},
4031	},
4032};
4033
4034static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
4035	.halt_reg = 0xf058,
4036	.halt_check = BRANCH_HALT_SKIP,
4037	.clkr = {
4038		.enable_reg = 0xf058,
4039		.enable_mask = BIT(0),
4040		.hw.init = &(struct clk_init_data){
4041			.name = "gcc_usb3_prim_phy_pipe_clk",
4042			.ops = &clk_branch2_ops,
4043		},
4044	},
4045};
4046
4047static struct clk_branch gcc_usb3_sec_clkref_clk = {
4048	.halt_reg = 0x8c028,
4049	.halt_check = BRANCH_HALT,
4050	.clkr = {
4051		.enable_reg = 0x8c028,
4052		.enable_mask = BIT(0),
4053		.hw.init = &(struct clk_init_data){
4054			.name = "gcc_usb3_sec_clkref_clk",
4055			.ops = &clk_branch2_ops,
4056		},
4057	},
4058};
4059
4060static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
4061	.halt_reg = 0x10050,
4062	.halt_check = BRANCH_HALT,
4063	.clkr = {
4064		.enable_reg = 0x10050,
4065		.enable_mask = BIT(0),
4066		.hw.init = &(struct clk_init_data){
4067			.name = "gcc_usb3_sec_phy_aux_clk",
4068			.parent_hws = (const struct clk_hw *[]){
4069				      &gcc_usb3_sec_phy_aux_clk_src.clkr.hw
4070			},
4071			.num_parents = 1,
4072			.flags = CLK_SET_RATE_PARENT,
4073			.ops = &clk_branch2_ops,
4074		},
4075	},
4076};
4077
4078static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
4079	.halt_reg = 0x10054,
4080	.halt_check = BRANCH_HALT,
4081	.clkr = {
4082		.enable_reg = 0x10054,
4083		.enable_mask = BIT(0),
4084		.hw.init = &(struct clk_init_data){
4085			.name = "gcc_usb3_sec_phy_com_aux_clk",
4086			.parent_hws = (const struct clk_hw *[]){
4087				      &gcc_usb3_sec_phy_aux_clk_src.clkr.hw
4088			},
4089			.num_parents = 1,
4090			.flags = CLK_SET_RATE_PARENT,
4091			.ops = &clk_branch2_ops,
4092		},
4093	},
4094};
4095
4096static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
4097	.halt_reg = 0x10058,
4098	.halt_check = BRANCH_HALT_SKIP,
4099	.clkr = {
4100		.enable_reg = 0x10058,
4101		.enable_mask = BIT(0),
4102		.hw.init = &(struct clk_init_data){
4103			.name = "gcc_usb3_sec_phy_pipe_clk",
4104			.ops = &clk_branch2_ops,
4105		},
4106	},
4107};
4108
4109static struct clk_branch gcc_video_axi0_clk = {
4110	.halt_reg = 0xb024,
4111	.halt_check = BRANCH_HALT,
4112	.clkr = {
4113		.enable_reg = 0xb024,
4114		.enable_mask = BIT(0),
4115		.hw.init = &(struct clk_init_data){
4116			.name = "gcc_video_axi0_clk",
4117			.ops = &clk_branch2_ops,
4118		},
4119	},
4120};
4121
4122static struct clk_branch gcc_video_axi1_clk = {
4123	.halt_reg = 0xb028,
4124	.halt_check = BRANCH_HALT,
4125	.clkr = {
4126		.enable_reg = 0xb028,
4127		.enable_mask = BIT(0),
4128		.hw.init = &(struct clk_init_data){
4129			.name = "gcc_video_axi1_clk",
4130			.ops = &clk_branch2_ops,
4131		},
4132	},
4133};
4134
4135static struct clk_branch gcc_video_axic_clk = {
4136	.halt_reg = 0xb02c,
4137	.halt_check = BRANCH_HALT,
4138	.clkr = {
4139		.enable_reg = 0xb02c,
4140		.enable_mask = BIT(0),
4141		.hw.init = &(struct clk_init_data){
4142			.name = "gcc_video_axic_clk",
4143			.ops = &clk_branch2_ops,
4144		},
4145	},
4146};
4147
4148static struct gdsc usb30_sec_gdsc = {
4149	.gdscr = 0x10004,
4150	.pd = {
4151		.name = "usb30_sec_gdsc",
4152	},
4153	.pwrsts = PWRSTS_OFF_ON,
4154	.flags = POLL_CFG_GDSCR,
4155};
4156
4157static struct gdsc emac_gdsc = {
4158	.gdscr = 0x6004,
4159	.pd = {
4160		.name = "emac_gdsc",
4161	},
4162	.pwrsts = PWRSTS_OFF_ON,
4163	.flags = POLL_CFG_GDSCR,
4164};
4165
4166static struct gdsc usb30_prim_gdsc = {
4167	.gdscr = 0xf004,
4168	.pd = {
4169		.name = "usb30_prim_gdsc",
4170	},
4171	.pwrsts = PWRSTS_OFF_ON,
4172	.flags = POLL_CFG_GDSCR,
4173};
4174
4175static struct gdsc pcie_0_gdsc = {
4176	.gdscr = 0x6b004,
4177	.pd = {
4178		.name = "pcie_0_gdsc",
4179	},
4180	.pwrsts = PWRSTS_OFF_ON,
4181	.flags = POLL_CFG_GDSCR,
4182};
4183
4184static struct gdsc ufs_card_gdsc = {
4185	.gdscr = 0x75004,
4186	.pd = {
4187		.name = "ufs_card_gdsc",
4188	},
4189	.pwrsts = PWRSTS_OFF_ON,
4190	.flags = POLL_CFG_GDSCR,
4191};
4192
4193static struct gdsc ufs_phy_gdsc = {
4194	.gdscr = 0x77004,
4195	.pd = {
4196		.name = "ufs_phy_gdsc",
4197	},
4198	.pwrsts = PWRSTS_OFF_ON,
4199	.flags = POLL_CFG_GDSCR,
4200};
4201
4202static struct gdsc pcie_1_gdsc = {
4203	.gdscr = 0x8d004,
4204	.pd = {
4205		.name = "pcie_1_gdsc",
4206	},
4207	.pwrsts = PWRSTS_OFF_ON,
4208	.flags = POLL_CFG_GDSCR,
4209};
4210
4211static struct gdsc pcie_2_gdsc = {
4212	.gdscr = 0x9d004,
4213	.pd = {
4214		.name = "pcie_2_gdsc",
4215	},
4216	.pwrsts = PWRSTS_OFF_ON,
4217	.flags = POLL_CFG_GDSCR,
4218};
4219
4220static struct gdsc ufs_card_2_gdsc = {
4221	.gdscr = 0xa2004,
4222	.pd = {
4223		.name = "ufs_card_2_gdsc",
4224	},
4225	.pwrsts = PWRSTS_OFF_ON,
4226	.flags = POLL_CFG_GDSCR,
4227};
4228
4229static struct gdsc pcie_3_gdsc = {
4230	.gdscr = 0xa3004,
4231	.pd = {
4232		.name = "pcie_3_gdsc",
4233	},
4234	.pwrsts = PWRSTS_OFF_ON,
4235	.flags = POLL_CFG_GDSCR,
4236};
4237
4238static struct gdsc usb30_mp_gdsc = {
4239	.gdscr = 0xa6004,
4240	.pd = {
4241		.name = "usb30_mp_gdsc",
4242	},
4243	.pwrsts = PWRSTS_OFF_ON,
4244	.flags = POLL_CFG_GDSCR,
4245};
4246
4247static struct clk_regmap *gcc_sc8180x_clocks[] = {
4248	[GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
4249	[GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
4250	[GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_card_axi_hw_ctl_clk.clkr,
4251	[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
4252	[GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
4253	[GCC_AGGRE_USB3_MP_AXI_CLK] = &gcc_aggre_usb3_mp_axi_clk.clkr,
4254	[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
4255	[GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
4256	[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
4257	[GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
4258	[GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
4259	[GCC_CFG_NOC_USB3_MP_AXI_CLK] = &gcc_cfg_noc_usb3_mp_axi_clk.clkr,
4260	[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
4261	[GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
4262	[GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
4263	[GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
4264	[GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
4265	[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
4266	[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
4267	[GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,
4268	[GCC_EMAC_AXI_CLK] = &gcc_emac_axi_clk.clkr,
4269	[GCC_EMAC_PTP_CLK] = &gcc_emac_ptp_clk.clkr,
4270	[GCC_EMAC_PTP_CLK_SRC] = &gcc_emac_ptp_clk_src.clkr,
4271	[GCC_EMAC_RGMII_CLK] = &gcc_emac_rgmii_clk.clkr,
4272	[GCC_EMAC_RGMII_CLK_SRC] = &gcc_emac_rgmii_clk_src.clkr,
4273	[GCC_EMAC_SLV_AHB_CLK] = &gcc_emac_slv_ahb_clk.clkr,
4274	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
4275	[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
4276	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
4277	[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
4278	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
4279	[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
4280	[GCC_GP4_CLK] = &gcc_gp4_clk.clkr,
4281	[GCC_GP4_CLK_SRC] = &gcc_gp4_clk_src.clkr,
4282	[GCC_GP5_CLK] = &gcc_gp5_clk.clkr,
4283	[GCC_GP5_CLK_SRC] = &gcc_gp5_clk_src.clkr,
4284	[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
4285	[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
4286	[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
4287	[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
4288	[GCC_NPU_AT_CLK] = &gcc_npu_at_clk.clkr,
4289	[GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr,
4290	[GCC_NPU_AXI_CLK_SRC] = &gcc_npu_axi_clk_src.clkr,
4291	[GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr,
4292	[GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr,
4293	[GCC_NPU_TRIG_CLK] = &gcc_npu_trig_clk.clkr,
4294	[GCC_PCIE0_PHY_REFGEN_CLK] = &gcc_pcie0_phy_refgen_clk.clkr,
4295	[GCC_PCIE1_PHY_REFGEN_CLK] = &gcc_pcie1_phy_refgen_clk.clkr,
4296	[GCC_PCIE2_PHY_REFGEN_CLK] = &gcc_pcie2_phy_refgen_clk.clkr,
4297	[GCC_PCIE3_PHY_REFGEN_CLK] = &gcc_pcie3_phy_refgen_clk.clkr,
4298	[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
4299	[GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
4300	[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
4301	[GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr,
4302	[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
4303	[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
4304	[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
4305	[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
4306	[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
4307	[GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
4308	[GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
4309	[GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr,
4310	[GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
4311	[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
4312	[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
4313	[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
4314	[GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr,
4315	[GCC_PCIE_2_AUX_CLK_SRC] = &gcc_pcie_2_aux_clk_src.clkr,
4316	[GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr,
4317	[GCC_PCIE_2_CLKREF_CLK] = &gcc_pcie_2_clkref_clk.clkr,
4318	[GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr,
4319	[GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr,
4320	[GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr,
4321	[GCC_PCIE_2_SLV_Q2A_AXI_CLK] = &gcc_pcie_2_slv_q2a_axi_clk.clkr,
4322	[GCC_PCIE_3_AUX_CLK] = &gcc_pcie_3_aux_clk.clkr,
4323	[GCC_PCIE_3_AUX_CLK_SRC] = &gcc_pcie_3_aux_clk_src.clkr,
4324	[GCC_PCIE_3_CFG_AHB_CLK] = &gcc_pcie_3_cfg_ahb_clk.clkr,
4325	[GCC_PCIE_3_CLKREF_CLK] = &gcc_pcie_3_clkref_clk.clkr,
4326	[GCC_PCIE_3_MSTR_AXI_CLK] = &gcc_pcie_3_mstr_axi_clk.clkr,
4327	[GCC_PCIE_3_PIPE_CLK] = &gcc_pcie_3_pipe_clk.clkr,
4328	[GCC_PCIE_3_SLV_AXI_CLK] = &gcc_pcie_3_slv_axi_clk.clkr,
4329	[GCC_PCIE_3_SLV_Q2A_AXI_CLK] = &gcc_pcie_3_slv_q2a_axi_clk.clkr,
4330	[GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
4331	[GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr,
4332	[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
4333	[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
4334	[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
4335	[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
4336	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
4337	[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
4338	[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
4339	[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
4340	[GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
4341	[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
4342	[GCC_QSPI_1_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_1_cnoc_periph_ahb_clk.clkr,
4343	[GCC_QSPI_1_CORE_CLK] = &gcc_qspi_1_core_clk.clkr,
4344	[GCC_QSPI_1_CORE_CLK_SRC] = &gcc_qspi_1_core_clk_src.clkr,
4345	[GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
4346	[GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
4347	[GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
4348	[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
4349	[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
4350	[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
4351	[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
4352	[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
4353	[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
4354	[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
4355	[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
4356	[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
4357	[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
4358	[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
4359	[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
4360	[GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
4361	[GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
4362	[GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
4363	[GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
4364	[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
4365	[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
4366	[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
4367	[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
4368	[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
4369	[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
4370	[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
4371	[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
4372	[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
4373	[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
4374	[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
4375	[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
4376	[GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
4377	[GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
4378	[GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
4379	[GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
4380	[GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
4381	[GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
4382	[GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
4383	[GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
4384	[GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
4385	[GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
4386	[GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
4387	[GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
4388	[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
4389	[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
4390	[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
4391	[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
4392	[GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
4393	[GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
4394	[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
4395	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
4396	[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
4397	[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
4398	[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
4399	[GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
4400	[GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
4401	[GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
4402	[GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
4403	[GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
4404	[GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr,
4405	[GCC_UFS_CARD_2_AHB_CLK] = &gcc_ufs_card_2_ahb_clk.clkr,
4406	[GCC_UFS_CARD_2_AXI_CLK] = &gcc_ufs_card_2_axi_clk.clkr,
4407	[GCC_UFS_CARD_2_AXI_CLK_SRC] = &gcc_ufs_card_2_axi_clk_src.clkr,
4408	[GCC_UFS_CARD_2_ICE_CORE_CLK] = &gcc_ufs_card_2_ice_core_clk.clkr,
4409	[GCC_UFS_CARD_2_ICE_CORE_CLK_SRC] = &gcc_ufs_card_2_ice_core_clk_src.clkr,
4410	[GCC_UFS_CARD_2_PHY_AUX_CLK] = &gcc_ufs_card_2_phy_aux_clk.clkr,
4411	[GCC_UFS_CARD_2_PHY_AUX_CLK_SRC] = &gcc_ufs_card_2_phy_aux_clk_src.clkr,
4412	[GCC_UFS_CARD_2_RX_SYMBOL_0_CLK] = &gcc_ufs_card_2_rx_symbol_0_clk.clkr,
4413	[GCC_UFS_CARD_2_RX_SYMBOL_1_CLK] = &gcc_ufs_card_2_rx_symbol_1_clk.clkr,
4414	[GCC_UFS_CARD_2_TX_SYMBOL_0_CLK] = &gcc_ufs_card_2_tx_symbol_0_clk.clkr,
4415	[GCC_UFS_CARD_2_UNIPRO_CORE_CLK] = &gcc_ufs_card_2_unipro_core_clk.clkr,
4416	[GCC_UFS_CARD_2_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_2_unipro_core_clk_src.clkr,
4417	[GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
4418	[GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
4419	[GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
4420	[GCC_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_ufs_card_axi_hw_ctl_clk.clkr,
4421	[GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,
4422	[GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,
4423	[GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_card_ice_core_hw_ctl_clk.clkr,
4424	[GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,
4425	[GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
4426	[GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_card_phy_aux_hw_ctl_clk.clkr,
4427	[GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr,
4428	[GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr,
4429	[GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr,
4430	[GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
4431	[GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_unipro_core_clk_src.clkr,
4432	[GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr,
4433	[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
4434	[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
4435	[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
4436	[GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
4437	[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
4438	[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
4439	[GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
4440	[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
4441	[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
4442	[GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
4443	[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
4444	[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
4445	[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
4446	[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
4447	[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
4448	[GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
4449	[GCC_USB30_MP_MASTER_CLK] = &gcc_usb30_mp_master_clk.clkr,
4450	[GCC_USB30_MP_MASTER_CLK_SRC] = &gcc_usb30_mp_master_clk_src.clkr,
4451	[GCC_USB30_MP_MOCK_UTMI_CLK] = &gcc_usb30_mp_mock_utmi_clk.clkr,
4452	[GCC_USB30_MP_MOCK_UTMI_CLK_SRC] = &gcc_usb30_mp_mock_utmi_clk_src.clkr,
4453	[GCC_USB30_MP_SLEEP_CLK] = &gcc_usb30_mp_sleep_clk.clkr,
4454	[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
4455	[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
4456	[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
4457	[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
4458	[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
4459	[GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
4460	[GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
4461	[GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
4462	[GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = &gcc_usb30_sec_mock_utmi_clk_src.clkr,
4463	[GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
4464	[GCC_USB3_MP_PHY_AUX_CLK] = &gcc_usb3_mp_phy_aux_clk.clkr,
4465	[GCC_USB3_MP_PHY_AUX_CLK_SRC] = &gcc_usb3_mp_phy_aux_clk_src.clkr,
4466	[GCC_USB3_MP_PHY_COM_AUX_CLK] = &gcc_usb3_mp_phy_com_aux_clk.clkr,
4467	[GCC_USB3_MP_PHY_PIPE_0_CLK] = &gcc_usb3_mp_phy_pipe_0_clk.clkr,
4468	[GCC_USB3_MP_PHY_PIPE_1_CLK] = &gcc_usb3_mp_phy_pipe_1_clk.clkr,
4469	[GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
4470	[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
4471	[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
4472	[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
4473	[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
4474	[GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr,
4475	[GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
4476	[GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
4477	[GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
4478	[GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
4479	[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
4480	[GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
4481	[GCC_VIDEO_AXIC_CLK] = &gcc_video_axic_clk.clkr,
4482	[GPLL0] = &gpll0.clkr,
4483	[GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
4484	[GPLL1] = &gpll1.clkr,
4485	[GPLL4] = &gpll4.clkr,
4486	[GPLL7] = &gpll7.clkr,
4487};
4488
4489static const struct qcom_reset_map gcc_sc8180x_resets[] = {
4490	[GCC_EMAC_BCR] = { 0x6000 },
4491	[GCC_GPU_BCR] = { 0x71000 },
4492	[GCC_MMSS_BCR] = { 0xb000 },
4493	[GCC_NPU_BCR] = { 0x4d000 },
4494	[GCC_PCIE_0_BCR] = { 0x6b000 },
4495	[GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
4496	[GCC_PCIE_1_BCR] = { 0x8d000 },
4497	[GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
4498	[GCC_PCIE_2_BCR] = { 0x9d000 },
4499	[GCC_PCIE_2_PHY_BCR] = { 0xa701c },
4500	[GCC_PCIE_3_BCR] = { 0xa3000 },
4501	[GCC_PCIE_3_PHY_BCR] = { 0xa801c },
4502	[GCC_PCIE_PHY_BCR] = { 0x6f000 },
4503	[GCC_PDM_BCR] = { 0x33000 },
4504	[GCC_PRNG_BCR] = { 0x34000 },
4505	[GCC_QSPI_1_BCR] = { 0x4a000 },
4506	[GCC_QSPI_BCR] = { 0x24008 },
4507	[GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
4508	[GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
4509	[GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
4510	[GCC_QUSB2PHY_5_BCR] = { 0x12010 },
4511	[GCC_QUSB2PHY_MP0_BCR] = { 0x12008 },
4512	[GCC_QUSB2PHY_MP1_BCR] = { 0x1200c },
4513	[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
4514	[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
4515	[GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x50000 },
4516	[GCC_USB3_PHY_PRIM_SP1_BCR] = { 0x50004 },
4517	[GCC_USB3_DP_PHY_PRIM_SP0_BCR] = { 0x50010 },
4518	[GCC_USB3_DP_PHY_PRIM_SP1_BCR] = { 0x50014 },
4519	[GCC_USB3_PHY_SEC_BCR] = { 0x50018 },
4520	[GCC_USB3PHY_PHY_SEC_BCR] = { 0x5001c },
4521	[GCC_USB3_DP_PHY_SEC_BCR] = { 0x50020 },
4522	[GCC_SDCC2_BCR] = { 0x14000 },
4523	[GCC_SDCC4_BCR] = { 0x16000 },
4524	[GCC_TSIF_BCR] = { 0x36000 },
4525	[GCC_UFS_CARD_2_BCR] = { 0xa2000 },
4526	[GCC_UFS_CARD_BCR] = { 0x75000 },
4527	[GCC_UFS_PHY_BCR] = { 0x77000 },
4528	[GCC_USB30_MP_BCR] = { 0xa6000 },
4529	[GCC_USB30_PRIM_BCR] = { 0xf000 },
4530	[GCC_USB30_SEC_BCR] = { 0x10000 },
4531	[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
4532	[GCC_VIDEO_AXIC_CLK_BCR] = { 0xb02c, 2 },
4533	[GCC_VIDEO_AXI0_CLK_BCR] = { 0xb024, 2 },
4534	[GCC_VIDEO_AXI1_CLK_BCR] = { 0xb028, 2 },
4535};
4536
4537static struct gdsc *gcc_sc8180x_gdscs[] = {
4538	[EMAC_GDSC] = &emac_gdsc,
4539	[PCIE_0_GDSC] = &pcie_0_gdsc,
4540	[PCIE_1_GDSC] = &pcie_1_gdsc,
4541	[PCIE_2_GDSC] = &pcie_2_gdsc,
4542	[PCIE_3_GDSC] = &pcie_3_gdsc,
4543	[UFS_CARD_GDSC] = &ufs_card_gdsc,
4544	[UFS_CARD_2_GDSC] = &ufs_card_2_gdsc,
4545	[UFS_PHY_GDSC] = &ufs_phy_gdsc,
4546	[USB30_MP_GDSC] = &usb30_mp_gdsc,
4547	[USB30_PRIM_GDSC] = &usb30_prim_gdsc,
4548	[USB30_SEC_GDSC] = &usb30_sec_gdsc,
4549};
4550
4551static const struct regmap_config gcc_sc8180x_regmap_config = {
4552	.reg_bits	= 32,
4553	.reg_stride	= 4,
4554	.val_bits	= 32,
4555	.max_register	= 0xc0004,
4556	.fast_io	= true,
4557};
4558
4559static const struct qcom_cc_desc gcc_sc8180x_desc = {
4560	.config = &gcc_sc8180x_regmap_config,
4561	.clks = gcc_sc8180x_clocks,
4562	.num_clks = ARRAY_SIZE(gcc_sc8180x_clocks),
4563	.resets = gcc_sc8180x_resets,
4564	.num_resets = ARRAY_SIZE(gcc_sc8180x_resets),
4565	.gdscs = gcc_sc8180x_gdscs,
4566	.num_gdscs = ARRAY_SIZE(gcc_sc8180x_gdscs),
4567};
4568
4569static const struct of_device_id gcc_sc8180x_match_table[] = {
4570	{ .compatible = "qcom,gcc-sc8180x" },
4571	{ }
4572};
4573MODULE_DEVICE_TABLE(of, gcc_sc8180x_match_table);
4574
4575static int gcc_sc8180x_probe(struct platform_device *pdev)
4576{
4577	struct regmap *regmap;
4578
4579	regmap = qcom_cc_map(pdev, &gcc_sc8180x_desc);
4580	if (IS_ERR(regmap))
4581		return PTR_ERR(regmap);
4582
4583	/*
4584	 * Enable the following always-on clocks:
4585	 * GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK, GCC_DISP_AHB_CLK,
4586	 * GCC_VIDEO_XO_CLK, GCC_CAMERA_XO_CLK, GCC_DISP_XO_CLK,
4587	 * GCC_CPUSS_GNOC_CLK, GCC_CPUSS_DVM_BUS_CLK, GCC_NPU_CFG_AHB_CLK and
4588	 * GCC_GPU_CFG_AHB_CLK
4589	 */
4590	regmap_update_bits(regmap, 0xb004, BIT(0), BIT(0));
4591	regmap_update_bits(regmap, 0xb008, BIT(0), BIT(0));
4592	regmap_update_bits(regmap, 0xb00c, BIT(0), BIT(0));
4593	regmap_update_bits(regmap, 0xb040, BIT(0), BIT(0));
4594	regmap_update_bits(regmap, 0xb044, BIT(0), BIT(0));
4595	regmap_update_bits(regmap, 0xb048, BIT(0), BIT(0));
4596	regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0));
4597	regmap_update_bits(regmap, 0x48190, BIT(0), BIT(0));
4598	regmap_update_bits(regmap, 0x4d004, BIT(0), BIT(0));
4599	regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
4600
4601	/* Disable the GPLL0 active input to NPU and GPU via MISC registers */
4602	regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
4603	regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
4604
4605	return qcom_cc_really_probe(pdev, &gcc_sc8180x_desc, regmap);
4606}
4607
4608static struct platform_driver gcc_sc8180x_driver = {
4609	.probe		= gcc_sc8180x_probe,
4610	.driver		= {
4611		.name	= "gcc-sc8180x",
4612		.of_match_table = gcc_sc8180x_match_table,
4613	},
4614};
4615
4616static int __init gcc_sc8180x_init(void)
4617{
4618	return platform_driver_register(&gcc_sc8180x_driver);
4619}
4620core_initcall(gcc_sc8180x_init);
4621
4622static void __exit gcc_sc8180x_exit(void)
4623{
4624	platform_driver_unregister(&gcc_sc8180x_driver);
4625}
4626module_exit(gcc_sc8180x_exit);
4627
4628MODULE_DESCRIPTION("QTI GCC SC8180x driver");
4629MODULE_LICENSE("GPL v2");