1// SPDX-License-Identifier: GPL-2.0-only
   2// Copyright (c) 2021, The Linux Foundation. All rights reserved.
   3
   4#include <linux/kernel.h>
   5#include <linux/bitops.h>
   6#include <linux/err.h>
   7#include <linux/module.h>
   8#include <linux/platform_device.h>
   9#include <linux/of.h>
  10#include <linux/of_device.h>
  11#include <linux/clk-provider.h>
  12#include <linux/regmap.h>
  13#include <linux/reset-controller.h>
  14
  15#include <dt-bindings/clock/qcom,gcc-msm8953.h>
  16
  17#include "clk-alpha-pll.h"
  18#include "clk-branch.h"
  19#include "clk-rcg.h"
  20#include "common.h"
  21#include "gdsc.h"
  22#include "reset.h"
  23
  24enum {
  25	P_XO,
  26	P_SLEEP_CLK,
  27	P_GPLL0,
  28	P_GPLL0_DIV2,
  29	P_GPLL2,
  30	P_GPLL3,
  31	P_GPLL4,
  32	P_GPLL6,
  33	P_GPLL6_DIV2,
  34	P_DSI0PLL,
  35	P_DSI0PLL_BYTE,
  36	P_DSI1PLL,
  37	P_DSI1PLL_BYTE,
  38};
  39
  40static struct clk_alpha_pll gpll0_early = {
  41	.offset = 0x21000,
  42	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  43	.clkr = {
  44		.enable_reg = 0x45000,
  45		.enable_mask = BIT(0),
  46		.hw.init = &(struct clk_init_data) {
  47			.name = "gpll0_early",
  48			.parent_data = &(const struct clk_parent_data) {
  49				.fw_name = "xo",
  50			},
  51			.num_parents = 1,
  52			.ops = &clk_alpha_pll_fixed_ops,
  53		},
  54	},
  55};
  56
  57static struct clk_fixed_factor gpll0_early_div = {
  58	.mult = 1,
  59	.div = 2,
  60	.hw.init = &(struct clk_init_data){
  61		.name = "gpll0_early_div",
  62		.parent_hws = (const struct clk_hw*[]){
  63			&gpll0_early.clkr.hw,
  64		},
  65		.num_parents = 1,
  66		.ops = &clk_fixed_factor_ops,
  67	},
  68};
  69
  70static struct clk_alpha_pll_postdiv gpll0 = {
  71	.offset = 0x21000,
  72	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  73	.clkr.hw.init = &(struct clk_init_data){
  74		.name = "gpll0",
  75		.parent_hws = (const struct clk_hw*[]){
  76			&gpll0_early.clkr.hw,
  77		},
  78		.num_parents = 1,
  79		.ops = &clk_alpha_pll_postdiv_ro_ops,
  80	},
  81};
  82
  83static struct clk_alpha_pll gpll2_early = {
  84	.offset = 0x4a000,
  85	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  86	.clkr = {
  87		.enable_reg = 0x45000,
  88		.enable_mask = BIT(2),
  89		.hw.init = &(struct clk_init_data){
  90			.name = "gpll2_early",
  91			.parent_data = &(const struct clk_parent_data) {
  92				.fw_name = "xo",
  93			},
  94			.num_parents = 1,
  95			.ops = &clk_alpha_pll_fixed_ops,
  96		},
  97	},
  98};
  99
 100static struct clk_alpha_pll_postdiv gpll2 = {
 101	.offset = 0x4a000,
 102	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 103	.clkr.hw.init = &(struct clk_init_data){
 104		.name = "gpll2",
 105		.parent_hws = (const struct clk_hw*[]){
 106			&gpll2_early.clkr.hw,
 107		},
 108		.num_parents = 1,
 109		.ops = &clk_alpha_pll_postdiv_ro_ops,
 110	},
 111};
 112
 113static const struct pll_vco gpll3_p_vco[] = {
 114	{ 1000000000, 2000000000, 0 },
 115};
 116
 117static const struct alpha_pll_config gpll3_early_config = {
 118	.l = 63,
 119	.config_ctl_val = 0x4001055b,
 120	.early_output_mask = 0,
 121	.post_div_mask = GENMASK(11, 8),
 122	.post_div_val = BIT(8),
 123};
 124
 125static struct clk_alpha_pll gpll3_early = {
 126	.offset = 0x22000,
 127	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 128	.vco_table = gpll3_p_vco,
 129	.num_vco = ARRAY_SIZE(gpll3_p_vco),
 130	.flags = SUPPORTS_DYNAMIC_UPDATE,
 131	.clkr = {
 132		.hw.init = &(struct clk_init_data){
 133			.name = "gpll3_early",
 134			.parent_data = &(const struct clk_parent_data) {
 135				.fw_name = "xo",
 136			},
 137			.num_parents = 1,
 138			.ops = &clk_alpha_pll_ops,
 139		},
 140	},
 141};
 142
 143static struct clk_alpha_pll_postdiv gpll3 = {
 144	.offset = 0x22000,
 145	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 146	.clkr.hw.init = &(struct clk_init_data){
 147		.name = "gpll3",
 148		.parent_hws = (const struct clk_hw*[]){
 149			&gpll3_early.clkr.hw,
 150		},
 151		.num_parents = 1,
 152		.ops = &clk_alpha_pll_postdiv_ops,
 153		.flags = CLK_SET_RATE_PARENT,
 154	},
 155};
 156
 157static struct clk_alpha_pll gpll4_early = {
 158	.offset = 0x24000,
 159	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 160	.clkr = {
 161		.enable_reg = 0x45000,
 162		.enable_mask = BIT(5),
 163		.hw.init = &(struct clk_init_data){
 164			.name = "gpll4_early",
 165			.parent_data = &(const struct clk_parent_data) {
 166				.fw_name = "xo",
 167			},
 168			.num_parents = 1,
 169			.ops = &clk_alpha_pll_fixed_ops,
 170		},
 171	},
 172};
 173
 174static struct clk_alpha_pll_postdiv gpll4 = {
 175	.offset = 0x24000,
 176	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 177	.clkr.hw.init = &(struct clk_init_data){
 178		.name = "gpll4",
 179		.parent_hws = (const struct clk_hw*[]){
 180			&gpll4_early.clkr.hw,
 181		},
 182		.num_parents = 1,
 183		.ops = &clk_alpha_pll_postdiv_ro_ops,
 184	},
 185};
 186
 187static struct clk_alpha_pll gpll6_early = {
 188	.offset = 0x37000,
 189	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 190	.clkr = {
 191		.enable_reg = 0x45000,
 192		.enable_mask = BIT(7),
 193		.hw.init = &(struct clk_init_data){
 194			.name = "gpll6_early",
 195			.parent_data = &(const struct clk_parent_data) {
 196				.fw_name = "xo",
 197			},
 198			.num_parents = 1,
 199			.ops = &clk_alpha_pll_fixed_ops,
 200		},
 201	},
 202};
 203
 204static struct clk_fixed_factor gpll6_early_div = {
 205	.mult = 1,
 206	.div = 2,
 207	.hw.init = &(struct clk_init_data){
 208		.name = "gpll6_early_div",
 209		.parent_hws = (const struct clk_hw*[]){
 210			&gpll6_early.clkr.hw,
 211		},
 212		.num_parents = 1,
 213		.ops = &clk_fixed_factor_ops,
 214	},
 215};
 216
 217static struct clk_alpha_pll_postdiv gpll6 = {
 218	.offset = 0x37000,
 219	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 220	.clkr.hw.init = &(struct clk_init_data){
 221		.name = "gpll6",
 222		.parent_hws = (const struct clk_hw*[]){
 223			&gpll6_early.clkr.hw,
 224		},
 225		.num_parents = 1,
 226		.ops = &clk_alpha_pll_postdiv_ro_ops,
 227	},
 228};
 229
 230static const struct parent_map gcc_xo_gpll0_gpll0div2_2_map[] = {
 231	{ P_XO, 0 },
 232	{ P_GPLL0, 1 },
 233	{ P_GPLL0_DIV2, 2 },
 234};
 235
 236static const struct parent_map gcc_xo_gpll0_gpll0div2_4_map[] = {
 237	{ P_XO, 0 },
 238	{ P_GPLL0, 1 },
 239	{ P_GPLL0_DIV2, 4 },
 240};
 241
 242static const struct clk_parent_data gcc_xo_gpll0_gpll0div2_data[] = {
 243	{ .fw_name = "xo" },
 244	{ .hw = &gpll0.clkr.hw },
 245	{ .hw = &gpll0_early_div.hw },
 246};
 247
 248static const struct parent_map gcc_apc_droop_detector_map[] = {
 249	{ P_XO, 0 },
 250	{ P_GPLL0, 1 },
 251	{ P_GPLL4, 2 },
 252};
 253
 254static const struct clk_parent_data gcc_apc_droop_detector_data[] = {
 255	{ .fw_name = "xo" },
 256	{ .hw = &gpll0.clkr.hw },
 257	{ .hw = &gpll4.clkr.hw },
 258};
 259
 260static const struct freq_tbl ftbl_apc_droop_detector_clk_src[] = {
 261	F(19200000, P_XO, 1, 0, 0),
 262	F(400000000, P_GPLL0, 2, 0, 0),
 263	F(576000000, P_GPLL4, 2, 0, 0),
 264	{ }
 265};
 266
 267static struct clk_rcg2 apc0_droop_detector_clk_src = {
 268	.cmd_rcgr = 0x78008,
 269	.hid_width = 5,
 270	.freq_tbl = ftbl_apc_droop_detector_clk_src,
 271	.parent_map = gcc_apc_droop_detector_map,
 272	.clkr.hw.init = &(struct clk_init_data) {
 273		.name = "apc0_droop_detector_clk_src",
 274		.parent_data = gcc_apc_droop_detector_data,
 275		.num_parents = ARRAY_SIZE(gcc_apc_droop_detector_data),
 276		.ops = &clk_rcg2_ops,
 277	}
 278};
 279static struct clk_rcg2 apc1_droop_detector_clk_src = {
 280	.cmd_rcgr = 0x79008,
 281	.hid_width = 5,
 282	.freq_tbl = ftbl_apc_droop_detector_clk_src,
 283	.parent_map = gcc_apc_droop_detector_map,
 284	.clkr.hw.init = &(struct clk_init_data) {
 285		.name = "apc1_droop_detector_clk_src",
 286		.parent_data = gcc_apc_droop_detector_data,
 287		.num_parents = ARRAY_SIZE(gcc_apc_droop_detector_data),
 288		.ops = &clk_rcg2_ops,
 289	}
 290};
 291
 292static const struct freq_tbl ftbl_apss_ahb_clk_src[] = {
 293	F(19200000, P_XO, 1, 0, 0),
 294	F(25000000, P_GPLL0_DIV2, 16, 0, 0),
 295	F(50000000, P_GPLL0, 16, 0, 0),
 296	F(100000000, P_GPLL0, 8, 0, 0),
 297	F(133330000, P_GPLL0, 6, 0, 0),
 298	{ }
 299};
 300
 301static struct clk_rcg2 apss_ahb_clk_src = {
 302	.cmd_rcgr = 0x46000,
 303	.hid_width = 5,
 304	.freq_tbl = ftbl_apss_ahb_clk_src,
 305	.parent_map = gcc_xo_gpll0_gpll0div2_4_map,
 306	.clkr.hw.init = &(struct clk_init_data) {
 307		.name = "apss_ahb_clk_src",
 308		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 309		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 310		.ops = &clk_rcg2_ops,
 311	}
 312};
 313
 314static const struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = {
 315	F(19200000, P_XO, 1, 0, 0),
 316	F(25000000, P_GPLL0_DIV2, 16, 0, 0),
 317	F(50000000, P_GPLL0, 16, 0, 0),
 318	{ }
 319};
 320
 321static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 322	.cmd_rcgr = 0x0200c,
 323	.hid_width = 5,
 324	.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 325	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
 326	.clkr.hw.init = &(struct clk_init_data) {
 327		.name = "blsp1_qup1_i2c_apps_clk_src",
 328		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 329		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 330		.ops = &clk_rcg2_ops,
 331	}
 332};
 333
 334static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 335	.cmd_rcgr = 0x03000,
 336	.hid_width = 5,
 337	.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 338	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
 339	.clkr.hw.init = &(struct clk_init_data) {
 340		.name = "blsp1_qup2_i2c_apps_clk_src",
 341		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 342		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 343		.ops = &clk_rcg2_ops,
 344	}
 345};
 346
 347static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 348	.cmd_rcgr = 0x04000,
 349	.hid_width = 5,
 350	.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 351	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
 352	.clkr.hw.init = &(struct clk_init_data) {
 353		.name = "blsp1_qup3_i2c_apps_clk_src",
 354		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 355		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 356		.ops = &clk_rcg2_ops,
 357	}
 358};
 359
 360static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 361	.cmd_rcgr = 0x05000,
 362	.hid_width = 5,
 363	.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 364	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
 365	.clkr.hw.init = &(struct clk_init_data) {
 366		.name = "blsp1_qup4_i2c_apps_clk_src",
 367		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 368		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 369		.ops = &clk_rcg2_ops,
 370	}
 371};
 372
 373static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
 374	.cmd_rcgr = 0x0c00c,
 375	.hid_width = 5,
 376	.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 377	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
 378	.clkr.hw.init = &(struct clk_init_data) {
 379		.name = "blsp2_qup1_i2c_apps_clk_src",
 380		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 381		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 382		.ops = &clk_rcg2_ops,
 383	}
 384};
 385
 386static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
 387	.cmd_rcgr = 0x0d000,
 388	.hid_width = 5,
 389	.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 390	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
 391	.clkr.hw.init = &(struct clk_init_data) {
 392		.name = "blsp2_qup2_i2c_apps_clk_src",
 393		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 394		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 395		.ops = &clk_rcg2_ops,
 396	}
 397};
 398
 399static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
 400	.cmd_rcgr = 0x0f000,
 401	.hid_width = 5,
 402	.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 403	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
 404	.clkr.hw.init = &(struct clk_init_data) {
 405		.name = "blsp2_qup3_i2c_apps_clk_src",
 406		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 407		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 408		.ops = &clk_rcg2_ops,
 409	}
 410};
 411
 412static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
 413	.cmd_rcgr = 0x18000,
 414	.hid_width = 5,
 415	.freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 416	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
 417	.clkr.hw.init = &(struct clk_init_data) {
 418		.name = "blsp2_qup4_i2c_apps_clk_src",
 419		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 420		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 421		.ops = &clk_rcg2_ops,
 422	}
 423};
 424
 425static const struct freq_tbl ftbl_blsp_spi_apps_clk_src[] = {
 426	F(960000, P_XO, 10, 1, 2),
 427	F(4800000, P_XO, 4, 0, 0),
 428	F(9600000, P_XO, 2, 0, 0),
 429	F(12500000, P_GPLL0_DIV2, 16, 1, 2),
 430	F(16000000, P_GPLL0, 10, 1, 5),
 431	F(19200000, P_XO, 1, 0, 0),
 432	F(25000000, P_GPLL0, 16, 1, 2),
 433	F(50000000, P_GPLL0, 16, 0, 0),
 434	{ }
 435};
 436
 437static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 438	.cmd_rcgr = 0x02024,
 439	.hid_width = 5,
 440	.mnd_width = 8,
 441	.freq_tbl = ftbl_blsp_spi_apps_clk_src,
 442	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
 443	.clkr.hw.init = &(struct clk_init_data) {
 444		.name = "blsp1_qup1_spi_apps_clk_src",
 445		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 446		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 447		.ops = &clk_rcg2_ops,
 448	}
 449};
 450
 451static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 452	.cmd_rcgr = 0x03014,
 453	.hid_width = 5,
 454	.mnd_width = 8,
 455	.freq_tbl = ftbl_blsp_spi_apps_clk_src,
 456	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
 457	.clkr.hw.init = &(struct clk_init_data) {
 458		.name = "blsp1_qup2_spi_apps_clk_src",
 459		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 460		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 461		.ops = &clk_rcg2_ops,
 462	}
 463};
 464
 465static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 466	.cmd_rcgr = 0x04024,
 467	.hid_width = 5,
 468	.mnd_width = 8,
 469	.freq_tbl = ftbl_blsp_spi_apps_clk_src,
 470	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
 471	.clkr.hw.init = &(struct clk_init_data) {
 472		.name = "blsp1_qup3_spi_apps_clk_src",
 473		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 474		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 475		.ops = &clk_rcg2_ops,
 476	}
 477};
 478
 479static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 480	.cmd_rcgr = 0x05024,
 481	.hid_width = 5,
 482	.mnd_width = 8,
 483	.freq_tbl = ftbl_blsp_spi_apps_clk_src,
 484	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
 485	.clkr.hw.init = &(struct clk_init_data) {
 486		.name = "blsp1_qup4_spi_apps_clk_src",
 487		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 488		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 489		.ops = &clk_rcg2_ops,
 490	}
 491};
 492
 493static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
 494	.cmd_rcgr = 0x0c024,
 495	.hid_width = 5,
 496	.mnd_width = 8,
 497	.freq_tbl = ftbl_blsp_spi_apps_clk_src,
 498	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
 499	.clkr.hw.init = &(struct clk_init_data) {
 500		.name = "blsp2_qup1_spi_apps_clk_src",
 501		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 502		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 503		.ops = &clk_rcg2_ops,
 504	}
 505};
 506
 507static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
 508	.cmd_rcgr = 0x0d014,
 509	.hid_width = 5,
 510	.mnd_width = 8,
 511	.freq_tbl = ftbl_blsp_spi_apps_clk_src,
 512	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
 513	.clkr.hw.init = &(struct clk_init_data) {
 514		.name = "blsp2_qup2_spi_apps_clk_src",
 515		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 516		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 517		.ops = &clk_rcg2_ops,
 518	}
 519};
 520
 521static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
 522	.cmd_rcgr = 0x0f024,
 523	.hid_width = 5,
 524	.mnd_width = 8,
 525	.freq_tbl = ftbl_blsp_spi_apps_clk_src,
 526	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
 527	.clkr.hw.init = &(struct clk_init_data) {
 528		.name = "blsp2_qup3_spi_apps_clk_src",
 529		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 530		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 531		.ops = &clk_rcg2_ops,
 532	}
 533};
 534
 535static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
 536	.cmd_rcgr = 0x18024,
 537	.hid_width = 5,
 538	.mnd_width = 8,
 539	.freq_tbl = ftbl_blsp_spi_apps_clk_src,
 540	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
 541	.clkr.hw.init = &(struct clk_init_data) {
 542		.name = "blsp2_qup4_spi_apps_clk_src",
 543		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 544		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 545		.ops = &clk_rcg2_ops,
 546	}
 547};
 548
 549static const struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = {
 550	F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
 551	F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
 552	F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
 553	F(16000000, P_GPLL0_DIV2, 5, 1, 5),
 554	F(19200000, P_XO, 1, 0, 0),
 555	F(24000000, P_GPLL0, 1, 3, 100),
 556	F(25000000, P_GPLL0, 16, 1, 2),
 557	F(32000000, P_GPLL0, 1, 1, 25),
 558	F(40000000, P_GPLL0, 1, 1, 20),
 559	F(46400000, P_GPLL0, 1, 29, 500),
 560	F(48000000, P_GPLL0, 1, 3, 50),
 561	F(51200000, P_GPLL0, 1, 8, 125),
 562	F(56000000, P_GPLL0, 1, 7, 100),
 563	F(58982400, P_GPLL0, 1, 1152, 15625),
 564	F(60000000, P_GPLL0, 1, 3, 40),
 565	F(64000000, P_GPLL0, 1, 2, 25),
 566	{ }
 567};
 568
 569static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 570	.cmd_rcgr = 0x02044,
 571	.hid_width = 5,
 572	.mnd_width = 16,
 573	.freq_tbl = ftbl_blsp_uart_apps_clk_src,
 574	.parent_map = gcc_xo_gpll0_gpll0div2_4_map,
 575	.clkr.hw.init = &(struct clk_init_data) {
 576		.name = "blsp1_uart1_apps_clk_src",
 577		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 578		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 579		.ops = &clk_rcg2_ops,
 580	}
 581};
 582
 583static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 584	.cmd_rcgr = 0x03034,
 585	.hid_width = 5,
 586	.mnd_width = 16,
 587	.freq_tbl = ftbl_blsp_uart_apps_clk_src,
 588	.parent_map = gcc_xo_gpll0_gpll0div2_4_map,
 589	.clkr.hw.init = &(struct clk_init_data) {
 590		.name = "blsp1_uart2_apps_clk_src",
 591		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 592		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 593		.ops = &clk_rcg2_ops,
 594	}
 595};
 596
 597static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
 598	.cmd_rcgr = 0x0c044,
 599	.hid_width = 5,
 600	.mnd_width = 16,
 601	.freq_tbl = ftbl_blsp_uart_apps_clk_src,
 602	.parent_map = gcc_xo_gpll0_gpll0div2_4_map,
 603	.clkr.hw.init = &(struct clk_init_data) {
 604		.name = "blsp2_uart1_apps_clk_src",
 605		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 606		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 607		.ops = &clk_rcg2_ops,
 608	}
 609};
 610
 611static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
 612	.cmd_rcgr = 0x0d034,
 613	.hid_width = 5,
 614	.mnd_width = 16,
 615	.freq_tbl = ftbl_blsp_uart_apps_clk_src,
 616	.parent_map = gcc_xo_gpll0_gpll0div2_4_map,
 617	.clkr.hw.init = &(struct clk_init_data) {
 618		.name = "blsp2_uart2_apps_clk_src",
 619		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 620		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 621		.ops = &clk_rcg2_ops,
 622	}
 623};
 624
 625static const struct parent_map gcc_byte0_map[] = {
 626	{ P_XO, 0 },
 627	{ P_DSI0PLL_BYTE, 1 },
 628	{ P_DSI1PLL_BYTE, 3 },
 629};
 630
 631static const struct parent_map gcc_byte1_map[] = {
 632	{ P_XO, 0 },
 633	{ P_DSI0PLL_BYTE, 3 },
 634	{ P_DSI1PLL_BYTE, 1 },
 635};
 636
 637static const struct clk_parent_data gcc_byte_data[] = {
 638	{ .fw_name = "xo" },
 639	{ .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
 640	{ .fw_name = "dsi1pllbyte", .name = "dsi1pllbyte" },
 641};
 642
 643static struct clk_rcg2 byte0_clk_src = {
 644	.cmd_rcgr = 0x4d044,
 645	.hid_width = 5,
 646	.parent_map = gcc_byte0_map,
 647	.clkr.hw.init = &(struct clk_init_data) {
 648		.name = "byte0_clk_src",
 649		.parent_data = gcc_byte_data,
 650		.num_parents = ARRAY_SIZE(gcc_byte_data),
 651		.ops = &clk_byte2_ops,
 652		.flags = CLK_SET_RATE_PARENT,
 653	}
 654};
 655
 656static struct clk_rcg2 byte1_clk_src = {
 657	.cmd_rcgr = 0x4d0b0,
 658	.hid_width = 5,
 659	.parent_map = gcc_byte1_map,
 660	.clkr.hw.init = &(struct clk_init_data) {
 661		.name = "byte1_clk_src",
 662		.parent_data = gcc_byte_data,
 663		.num_parents = ARRAY_SIZE(gcc_byte_data),
 664		.ops = &clk_byte2_ops,
 665		.flags = CLK_SET_RATE_PARENT,
 666	}
 667};
 668
 669static const struct parent_map gcc_gp_map[] = {
 670	{ P_XO, 0 },
 671	{ P_GPLL0, 1 },
 672	{ P_GPLL6, 2 },
 673	{ P_GPLL0_DIV2, 4 },
 674	{ P_SLEEP_CLK, 6 },
 675};
 676
 677static const struct clk_parent_data gcc_gp_data[] = {
 678	{ .fw_name = "xo" },
 679	{ .hw = &gpll0.clkr.hw },
 680	{ .hw = &gpll6.clkr.hw },
 681	{ .hw = &gpll0_early_div.hw },
 682	{ .fw_name = "sleep", .name = "sleep" },
 683};
 684
 685static const struct freq_tbl ftbl_camss_gp_clk_src[] = {
 686	F(50000000, P_GPLL0_DIV2, 8, 0, 0),
 687	F(100000000, P_GPLL0, 8, 0, 0),
 688	F(200000000, P_GPLL0, 4, 0, 0),
 689	F(266670000, P_GPLL0, 3, 0, 0),
 690	{ }
 691};
 692
 693static struct clk_rcg2 camss_gp0_clk_src = {
 694	.cmd_rcgr = 0x54000,
 695	.hid_width = 5,
 696	.mnd_width = 8,
 697	.freq_tbl = ftbl_camss_gp_clk_src,
 698	.parent_map = gcc_gp_map,
 699	.clkr.hw.init = &(struct clk_init_data) {
 700		.name = "camss_gp0_clk_src",
 701		.parent_data = gcc_gp_data,
 702		.num_parents = ARRAY_SIZE(gcc_gp_data),
 703		.ops = &clk_rcg2_ops,
 704	}
 705};
 706
 707static struct clk_rcg2 camss_gp1_clk_src = {
 708	.cmd_rcgr = 0x55000,
 709	.hid_width = 5,
 710	.mnd_width = 8,
 711	.freq_tbl = ftbl_camss_gp_clk_src,
 712	.parent_map = gcc_gp_map,
 713	.clkr.hw.init = &(struct clk_init_data) {
 714		.name = "camss_gp1_clk_src",
 715		.parent_data = gcc_gp_data,
 716		.num_parents = ARRAY_SIZE(gcc_gp_data),
 717		.ops = &clk_rcg2_ops,
 718	}
 719};
 720
 721static const struct freq_tbl ftbl_camss_top_ahb_clk_src[] = {
 722	F(40000000, P_GPLL0_DIV2, 10, 0, 0),
 723	F(80000000, P_GPLL0, 10, 0, 0),
 724	{ }
 725};
 726
 727static struct clk_rcg2 camss_top_ahb_clk_src = {
 728	.cmd_rcgr = 0x5a000,
 729	.hid_width = 5,
 730	.freq_tbl = ftbl_camss_top_ahb_clk_src,
 731	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
 732	.clkr.hw.init = &(struct clk_init_data) {
 733		.name = "camss_top_ahb_clk_src",
 734		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 735		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 736		.ops = &clk_rcg2_ops,
 737	}
 738};
 739
 740static const struct parent_map gcc_cci_map[] = {
 741	{ P_XO, 0 },
 742	{ P_GPLL0, 2 },
 743	{ P_GPLL0_DIV2, 3 },
 744	{ P_SLEEP_CLK, 6 },
 745};
 746
 747static const struct clk_parent_data gcc_cci_data[] = {
 748	{ .fw_name = "xo" },
 749	{ .hw = &gpll0.clkr.hw },
 750	{ .hw = &gpll0_early_div.hw },
 751	{ .fw_name = "sleep", .name = "sleep" },
 752};
 753
 754static const struct freq_tbl ftbl_cci_clk_src[] = {
 755	F(19200000, P_XO, 1, 0, 0),
 756	F(37500000, P_GPLL0_DIV2, 1, 3, 32),
 757	{ }
 758};
 759
 760static struct clk_rcg2 cci_clk_src = {
 761	.cmd_rcgr = 0x51000,
 762	.hid_width = 5,
 763	.mnd_width = 8,
 764	.freq_tbl = ftbl_cci_clk_src,
 765	.parent_map = gcc_cci_map,
 766	.clkr.hw.init = &(struct clk_init_data) {
 767		.name = "cci_clk_src",
 768		.parent_data = gcc_cci_data,
 769		.num_parents = ARRAY_SIZE(gcc_cci_data),
 770		.ops = &clk_rcg2_ops,
 771	}
 772};
 773
 774static const struct parent_map gcc_cpp_map[] = {
 775	{ P_XO, 0 },
 776	{ P_GPLL0, 1 },
 777	{ P_GPLL6, 3 },
 778	{ P_GPLL2, 4 },
 779	{ P_GPLL0_DIV2, 5 },
 780};
 781
 782static const struct clk_parent_data gcc_cpp_data[] = {
 783	{ .fw_name = "xo" },
 784	{ .hw = &gpll0.clkr.hw },
 785	{ .hw = &gpll6.clkr.hw },
 786	{ .hw = &gpll2.clkr.hw },
 787	{ .hw = &gpll0_early_div.hw },
 788};
 789
 790static const struct freq_tbl ftbl_cpp_clk_src[] = {
 791	F(100000000, P_GPLL0_DIV2, 4, 0, 0),
 792	F(200000000, P_GPLL0, 4, 0, 0),
 793	F(266670000, P_GPLL0, 3, 0, 0),
 794	F(320000000, P_GPLL0, 2.5, 0, 0),
 795	F(400000000, P_GPLL0, 2, 0, 0),
 796	F(465000000, P_GPLL2, 2, 0, 0),
 797	{ }
 798};
 799
 800static struct clk_rcg2 cpp_clk_src = {
 801	.cmd_rcgr = 0x58018,
 802	.hid_width = 5,
 803	.freq_tbl = ftbl_cpp_clk_src,
 804	.parent_map = gcc_cpp_map,
 805	.clkr.hw.init = &(struct clk_init_data) {
 806		.name = "cpp_clk_src",
 807		.parent_data = gcc_cpp_data,
 808		.num_parents = ARRAY_SIZE(gcc_cpp_data),
 809		.ops = &clk_rcg2_ops,
 810	}
 811};
 812
 813static const struct freq_tbl ftbl_crypto_clk_src[] = {
 814	F(40000000, P_GPLL0_DIV2, 10, 0, 0),
 815	F(80000000, P_GPLL0, 10, 0, 0),
 816	F(100000000, P_GPLL0, 8, 0, 0),
 817	F(160000000, P_GPLL0, 5, 0, 0),
 818	{ }
 819};
 820
 821static struct clk_rcg2 crypto_clk_src = {
 822	.cmd_rcgr = 0x16004,
 823	.hid_width = 5,
 824	.freq_tbl = ftbl_crypto_clk_src,
 825	.parent_map = gcc_xo_gpll0_gpll0div2_4_map,
 826	.clkr.hw.init = &(struct clk_init_data) {
 827		.name = "crypto_clk_src",
 828		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 829		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 830		.ops = &clk_rcg2_ops,
 831	}
 832};
 833
 834static const struct parent_map gcc_csi0_map[] = {
 835	{ P_XO, 0 },
 836	{ P_GPLL0, 1 },
 837	{ P_GPLL2, 4 },
 838	{ P_GPLL0_DIV2, 5 },
 839};
 840
 841static const struct parent_map gcc_csi12_map[] = {
 842	{ P_XO, 0 },
 843	{ P_GPLL0, 1 },
 844	{ P_GPLL2, 5 },
 845	{ P_GPLL0_DIV2, 4 },
 846};
 847
 848static const struct clk_parent_data gcc_csi_data[] = {
 849	{ .fw_name = "xo" },
 850	{ .hw = &gpll0.clkr.hw },
 851	{ .hw = &gpll2.clkr.hw },
 852	{ .hw = &gpll0_early_div.hw },
 853};
 854
 855static const struct freq_tbl ftbl_csi_clk_src[] = {
 856	F(100000000, P_GPLL0_DIV2, 4, 0, 0),
 857	F(200000000, P_GPLL0, 4, 0, 0),
 858	F(310000000, P_GPLL2, 3, 0, 0),
 859	F(400000000, P_GPLL0, 2, 0, 0),
 860	F(465000000, P_GPLL2, 2, 0, 0),
 861	{ }
 862};
 863
 864static struct clk_rcg2 csi0_clk_src = {
 865	.cmd_rcgr = 0x4e020,
 866	.hid_width = 5,
 867	.freq_tbl = ftbl_csi_clk_src,
 868	.parent_map = gcc_csi0_map,
 869	.clkr.hw.init = &(struct clk_init_data) {
 870		.name = "csi0_clk_src",
 871		.parent_data = gcc_csi_data,
 872		.num_parents = ARRAY_SIZE(gcc_csi_data),
 873		.ops = &clk_rcg2_ops,
 874	}
 875};
 876
 877static struct clk_rcg2 csi1_clk_src = {
 878	.cmd_rcgr = 0x4f020,
 879	.hid_width = 5,
 880	.freq_tbl = ftbl_csi_clk_src,
 881	.parent_map = gcc_csi12_map,
 882	.clkr.hw.init = &(struct clk_init_data) {
 883		.name = "csi1_clk_src",
 884		.parent_data = gcc_csi_data,
 885		.num_parents = ARRAY_SIZE(gcc_csi_data),
 886		.ops = &clk_rcg2_ops,
 887	}
 888};
 889
 890static struct clk_rcg2 csi2_clk_src = {
 891	.cmd_rcgr = 0x3c020,
 892	.hid_width = 5,
 893	.freq_tbl = ftbl_csi_clk_src,
 894	.parent_map = gcc_csi12_map,
 895	.clkr.hw.init = &(struct clk_init_data) {
 896		.name = "csi2_clk_src",
 897		.parent_data = gcc_csi_data,
 898		.num_parents = ARRAY_SIZE(gcc_csi_data),
 899		.ops = &clk_rcg2_ops,
 900	}
 901};
 902
 903static const struct parent_map gcc_csip_map[] = {
 904	{ P_XO, 0 },
 905	{ P_GPLL0, 1 },
 906	{ P_GPLL4, 3 },
 907	{ P_GPLL2, 4 },
 908	{ P_GPLL0_DIV2, 5 },
 909};
 910
 911static const struct clk_parent_data gcc_csip_data[] = {
 912	{ .fw_name = "xo" },
 913	{ .hw = &gpll0.clkr.hw },
 914	{ .hw = &gpll4.clkr.hw },
 915	{ .hw = &gpll2.clkr.hw },
 916	{ .hw = &gpll0_early_div.hw },
 917};
 918
 919static const struct freq_tbl ftbl_csi_p_clk_src[] = {
 920	F(66670000, P_GPLL0_DIV2, 6, 0, 0),
 921	F(133330000, P_GPLL0, 6, 0, 0),
 922	F(200000000, P_GPLL0, 4, 0, 0),
 923	F(266670000, P_GPLL0, 3, 0, 0),
 924	F(310000000, P_GPLL2, 3, 0, 0),
 925	{ }
 926};
 927
 928static struct clk_rcg2 csi0p_clk_src = {
 929	.cmd_rcgr = 0x58084,
 930	.hid_width = 5,
 931	.freq_tbl = ftbl_csi_p_clk_src,
 932	.parent_map = gcc_csip_map,
 933	.clkr.hw.init = &(struct clk_init_data) {
 934		.name = "csi0p_clk_src",
 935		.parent_data = gcc_csip_data,
 936		.num_parents = ARRAY_SIZE(gcc_csip_data),
 937		.ops = &clk_rcg2_ops,
 938	}
 939};
 940
 941static struct clk_rcg2 csi1p_clk_src = {
 942	.cmd_rcgr = 0x58094,
 943	.hid_width = 5,
 944	.freq_tbl = ftbl_csi_p_clk_src,
 945	.parent_map = gcc_csip_map,
 946	.clkr.hw.init = &(struct clk_init_data) {
 947		.name = "csi1p_clk_src",
 948		.parent_data = gcc_csip_data,
 949		.num_parents = ARRAY_SIZE(gcc_csip_data),
 950		.ops = &clk_rcg2_ops,
 951	}
 952};
 953
 954static struct clk_rcg2 csi2p_clk_src = {
 955	.cmd_rcgr = 0x580a4,
 956	.hid_width = 5,
 957	.freq_tbl = ftbl_csi_p_clk_src,
 958	.parent_map = gcc_csip_map,
 959	.clkr.hw.init = &(struct clk_init_data) {
 960		.name = "csi2p_clk_src",
 961		.parent_data = gcc_csip_data,
 962		.num_parents = ARRAY_SIZE(gcc_csip_data),
 963		.ops = &clk_rcg2_ops,
 964	}
 965};
 966
 967static const struct freq_tbl ftbl_csi_phytimer_clk_src[] = {
 968	F(100000000, P_GPLL0_DIV2, 4, 0, 0),
 969	F(200000000, P_GPLL0, 4, 0, 0),
 970	F(266670000, P_GPLL0, 3, 0, 0),
 971	{ }
 972};
 973
 974static struct clk_rcg2 csi0phytimer_clk_src = {
 975	.cmd_rcgr = 0x4e000,
 976	.hid_width = 5,
 977	.freq_tbl = ftbl_csi_phytimer_clk_src,
 978	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
 979	.clkr.hw.init = &(struct clk_init_data) {
 980		.name = "csi0phytimer_clk_src",
 981		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 982		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 983		.ops = &clk_rcg2_ops,
 984	}
 985};
 986
 987static struct clk_rcg2 csi1phytimer_clk_src = {
 988	.cmd_rcgr = 0x4f000,
 989	.hid_width = 5,
 990	.freq_tbl = ftbl_csi_phytimer_clk_src,
 991	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
 992	.clkr.hw.init = &(struct clk_init_data) {
 993		.name = "csi1phytimer_clk_src",
 994		.parent_data = gcc_xo_gpll0_gpll0div2_data,
 995		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
 996		.ops = &clk_rcg2_ops,
 997	}
 998};
 999
1000static struct clk_rcg2 csi2phytimer_clk_src = {
1001	.cmd_rcgr = 0x4f05c,
1002	.hid_width = 5,
1003	.freq_tbl = ftbl_csi_phytimer_clk_src,
1004	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
1005	.clkr.hw.init = &(struct clk_init_data) {
1006		.name = "csi2phytimer_clk_src",
1007		.parent_data = gcc_xo_gpll0_gpll0div2_data,
1008		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
1009		.ops = &clk_rcg2_ops,
1010	}
1011};
1012
1013static const struct parent_map gcc_esc_map[] = {
1014	{ P_XO, 0 },
1015	{ P_GPLL0, 3 },
1016};
1017
1018static const struct clk_parent_data gcc_esc_vsync_data[] = {
1019	{ .fw_name = "xo" },
1020	{ .hw = &gpll0.clkr.hw },
1021};
1022
1023static const struct freq_tbl ftbl_esc0_1_clk_src[] = {
1024	F(19200000, P_XO, 1, 0, 0),
1025	{ }
1026};
1027
1028static struct clk_rcg2 esc0_clk_src = {
1029	.cmd_rcgr = 0x4d05c,
1030	.hid_width = 5,
1031	.freq_tbl = ftbl_esc0_1_clk_src,
1032	.parent_map = gcc_esc_map,
1033	.clkr.hw.init = &(struct clk_init_data) {
1034		.name = "esc0_clk_src",
1035		.parent_data = gcc_esc_vsync_data,
1036		.num_parents = ARRAY_SIZE(gcc_esc_vsync_data),
1037		.ops = &clk_rcg2_ops,
1038	}
1039};
1040
1041static struct clk_rcg2 esc1_clk_src = {
1042	.cmd_rcgr = 0x4d0a8,
1043	.hid_width = 5,
1044	.freq_tbl = ftbl_esc0_1_clk_src,
1045	.parent_map = gcc_esc_map,
1046	.clkr.hw.init = &(struct clk_init_data) {
1047		.name = "esc1_clk_src",
1048		.parent_data = gcc_esc_vsync_data,
1049		.num_parents = ARRAY_SIZE(gcc_esc_vsync_data),
1050		.ops = &clk_rcg2_ops,
1051	}
1052};
1053
1054static const struct parent_map gcc_gfx3d_map[] = {
1055	{ P_XO, 0 },
1056	{ P_GPLL0, 1 },
1057	{ P_GPLL3, 2 },
1058	{ P_GPLL6, 3 },
1059	{ P_GPLL4, 4 },
1060	{ P_GPLL0_DIV2, 5 },
1061	{ P_GPLL6_DIV2, 6 },
1062};
1063
1064static const struct clk_parent_data gcc_gfx3d_data[] = {
1065	{ .fw_name = "xo" },
1066	{ .hw = &gpll0.clkr.hw },
1067	{ .hw = &gpll3.clkr.hw },
1068	{ .hw = &gpll6.clkr.hw },
1069	{ .hw = &gpll4.clkr.hw },
1070	{ .hw = &gpll0_early_div.hw },
1071	{ .hw = &gpll6_early_div.hw },
1072};
1073
1074static const struct freq_tbl ftbl_gfx3d_clk_src[] = {
1075	F(19200000, P_XO, 1, 0, 0),
1076	F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1077	F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1078	F(100000000, P_GPLL0_DIV2, 4, 0, 0),
1079	F(133330000, P_GPLL0_DIV2, 3, 0, 0),
1080	F(160000000, P_GPLL0_DIV2, 2.5, 0, 0),
1081	F(200000000, P_GPLL0_DIV2, 2, 0, 0),
1082	F(266670000, P_GPLL0, 3.0, 0, 0),
1083	F(320000000, P_GPLL0, 2.5, 0, 0),
1084	F(400000000, P_GPLL0, 2, 0, 0),
1085	F(460800000, P_GPLL4, 2.5, 0, 0),
1086	F(510000000, P_GPLL3, 2, 0, 0),
1087	F(560000000, P_GPLL3, 2, 0, 0),
1088	F(600000000, P_GPLL3, 2, 0, 0),
1089	F(650000000, P_GPLL3, 2, 0, 0),
1090	F(685000000, P_GPLL3, 2, 0, 0),
1091	F(725000000, P_GPLL3, 2, 0, 0),
1092	{ }
1093};
1094
1095static struct clk_rcg2 gfx3d_clk_src = {
1096	.cmd_rcgr = 0x59000,
1097	.hid_width = 5,
1098	.freq_tbl = ftbl_gfx3d_clk_src,
1099	.parent_map = gcc_gfx3d_map,
1100	.clkr.hw.init = &(struct clk_init_data) {
1101		.name = "gfx3d_clk_src",
1102		.parent_data = gcc_gfx3d_data,
1103		.num_parents = ARRAY_SIZE(gcc_gfx3d_data),
1104		.ops = &clk_rcg2_floor_ops,
1105		.flags = CLK_SET_RATE_PARENT,
1106	}
1107};
1108
1109static const struct freq_tbl ftbl_gp_clk_src[] = {
1110	F(19200000, P_XO, 1, 0, 0),
1111	{ }
1112};
1113
1114static struct clk_rcg2 gp1_clk_src = {
1115	.cmd_rcgr = 0x08004,
1116	.hid_width = 5,
1117	.mnd_width = 8,
1118	.freq_tbl = ftbl_gp_clk_src,
1119	.parent_map = gcc_gp_map,
1120	.clkr.hw.init = &(struct clk_init_data) {
1121		.name = "gp1_clk_src",
1122		.parent_data = gcc_gp_data,
1123		.num_parents = ARRAY_SIZE(gcc_gp_data),
1124		.ops = &clk_rcg2_ops,
1125	}
1126};
1127
1128static struct clk_rcg2 gp2_clk_src = {
1129	.cmd_rcgr = 0x09004,
1130	.hid_width = 5,
1131	.mnd_width = 8,
1132	.freq_tbl = ftbl_gp_clk_src,
1133	.parent_map = gcc_gp_map,
1134	.clkr.hw.init = &(struct clk_init_data) {
1135		.name = "gp2_clk_src",
1136		.parent_data = gcc_gp_data,
1137		.num_parents = ARRAY_SIZE(gcc_gp_data),
1138		.ops = &clk_rcg2_ops,
1139	}
1140};
1141
1142static struct clk_rcg2 gp3_clk_src = {
1143	.cmd_rcgr = 0x0a004,
1144	.hid_width = 5,
1145	.mnd_width = 8,
1146	.freq_tbl = ftbl_gp_clk_src,
1147	.parent_map = gcc_gp_map,
1148	.clkr.hw.init = &(struct clk_init_data) {
1149		.name = "gp3_clk_src",
1150		.parent_data = gcc_gp_data,
1151		.num_parents = ARRAY_SIZE(gcc_gp_data),
1152		.ops = &clk_rcg2_ops,
1153	}
1154};
1155
1156static const struct parent_map gcc_jpeg0_map[] = {
1157	{ P_XO, 0 },
1158	{ P_GPLL0, 1 },
1159	{ P_GPLL6, 2 },
1160	{ P_GPLL0_DIV2, 4 },
1161	{ P_GPLL2, 5 },
1162};
1163
1164static const struct clk_parent_data gcc_jpeg0_data[] = {
1165	{ .fw_name = "xo" },
1166	{ .hw = &gpll0.clkr.hw },
1167	{ .hw = &gpll6.clkr.hw },
1168	{ .hw = &gpll0_early_div.hw },
1169	{ .hw = &gpll2.clkr.hw },
1170};
1171
1172static const struct freq_tbl ftbl_jpeg0_clk_src[] = {
1173	F(66670000, P_GPLL0_DIV2, 6, 0, 0),
1174	F(133330000, P_GPLL0, 6, 0, 0),
1175	F(200000000, P_GPLL0, 4, 0, 0),
1176	F(266670000, P_GPLL0, 3, 0, 0),
1177	F(310000000, P_GPLL2, 3, 0, 0),
1178	F(320000000, P_GPLL0, 2.5, 0, 0),
1179	{ }
1180};
1181
1182static struct clk_rcg2 jpeg0_clk_src = {
1183	.cmd_rcgr = 0x57000,
1184	.hid_width = 5,
1185	.freq_tbl = ftbl_jpeg0_clk_src,
1186	.parent_map = gcc_jpeg0_map,
1187	.clkr.hw.init = &(struct clk_init_data) {
1188		.name = "jpeg0_clk_src",
1189		.parent_data = gcc_jpeg0_data,
1190		.num_parents = ARRAY_SIZE(gcc_jpeg0_data),
1191		.ops = &clk_rcg2_ops,
1192	}
1193};
1194
1195static const struct parent_map gcc_mclk_map[] = {
1196	{ P_XO, 0 },
1197	{ P_GPLL0, 1 },
1198	{ P_GPLL6, 2 },
1199	{ P_GPLL0_DIV2, 4 },
1200	{ P_GPLL6_DIV2, 5 },
1201	{ P_SLEEP_CLK, 6 },
1202};
1203
1204static const struct clk_parent_data gcc_mclk_data[] = {
1205	{ .fw_name = "xo" },
1206	{ .hw = &gpll0.clkr.hw },
1207	{ .hw = &gpll6.clkr.hw },
1208	{ .hw = &gpll0_early_div.hw },
1209	{ .hw = &gpll6_early_div.hw },
1210	{ .fw_name = "sleep", .name = "sleep" },
1211};
1212
1213static const struct freq_tbl ftbl_mclk_clk_src[] = {
1214	F(19200000, P_GPLL6, 5, 4, 45),
1215	F(24000000, P_GPLL6_DIV2, 1, 2, 45),
1216	F(26000000, P_GPLL0, 1, 4, 123),
1217	F(33330000, P_GPLL0_DIV2, 12, 0, 0),
1218	F(36610000, P_GPLL6, 1, 2, 59),
1219	F(66667000, P_GPLL0, 12, 0, 0),
1220	{ }
1221};
1222
1223static struct clk_rcg2 mclk0_clk_src = {
1224	.cmd_rcgr = 0x52000,
1225	.hid_width = 5,
1226	.mnd_width = 8,
1227	.freq_tbl = ftbl_mclk_clk_src,
1228	.parent_map = gcc_mclk_map,
1229	.clkr.hw.init = &(struct clk_init_data) {
1230		.name = "mclk0_clk_src",
1231		.parent_data = gcc_mclk_data,
1232		.num_parents = ARRAY_SIZE(gcc_mclk_data),
1233		.ops = &clk_rcg2_ops,
1234	}
1235};
1236
1237static struct clk_rcg2 mclk1_clk_src = {
1238	.cmd_rcgr = 0x53000,
1239	.hid_width = 5,
1240	.mnd_width = 8,
1241	.freq_tbl = ftbl_mclk_clk_src,
1242	.parent_map = gcc_mclk_map,
1243	.clkr.hw.init = &(struct clk_init_data) {
1244		.name = "mclk1_clk_src",
1245		.parent_data = gcc_mclk_data,
1246		.num_parents = ARRAY_SIZE(gcc_mclk_data),
1247		.ops = &clk_rcg2_ops,
1248	}
1249};
1250
1251static struct clk_rcg2 mclk2_clk_src = {
1252	.cmd_rcgr = 0x5c000,
1253	.hid_width = 5,
1254	.mnd_width = 8,
1255	.freq_tbl = ftbl_mclk_clk_src,
1256	.parent_map = gcc_mclk_map,
1257	.clkr.hw.init = &(struct clk_init_data) {
1258		.name = "mclk2_clk_src",
1259		.parent_data = gcc_mclk_data,
1260		.num_parents = ARRAY_SIZE(gcc_mclk_data),
1261		.ops = &clk_rcg2_ops,
1262	}
1263};
1264
1265static struct clk_rcg2 mclk3_clk_src = {
1266	.cmd_rcgr = 0x5e000,
1267	.hid_width = 5,
1268	.mnd_width = 8,
1269	.freq_tbl = ftbl_mclk_clk_src,
1270	.parent_map = gcc_mclk_map,
1271	.clkr.hw.init = &(struct clk_init_data) {
1272		.name = "mclk3_clk_src",
1273		.parent_data = gcc_mclk_data,
1274		.num_parents = ARRAY_SIZE(gcc_mclk_data),
1275		.ops = &clk_rcg2_ops,
1276	}
1277};
1278
1279static const struct parent_map gcc_mdp_map[] = {
1280	{ P_XO, 0 },
1281	{ P_GPLL0, 1 },
1282	{ P_GPLL6, 3 },
1283	{ P_GPLL0_DIV2, 4 },
1284};
1285
1286static const struct clk_parent_data gcc_mdp_data[] = {
1287	{ .fw_name = "xo" },
1288	{ .hw = &gpll0.clkr.hw },
1289	{ .hw = &gpll6.clkr.hw },
1290	{ .hw = &gpll0_early_div.hw },
1291};
1292
1293static const struct freq_tbl ftbl_mdp_clk_src[] = {
1294	F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1295	F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1296	F(160000000, P_GPLL0_DIV2, 2.5, 0, 0),
1297	F(200000000, P_GPLL0, 4, 0, 0),
1298	F(266670000, P_GPLL0, 3, 0, 0),
1299	F(320000000, P_GPLL0, 2.5, 0, 0),
1300	F(400000000, P_GPLL0, 2, 0, 0),
1301	{ }
1302};
1303
1304static struct clk_rcg2 mdp_clk_src = {
1305	.cmd_rcgr = 0x4d014,
1306	.hid_width = 5,
1307	.freq_tbl = ftbl_mdp_clk_src,
1308	.parent_map = gcc_mdp_map,
1309	.clkr.hw.init = &(struct clk_init_data) {
1310		.name = "mdp_clk_src",
1311		.parent_data = gcc_mdp_data,
1312		.num_parents = ARRAY_SIZE(gcc_mdp_data),
1313		.ops = &clk_rcg2_ops,
1314	}
1315};
1316
1317static const struct parent_map gcc_pclk0_map[] = {
1318	{ P_XO, 0 },
1319	{ P_DSI0PLL, 1 },
1320	{ P_DSI1PLL, 3 },
1321};
1322
1323static const struct parent_map gcc_pclk1_map[] = {
1324	{ P_XO, 0 },
1325	{ P_DSI0PLL, 3 },
1326	{ P_DSI1PLL, 1 },
1327};
1328
1329static const struct clk_parent_data gcc_pclk_data[] = {
1330	{ .fw_name = "xo" },
1331	{ .fw_name = "dsi0pll", .name = "dsi0pll" },
1332	{ .fw_name = "dsi1pll", .name = "dsi1pll" },
1333};
1334
1335static struct clk_rcg2 pclk0_clk_src = {
1336	.cmd_rcgr = 0x4d000,
1337	.hid_width = 5,
1338	.mnd_width = 8,
1339	.parent_map = gcc_pclk0_map,
1340	.clkr.hw.init = &(struct clk_init_data) {
1341		.name = "pclk0_clk_src",
1342		.parent_data = gcc_pclk_data,
1343		.num_parents = ARRAY_SIZE(gcc_pclk_data),
1344		.ops = &clk_pixel_ops,
1345		.flags = CLK_SET_RATE_PARENT,
1346	}
1347};
1348
1349static struct clk_rcg2 pclk1_clk_src = {
1350	.cmd_rcgr = 0x4d0b8,
1351	.hid_width = 5,
1352	.mnd_width = 8,
1353	.parent_map = gcc_pclk1_map,
1354	.clkr.hw.init = &(struct clk_init_data) {
1355		.name = "pclk1_clk_src",
1356		.parent_data = gcc_pclk_data,
1357		.num_parents = ARRAY_SIZE(gcc_pclk_data),
1358		.ops = &clk_pixel_ops,
1359		.flags = CLK_SET_RATE_PARENT,
1360	}
1361};
1362
1363static const struct freq_tbl ftbl_pdm2_clk_src[] = {
1364	F(32000000, P_GPLL0_DIV2, 12.5, 0, 0),
1365	F(64000000, P_GPLL0, 12.5, 0, 0),
1366	{ }
1367};
1368
1369static struct clk_rcg2 pdm2_clk_src = {
1370	.cmd_rcgr = 0x44010,
1371	.hid_width = 5,
1372	.freq_tbl = ftbl_pdm2_clk_src,
1373	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
1374	.clkr.hw.init = &(struct clk_init_data) {
1375		.name = "pdm2_clk_src",
1376		.parent_data = gcc_xo_gpll0_gpll0div2_data,
1377		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
1378		.ops = &clk_rcg2_ops,
1379	}
1380};
1381
1382static const struct freq_tbl ftbl_rbcpr_gfx_clk_src[] = {
1383	F(19200000, P_XO, 1, 0, 0),
1384	F(50000000, P_GPLL0, 16, 0, 0),
1385	{ }
1386};
1387
1388static struct clk_rcg2 rbcpr_gfx_clk_src = {
1389	.cmd_rcgr = 0x3a00c,
1390	.hid_width = 5,
1391	.freq_tbl = ftbl_rbcpr_gfx_clk_src,
1392	.parent_map = gcc_xo_gpll0_gpll0div2_4_map,
1393	.clkr.hw.init = &(struct clk_init_data) {
1394		.name = "rbcpr_gfx_clk_src",
1395		.parent_data = gcc_xo_gpll0_gpll0div2_data,
1396		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
1397		.ops = &clk_rcg2_ops,
1398	}
1399};
1400
1401static const struct parent_map gcc_sdcc1_ice_core_map[] = {
1402	{ P_XO, 0 },
1403	{ P_GPLL0, 1 },
1404	{ P_GPLL6, 2 },
1405	{ P_GPLL0_DIV2, 4 },
1406};
1407
1408static const struct clk_parent_data gcc_sdcc1_ice_core_data[] = {
1409	{ .fw_name = "xo" },
1410	{ .hw = &gpll0.clkr.hw },
1411	{ .hw = &gpll6.clkr.hw },
1412	{ .hw = &gpll0_early_div.hw },
1413};
1414
1415static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
1416	F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1417	F(160000000, P_GPLL0, 5, 0, 0),
1418	F(270000000, P_GPLL6, 4, 0, 0),
1419	{ }
1420};
1421
1422static struct clk_rcg2 sdcc1_ice_core_clk_src = {
1423	.cmd_rcgr = 0x5d000,
1424	.hid_width = 5,
1425	.freq_tbl = ftbl_sdcc1_ice_core_clk_src,
1426	.parent_map = gcc_sdcc1_ice_core_map,
1427	.clkr.hw.init = &(struct clk_init_data) {
1428		.name = "sdcc1_ice_core_clk_src",
1429		.parent_data = gcc_sdcc1_ice_core_data,
1430		.num_parents = ARRAY_SIZE(gcc_sdcc1_ice_core_data),
1431		.ops = &clk_rcg2_ops,
1432	}
1433};
1434
1435static const struct parent_map gcc_sdcc_apps_map[] = {
1436	{ P_XO, 0 },
1437	{ P_GPLL0, 1 },
1438	{ P_GPLL4, 2 },
1439	{ P_GPLL0_DIV2, 4 },
1440};
1441
1442static const struct clk_parent_data gcc_sdcc_apss_data[] = {
1443	{ .fw_name = "xo" },
1444	{ .hw = &gpll0.clkr.hw },
1445	{ .hw = &gpll4.clkr.hw },
1446	{ .hw = &gpll0_early_div.hw },
1447};
1448
1449static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
1450	F(144000, P_XO, 16, 3, 25),
1451	F(400000, P_XO, 12, 1, 4),
1452	F(20000000, P_GPLL0_DIV2, 5, 1, 4),
1453	F(25000000, P_GPLL0_DIV2, 16, 0, 0),
1454	F(50000000, P_GPLL0, 16, 0, 0),
1455	F(100000000, P_GPLL0, 8, 0, 0),
1456	F(177770000, P_GPLL0, 4.5, 0, 0),
1457	F(192000000, P_GPLL4, 6, 0, 0),
1458	F(384000000, P_GPLL4, 3, 0, 0),
1459	{ }
1460};
1461
1462static struct clk_rcg2 sdcc1_apps_clk_src = {
1463	.cmd_rcgr = 0x42004,
1464	.hid_width = 5,
1465	.mnd_width = 8,
1466	.freq_tbl = ftbl_sdcc1_apps_clk_src,
1467	.parent_map = gcc_sdcc_apps_map,
1468	.clkr.hw.init = &(struct clk_init_data) {
1469		.name = "sdcc1_apps_clk_src",
1470		.parent_data = gcc_sdcc_apss_data,
1471		.num_parents = ARRAY_SIZE(gcc_sdcc_apss_data),
1472		.ops = &clk_rcg2_floor_ops,
1473	}
1474};
1475
1476static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
1477	F(144000, P_XO, 16, 3, 25),
1478	F(400000, P_XO, 12, 1, 4),
1479	F(20000000, P_GPLL0_DIV2, 5, 1, 4),
1480	F(25000000, P_GPLL0_DIV2, 16, 0, 0),
1481	F(50000000, P_GPLL0, 16, 0, 0),
1482	F(100000000, P_GPLL0, 8, 0, 0),
1483	F(177770000, P_GPLL0, 4.5, 0, 0),
1484	F(192000000, P_GPLL4, 6, 0, 0),
1485	F(200000000, P_GPLL0, 4, 0, 0),
1486	{ }
1487};
1488
1489static struct clk_rcg2 sdcc2_apps_clk_src = {
1490	.cmd_rcgr = 0x43004,
1491	.hid_width = 5,
1492	.mnd_width = 8,
1493	.freq_tbl = ftbl_sdcc2_apps_clk_src,
1494	.parent_map = gcc_sdcc_apps_map,
1495	.clkr.hw.init = &(struct clk_init_data) {
1496		.name = "sdcc2_apps_clk_src",
1497		.parent_data = gcc_sdcc_apss_data,
1498		.num_parents = ARRAY_SIZE(gcc_sdcc_apss_data),
1499		.ops = &clk_rcg2_floor_ops,
1500	}
1501};
1502
1503static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
1504	F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1505	F(100000000, P_GPLL0, 8, 0, 0),
1506	F(133330000, P_GPLL0, 6, 0, 0),
1507	{ }
1508};
1509
1510static struct clk_rcg2 usb30_master_clk_src = {
1511	.cmd_rcgr = 0x3f00c,
1512	.hid_width = 5,
1513	.freq_tbl = ftbl_usb30_master_clk_src,
1514	.parent_map = gcc_xo_gpll0_gpll0div2_2_map,
1515	.clkr.hw.init = &(struct clk_init_data) {
1516		.name = "usb30_master_clk_src",
1517		.parent_data = gcc_xo_gpll0_gpll0div2_data,
1518		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0div2_data),
1519		.ops = &clk_rcg2_ops,
1520	}
1521};
1522
1523static const struct parent_map gcc_usb30_mock_utmi_map[] = {
1524	{ P_XO, 0 },
1525	{ P_GPLL6, 1 },
1526	{ P_GPLL6_DIV2, 2 },
1527	{ P_GPLL0, 3 },
1528	{ P_GPLL0_DIV2, 4 },
1529};
1530
1531static const struct clk_parent_data gcc_usb30_mock_utmi_data[] = {
1532	{ .fw_name = "xo" },
1533	{ .hw = &gpll6.clkr.hw },
1534	{ .hw = &gpll6_early_div.hw },
1535	{ .hw = &gpll0.clkr.hw },
1536	{ .hw = &gpll0_early_div.hw },
1537};
1538
1539static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
1540	F(19200000, P_XO, 1, 0, 0),
1541	F(60000000, P_GPLL6_DIV2, 9, 1, 1),
1542	{ }
1543};
1544
1545static struct clk_rcg2 usb30_mock_utmi_clk_src = {
1546	.cmd_rcgr = 0x3f020,
1547	.hid_width = 5,
1548	.mnd_width = 8,
1549	.freq_tbl = ftbl_usb30_mock_utmi_clk_src,
1550	.parent_map = gcc_usb30_mock_utmi_map,
1551	.clkr.hw.init = &(struct clk_init_data) {
1552		.name = "usb30_mock_utmi_clk_src",
1553		.parent_data = gcc_usb30_mock_utmi_data,
1554		.num_parents = ARRAY_SIZE(gcc_usb30_mock_utmi_data),
1555		.ops = &clk_rcg2_ops,
1556	}
1557};
1558
1559static const struct parent_map gcc_usb3_aux_map[] = {
1560	{ P_XO, 0 },
1561	{ P_SLEEP_CLK, 6 },
1562};
1563
1564static const struct clk_parent_data gcc_usb3_aux_data[] = {
1565	{ .fw_name = "xo" },
1566	{ .fw_name = "sleep", .name = "sleep" },
1567};
1568
1569static const struct freq_tbl ftbl_usb3_aux_clk_src[] = {
1570	F(19200000, P_XO, 1, 0, 0),
1571	{ }
1572};
1573
1574static struct clk_rcg2 usb3_aux_clk_src = {
1575	.cmd_rcgr = 0x3f05c,
1576	.hid_width = 5,
1577	.mnd_width = 8,
1578	.freq_tbl = ftbl_usb3_aux_clk_src,
1579	.parent_map = gcc_usb3_aux_map,
1580	.clkr.hw.init = &(struct clk_init_data) {
1581		.name = "usb3_aux_clk_src",
1582		.parent_data = gcc_usb3_aux_data,
1583		.num_parents = ARRAY_SIZE(gcc_usb3_aux_data),
1584		.ops = &clk_rcg2_ops,
1585	}
1586};
1587
1588static const struct parent_map gcc_vcodec0_map[] = {
1589	{ P_XO, 0 },
1590	{ P_GPLL0, 1 },
1591	{ P_GPLL6, 2 },
1592	{ P_GPLL2, 3 },
1593	{ P_GPLL0_DIV2, 4 },
1594};
1595
1596static const struct clk_parent_data gcc_vcodec0_data[] = {
1597	{ .fw_name = "xo" },
1598	{ .hw = &gpll0.clkr.hw },
1599	{ .hw = &gpll6.clkr.hw },
1600	{ .hw = &gpll2.clkr.hw },
1601	{ .hw = &gpll0_early_div.hw },
1602};
1603
1604static const struct freq_tbl ftbl_vcodec0_clk_src[] = {
1605	F(114290000, P_GPLL0_DIV2, 3.5, 0, 0),
1606	F(228570000, P_GPLL0, 3.5, 0, 0),
1607	F(310000000, P_GPLL2, 3, 0, 0),
1608	F(360000000, P_GPLL6, 3, 0, 0),
1609	F(400000000, P_GPLL0, 2, 0, 0),
1610	F(465000000, P_GPLL2, 2, 0, 0),
1611	F(540000000, P_GPLL6, 2, 0, 0),
1612	{ }
1613};
1614
1615static struct clk_rcg2 vcodec0_clk_src = {
1616	.cmd_rcgr = 0x4c000,
1617	.hid_width = 5,
1618	.freq_tbl = ftbl_vcodec0_clk_src,
1619	.parent_map = gcc_vcodec0_map,
1620	.clkr.hw.init = &(struct clk_init_data) {
1621		.name = "vcodec0_clk_src",
1622		.parent_data = gcc_vcodec0_data,
1623		.num_parents = ARRAY_SIZE(gcc_vcodec0_data),
1624		.ops = &clk_rcg2_ops,
1625	}
1626};
1627
1628static const struct parent_map gcc_vfe_map[] = {
1629	{ P_XO, 0 },
1630	{ P_GPLL0, 1 },
1631	{ P_GPLL6, 2 },
1632	{ P_GPLL4, 3 },
1633	{ P_GPLL2, 4 },
1634	{ P_GPLL0_DIV2, 5 },
1635};
1636
1637static const struct clk_parent_data gcc_vfe_data[] = {
1638	{ .fw_name = "xo" },
1639	{ .hw = &gpll0.clkr.hw },
1640	{ .hw = &gpll6.clkr.hw },
1641	{ .hw = &gpll4.clkr.hw },
1642	{ .hw = &gpll2.clkr.hw },
1643	{ .hw = &gpll0_early_div.hw },
1644};
1645
1646static const struct freq_tbl ftbl_vfe_clk_src[] = {
1647	F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1648	F(100000000, P_GPLL0_DIV2, 4, 0, 0),
1649	F(133330000, P_GPLL0, 6, 0, 0),
1650	F(160000000, P_GPLL0, 5, 0, 0),
1651	F(200000000, P_GPLL0, 4, 0, 0),
1652	F(266670000, P_GPLL0, 3, 0, 0),
1653	F(310000000, P_GPLL2, 3, 0, 0),
1654	F(400000000, P_GPLL0, 2, 0, 0),
1655	F(465000000, P_GPLL2, 2, 0, 0),
1656	{ }
1657};
1658
1659static struct clk_rcg2 vfe0_clk_src = {
1660	.cmd_rcgr = 0x58000,
1661	.hid_width = 5,
1662	.freq_tbl = ftbl_vfe_clk_src,
1663	.parent_map = gcc_vfe_map,
1664	.clkr.hw.init = &(struct clk_init_data) {
1665		.name = "vfe0_clk_src",
1666		.parent_data = gcc_vfe_data,
1667		.num_parents = ARRAY_SIZE(gcc_vfe_data),
1668		.ops = &clk_rcg2_ops,
1669	}
1670};
1671
1672static struct clk_rcg2 vfe1_clk_src = {
1673	.cmd_rcgr = 0x58054,
1674	.hid_width = 5,
1675	.freq_tbl = ftbl_vfe_clk_src,
1676	.parent_map = gcc_vfe_map,
1677	.clkr.hw.init = &(struct clk_init_data) {
1678		.name = "vfe1_clk_src",
1679		.parent_data = gcc_vfe_data,
1680		.num_parents = ARRAY_SIZE(gcc_vfe_data),
1681		.ops = &clk_rcg2_ops,
1682	}
1683};
1684
1685static const struct parent_map gcc_vsync_map[] = {
1686	{ P_XO, 0 },
1687	{ P_GPLL0, 2 },
1688};
1689
1690static const struct freq_tbl ftbl_vsync_clk_src[] = {
1691	F(19200000, P_XO, 1, 0, 0),
1692	{ }
1693};
1694
1695static struct clk_rcg2 vsync_clk_src = {
1696	.cmd_rcgr = 0x4d02c,
1697	.hid_width = 5,
1698	.freq_tbl = ftbl_vsync_clk_src,
1699	.parent_map = gcc_vsync_map,
1700	.clkr.hw.init = &(struct clk_init_data) {
1701		.name = "vsync_clk_src",
1702		.parent_data = gcc_esc_vsync_data,
1703		.num_parents = ARRAY_SIZE(gcc_esc_vsync_data),
1704		.ops = &clk_rcg2_ops,
1705	}
1706};
1707
1708static struct clk_branch gcc_apc0_droop_detector_gpll0_clk = {
1709	.halt_reg = 0x78004,
1710	.halt_check = BRANCH_HALT,
1711	.clkr = {
1712		.enable_reg = 0x78004,
1713		.enable_mask = BIT(0),
1714		.hw.init = &(struct clk_init_data) {
1715			.name = "gcc_apc0_droop_detector_gpll0_clk",
1716			.parent_hws = (const struct clk_hw*[]){
1717				&apc0_droop_detector_clk_src.clkr.hw,
1718			},
1719			.num_parents = 1,
1720			.ops = &clk_branch2_ops,
1721			.flags = CLK_SET_RATE_PARENT,
1722		}
1723	}
1724};
1725
1726static struct clk_branch gcc_apc1_droop_detector_gpll0_clk = {
1727	.halt_reg = 0x79004,
1728	.halt_check = BRANCH_HALT,
1729	.clkr = {
1730		.enable_reg = 0x79004,
1731		.enable_mask = BIT(0),
1732		.hw.init = &(struct clk_init_data) {
1733			.name = "gcc_apc1_droop_detector_gpll0_clk",
1734			.parent_hws = (const struct clk_hw*[]){
1735				&apc1_droop_detector_clk_src.clkr.hw,
1736			},
1737			.num_parents = 1,
1738			.ops = &clk_branch2_ops,
1739			.flags = CLK_SET_RATE_PARENT,
1740		}
1741	}
1742};
1743
1744static struct clk_branch gcc_apss_ahb_clk = {
1745	.halt_reg = 0x4601c,
1746	.halt_check = BRANCH_HALT_VOTED,
1747	.clkr = {
1748		.enable_reg = 0x45004,
1749		.enable_mask = BIT(14),
1750		.hw.init = &(struct clk_init_data) {
1751			.name = "gcc_apss_ahb_clk",
1752			.parent_hws = (const struct clk_hw*[]){
1753				&apss_ahb_clk_src.clkr.hw,
1754			},
1755			.num_parents = 1,
1756			.ops = &clk_branch2_ops,
1757			.flags = CLK_SET_RATE_PARENT,
1758		}
1759	}
1760};
1761
1762static struct clk_branch gcc_apss_axi_clk = {
1763	.halt_reg = 0x46020,
1764	.halt_check = BRANCH_HALT_VOTED,
1765	.clkr = {
1766		.enable_reg = 0x45004,
1767		.enable_mask = BIT(13),
1768		.hw.init = &(struct clk_init_data) {
1769			.name = "gcc_apss_axi_clk",
1770			.ops = &clk_branch2_ops,
1771		}
1772	}
1773};
1774
1775static struct clk_branch gcc_apss_tcu_async_clk = {
1776	.halt_reg = 0x12018,
1777	.halt_check = BRANCH_HALT_VOTED,
1778	.clkr = {
1779		.enable_reg = 0x4500c,
1780		.enable_mask = BIT(1),
1781		.hw.init = &(struct clk_init_data) {
1782			.name = "gcc_apss_tcu_async_clk",
1783			.ops = &clk_branch2_ops,
1784		}
1785	}
1786};
1787
1788static struct clk_branch gcc_bimc_gfx_clk = {
1789	.halt_reg = 0x59034,
1790	.halt_check = BRANCH_HALT,
1791	.clkr = {
1792		.enable_reg = 0x59034,
1793		.enable_mask = BIT(0),
1794		.hw.init = &(struct clk_init_data) {
1795			.name = "gcc_bimc_gfx_clk",
1796			.ops = &clk_branch2_ops,
1797		}
1798	}
1799};
1800
1801static struct clk_branch gcc_bimc_gpu_clk = {
1802	.halt_reg = 0x59030,
1803	.halt_check = BRANCH_HALT,
1804	.clkr = {
1805		.enable_reg = 0x59030,
1806		.enable_mask = BIT(0),
1807		.hw.init = &(struct clk_init_data) {
1808			.name = "gcc_bimc_gpu_clk",
1809			.ops = &clk_branch2_ops,
1810		}
1811	}
1812};
1813
1814static struct clk_branch gcc_blsp1_ahb_clk = {
1815	.halt_reg = 0x01008,
1816	.halt_check = BRANCH_HALT_VOTED,
1817	.clkr = {
1818		.enable_reg = 0x45004,
1819		.enable_mask = BIT(10),
1820		.hw.init = &(struct clk_init_data) {
1821			.name = "gcc_blsp1_ahb_clk",
1822			.ops = &clk_branch2_ops,
1823		}
1824	}
1825};
1826
1827static struct clk_branch gcc_blsp2_ahb_clk = {
1828	.halt_reg = 0x0b008,
1829	.halt_check = BRANCH_HALT_VOTED,
1830	.clkr = {
1831		.enable_reg = 0x45004,
1832		.enable_mask = BIT(20),
1833		.hw.init = &(struct clk_init_data) {
1834			.name = "gcc_blsp2_ahb_clk",
1835			.ops = &clk_branch2_ops,
1836		}
1837	}
1838};
1839
1840static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1841	.halt_reg = 0x02008,
1842	.halt_check = BRANCH_HALT,
1843	.clkr = {
1844		.enable_reg = 0x02008,
1845		.enable_mask = BIT(0),
1846		.hw.init = &(struct clk_init_data) {
1847			.name = "gcc_blsp1_qup1_i2c_apps_clk",
1848			.parent_hws = (const struct clk_hw*[]){
1849				&blsp1_qup1_i2c_apps_clk_src.clkr.hw,
1850			},
1851			.num_parents = 1,
1852			.ops = &clk_branch2_ops,
1853			.flags = CLK_SET_RATE_PARENT,
1854		}
1855	}
1856};
1857
1858static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1859	.halt_reg = 0x03010,
1860	.halt_check = BRANCH_HALT,
1861	.clkr = {
1862		.enable_reg = 0x03010,
1863		.enable_mask = BIT(0),
1864		.hw.init = &(struct clk_init_data) {
1865			.name = "gcc_blsp1_qup2_i2c_apps_clk",
1866			.parent_hws = (const struct clk_hw*[]){
1867				&blsp1_qup2_i2c_apps_clk_src.clkr.hw,
1868			},
1869			.num_parents = 1,
1870			.ops = &clk_branch2_ops,
1871			.flags = CLK_SET_RATE_PARENT,
1872		}
1873	}
1874};
1875
1876static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1877	.halt_reg = 0x04020,
1878	.halt_check = BRANCH_HALT,
1879	.clkr = {
1880		.enable_reg = 0x04020,
1881		.enable_mask = BIT(0),
1882		.hw.init = &(struct clk_init_data) {
1883			.name = "gcc_blsp1_qup3_i2c_apps_clk",
1884			.parent_hws = (const struct clk_hw*[]){
1885				&blsp1_qup3_i2c_apps_clk_src.clkr.hw,
1886			},
1887			.num_parents = 1,
1888			.ops = &clk_branch2_ops,
1889			.flags = CLK_SET_RATE_PARENT,
1890		}
1891	}
1892};
1893
1894static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1895	.halt_reg = 0x05020,
1896	.halt_check = BRANCH_HALT,
1897	.clkr = {
1898		.enable_reg = 0x05020,
1899		.enable_mask = BIT(0),
1900		.hw.init = &(struct clk_init_data) {
1901			.name = "gcc_blsp1_qup4_i2c_apps_clk",
1902			.parent_hws = (const struct clk_hw*[]){
1903				&blsp1_qup4_i2c_apps_clk_src.clkr.hw,
1904			},
1905			.num_parents = 1,
1906			.ops = &clk_branch2_ops,
1907			.flags = CLK_SET_RATE_PARENT,
1908		}
1909	}
1910};
1911
1912static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1913	.halt_reg = 0x0c008,
1914	.halt_check = BRANCH_HALT,
1915	.clkr = {
1916		.enable_reg = 0x0c008,
1917		.enable_mask = BIT(0),
1918		.hw.init = &(struct clk_init_data) {
1919			.name = "gcc_blsp2_qup1_i2c_apps_clk",
1920			.parent_hws = (const struct clk_hw*[]){
1921				&blsp2_qup1_i2c_apps_clk_src.clkr.hw,
1922			},
1923			.num_parents = 1,
1924			.ops = &clk_branch2_ops,
1925			.flags = CLK_SET_RATE_PARENT,
1926		}
1927	}
1928};
1929
1930static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1931	.halt_reg = 0x0d010,
1932	.halt_check = BRANCH_HALT,
1933	.clkr = {
1934		.enable_reg = 0x0d010,
1935		.enable_mask = BIT(0),
1936		.hw.init = &(struct clk_init_data) {
1937			.name = "gcc_blsp2_qup2_i2c_apps_clk",
1938			.parent_hws = (const struct clk_hw*[]){
1939				&blsp2_qup2_i2c_apps_clk_src.clkr.hw,
1940			},
1941			.num_parents = 1,
1942			.ops = &clk_branch2_ops,
1943			.flags = CLK_SET_RATE_PARENT,
1944		}
1945	}
1946};
1947
1948static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1949	.halt_reg = 0x0f020,
1950	.halt_check = BRANCH_HALT,
1951	.clkr = {
1952		.enable_reg = 0x0f020,
1953		.enable_mask = BIT(0),
1954		.hw.init = &(struct clk_init_data) {
1955			.name = "gcc_blsp2_qup3_i2c_apps_clk",
1956			.parent_hws = (const struct clk_hw*[]){
1957				&blsp2_qup3_i2c_apps_clk_src.clkr.hw,
1958			},
1959			.num_parents = 1,
1960			.ops = &clk_branch2_ops,
1961			.flags = CLK_SET_RATE_PARENT,
1962		}
1963	}
1964};
1965
1966static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1967	.halt_reg = 0x18020,
1968	.halt_check = BRANCH_HALT,
1969	.clkr = {
1970		.enable_reg = 0x18020,
1971		.enable_mask = BIT(0),
1972		.hw.init = &(struct clk_init_data) {
1973			.name = "gcc_blsp2_qup4_i2c_apps_clk",
1974			.parent_hws = (const struct clk_hw*[]){
1975				&blsp2_qup4_i2c_apps_clk_src.clkr.hw,
1976			},
1977			.num_parents = 1,
1978			.ops = &clk_branch2_ops,
1979			.flags = CLK_SET_RATE_PARENT,
1980		}
1981	}
1982};
1983
1984static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1985	.halt_reg = 0x02004,
1986	.halt_check = BRANCH_HALT,
1987	.clkr = {
1988		.enable_reg = 0x02004,
1989		.enable_mask = BIT(0),
1990		.hw.init = &(struct clk_init_data) {
1991			.name = "gcc_blsp1_qup1_spi_apps_clk",
1992			.parent_hws = (const struct clk_hw*[]){
1993				&blsp1_qup1_spi_apps_clk_src.clkr.hw,
1994			},
1995			.num_parents = 1,
1996			.ops = &clk_branch2_ops,
1997			.flags = CLK_SET_RATE_PARENT,
1998		}
1999	}
2000};
2001
2002static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
2003	.halt_reg = 0x0300c,
2004	.halt_check = BRANCH_HALT,
2005	.clkr = {
2006		.enable_reg = 0x0300c,
2007		.enable_mask = BIT(0),
2008		.hw.init = &(struct clk_init_data) {
2009			.name = "gcc_blsp1_qup2_spi_apps_clk",
2010			.parent_hws = (const struct clk_hw*[]){
2011				&blsp1_qup2_spi_apps_clk_src.clkr.hw,
2012			},
2013			.num_parents = 1,
2014			.ops = &clk_branch2_ops,
2015			.flags = CLK_SET_RATE_PARENT,
2016		}
2017	}
2018};
2019
2020static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
2021	.halt_reg = 0x0401c,
2022	.halt_check = BRANCH_HALT,
2023	.clkr = {
2024		.enable_reg = 0x0401c,
2025		.enable_mask = BIT(0),
2026		.hw.init = &(struct clk_init_data) {
2027			.name = "gcc_blsp1_qup3_spi_apps_clk",
2028			.parent_hws = (const struct clk_hw*[]){
2029				&blsp1_qup3_spi_apps_clk_src.clkr.hw,
2030			},
2031			.num_parents = 1,
2032			.ops = &clk_branch2_ops,
2033			.flags = CLK_SET_RATE_PARENT,
2034		}
2035	}
2036};
2037
2038static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
2039	.halt_reg = 0x0501c,
2040	.halt_check = BRANCH_HALT,
2041	.clkr = {
2042		.enable_reg = 0x0501c,
2043		.enable_mask = BIT(0),
2044		.hw.init = &(struct clk_init_data) {
2045			.name = "gcc_blsp1_qup4_spi_apps_clk",
2046			.parent_hws = (const struct clk_hw*[]){
2047				&blsp1_qup4_spi_apps_clk_src.clkr.hw,
2048			},
2049			.num_parents = 1,
2050			.ops = &clk_branch2_ops,
2051			.flags = CLK_SET_RATE_PARENT,
2052		}
2053	}
2054};
2055
2056static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
2057	.halt_reg = 0x0c004,
2058	.halt_check = BRANCH_HALT,
2059	.clkr = {
2060		.enable_reg = 0x0c004,
2061		.enable_mask = BIT(0),
2062		.hw.init = &(struct clk_init_data) {
2063			.name = "gcc_blsp2_qup1_spi_apps_clk",
2064			.parent_hws = (const struct clk_hw*[]){
2065				&blsp2_qup1_spi_apps_clk_src.clkr.hw,
2066			},
2067			.num_parents = 1,
2068			.ops = &clk_branch2_ops,
2069			.flags = CLK_SET_RATE_PARENT,
2070		}
2071	}
2072};
2073
2074static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
2075	.halt_reg = 0x0d00c,
2076	.halt_check = BRANCH_HALT,
2077	.clkr = {
2078		.enable_reg = 0x0d00c,
2079		.enable_mask = BIT(0),
2080		.hw.init = &(struct clk_init_data) {
2081			.name = "gcc_blsp2_qup2_spi_apps_clk",
2082			.parent_hws = (const struct clk_hw*[]){
2083				&blsp2_qup2_spi_apps_clk_src.clkr.hw,
2084			},
2085			.num_parents = 1,
2086			.ops = &clk_branch2_ops,
2087			.flags = CLK_SET_RATE_PARENT,
2088		}
2089	}
2090};
2091
2092static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
2093	.halt_reg = 0x0f01c,
2094	.halt_check = BRANCH_HALT,
2095	.clkr = {
2096		.enable_reg = 0x0f01c,
2097		.enable_mask = BIT(0),
2098		.hw.init = &(struct clk_init_data) {
2099			.name = "gcc_blsp2_qup3_spi_apps_clk",
2100			.parent_hws = (const struct clk_hw*[]){
2101				&blsp2_qup3_spi_apps_clk_src.clkr.hw,
2102			},
2103			.num_parents = 1,
2104			.ops = &clk_branch2_ops,
2105			.flags = CLK_SET_RATE_PARENT,
2106		}
2107	}
2108};
2109
2110static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
2111	.halt_reg = 0x1801c,
2112	.halt_check = BRANCH_HALT,
2113	.clkr = {
2114		.enable_reg = 0x1801c,
2115		.enable_mask = BIT(0),
2116		.hw.init = &(struct clk_init_data) {
2117			.name = "gcc_blsp2_qup4_spi_apps_clk",
2118			.parent_hws = (const struct clk_hw*[]){
2119				&blsp2_qup4_spi_apps_clk_src.clkr.hw,
2120			},
2121			.num_parents = 1,
2122			.ops = &clk_branch2_ops,
2123			.flags = CLK_SET_RATE_PARENT,
2124		}
2125	}
2126};
2127
2128static struct clk_branch gcc_blsp1_uart1_apps_clk = {
2129	.halt_reg = 0x0203c,
2130	.halt_check = BRANCH_HALT,
2131	.clkr = {
2132		.enable_reg = 0x0203c,
2133		.enable_mask = BIT(0),
2134		.hw.init = &(struct clk_init_data) {
2135			.name = "gcc_blsp1_uart1_apps_clk",
2136			.parent_hws = (const struct clk_hw*[]){
2137				&blsp1_uart1_apps_clk_src.clkr.hw,
2138			},
2139			.num_parents = 1,
2140			.ops = &clk_branch2_ops,
2141			.flags = CLK_SET_RATE_PARENT,
2142		}
2143	}
2144};
2145
2146static struct clk_branch gcc_blsp1_uart2_apps_clk = {
2147	.halt_reg = 0x0302c,
2148	.halt_check = BRANCH_HALT,
2149	.clkr = {
2150		.enable_reg = 0x0302c,
2151		.enable_mask = BIT(0),
2152		.hw.init = &(struct clk_init_data) {
2153			.name = "gcc_blsp1_uart2_apps_clk",
2154			.parent_hws = (const struct clk_hw*[]){
2155				&blsp1_uart2_apps_clk_src.clkr.hw,
2156			},
2157			.num_parents = 1,
2158			.ops = &clk_branch2_ops,
2159			.flags = CLK_SET_RATE_PARENT,
2160		}
2161	}
2162};
2163
2164static struct clk_branch gcc_blsp2_uart1_apps_clk = {
2165	.halt_reg = 0x0c03c,
2166	.halt_check = BRANCH_HALT,
2167	.clkr = {
2168		.enable_reg = 0x0c03c,
2169		.enable_mask = BIT(0),
2170		.hw.init = &(struct clk_init_data) {
2171			.name = "gcc_blsp2_uart1_apps_clk",
2172			.parent_hws = (const struct clk_hw*[]){
2173				&blsp2_uart1_apps_clk_src.clkr.hw,
2174			},
2175			.num_parents = 1,
2176			.ops = &clk_branch2_ops,
2177			.flags = CLK_SET_RATE_PARENT,
2178		}
2179	}
2180};
2181
2182static struct clk_branch gcc_blsp2_uart2_apps_clk = {
2183	.halt_reg = 0x0d02c,
2184	.halt_check = BRANCH_HALT,
2185	.clkr = {
2186		.enable_reg = 0x0d02c,
2187		.enable_mask = BIT(0),
2188		.hw.init = &(struct clk_init_data) {
2189			.name = "gcc_blsp2_uart2_apps_clk",
2190			.parent_hws = (const struct clk_hw*[]){
2191				&blsp2_uart2_apps_clk_src.clkr.hw,
2192			},
2193			.num_parents = 1,
2194			.ops = &clk_branch2_ops,
2195			.flags = CLK_SET_RATE_PARENT,
2196		}
2197	}
2198};
2199
2200static struct clk_branch gcc_boot_rom_ahb_clk = {
2201	.halt_reg = 0x1300c,
2202	.halt_check = BRANCH_HALT_VOTED,
2203	.clkr = {
2204		.enable_reg = 0x45004,
2205		.enable_mask = BIT(7),
2206		.hw.init = &(struct clk_init_data) {
2207			.name = "gcc_boot_rom_ahb_clk",
2208			.ops = &clk_branch2_ops,
2209		}
2210	}
2211};
2212
2213static struct clk_branch gcc_camss_ahb_clk = {
2214	.halt_reg = 0x56004,
2215	.halt_check = BRANCH_HALT,
2216	.clkr = {
2217		.enable_reg = 0x56004,
2218		.enable_mask = BIT(0),
2219		.hw.init = &(struct clk_init_data) {
2220			.name = "gcc_camss_ahb_clk",
2221			.ops = &clk_branch2_ops,
2222		}
2223	}
2224};
2225
2226static struct clk_branch gcc_camss_cci_ahb_clk = {
2227	.halt_reg = 0x5101c,
2228	.halt_check = BRANCH_HALT,
2229	.clkr = {
2230		.enable_reg = 0x5101c,
2231		.enable_mask = BIT(0),
2232		.hw.init = &(struct clk_init_data) {
2233			.name = "gcc_camss_cci_ahb_clk",
2234			.parent_hws = (const struct clk_hw*[]){
2235				&camss_top_ahb_clk_src.clkr.hw,
2236			},
2237			.num_parents = 1,
2238			.ops = &clk_branch2_ops,
2239			.flags = CLK_SET_RATE_PARENT,
2240		}
2241	}
2242};
2243
2244static struct clk_branch gcc_camss_cci_clk = {
2245	.halt_reg = 0x51018,
2246	.halt_check = BRANCH_HALT,
2247	.clkr = {
2248		.enable_reg = 0x51018,
2249		.enable_mask = BIT(0),
2250		.hw.init = &(struct clk_init_data) {
2251			.name = "gcc_camss_cci_clk",
2252			.parent_hws = (const struct clk_hw*[]){
2253				&cci_clk_src.clkr.hw,
2254			},
2255			.num_parents = 1,
2256			.ops = &clk_branch2_ops,
2257			.flags = CLK_SET_RATE_PARENT,
2258		}
2259	}
2260};
2261
2262static struct clk_branch gcc_camss_cpp_ahb_clk = {
2263	.halt_reg = 0x58040,
2264	.halt_check = BRANCH_HALT,
2265	.clkr = {
2266		.enable_reg = 0x58040,
2267		.enable_mask = BIT(0),
2268		.hw.init = &(struct clk_init_data) {
2269			.name = "gcc_camss_cpp_ahb_clk",
2270			.parent_hws = (const struct clk_hw*[]){
2271				&camss_top_ahb_clk_src.clkr.hw,
2272			},
2273			.num_parents = 1,
2274			.ops = &clk_branch2_ops,
2275			.flags = CLK_SET_RATE_PARENT,
2276		}
2277	}
2278};
2279
2280static struct clk_branch gcc_camss_cpp_axi_clk = {
2281	.halt_reg = 0x58064,
2282	.halt_check = BRANCH_HALT,
2283	.clkr = {
2284		.enable_reg = 0x58064,
2285		.enable_mask = BIT(0),
2286		.hw.init = &(struct clk_init_data) {
2287			.name = "gcc_camss_cpp_axi_clk",
2288			.ops = &clk_branch2_ops,
2289		}
2290	}
2291};
2292
2293static struct clk_branch gcc_camss_cpp_clk = {
2294	.halt_reg = 0x5803c,
2295	.halt_check = BRANCH_HALT,
2296	.clkr = {
2297		.enable_reg = 0x5803c,
2298		.enable_mask = BIT(0),
2299		.hw.init = &(struct clk_init_data) {
2300			.name = "gcc_camss_cpp_clk",
2301			.parent_hws = (const struct clk_hw*[]){
2302				&cpp_clk_src.clkr.hw,
2303			},
2304			.num_parents = 1,
2305			.ops = &clk_branch2_ops,
2306			.flags = CLK_SET_RATE_PARENT,
2307		}
2308	}
2309};
2310
2311static struct clk_branch gcc_camss_csi0_ahb_clk = {
2312	.halt_reg = 0x4e040,
2313	.halt_check = BRANCH_HALT,
2314	.clkr = {
2315		.enable_reg = 0x4e040,
2316		.enable_mask = BIT(0),
2317		.hw.init = &(struct clk_init_data) {
2318			.name = "gcc_camss_csi0_ahb_clk",
2319			.parent_hws = (const struct clk_hw*[]){
2320				&camss_top_ahb_clk_src.clkr.hw,
2321			},
2322			.num_parents = 1,
2323			.ops = &clk_branch2_ops,
2324			.flags = CLK_SET_RATE_PARENT,
2325		}
2326	}
2327};
2328
2329static struct clk_branch gcc_camss_csi1_ahb_clk = {
2330	.halt_reg = 0x4f040,
2331	.halt_check = BRANCH_HALT,
2332	.clkr = {
2333		.enable_reg = 0x4f040,
2334		.enable_mask = BIT(0),
2335		.hw.init = &(struct clk_init_data) {
2336			.name = "gcc_camss_csi1_ahb_clk",
2337			.parent_hws = (const struct clk_hw*[]){
2338				&camss_top_ahb_clk_src.clkr.hw,
2339			},
2340			.num_parents = 1,
2341			.ops = &clk_branch2_ops,
2342			.flags = CLK_SET_RATE_PARENT,
2343		}
2344	}
2345};
2346
2347static struct clk_branch gcc_camss_csi2_ahb_clk = {
2348	.halt_reg = 0x3c040,
2349	.halt_check = BRANCH_HALT,
2350	.clkr = {
2351		.enable_reg = 0x3c040,
2352		.enable_mask = BIT(0),
2353		.hw.init = &(struct clk_init_data) {
2354			.name = "gcc_camss_csi2_ahb_clk",
2355			.parent_hws = (const struct clk_hw*[]){
2356				&camss_top_ahb_clk_src.clkr.hw,
2357			},
2358			.num_parents = 1,
2359			.ops = &clk_branch2_ops,
2360			.flags = CLK_SET_RATE_PARENT,
2361		}
2362	}
2363};
2364
2365static struct clk_branch gcc_camss_csi0_clk = {
2366	.halt_reg = 0x4e03c,
2367	.halt_check = BRANCH_HALT,
2368	.clkr = {
2369		.enable_reg = 0x4e03c,
2370		.enable_mask = BIT(0),
2371		.hw.init = &(struct clk_init_data) {
2372			.name = "gcc_camss_csi0_clk",
2373			.parent_hws = (const struct clk_hw*[]){
2374				&csi0_clk_src.clkr.hw,
2375			},
2376			.num_parents = 1,
2377			.ops = &clk_branch2_ops,
2378			.flags = CLK_SET_RATE_PARENT,
2379		}
2380	}
2381};
2382
2383static struct clk_branch gcc_camss_csi1_clk = {
2384	.halt_reg = 0x4f03c,
2385	.halt_check = BRANCH_HALT,
2386	.clkr = {
2387		.enable_reg = 0x4f03c,
2388		.enable_mask = BIT(0),
2389		.hw.init = &(struct clk_init_data) {
2390			.name = "gcc_camss_csi1_clk",
2391			.parent_hws = (const struct clk_hw*[]){
2392				&csi1_clk_src.clkr.hw,
2393			},
2394			.num_parents = 1,
2395			.ops = &clk_branch2_ops,
2396			.flags = CLK_SET_RATE_PARENT,
2397		}
2398	}
2399};
2400
2401static struct clk_branch gcc_camss_csi2_clk = {
2402	.halt_reg = 0x3c03c,
2403	.halt_check = BRANCH_HALT,
2404	.clkr = {
2405		.enable_reg = 0x3c03c,
2406		.enable_mask = BIT(0),
2407		.hw.init = &(struct clk_init_data) {
2408			.name = "gcc_camss_csi2_clk",
2409			.parent_hws = (const struct clk_hw*[]){
2410				&csi2_clk_src.clkr.hw,
2411			},
2412			.num_parents = 1,
2413			.ops = &clk_branch2_ops,
2414			.flags = CLK_SET_RATE_PARENT,
2415		}
2416	}
2417};
2418
2419static struct clk_branch gcc_camss_csi0_csiphy_3p_clk = {
2420	.halt_reg = 0x58090,
2421	.halt_check = BRANCH_HALT,
2422	.clkr = {
2423		.enable_reg = 0x58090,
2424		.enable_mask = BIT(0),
2425		.hw.init = &(struct clk_init_data) {
2426			.name = "gcc_camss_csi0_csiphy_3p_clk",
2427			.parent_hws = (const struct clk_hw*[]){
2428				&csi0p_clk_src.clkr.hw,
2429			},
2430			.num_parents = 1,
2431			.ops = &clk_branch2_ops,
2432			.flags = CLK_SET_RATE_PARENT,
2433		}
2434	}
2435};
2436
2437static struct clk_branch gcc_camss_csi1_csiphy_3p_clk = {
2438	.halt_reg = 0x580a0,
2439	.halt_check = BRANCH_HALT,
2440	.clkr = {
2441		.enable_reg = 0x580a0,
2442		.enable_mask = BIT(0),
2443		.hw.init = &(struct clk_init_data) {
2444			.name = "gcc_camss_csi1_csiphy_3p_clk",
2445			.parent_hws = (const struct clk_hw*[]){
2446				&csi1p_clk_src.clkr.hw,
2447			},
2448			.num_parents = 1,
2449			.ops = &clk_branch2_ops,
2450			.flags = CLK_SET_RATE_PARENT,
2451		}
2452	}
2453};
2454
2455static struct clk_branch gcc_camss_csi2_csiphy_3p_clk = {
2456	.halt_reg = 0x580b0,
2457	.halt_check = BRANCH_HALT,
2458	.clkr = {
2459		.enable_reg = 0x580b0,
2460		.enable_mask = BIT(0),
2461		.hw.init = &(struct clk_init_data) {
2462			.name = "gcc_camss_csi2_csiphy_3p_clk",
2463			.parent_hws = (const struct clk_hw*[]){
2464				&csi2p_clk_src.clkr.hw,
2465			},
2466			.num_parents = 1,
2467			.ops = &clk_branch2_ops,
2468			.flags = CLK_SET_RATE_PARENT,
2469		}
2470	}
2471};
2472
2473static struct clk_branch gcc_camss_csi0phy_clk = {
2474	.halt_reg = 0x4e048,
2475	.halt_check = BRANCH_HALT,
2476	.clkr = {
2477		.enable_reg = 0x4e048,
2478		.enable_mask = BIT(0),
2479		.hw.init = &(struct clk_init_data) {
2480			.name = "gcc_camss_csi0phy_clk",
2481			.parent_hws = (const struct clk_hw*[]){
2482				&csi0_clk_src.clkr.hw,
2483			},
2484			.num_parents = 1,
2485			.ops = &clk_branch2_ops,
2486			.flags = CLK_SET_RATE_PARENT,
2487		}
2488	}
2489};
2490
2491static struct clk_branch gcc_camss_csi1phy_clk = {
2492	.halt_reg = 0x4f048,
2493	.halt_check = BRANCH_HALT,
2494	.clkr = {
2495		.enable_reg = 0x4f048,
2496		.enable_mask = BIT(0),
2497		.hw.init = &(struct clk_init_data) {
2498			.name = "gcc_camss_csi1phy_clk",
2499			.parent_hws = (const struct clk_hw*[]){
2500				&csi1_clk_src.clkr.hw,
2501			},
2502			.num_parents = 1,
2503			.ops = &clk_branch2_ops,
2504			.flags = CLK_SET_RATE_PARENT,
2505		}
2506	}
2507};
2508
2509static struct clk_branch gcc_camss_csi2phy_clk = {
2510	.halt_reg = 0x3c048,
2511	.halt_check = BRANCH_HALT,
2512	.clkr = {
2513		.enable_reg = 0x3c048,
2514		.enable_mask = BIT(0),
2515		.hw.init = &(struct clk_init_data) {
2516			.name = "gcc_camss_csi2phy_clk",
2517			.parent_hws = (const struct clk_hw*[]){
2518				&csi2_clk_src.clkr.hw,
2519			},
2520			.num_parents = 1,
2521			.ops = &clk_branch2_ops,
2522			.flags = CLK_SET_RATE_PARENT,
2523		}
2524	}
2525};
2526
2527static struct clk_branch gcc_camss_csi0phytimer_clk = {
2528	.halt_reg = 0x4e01c,
2529	.halt_check = BRANCH_HALT,
2530	.clkr = {
2531		.enable_reg = 0x4e01c,
2532		.enable_mask = BIT(0),
2533		.hw.init = &(struct clk_init_data) {
2534			.name = "gcc_camss_csi0phytimer_clk",
2535			.parent_hws = (const struct clk_hw*[]){
2536				&csi0phytimer_clk_src.clkr.hw,
2537			},
2538			.num_parents = 1,
2539			.ops = &clk_branch2_ops,
2540			.flags = CLK_SET_RATE_PARENT,
2541		}
2542	}
2543};
2544
2545static struct clk_branch gcc_camss_csi1phytimer_clk = {
2546	.halt_reg = 0x4f01c,
2547	.halt_check = BRANCH_HALT,
2548	.clkr = {
2549		.enable_reg = 0x4f01c,
2550		.enable_mask = BIT(0),
2551		.hw.init = &(struct clk_init_data) {
2552			.name = "gcc_camss_csi1phytimer_clk",
2553			.parent_hws = (const struct clk_hw*[]){
2554				&csi1phytimer_clk_src.clkr.hw,
2555			},
2556			.num_parents = 1,
2557			.ops = &clk_branch2_ops,
2558			.flags = CLK_SET_RATE_PARENT,
2559		}
2560	}
2561};
2562
2563static struct clk_branch gcc_camss_csi2phytimer_clk = {
2564	.halt_reg = 0x4f068,
2565	.halt_check = BRANCH_HALT,
2566	.clkr = {
2567		.enable_reg = 0x4f068,
2568		.enable_mask = BIT(0),
2569		.hw.init = &(struct clk_init_data) {
2570			.name = "gcc_camss_csi2phytimer_clk",
2571			.parent_hws = (const struct clk_hw*[]){
2572				&csi2phytimer_clk_src.clkr.hw,
2573			},
2574			.num_parents = 1,
2575			.ops = &clk_branch2_ops,
2576			.flags = CLK_SET_RATE_PARENT,
2577		}
2578	}
2579};
2580
2581static struct clk_branch gcc_camss_csi0pix_clk = {
2582	.halt_reg = 0x4e058,
2583	.halt_check = BRANCH_HALT,
2584	.clkr = {
2585		.enable_reg = 0x4e058,
2586		.enable_mask = BIT(0),
2587		.hw.init = &(struct clk_init_data) {
2588			.name = "gcc_camss_csi0pix_clk",
2589			.parent_hws = (const struct clk_hw*[]){
2590				&csi0_clk_src.clkr.hw,
2591			},
2592			.num_parents = 1,
2593			.ops = &clk_branch2_ops,
2594			.flags = CLK_SET_RATE_PARENT,
2595		}
2596	}
2597};
2598
2599static struct clk_branch gcc_camss_csi1pix_clk = {
2600	.halt_reg = 0x4f058,
2601	.halt_check = BRANCH_HALT,
2602	.clkr = {
2603		.enable_reg = 0x4f058,
2604		.enable_mask = BIT(0),
2605		.hw.init = &(struct clk_init_data) {
2606			.name = "gcc_camss_csi1pix_clk",
2607			.parent_hws = (const struct clk_hw*[]){
2608				&csi1_clk_src.clkr.hw,
2609			},
2610			.num_parents = 1,
2611			.ops = &clk_branch2_ops,
2612			.flags = CLK_SET_RATE_PARENT,
2613		}
2614	}
2615};
2616
2617static struct clk_branch gcc_camss_csi2pix_clk = {
2618	.halt_reg = 0x3c058,
2619	.halt_check = BRANCH_HALT,
2620	.clkr = {
2621		.enable_reg = 0x3c058,
2622		.enable_mask = BIT(0),
2623		.hw.init = &(struct clk_init_data) {
2624			.name = "gcc_camss_csi2pix_clk",
2625			.parent_hws = (const struct clk_hw*[]){
2626				&csi2_clk_src.clkr.hw,
2627			},
2628			.num_parents = 1,
2629			.ops = &clk_branch2_ops,
2630			.flags = CLK_SET_RATE_PARENT,
2631		}
2632	}
2633};
2634
2635static struct clk_branch gcc_camss_csi0rdi_clk = {
2636	.halt_reg = 0x4e050,
2637	.halt_check = BRANCH_HALT,
2638	.clkr = {
2639		.enable_reg = 0x4e050,
2640		.enable_mask = BIT(0),
2641		.hw.init = &(struct clk_init_data) {
2642			.name = "gcc_camss_csi0rdi_clk",
2643			.parent_hws = (const struct clk_hw*[]){
2644				&csi0_clk_src.clkr.hw,
2645			},
2646			.num_parents = 1,
2647			.ops = &clk_branch2_ops,
2648			.flags = CLK_SET_RATE_PARENT,
2649		}
2650	}
2651};
2652
2653static struct clk_branch gcc_camss_csi1rdi_clk = {
2654	.halt_reg = 0x4f050,
2655	.halt_check = BRANCH_HALT,
2656	.clkr = {
2657		.enable_reg = 0x4f050,
2658		.enable_mask = BIT(0),
2659		.hw.init = &(struct clk_init_data) {
2660			.name = "gcc_camss_csi1rdi_clk",
2661			.parent_hws = (const struct clk_hw*[]){
2662				&csi1_clk_src.clkr.hw,
2663			},
2664			.num_parents = 1,
2665			.ops = &clk_branch2_ops,
2666			.flags = CLK_SET_RATE_PARENT,
2667		}
2668	}
2669};
2670
2671static struct clk_branch gcc_camss_csi2rdi_clk = {
2672	.halt_reg = 0x3c050,
2673	.halt_check = BRANCH_HALT,
2674	.clkr = {
2675		.enable_reg = 0x3c050,
2676		.enable_mask = BIT(0),
2677		.hw.init = &(struct clk_init_data) {
2678			.name = "gcc_camss_csi2rdi_clk",
2679			.parent_hws = (const struct clk_hw*[]){
2680				&csi2_clk_src.clkr.hw,
2681			},
2682			.num_parents = 1,
2683			.ops = &clk_branch2_ops,
2684			.flags = CLK_SET_RATE_PARENT,
2685		}
2686	}
2687};
2688
2689static struct clk_branch gcc_camss_csi_vfe0_clk = {
2690	.halt_reg = 0x58050,
2691	.halt_check = BRANCH_HALT,
2692	.clkr = {
2693		.enable_reg = 0x58050,
2694		.enable_mask = BIT(0),
2695		.hw.init = &(struct clk_init_data) {
2696			.name = "gcc_camss_csi_vfe0_clk",
2697			.parent_hws = (const struct clk_hw*[]){
2698				&vfe0_clk_src.clkr.hw,
2699			},
2700			.num_parents = 1,
2701			.ops = &clk_branch2_ops,
2702			.flags = CLK_SET_RATE_PARENT,
2703		}
2704	}
2705};
2706
2707static struct clk_branch gcc_camss_csi_vfe1_clk = {
2708	.halt_reg = 0x58074,
2709	.halt_check = BRANCH_HALT,
2710	.clkr = {
2711		.enable_reg = 0x58074,
2712		.enable_mask = BIT(0),
2713		.hw.init = &(struct clk_init_data) {
2714			.name = "gcc_camss_csi_vfe1_clk",
2715			.parent_hws = (const struct clk_hw*[]){
2716				&vfe1_clk_src.clkr.hw,
2717			},
2718			.num_parents = 1,
2719			.ops = &clk_branch2_ops,
2720			.flags = CLK_SET_RATE_PARENT,
2721		}
2722	}
2723};
2724
2725static struct clk_branch gcc_camss_gp0_clk = {
2726	.halt_reg = 0x54018,
2727	.halt_check = BRANCH_HALT,
2728	.clkr = {
2729		.enable_reg = 0x54018,
2730		.enable_mask = BIT(0),
2731		.hw.init = &(struct clk_init_data) {
2732			.name = "gcc_camss_gp0_clk",
2733			.parent_hws = (const struct clk_hw*[]){
2734				&camss_gp0_clk_src.clkr.hw,
2735			},
2736			.num_parents = 1,
2737			.ops = &clk_branch2_ops,
2738			.flags = CLK_SET_RATE_PARENT,
2739		}
2740	}
2741};
2742
2743static struct clk_branch gcc_camss_gp1_clk = {
2744	.halt_reg = 0x55018,
2745	.halt_check = BRANCH_HALT,
2746	.clkr = {
2747		.enable_reg = 0x55018,
2748		.enable_mask = BIT(0),
2749		.hw.init = &(struct clk_init_data) {
2750			.name = "gcc_camss_gp1_clk",
2751			.parent_hws = (const struct clk_hw*[]){
2752				&camss_gp1_clk_src.clkr.hw,
2753			},
2754			.num_parents = 1,
2755			.ops = &clk_branch2_ops,
2756			.flags = CLK_SET_RATE_PARENT,
2757		}
2758	}
2759};
2760
2761static struct clk_branch gcc_camss_ispif_ahb_clk = {
2762	.halt_reg = 0x50004,
2763	.halt_check = BRANCH_HALT,
2764	.clkr = {
2765		.enable_reg = 0x50004,
2766		.enable_mask = BIT(0),
2767		.hw.init = &(struct clk_init_data) {
2768			.name = "gcc_camss_ispif_ahb_clk",
2769			.parent_hws = (const struct clk_hw*[]){
2770				&camss_top_ahb_clk_src.clkr.hw,
2771			},
2772			.num_parents = 1,
2773			.ops = &clk_branch2_ops,
2774			.flags = CLK_SET_RATE_PARENT,
2775		}
2776	}
2777};
2778
2779static struct clk_branch gcc_camss_jpeg0_clk = {
2780	.halt_reg = 0x57020,
2781	.halt_check = BRANCH_HALT,
2782	.clkr = {
2783		.enable_reg = 0x57020,
2784		.enable_mask = BIT(0),
2785		.hw.init = &(struct clk_init_data) {
2786			.name = "gcc_camss_jpeg0_clk",
2787			.parent_hws = (const struct clk_hw*[]){
2788				&jpeg0_clk_src.clkr.hw,
2789			},
2790			.num_parents = 1,
2791			.ops = &clk_branch2_ops,
2792			.flags = CLK_SET_RATE_PARENT,
2793		}
2794	}
2795};
2796
2797static struct clk_branch gcc_camss_jpeg_ahb_clk = {
2798	.halt_reg = 0x57024,
2799	.halt_check = BRANCH_HALT,
2800	.clkr = {
2801		.enable_reg = 0x57024,
2802		.enable_mask = BIT(0),
2803		.hw.init = &(struct clk_init_data) {
2804			.name = "gcc_camss_jpeg_ahb_clk",
2805			.parent_hws = (const struct clk_hw*[]){
2806				&camss_top_ahb_clk_src.clkr.hw,
2807			},
2808			.num_parents = 1,
2809			.ops = &clk_branch2_ops,
2810			.flags = CLK_SET_RATE_PARENT,
2811		}
2812	}
2813};
2814
2815static struct clk_branch gcc_camss_jpeg_axi_clk = {
2816	.halt_reg = 0x57028,
2817	.halt_check = BRANCH_HALT,
2818	.clkr = {
2819		.enable_reg = 0x57028,
2820		.enable_mask = BIT(0),
2821		.hw.init = &(struct clk_init_data) {
2822			.name = "gcc_camss_jpeg_axi_clk",
2823			.ops = &clk_branch2_ops,
2824		}
2825	}
2826};
2827
2828static struct clk_branch gcc_camss_mclk0_clk = {
2829	.halt_reg = 0x52018,
2830	.halt_check = BRANCH_HALT,
2831	.clkr = {
2832		.enable_reg = 0x52018,
2833		.enable_mask = BIT(0),
2834		.hw.init = &(struct clk_init_data) {
2835			.name = "gcc_camss_mclk0_clk",
2836			.parent_hws = (const struct clk_hw*[]){
2837				&mclk0_clk_src.clkr.hw,
2838			},
2839			.num_parents = 1,
2840			.ops = &clk_branch2_ops,
2841			.flags = CLK_SET_RATE_PARENT,
2842		}
2843	}
2844};
2845
2846static struct clk_branch gcc_camss_mclk1_clk = {
2847	.halt_reg = 0x53018,
2848	.halt_check = BRANCH_HALT,
2849	.clkr = {
2850		.enable_reg = 0x53018,
2851		.enable_mask = BIT(0),
2852		.hw.init = &(struct clk_init_data) {
2853			.name = "gcc_camss_mclk1_clk",
2854			.parent_hws = (const struct clk_hw*[]){
2855				&mclk1_clk_src.clkr.hw,
2856			},
2857			.num_parents = 1,
2858			.ops = &clk_branch2_ops,
2859			.flags = CLK_SET_RATE_PARENT,
2860		}
2861	}
2862};
2863
2864static struct clk_branch gcc_camss_mclk2_clk = {
2865	.halt_reg = 0x5c018,
2866	.halt_check = BRANCH_HALT,
2867	.clkr = {
2868		.enable_reg = 0x5c018,
2869		.enable_mask = BIT(0),
2870		.hw.init = &(struct clk_init_data) {
2871			.name = "gcc_camss_mclk2_clk",
2872			.parent_hws = (const struct clk_hw*[]){
2873				&mclk2_clk_src.clkr.hw,
2874			},
2875			.num_parents = 1,
2876			.ops = &clk_branch2_ops,
2877			.flags = CLK_SET_RATE_PARENT,
2878		}
2879	}
2880};
2881
2882static struct clk_branch gcc_camss_mclk3_clk = {
2883	.halt_reg = 0x5e018,
2884	.halt_check = BRANCH_HALT,
2885	.clkr = {
2886		.enable_reg = 0x5e018,
2887		.enable_mask = BIT(0),
2888		.hw.init = &(struct clk_init_data) {
2889			.name = "gcc_camss_mclk3_clk",
2890			.parent_hws = (const struct clk_hw*[]){
2891				&mclk3_clk_src.clkr.hw,
2892			},
2893			.num_parents = 1,
2894			.ops = &clk_branch2_ops,
2895			.flags = CLK_SET_RATE_PARENT,
2896		}
2897	}
2898};
2899
2900static struct clk_branch gcc_camss_micro_ahb_clk = {
2901	.halt_reg = 0x5600c,
2902	.halt_check = BRANCH_HALT,
2903	.clkr = {
2904		.enable_reg = 0x5600c,
2905		.enable_mask = BIT(0),
2906		.hw.init = &(struct clk_init_data) {
2907			.name = "gcc_camss_micro_ahb_clk",
2908			.parent_hws = (const struct clk_hw*[]){
2909				&camss_top_ahb_clk_src.clkr.hw,
2910			},
2911			.num_parents = 1,
2912			.ops = &clk_branch2_ops,
2913			.flags = CLK_SET_RATE_PARENT,
2914		}
2915	}
2916};
2917
2918static struct clk_branch gcc_camss_top_ahb_clk = {
2919	.halt_reg = 0x5a014,
2920	.halt_check = BRANCH_HALT,
2921	.clkr = {
2922		.enable_reg = 0x5a014,
2923		.enable_mask = BIT(0),
2924		.hw.init = &(struct clk_init_data) {
2925			.name = "gcc_camss_top_ahb_clk",
2926			.parent_hws = (const struct clk_hw*[]){
2927				&camss_top_ahb_clk_src.clkr.hw,
2928			},
2929			.num_parents = 1,
2930			.ops = &clk_branch2_ops,
2931			.flags = CLK_SET_RATE_PARENT,
2932		}
2933	}
2934};
2935
2936static struct clk_branch gcc_camss_vfe0_ahb_clk = {
2937	.halt_reg = 0x58044,
2938	.halt_check = BRANCH_HALT,
2939	.clkr = {
2940		.enable_reg = 0x58044,
2941		.enable_mask = BIT(0),
2942		.hw.init = &(struct clk_init_data) {
2943			.name = "gcc_camss_vfe0_ahb_clk",
2944			.parent_hws = (const struct clk_hw*[]){
2945				&camss_top_ahb_clk_src.clkr.hw,
2946			},
2947			.num_parents = 1,
2948			.ops = &clk_branch2_ops,
2949			.flags = CLK_SET_RATE_PARENT,
2950		}
2951	}
2952};
2953
2954static struct clk_branch gcc_camss_vfe0_axi_clk = {
2955	.halt_reg = 0x58048,
2956	.halt_check = BRANCH_HALT,
2957	.clkr = {
2958		.enable_reg = 0x58048,
2959		.enable_mask = BIT(0),
2960		.hw.init = &(struct clk_init_data) {
2961			.name = "gcc_camss_vfe0_axi_clk",
2962			.ops = &clk_branch2_ops,
2963		}
2964	}
2965};
2966
2967static struct clk_branch gcc_camss_vfe0_clk = {
2968	.halt_reg = 0x58038,
2969	.halt_check = BRANCH_HALT,
2970	.clkr = {
2971		.enable_reg = 0x58038,
2972		.enable_mask = BIT(0),
2973		.hw.init = &(struct clk_init_data) {
2974			.name = "gcc_camss_vfe0_clk",
2975			.parent_hws = (const struct clk_hw*[]){
2976				&vfe0_clk_src.clkr.hw,
2977			},
2978			.num_parents = 1,
2979			.ops = &clk_branch2_ops,
2980			.flags = CLK_SET_RATE_PARENT,
2981		}
2982	}
2983};
2984
2985static struct clk_branch gcc_camss_vfe1_ahb_clk = {
2986	.halt_reg = 0x58060,
2987	.halt_check = BRANCH_HALT,
2988	.clkr = {
2989		.enable_reg = 0x58060,
2990		.enable_mask = BIT(0),
2991		.hw.init = &(struct clk_init_data) {
2992			.name = "gcc_camss_vfe1_ahb_clk",
2993			.parent_hws = (const struct clk_hw*[]){
2994				&camss_top_ahb_clk_src.clkr.hw,
2995			},
2996			.num_parents = 1,
2997			.ops = &clk_branch2_ops,
2998			.flags = CLK_SET_RATE_PARENT,
2999		}
3000	}
3001};
3002
3003static struct clk_branch gcc_camss_vfe1_axi_clk = {
3004	.halt_reg = 0x58068,
3005	.halt_check = BRANCH_HALT,
3006	.clkr = {
3007		.enable_reg = 0x58068,
3008		.enable_mask = BIT(0),
3009		.hw.init = &(struct clk_init_data) {
3010			.name = "gcc_camss_vfe1_axi_clk",
3011			.ops = &clk_branch2_ops,
3012		}
3013	}
3014};
3015
3016static struct clk_branch gcc_camss_vfe1_clk = {
3017	.halt_reg = 0x5805c,
3018	.halt_check = BRANCH_HALT,
3019	.clkr = {
3020		.enable_reg = 0x5805c,
3021		.enable_mask = BIT(0),
3022		.hw.init = &(struct clk_init_data) {
3023			.name = "gcc_camss_vfe1_clk",
3024			.parent_hws = (const struct clk_hw*[]){
3025				&vfe1_clk_src.clkr.hw,
3026			},
3027			.num_parents = 1,
3028			.ops = &clk_branch2_ops,
3029			.flags = CLK_SET_RATE_PARENT,
3030		}
3031	}
3032};
3033
3034static struct clk_branch gcc_cpp_tbu_clk = {
3035	.halt_reg = 0x12040,
3036	.halt_check = BRANCH_HALT_VOTED,
3037	.clkr = {
3038		.enable_reg = 0x4500c,
3039		.enable_mask = BIT(14),
3040		.hw.init = &(struct clk_init_data) {
3041			.name = "gcc_cpp_tbu_clk",
3042			.ops = &clk_branch2_ops,
3043		}
3044	}
3045};
3046
3047static struct clk_branch gcc_crypto_ahb_clk = {
3048	.halt_reg = 0x16024,
3049	.halt_check = BRANCH_HALT_VOTED,
3050	.clkr = {
3051		.enable_reg = 0x45004,
3052		.enable_mask = BIT(0),
3053		.hw.init = &(struct clk_init_data) {
3054			.name = "gcc_crypto_ahb_clk",
3055			.ops = &clk_branch2_ops,
3056		}
3057	}
3058};
3059
3060static struct clk_branch gcc_crypto_axi_clk = {
3061	.halt_reg = 0x16020,
3062	.halt_check = BRANCH_HALT_VOTED,
3063	.clkr = {
3064		.enable_reg = 0x45004,
3065		.enable_mask = BIT(1),
3066		.hw.init = &(struct clk_init_data) {
3067			.name = "gcc_crypto_axi_clk",
3068			.ops = &clk_branch2_ops,
3069		}
3070	}
3071};
3072
3073static struct clk_branch gcc_crypto_clk = {
3074	.halt_reg = 0x1601c,
3075	.halt_check = BRANCH_HALT_VOTED,
3076	.clkr = {
3077		.enable_reg = 0x45004,
3078		.enable_mask = BIT(2),
3079		.hw.init = &(struct clk_init_data) {
3080			.name = "gcc_crypto_clk",
3081			.parent_hws = (const struct clk_hw*[]){
3082				&crypto_clk_src.clkr.hw,
3083			},
3084			.num_parents = 1,
3085			.ops = &clk_branch2_ops,
3086			.flags = CLK_SET_RATE_PARENT,
3087		}
3088	}
3089};
3090
3091static struct clk_branch gcc_dcc_clk = {
3092	.halt_reg = 0x77004,
3093	.halt_check = BRANCH_HALT,
3094	.clkr = {
3095		.enable_reg = 0x77004,
3096		.enable_mask = BIT(0),
3097		.hw.init = &(struct clk_init_data) {
3098			.name = "gcc_dcc_clk",
3099			.ops = &clk_branch2_ops,
3100		}
3101	}
3102};
3103
3104static struct clk_branch gcc_gp1_clk = {
3105	.halt_reg = 0x08000,
3106	.halt_check = BRANCH_HALT,
3107	.clkr = {
3108		.enable_reg = 0x08000,
3109		.enable_mask = BIT(0),
3110		.hw.init = &(struct clk_init_data) {
3111			.name = "gcc_gp1_clk",
3112			.parent_hws = (const struct clk_hw*[]){
3113				&gp1_clk_src.clkr.hw,
3114			},
3115			.num_parents = 1,
3116			.ops = &clk_branch2_ops,
3117			.flags = CLK_SET_RATE_PARENT,
3118		}
3119	}
3120};
3121
3122static struct clk_branch gcc_gp2_clk = {
3123	.halt_reg = 0x09000,
3124	.halt_check = BRANCH_HALT,
3125	.clkr = {
3126		.enable_reg = 0x09000,
3127		.enable_mask = BIT(0),
3128		.hw.init = &(struct clk_init_data) {
3129			.name = "gcc_gp2_clk",
3130			.parent_hws = (const struct clk_hw*[]){
3131				&gp2_clk_src.clkr.hw,
3132			},
3133			.num_parents = 1,
3134			.ops = &clk_branch2_ops,
3135			.flags = CLK_SET_RATE_PARENT,
3136		}
3137	}
3138};
3139
3140static struct clk_branch gcc_gp3_clk = {
3141	.halt_reg = 0x0a000,
3142	.halt_check = BRANCH_HALT,
3143	.clkr = {
3144		.enable_reg = 0x0a000,
3145		.enable_mask = BIT(0),
3146		.hw.init = &(struct clk_init_data) {
3147			.name = "gcc_gp3_clk",
3148			.parent_hws = (const struct clk_hw*[]){
3149				&gp3_clk_src.clkr.hw,
3150			},
3151			.num_parents = 1,
3152			.ops = &clk_branch2_ops,
3153			.flags = CLK_SET_RATE_PARENT,
3154		}
3155	}
3156};
3157
3158static struct clk_branch gcc_jpeg_tbu_clk = {
3159	.halt_reg = 0x12034,
3160	.halt_check = BRANCH_HALT_VOTED,
3161	.clkr = {
3162		.enable_reg = 0x4500c,
3163		.enable_mask = BIT(10),
3164		.hw.init = &(struct clk_init_data) {
3165			.name = "gcc_jpeg_tbu_clk",
3166			.ops = &clk_branch2_ops,
3167		}
3168	}
3169};
3170
3171static struct clk_branch gcc_mdp_tbu_clk = {
3172	.halt_reg = 0x1201c,
3173	.halt_check = BRANCH_HALT_VOTED,
3174	.clkr = {
3175		.enable_reg = 0x4500c,
3176		.enable_mask = BIT(4),
3177		.hw.init = &(struct clk_init_data) {
3178			.name = "gcc_mdp_tbu_clk",
3179			.ops = &clk_branch2_ops,
3180		}
3181	}
3182};
3183
3184static struct clk_branch gcc_mdss_ahb_clk = {
3185	.halt_reg = 0x4d07c,
3186	.halt_check = BRANCH_HALT,
3187	.clkr = {
3188		.enable_reg = 0x4d07c,
3189		.enable_mask = BIT(0),
3190		.hw.init = &(struct clk_init_data) {
3191			.name = "gcc_mdss_ahb_clk",
3192			.ops = &clk_branch2_ops,
3193		}
3194	}
3195};
3196
3197static struct clk_branch gcc_mdss_axi_clk = {
3198	.halt_reg = 0x4d080,
3199	.halt_check = BRANCH_HALT,
3200	.clkr = {
3201		.enable_reg = 0x4d080,
3202		.enable_mask = BIT(0),
3203		.hw.init = &(struct clk_init_data) {
3204			.name = "gcc_mdss_axi_clk",
3205			.ops = &clk_branch2_ops,
3206		}
3207	}
3208};
3209
3210static struct clk_branch gcc_mdss_byte0_clk = {
3211	.halt_reg = 0x4d094,
3212	.halt_check = BRANCH_HALT,
3213	.clkr = {
3214		.enable_reg = 0x4d094,
3215		.enable_mask = BIT(0),
3216		.hw.init = &(struct clk_init_data) {
3217			.name = "gcc_mdss_byte0_clk",
3218			.parent_hws = (const struct clk_hw*[]){
3219				&byte0_clk_src.clkr.hw,
3220			},
3221			.num_parents = 1,
3222			.ops = &clk_branch2_ops,
3223			.flags = CLK_SET_RATE_PARENT,
3224		}
3225	}
3226};
3227
3228static struct clk_branch gcc_mdss_byte1_clk = {
3229	.halt_reg = 0x4d0a0,
3230	.halt_check = BRANCH_HALT,
3231	.clkr = {
3232		.enable_reg = 0x4d0a0,
3233		.enable_mask = BIT(0),
3234		.hw.init = &(struct clk_init_data) {
3235			.name = "gcc_mdss_byte1_clk",
3236			.parent_hws = (const struct clk_hw*[]){
3237				&byte1_clk_src.clkr.hw,
3238			},
3239			.num_parents = 1,
3240			.ops = &clk_branch2_ops,
3241			.flags = CLK_SET_RATE_PARENT,
3242		}
3243	}
3244};
3245
3246static struct clk_branch gcc_mdss_esc0_clk = {
3247	.halt_reg = 0x4d098,
3248	.halt_check = BRANCH_HALT,
3249	.clkr = {
3250		.enable_reg = 0x4d098,
3251		.enable_mask = BIT(0),
3252		.hw.init = &(struct clk_init_data) {
3253			.name = "gcc_mdss_esc0_clk",
3254			.parent_hws = (const struct clk_hw*[]){
3255				&esc0_clk_src.clkr.hw,
3256			},
3257			.num_parents = 1,
3258			.ops = &clk_branch2_ops,
3259			.flags = CLK_SET_RATE_PARENT,
3260		}
3261	}
3262};
3263
3264static struct clk_branch gcc_mdss_esc1_clk = {
3265	.halt_reg = 0x4d09c,
3266	.halt_check = BRANCH_HALT,
3267	.clkr = {
3268		.enable_reg = 0x4d09c,
3269		.enable_mask = BIT(0),
3270		.hw.init = &(struct clk_init_data) {
3271			.name = "gcc_mdss_esc1_clk",
3272			.parent_hws = (const struct clk_hw*[]){
3273				&esc1_clk_src.clkr.hw,
3274			},
3275			.num_parents = 1,
3276			.ops = &clk_branch2_ops,
3277			.flags = CLK_SET_RATE_PARENT,
3278		}
3279	}
3280};
3281
3282static struct clk_branch gcc_mdss_mdp_clk = {
3283	.halt_reg = 0x4d088,
3284	.halt_check = BRANCH_HALT,
3285	.clkr = {
3286		.enable_reg = 0x4d088,
3287		.enable_mask = BIT(0),
3288		.hw.init = &(struct clk_init_data) {
3289			.name = "gcc_mdss_mdp_clk",
3290			.parent_hws = (const struct clk_hw*[]){
3291				&mdp_clk_src.clkr.hw,
3292			},
3293			.num_parents = 1,
3294			.ops = &clk_branch2_ops,
3295			.flags = CLK_SET_RATE_PARENT,
3296		}
3297	}
3298};
3299
3300static struct clk_branch gcc_mdss_pclk0_clk = {
3301	.halt_reg = 0x4d084,
3302	.halt_check = BRANCH_HALT,
3303	.clkr = {
3304		.enable_reg = 0x4d084,
3305		.enable_mask = BIT(0),
3306		.hw.init = &(struct clk_init_data) {
3307			.name = "gcc_mdss_pclk0_clk",
3308			.parent_hws = (const struct clk_hw*[]){
3309				&pclk0_clk_src.clkr.hw,
3310			},
3311			.num_parents = 1,
3312			.ops = &clk_branch2_ops,
3313			.flags = CLK_SET_RATE_PARENT,
3314		}
3315	}
3316};
3317
3318static struct clk_branch gcc_mdss_pclk1_clk = {
3319	.halt_reg = 0x4d0a4,
3320	.halt_check = BRANCH_HALT,
3321	.clkr = {
3322		.enable_reg = 0x4d0a4,
3323		.enable_mask = BIT(0),
3324		.hw.init = &(struct clk_init_data) {
3325			.name = "gcc_mdss_pclk1_clk",
3326			.parent_hws = (const struct clk_hw*[]){
3327				&pclk1_clk_src.clkr.hw,
3328			},
3329			.num_parents = 1,
3330			.ops = &clk_branch2_ops,
3331			.flags = CLK_SET_RATE_PARENT,
3332		}
3333	}
3334};
3335
3336static struct clk_branch gcc_mdss_vsync_clk = {
3337	.halt_reg = 0x4d090,
3338	.halt_check = BRANCH_HALT,
3339	.clkr = {
3340		.enable_reg = 0x4d090,
3341		.enable_mask = BIT(0),
3342		.hw.init = &(struct clk_init_data) {
3343			.name = "gcc_mdss_vsync_clk",
3344			.parent_hws = (const struct clk_hw*[]){
3345				&vsync_clk_src.clkr.hw,
3346			},
3347			.num_parents = 1,
3348			.ops = &clk_branch2_ops,
3349			.flags = CLK_SET_RATE_PARENT,
3350		}
3351	}
3352};
3353
3354static struct clk_branch gcc_mss_cfg_ahb_clk = {
3355	.halt_reg = 0x49000,
3356	.halt_check = BRANCH_HALT,
3357	.clkr = {
3358		.enable_reg = 0x49000,
3359		.enable_mask = BIT(0),
3360		.hw.init = &(struct clk_init_data) {
3361			.name = "gcc_mss_cfg_ahb_clk",
3362			.ops = &clk_branch2_ops,
3363		}
3364	}
3365};
3366
3367static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
3368	.halt_reg = 0x49004,
3369	.halt_check = BRANCH_HALT,
3370	.clkr = {
3371		.enable_reg = 0x49004,
3372		.enable_mask = BIT(0),
3373		.hw.init = &(struct clk_init_data) {
3374			.name = "gcc_mss_q6_bimc_axi_clk",
3375			.ops = &clk_branch2_ops,
3376		}
3377	}
3378};
3379
3380static struct clk_branch gcc_oxili_ahb_clk = {
3381	.halt_reg = 0x59028,
3382	.halt_check = BRANCH_HALT,
3383	.clkr = {
3384		.enable_reg = 0x59028,
3385		.enable_mask = BIT(0),
3386		.hw.init = &(struct clk_init_data) {
3387			.name = "gcc_oxili_ahb_clk",
3388			.ops = &clk_branch2_ops,
3389		}
3390	}
3391};
3392
3393static struct clk_branch gcc_oxili_aon_clk = {
3394	.halt_reg = 0x59044,
3395	.halt_check = BRANCH_HALT,
3396	.clkr = {
3397		.enable_reg = 0x59044,
3398		.enable_mask = BIT(0),
3399		.hw.init = &(struct clk_init_data) {
3400			.name = "gcc_oxili_aon_clk",
3401			.parent_hws = (const struct clk_hw*[]){
3402				&gfx3d_clk_src.clkr.hw,
3403			},
3404			.num_parents = 1,
3405			.ops = &clk_branch2_ops,
3406		}
3407	}
3408};
3409
3410static struct clk_branch gcc_oxili_gfx3d_clk = {
3411	.halt_reg = 0x59020,
3412	.halt_check = BRANCH_HALT,
3413	.clkr = {
3414		.enable_reg = 0x59020,
3415		.enable_mask = BIT(0),
3416		.hw.init = &(struct clk_init_data) {
3417			.name = "gcc_oxili_gfx3d_clk",
3418			.parent_hws = (const struct clk_hw*[]){
3419				&gfx3d_clk_src.clkr.hw,
3420			},
3421			.num_parents = 1,
3422			.ops = &clk_branch2_ops,
3423			.flags = CLK_SET_RATE_PARENT,
3424		}
3425	}
3426};
3427
3428static struct clk_branch gcc_oxili_timer_clk = {
3429	.halt_reg = 0x59040,
3430	.halt_check = BRANCH_HALT,
3431	.clkr = {
3432		.enable_reg = 0x59040,
3433		.enable_mask = BIT(0),
3434		.hw.init = &(struct clk_init_data) {
3435			.name = "gcc_oxili_timer_clk",
3436			.ops = &clk_branch2_ops,
3437		}
3438	}
3439};
3440
3441static struct clk_branch gcc_pcnoc_usb3_axi_clk = {
3442	.halt_reg = 0x3f038,
3443	.halt_check = BRANCH_HALT,
3444	.clkr = {
3445		.enable_reg = 0x3f038,
3446		.enable_mask = BIT(0),
3447		.hw.init = &(struct clk_init_data) {
3448			.name = "gcc_pcnoc_usb3_axi_clk",
3449			.parent_hws = (const struct clk_hw*[]){
3450				&usb30_master_clk_src.clkr.hw,
3451			},
3452			.num_parents = 1,
3453			.ops = &clk_branch2_ops,
3454			.flags = CLK_SET_RATE_PARENT,
3455		}
3456	}
3457};
3458
3459static struct clk_branch gcc_pdm2_clk = {
3460	.halt_reg = 0x4400c,
3461	.halt_check = BRANCH_HALT,
3462	.clkr = {
3463		.enable_reg = 0x4400c,
3464		.enable_mask = BIT(0),
3465		.hw.init = &(struct clk_init_data) {
3466			.name = "gcc_pdm2_clk",
3467			.parent_hws = (const struct clk_hw*[]){
3468				&pdm2_clk_src.clkr.hw,
3469			},
3470			.num_parents = 1,
3471			.ops = &clk_branch2_ops,
3472			.flags = CLK_SET_RATE_PARENT,
3473		}
3474	}
3475};
3476
3477static struct clk_branch gcc_pdm_ahb_clk = {
3478	.halt_reg = 0x44004,
3479	.halt_check = BRANCH_HALT,
3480	.clkr = {
3481		.enable_reg = 0x44004,
3482		.enable_mask = BIT(0),
3483		.hw.init = &(struct clk_init_data) {
3484			.name = "gcc_pdm_ahb_clk",
3485			.ops = &clk_branch2_ops,
3486		}
3487	}
3488};
3489
3490static struct clk_branch gcc_prng_ahb_clk = {
3491	.halt_reg = 0x13004,
3492	.halt_check = BRANCH_HALT_VOTED,
3493	.clkr = {
3494		.enable_reg = 0x45004,
3495		.enable_mask = BIT(8),
3496		.hw.init = &(struct clk_init_data) {
3497			.name = "gcc_prng_ahb_clk",
3498			.ops = &clk_branch2_ops,
3499		}
3500	}
3501};
3502
3503static struct clk_branch gcc_qdss_dap_clk = {
3504	.halt_reg = 0x29084,
3505	.halt_check = BRANCH_HALT_VOTED,
3506	.clkr = {
3507		.enable_reg = 0x45004,
3508		.enable_mask = BIT(11),
3509		.hw.init = &(struct clk_init_data) {
3510			.name = "gcc_qdss_dap_clk",
3511			.ops = &clk_branch2_ops,
3512		}
3513	}
3514};
3515
3516static struct clk_branch gcc_qusb_ref_clk = {
3517	.halt_reg = 0,
3518	.halt_check = BRANCH_HALT_SKIP,
3519	.clkr = {
3520		.enable_reg = 0x41030,
3521		.enable_mask = BIT(0),
3522		.hw.init = &(struct clk_init_data) {
3523			.name = "gcc_qusb_ref_clk",
3524			.ops = &clk_branch2_ops,
3525		}
3526	}
3527};
3528
3529static struct clk_branch gcc_rbcpr_gfx_clk = {
3530	.halt_reg = 0x3a004,
3531	.halt_check = BRANCH_HALT,
3532	.clkr = {
3533		.enable_reg = 0x3a004,
3534		.enable_mask = BIT(0),
3535		.hw.init = &(struct clk_init_data) {
3536			.name = "gcc_rbcpr_gfx_clk",
3537			.parent_hws = (const struct clk_hw*[]){
3538				&rbcpr_gfx_clk_src.clkr.hw,
3539			},
3540			.num_parents = 1,
3541			.ops = &clk_branch2_ops,
3542			.flags = CLK_SET_RATE_PARENT,
3543		}
3544	}
3545};
3546
3547static struct clk_branch gcc_sdcc1_ice_core_clk = {
3548	.halt_reg = 0x5d014,
3549	.halt_check = BRANCH_HALT,
3550	.clkr = {
3551		.enable_reg = 0x5d014,
3552		.enable_mask = BIT(0),
3553		.hw.init = &(struct clk_init_data) {
3554			.name = "gcc_sdcc1_ice_core_clk",
3555			.parent_hws = (const struct clk_hw*[]){
3556				&sdcc1_ice_core_clk_src.clkr.hw,
3557			},
3558			.num_parents = 1,
3559			.ops = &clk_branch2_ops,
3560			.flags = CLK_SET_RATE_PARENT,
3561		}
3562	}
3563};
3564
3565static struct clk_branch gcc_sdcc1_ahb_clk = {
3566	.halt_reg = 0x4201c,
3567	.halt_check = BRANCH_HALT,
3568	.clkr = {
3569		.enable_reg = 0x4201c,
3570		.enable_mask = BIT(0),
3571		.hw.init = &(struct clk_init_data) {
3572			.name = "gcc_sdcc1_ahb_clk",
3573			.ops = &clk_branch2_ops,
3574		}
3575	}
3576};
3577
3578static struct clk_branch gcc_sdcc2_ahb_clk = {
3579	.halt_reg = 0x4301c,
3580	.halt_check = BRANCH_HALT,
3581	.clkr = {
3582		.enable_reg = 0x4301c,
3583		.enable_mask = BIT(0),
3584		.hw.init = &(struct clk_init_data) {
3585			.name = "gcc_sdcc2_ahb_clk",
3586			.ops = &clk_branch2_ops,
3587		}
3588	}
3589};
3590
3591static struct clk_branch gcc_sdcc1_apps_clk = {
3592	.halt_reg = 0x42018,
3593	.halt_check = BRANCH_HALT,
3594	.clkr = {
3595		.enable_reg = 0x42018,
3596		.enable_mask = BIT(0),
3597		.hw.init = &(struct clk_init_data) {
3598			.name = "gcc_sdcc1_apps_clk",
3599			.parent_hws = (const struct clk_hw*[]){
3600				&sdcc1_apps_clk_src.clkr.hw,
3601			},
3602			.num_parents = 1,
3603			.ops = &clk_branch2_ops,
3604			.flags = CLK_SET_RATE_PARENT,
3605		}
3606	}
3607};
3608
3609static struct clk_branch gcc_sdcc2_apps_clk = {
3610	.halt_reg = 0x43018,
3611	.halt_check = BRANCH_HALT,
3612	.clkr = {
3613		.enable_reg = 0x43018,
3614		.enable_mask = BIT(0),
3615		.hw.init = &(struct clk_init_data) {
3616			.name = "gcc_sdcc2_apps_clk",
3617			.parent_hws = (const struct clk_hw*[]){
3618				&sdcc2_apps_clk_src.clkr.hw,
3619			},
3620			.num_parents = 1,
3621			.ops = &clk_branch2_ops,
3622			.flags = CLK_SET_RATE_PARENT,
3623		}
3624	}
3625};
3626
3627static struct clk_branch gcc_smmu_cfg_clk = {
3628	.halt_reg = 0x12038,
3629	.halt_check = BRANCH_HALT_VOTED,
3630	.clkr = {
3631		.enable_reg = 0x4500c,
3632		.enable_mask = BIT(12),
3633		.hw.init = &(struct clk_init_data) {
3634			.name = "gcc_smmu_cfg_clk",
3635			.ops = &clk_branch2_ops,
3636		}
3637	}
3638};
3639
3640static struct clk_branch gcc_usb30_master_clk = {
3641	.halt_reg = 0x3f000,
3642	.halt_check = BRANCH_HALT,
3643	.clkr = {
3644		.enable_reg = 0x3f000,
3645		.enable_mask = BIT(0),
3646		.hw.init = &(struct clk_init_data) {
3647			.name = "gcc_usb30_master_clk",
3648			.parent_hws = (const struct clk_hw*[]){
3649				&usb30_master_clk_src.clkr.hw,
3650			},
3651			.num_parents = 1,
3652			.ops = &clk_branch2_ops,
3653			.flags = CLK_SET_RATE_PARENT,
3654		}
3655	}
3656};
3657
3658static struct clk_branch gcc_usb30_mock_utmi_clk = {
3659	.halt_reg = 0x3f008,
3660	.halt_check = BRANCH_HALT,
3661	.clkr = {
3662		.enable_reg = 0x3f008,
3663		.enable_mask = BIT(0),
3664		.hw.init = &(struct clk_init_data) {
3665			.name = "gcc_usb30_mock_utmi_clk",
3666			.parent_hws = (const struct clk_hw*[]){
3667				&usb30_mock_utmi_clk_src.clkr.hw,
3668			},
3669			.num_parents = 1,
3670			.ops = &clk_branch2_ops,
3671			.flags = CLK_SET_RATE_PARENT,
3672		}
3673	}
3674};
3675
3676static struct clk_branch gcc_usb30_sleep_clk = {
3677	.halt_reg = 0x3f004,
3678	.halt_check = BRANCH_HALT,
3679	.clkr = {
3680		.enable_reg = 0x3f004,
3681		.enable_mask = BIT(0),
3682		.hw.init = &(struct clk_init_data) {
3683			.name = "gcc_usb30_sleep_clk",
3684			.ops = &clk_branch2_ops,
3685		}
3686	}
3687};
3688
3689static struct clk_branch gcc_usb3_aux_clk = {
3690	.halt_reg = 0x3f044,
3691	.halt_check = BRANCH_HALT,
3692	.clkr = {
3693		.enable_reg = 0x3f044,
3694		.enable_mask = BIT(0),
3695		.hw.init = &(struct clk_init_data) {
3696			.name = "gcc_usb3_aux_clk",
3697			.parent_hws = (const struct clk_hw*[]){
3698				&usb3_aux_clk_src.clkr.hw,
3699			},
3700			.num_parents = 1,
3701			.ops = &clk_branch2_ops,
3702			.flags = CLK_SET_RATE_PARENT,
3703		}
3704	}
3705};
3706
3707static struct clk_branch gcc_usb3_pipe_clk = {
3708	.halt_reg = 0,
3709	.halt_check = BRANCH_HALT_DELAY,
3710	.clkr = {
3711		.enable_reg = 0x3f040,
3712		.enable_mask = BIT(0),
3713		.hw.init = &(struct clk_init_data) {
3714			.name = "gcc_usb3_pipe_clk",
3715			.ops = &clk_branch2_ops,
3716		}
3717	}
3718};
3719
3720static struct clk_branch gcc_usb_phy_cfg_ahb_clk = {
3721	.halt_reg = 0x3f080,
3722	.halt_check = BRANCH_VOTED,
3723	.clkr = {
3724		.enable_reg = 0x3f080,
3725		.enable_mask = BIT(0),
3726		.hw.init = &(struct clk_init_data) {
3727			.name = "gcc_usb_phy_cfg_ahb_clk",
3728			.ops = &clk_branch2_ops,
3729		}
3730	}
3731};
3732
3733static struct clk_branch gcc_usb_ss_ref_clk = {
3734	.halt_reg = 0,
3735	.halt_check = BRANCH_HALT_SKIP,
3736	.clkr = {
3737		.enable_reg = 0x3f07c,
3738		.enable_mask = BIT(0),
3739		.hw.init = &(struct clk_init_data) {
3740			.name = "gcc_usb_ss_ref_clk",
3741			.ops = &clk_branch2_ops,
3742		}
3743	}
3744};
3745
3746static struct clk_branch gcc_venus0_ahb_clk = {
3747	.halt_reg = 0x4c020,
3748	.halt_check = BRANCH_HALT,
3749	.clkr = {
3750		.enable_reg = 0x4c020,
3751		.enable_mask = BIT(0),
3752		.hw.init = &(struct clk_init_data) {
3753			.name = "gcc_venus0_ahb_clk",
3754			.ops = &clk_branch2_ops,
3755		}
3756	}
3757};
3758
3759static struct clk_branch gcc_venus0_axi_clk = {
3760	.halt_reg = 0x4c024,
3761	.halt_check = BRANCH_HALT,
3762	.clkr = {
3763		.enable_reg = 0x4c024,
3764		.enable_mask = BIT(0),
3765		.hw.init = &(struct clk_init_data) {
3766			.name = "gcc_venus0_axi_clk",
3767			.ops = &clk_branch2_ops,
3768		}
3769	}
3770};
3771
3772static struct clk_branch gcc_venus0_core0_vcodec0_clk = {
3773	.halt_reg = 0x4c02c,
3774	.halt_check = BRANCH_HALT,
3775	.clkr = {
3776		.enable_reg = 0x4c02c,
3777		.enable_mask = BIT(0),
3778		.hw.init = &(struct clk_init_data) {
3779			.name = "gcc_venus0_core0_vcodec0_clk",
3780			.parent_hws = (const struct clk_hw*[]){
3781				&vcodec0_clk_src.clkr.hw,
3782			},
3783			.num_parents = 1,
3784			.ops = &clk_branch2_ops,
3785			.flags = CLK_SET_RATE_PARENT,
3786		}
3787	}
3788};
3789
3790static struct clk_branch gcc_venus0_vcodec0_clk = {
3791	.halt_reg = 0x4c01c,
3792	.halt_check = BRANCH_HALT,
3793	.clkr = {
3794		.enable_reg = 0x4c01c,
3795		.enable_mask = BIT(0),
3796		.hw.init = &(struct clk_init_data) {
3797			.name = "gcc_venus0_vcodec0_clk",
3798			.parent_hws = (const struct clk_hw*[]){
3799				&vcodec0_clk_src.clkr.hw,
3800			},
3801			.num_parents = 1,
3802			.ops = &clk_branch2_ops,
3803			.flags = CLK_SET_RATE_PARENT,
3804		}
3805	}
3806};
3807
3808static struct clk_branch gcc_venus_tbu_clk = {
3809	.halt_reg = 0x12014,
3810	.halt_check = BRANCH_HALT_VOTED,
3811	.clkr = {
3812		.enable_reg = 0x4500c,
3813		.enable_mask = BIT(5),
3814		.hw.init = &(struct clk_init_data) {
3815			.name = "gcc_venus_tbu_clk",
3816			.ops = &clk_branch2_ops,
3817		}
3818	}
3819};
3820
3821static struct clk_branch gcc_vfe1_tbu_clk = {
3822	.halt_reg = 0x12090,
3823	.halt_check = BRANCH_HALT_VOTED,
3824	.clkr = {
3825		.enable_reg = 0x4500c,
3826		.enable_mask = BIT(17),
3827		.hw.init = &(struct clk_init_data) {
3828			.name = "gcc_vfe1_tbu_clk",
3829			.ops = &clk_branch2_ops,
3830		}
3831	}
3832};
3833
3834static struct clk_branch gcc_vfe_tbu_clk = {
3835	.halt_reg = 0x1203c,
3836	.halt_check = BRANCH_HALT_VOTED,
3837	.clkr = {
3838		.enable_reg = 0x4500c,
3839		.enable_mask = BIT(9),
3840		.hw.init = &(struct clk_init_data) {
3841			.name = "gcc_vfe_tbu_clk",
3842			.ops = &clk_branch2_ops,
3843		}
3844	}
3845};
3846
3847static struct gdsc usb30_gdsc = {
3848	.gdscr = 0x3f078,
3849	.pd = {
3850		.name = "usb30_gdsc",
3851	},
3852	.pwrsts = PWRSTS_OFF_ON,
3853	/*
3854	 * FIXME: dwc3 usb gadget cannot resume after GDSC power off
3855	 * dwc3 7000000.dwc3: failed to enable ep0out
3856	 */
3857	.flags = ALWAYS_ON,
3858};
3859
3860static struct gdsc venus_gdsc = {
3861	.gdscr = 0x4c018,
3862	.cxcs = (unsigned int []){ 0x4c024, 0x4c01c },
3863	.cxc_count = 2,
3864	.pd = {
3865		.name = "venus_gdsc",
3866	},
3867	.pwrsts = PWRSTS_OFF_ON,
3868};
3869
3870static struct gdsc venus_core0_gdsc = {
3871	.gdscr = 0x4c028,
3872	.cxcs = (unsigned int []){ 0x4c02c },
3873	.cxc_count = 1,
3874	.pd = {
3875		.name = "venus_core0",
3876	},
3877	.flags = HW_CTRL,
3878	.pwrsts = PWRSTS_OFF_ON,
3879};
3880
3881static struct gdsc mdss_gdsc = {
3882	.gdscr = 0x4d078,
3883	.cxcs = (unsigned int []){ 0x4d080, 0x4d088 },
3884	.cxc_count = 2,
3885	.pd = {
3886		.name = "mdss_gdsc",
3887	},
3888	.pwrsts = PWRSTS_OFF_ON,
3889};
3890
3891static struct gdsc jpeg_gdsc = {
3892	.gdscr = 0x5701c,
3893	.cxcs = (unsigned int []){ 0x57020, 0x57028 },
3894	.cxc_count = 2,
3895	.pd = {
3896		.name = "jpeg_gdsc",
3897	},
3898	.pwrsts = PWRSTS_OFF_ON,
3899};
3900
3901static struct gdsc vfe0_gdsc = {
3902	.gdscr = 0x58034,
3903	.cxcs = (unsigned int []){ 0x58038, 0x58048, 0x5600c, 0x58050 },
3904	.cxc_count = 4,
3905	.pd = {
3906		.name = "vfe0_gdsc",
3907	},
3908	.pwrsts = PWRSTS_OFF_ON,
3909};
3910
3911static struct gdsc vfe1_gdsc = {
3912	.gdscr = 0x5806c,
3913	.cxcs = (unsigned int []){ 0x5805c, 0x58068, 0x5600c, 0x58074 },
3914	.cxc_count = 4,
3915	.pd = {
3916		.name = "vfe1_gdsc",
3917	},
3918	.pwrsts = PWRSTS_OFF_ON,
3919};
3920
3921static struct gdsc oxili_gx_gdsc = {
3922	.gdscr = 0x5901c,
3923	.clamp_io_ctrl = 0x5b00c,
3924	.cxcs = (unsigned int []){ 0x59000, 0x59024 },
3925	.cxc_count = 2,
3926	.pd = {
3927		.name = "oxili_gx_gdsc",
3928	},
3929	.pwrsts = PWRSTS_OFF_ON,
3930	.flags = CLAMP_IO,
3931};
3932
3933static struct gdsc oxili_cx_gdsc = {
3934	.gdscr = 0x5904c,
3935	.cxcs = (unsigned int []){ 0x59020 },
3936	.cxc_count = 1,
3937	.pd = {
3938		.name = "oxili_cx_gdsc",
3939	},
3940	.pwrsts = PWRSTS_OFF_ON,
3941};
3942
3943static struct gdsc cpp_gdsc = {
3944	.gdscr = 0x58078,
3945	.cxcs = (unsigned int []){ 0x5803c, 0x58064 },
3946	.cxc_count = 2,
3947	.pd = {
3948		.name = "cpp_gdsc",
3949	},
3950	.flags = ALWAYS_ON,
3951	.pwrsts = PWRSTS_OFF_ON,
3952};
3953
3954static struct clk_hw *gcc_msm8953_hws[] = {
3955	&gpll0_early_div.hw,
3956	&gpll6_early_div.hw,
3957};
3958
3959static struct clk_regmap *gcc_msm8953_clocks[] = {
3960	[GPLL0] = &gpll0.clkr,
3961	[GPLL0_EARLY] = &gpll0_early.clkr,
3962	[GPLL2] = &gpll2.clkr,
3963	[GPLL2_EARLY] = &gpll2_early.clkr,
3964	[GPLL3] = &gpll3.clkr,
3965	[GPLL3_EARLY] = &gpll3_early.clkr,
3966	[GPLL4] = &gpll4.clkr,
3967	[GPLL4_EARLY] = &gpll4_early.clkr,
3968	[GPLL6] = &gpll6.clkr,
3969	[GPLL6_EARLY] = &gpll6_early.clkr,
3970	[GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,
3971	[GCC_APSS_AXI_CLK] = &gcc_apss_axi_clk.clkr,
3972	[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3973	[GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
3974	[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3975	[GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
3976	[GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
3977	[GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
3978	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3979	[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
3980	[GCC_APSS_TCU_ASYNC_CLK] = &gcc_apss_tcu_async_clk.clkr,
3981	[GCC_CPP_TBU_CLK] = &gcc_cpp_tbu_clk.clkr,
3982	[GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr,
3983	[GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
3984	[GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
3985	[GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr,
3986	[GCC_VFE1_TBU_CLK] = &gcc_vfe1_tbu_clk.clkr,
3987	[GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
3988	[CAMSS_TOP_AHB_CLK_SRC] = &camss_top_ahb_clk_src.clkr,
3989	[CSI0_CLK_SRC] = &csi0_clk_src.clkr,
3990	[APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
3991	[CSI1_CLK_SRC] = &csi1_clk_src.clkr,
3992	[CSI2_CLK_SRC] = &csi2_clk_src.clkr,
3993	[VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
3994	[VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
3995	[CPP_CLK_SRC] = &cpp_clk_src.clkr,
3996	[JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
3997	[USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
3998	[VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
3999	[APC0_DROOP_DETECTOR_CLK_SRC] = &apc0_droop_detector_clk_src.clkr,
4000	[APC1_DROOP_DETECTOR_CLK_SRC] = &apc1_droop_detector_clk_src.clkr,
4001	[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
4002	[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
4003	[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
4004	[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
4005	[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
4006	[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
4007	[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
4008	[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
4009	[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
4010	[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
4011	[BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
4012	[BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
4013	[BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
4014	[BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
4015	[BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
4016	[BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
4017	[BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
4018	[BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
4019	[BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
4020	[BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
4021	[CCI_CLK_SRC] = &cci_clk_src.clkr,
4022	[CSI0P_CLK_SRC] = &csi0p_clk_src.clkr,
4023	[CSI1P_CLK_SRC] = &csi1p_clk_src.clkr,
4024	[CSI2P_CLK_SRC] = &csi2p_clk_src.clkr,
4025	[CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
4026	[CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
4027	[MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
4028	[MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
4029	[MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
4030	[MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
4031	[CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
4032	[CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
4033	[CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
4034	[CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
4035	[GP1_CLK_SRC] = &gp1_clk_src.clkr,
4036	[GP2_CLK_SRC] = &gp2_clk_src.clkr,
4037	[GP3_CLK_SRC] = &gp3_clk_src.clkr,
4038	[PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
4039	[RBCPR_GFX_CLK_SRC] = &rbcpr_gfx_clk_src.clkr,
4040	[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
4041	[SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
4042	[SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
4043	[USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
4044	[USB3_AUX_CLK_SRC] = &usb3_aux_clk_src.clkr,
4045	[GCC_APC0_DROOP_DETECTOR_GPLL0_CLK] = &gcc_apc0_droop_detector_gpll0_clk.clkr,
4046	[GCC_APC1_DROOP_DETECTOR_GPLL0_CLK] = &gcc_apc1_droop_detector_gpll0_clk.clkr,
4047	[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
4048	[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
4049	[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
4050	[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
4051	[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
4052	[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
4053	[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
4054	[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
4055	[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
4056	[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
4057	[GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
4058	[GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
4059	[GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
4060	[GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
4061	[GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
4062	[GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
4063	[GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
4064	[GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
4065	[GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
4066	[GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
4067	[GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr,
4068	[GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr,
4069	[GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr,
4070	[GCC_CAMSS_CPP_AXI_CLK] = &gcc_camss_cpp_axi_clk.clkr,
4071	[GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr,
4072	[GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,
4073	[GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,
4074	[GCC_CAMSS_CSI0_CSIPHY_3P_CLK] = &gcc_camss_csi0_csiphy_3p_clk.clkr,
4075	[GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr,
4076	[GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,
4077	[GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,
4078	[GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,
4079	[GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,
4080	[GCC_CAMSS_CSI1_CSIPHY_3P_CLK] = &gcc_camss_csi1_csiphy_3p_clk.clkr,
4081	[GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,
4082	[GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
4083	[GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
4084	[GCC_CAMSS_CSI2_AHB_CLK] = &gcc_camss_csi2_ahb_clk.clkr,
4085	[GCC_CAMSS_CSI2_CLK] = &gcc_camss_csi2_clk.clkr,
4086	[GCC_CAMSS_CSI2_CSIPHY_3P_CLK] = &gcc_camss_csi2_csiphy_3p_clk.clkr,
4087	[GCC_CAMSS_CSI2PHY_CLK] = &gcc_camss_csi2phy_clk.clkr,
4088	[GCC_CAMSS_CSI2PIX_CLK] = &gcc_camss_csi2pix_clk.clkr,
4089	[GCC_CAMSS_CSI2RDI_CLK] = &gcc_camss_csi2rdi_clk.clkr,
4090	[GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
4091	[GCC_CAMSS_CSI_VFE1_CLK] = &gcc_camss_csi_vfe1_clk.clkr,
4092	[GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
4093	[GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,
4094	[GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,
4095	[GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr,
4096	[GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr,
4097	[GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr,
4098	[GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
4099	[GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
4100	[GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr,
4101	[GCC_CAMSS_MCLK3_CLK] = &gcc_camss_mclk3_clk.clkr,
4102	[GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr,
4103	[GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
4104	[GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
4105	[GCC_CAMSS_CSI2PHYTIMER_CLK] = &gcc_camss_csi2phytimer_clk.clkr,
4106	[GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr,
4107	[GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
4108	[GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,
4109	[GCC_CAMSS_VFE0_AHB_CLK] = &gcc_camss_vfe0_ahb_clk.clkr,
4110	[GCC_CAMSS_VFE0_AXI_CLK] = &gcc_camss_vfe0_axi_clk.clkr,
4111	[GCC_CAMSS_VFE1_AHB_CLK] = &gcc_camss_vfe1_ahb_clk.clkr,
4112	[GCC_CAMSS_VFE1_AXI_CLK] = &gcc_camss_vfe1_axi_clk.clkr,
4113	[GCC_CAMSS_VFE1_CLK] = &gcc_camss_vfe1_clk.clkr,
4114	[GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
4115	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
4116	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
4117	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
4118	[GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
4119	[GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
4120	[GCC_PCNOC_USB3_AXI_CLK] = &gcc_pcnoc_usb3_axi_clk.clkr,
4121	[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
4122	[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
4123	[GCC_RBCPR_GFX_CLK] = &gcc_rbcpr_gfx_clk.clkr,
4124	[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
4125	[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
4126	[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
4127	[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
4128	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
4129	[GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
4130	[GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
4131	[GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
4132	[GCC_USB3_AUX_CLK] = &gcc_usb3_aux_clk.clkr,
4133	[GCC_USB_PHY_CFG_AHB_CLK] = &gcc_usb_phy_cfg_ahb_clk.clkr,
4134	[GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr,
4135	[GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr,
4136	[GCC_VENUS0_CORE0_VCODEC0_CLK] = &gcc_venus0_core0_vcodec0_clk.clkr,
4137	[GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
4138	[GCC_QUSB_REF_CLK] = &gcc_qusb_ref_clk.clkr,
4139	[GCC_USB_SS_REF_CLK] = &gcc_usb_ss_ref_clk.clkr,
4140	[GCC_USB3_PIPE_CLK] = &gcc_usb3_pipe_clk.clkr,
4141	[MDP_CLK_SRC] = &mdp_clk_src.clkr,
4142	[PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
4143	[BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
4144	[ESC0_CLK_SRC] = &esc0_clk_src.clkr,
4145	[PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
4146	[BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
4147	[ESC1_CLK_SRC] = &esc1_clk_src.clkr,
4148	[VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
4149	[GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
4150	[GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
4151	[GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
4152	[GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
4153	[GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
4154	[GCC_MDSS_PCLK1_CLK] = &gcc_mdss_pclk1_clk.clkr,
4155	[GCC_MDSS_BYTE1_CLK] = &gcc_mdss_byte1_clk.clkr,
4156	[GCC_MDSS_ESC1_CLK] = &gcc_mdss_esc1_clk.clkr,
4157	[GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
4158	[GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
4159	[GCC_OXILI_TIMER_CLK] = &gcc_oxili_timer_clk.clkr,
4160	[GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
4161	[GCC_OXILI_AON_CLK] = &gcc_oxili_aon_clk.clkr,
4162	[GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
4163	[GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
4164	[GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
4165	[GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
4166};
4167
4168static const struct qcom_reset_map gcc_msm8953_resets[] = {
4169	[GCC_CAMSS_MICRO_BCR]	= { 0x56008 },
4170	[GCC_MSS_BCR]		= { 0x71000 },
4171	[GCC_QUSB2_PHY_BCR]	= { 0x4103c },
4172	[GCC_USB3PHY_PHY_BCR]	= { 0x3f03c },
4173	[GCC_USB3_PHY_BCR]	= { 0x3f034 },
4174	[GCC_USB_30_BCR]	= { 0x3f070 },
4175};
4176
4177static const struct regmap_config gcc_msm8953_regmap_config = {
4178	.reg_bits	= 32,
4179	.reg_stride	= 4,
4180	.val_bits	= 32,
4181	.max_register	= 0x80000,
4182	.fast_io	= true,
4183};
4184
4185static struct gdsc *gcc_msm8953_gdscs[] = {
4186	[CPP_GDSC] = &cpp_gdsc,
4187	[JPEG_GDSC] = &jpeg_gdsc,
4188	[MDSS_GDSC] = &mdss_gdsc,
4189	[OXILI_CX_GDSC] = &oxili_cx_gdsc,
4190	[OXILI_GX_GDSC] = &oxili_gx_gdsc,
4191	[USB30_GDSC] = &usb30_gdsc,
4192	[VENUS_CORE0_GDSC] = &venus_core0_gdsc,
4193	[VENUS_GDSC] = &venus_gdsc,
4194	[VFE0_GDSC] = &vfe0_gdsc,
4195	[VFE1_GDSC] = &vfe1_gdsc,
4196};
4197
4198static const struct qcom_cc_desc gcc_msm8953_desc = {
4199	.config = &gcc_msm8953_regmap_config,
4200	.clks = gcc_msm8953_clocks,
4201	.num_clks = ARRAY_SIZE(gcc_msm8953_clocks),
4202	.resets = gcc_msm8953_resets,
4203	.num_resets = ARRAY_SIZE(gcc_msm8953_resets),
4204	.gdscs = gcc_msm8953_gdscs,
4205	.num_gdscs = ARRAY_SIZE(gcc_msm8953_gdscs),
4206	.clk_hws = gcc_msm8953_hws,
4207	.num_clk_hws = ARRAY_SIZE(gcc_msm8953_hws),
4208};
4209
4210static int gcc_msm8953_probe(struct platform_device *pdev)
4211{
4212	struct regmap *regmap;
4213
4214	regmap  = qcom_cc_map(pdev, &gcc_msm8953_desc);
4215	if (IS_ERR(regmap))
4216		return PTR_ERR(regmap);
4217
4218	clk_alpha_pll_configure(&gpll3_early, regmap, &gpll3_early_config);
4219
4220	return qcom_cc_really_probe(pdev, &gcc_msm8953_desc, regmap);
4221}
4222
4223static const struct of_device_id gcc_msm8953_match_table[] = {
4224	{ .compatible = "qcom,gcc-msm8953" },
4225	{},
4226};
4227
4228static struct platform_driver gcc_msm8953_driver = {
4229	.probe = gcc_msm8953_probe,
4230	.driver = {
4231		.name = "gcc-msm8953",
4232		.of_match_table = gcc_msm8953_match_table,
4233	},
4234};
4235
4236static int __init gcc_msm8953_init(void)
4237{
4238	return platform_driver_register(&gcc_msm8953_driver);
4239}
4240core_initcall(gcc_msm8953_init);
4241
4242static void __exit gcc_msm8953_exit(void)
4243{
4244	platform_driver_unregister(&gcc_msm8953_driver);
4245}
4246module_exit(gcc_msm8953_exit);
4247
4248MODULE_DESCRIPTION("Qualcomm GCC MSM8953 Driver");
4249MODULE_LICENSE("GPL v2");