1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright 2015 Linaro Limited
   4 */
   5
   6#include <linux/kernel.h>
   7#include <linux/bitops.h>
   8#include <linux/err.h>
   9#include <linux/platform_device.h>
  10#include <linux/module.h>
  11#include <linux/of.h>
  12#include <linux/of_device.h>
  13#include <linux/clk-provider.h>
  14#include <linux/regmap.h>
  15#include <linux/reset-controller.h>
  16
  17#include <dt-bindings/clock/qcom,gcc-msm8916.h>
  18#include <dt-bindings/reset/qcom,gcc-msm8916.h>
  19
  20#include "common.h"
  21#include "clk-regmap.h"
  22#include "clk-pll.h"
  23#include "clk-rcg.h"
  24#include "clk-branch.h"
  25#include "reset.h"
  26#include "gdsc.h"
  27
  28enum {
  29	P_XO,
  30	P_GPLL0,
  31	P_GPLL0_AUX,
  32	P_BIMC,
  33	P_GPLL1,
  34	P_GPLL1_AUX,
  35	P_GPLL2,
  36	P_GPLL2_AUX,
  37	P_SLEEP_CLK,
  38	P_DSI0_PHYPLL_BYTE,
  39	P_DSI0_PHYPLL_DSI,
  40	P_EXT_PRI_I2S,
  41	P_EXT_SEC_I2S,
  42	P_EXT_MCLK,
  43};
  44
  45static struct clk_pll gpll0 = {
  46	.l_reg = 0x21004,
  47	.m_reg = 0x21008,
  48	.n_reg = 0x2100c,
  49	.config_reg = 0x21010,
  50	.mode_reg = 0x21000,
  51	.status_reg = 0x2101c,
  52	.status_bit = 17,
  53	.clkr.hw.init = &(struct clk_init_data){
  54		.name = "gpll0",
  55		.parent_data = &(const struct clk_parent_data){
  56			.fw_name = "xo", .name = "xo_board",
  57		},
  58		.num_parents = 1,
  59		.ops = &clk_pll_ops,
  60	},
  61};
  62
  63static struct clk_regmap gpll0_vote = {
  64	.enable_reg = 0x45000,
  65	.enable_mask = BIT(0),
  66	.hw.init = &(struct clk_init_data){
  67		.name = "gpll0_vote",
  68		.parent_hws = (const struct clk_hw*[]){
  69			&gpll0.clkr.hw,
  70		},
  71		.num_parents = 1,
  72		.ops = &clk_pll_vote_ops,
  73	},
  74};
  75
  76static struct clk_pll gpll1 = {
  77	.l_reg = 0x20004,
  78	.m_reg = 0x20008,
  79	.n_reg = 0x2000c,
  80	.config_reg = 0x20010,
  81	.mode_reg = 0x20000,
  82	.status_reg = 0x2001c,
  83	.status_bit = 17,
  84	.clkr.hw.init = &(struct clk_init_data){
  85		.name = "gpll1",
  86		.parent_data = &(const struct clk_parent_data){
  87			.fw_name = "xo", .name = "xo_board",
  88		},
  89		.num_parents = 1,
  90		.ops = &clk_pll_ops,
  91	},
  92};
  93
  94static struct clk_regmap gpll1_vote = {
  95	.enable_reg = 0x45000,
  96	.enable_mask = BIT(1),
  97	.hw.init = &(struct clk_init_data){
  98		.name = "gpll1_vote",
  99		.parent_hws = (const struct clk_hw*[]){
 100			&gpll1.clkr.hw,
 101		},
 102		.num_parents = 1,
 103		.ops = &clk_pll_vote_ops,
 104	},
 105};
 106
 107static struct clk_pll gpll2 = {
 108	.l_reg = 0x4a004,
 109	.m_reg = 0x4a008,
 110	.n_reg = 0x4a00c,
 111	.config_reg = 0x4a010,
 112	.mode_reg = 0x4a000,
 113	.status_reg = 0x4a01c,
 114	.status_bit = 17,
 115	.clkr.hw.init = &(struct clk_init_data){
 116		.name = "gpll2",
 117		.parent_data = &(const struct clk_parent_data){
 118			.fw_name = "xo", .name = "xo_board",
 119		},
 120		.num_parents = 1,
 121		.ops = &clk_pll_ops,
 122	},
 123};
 124
 125static struct clk_regmap gpll2_vote = {
 126	.enable_reg = 0x45000,
 127	.enable_mask = BIT(2),
 128	.hw.init = &(struct clk_init_data){
 129		.name = "gpll2_vote",
 130		.parent_hws = (const struct clk_hw*[]){
 131			&gpll2.clkr.hw,
 132		},
 133		.num_parents = 1,
 134		.ops = &clk_pll_vote_ops,
 135	},
 136};
 137
 138static struct clk_pll bimc_pll = {
 139	.l_reg = 0x23004,
 140	.m_reg = 0x23008,
 141	.n_reg = 0x2300c,
 142	.config_reg = 0x23010,
 143	.mode_reg = 0x23000,
 144	.status_reg = 0x2301c,
 145	.status_bit = 17,
 146	.clkr.hw.init = &(struct clk_init_data){
 147		.name = "bimc_pll",
 148		.parent_data = &(const struct clk_parent_data){
 149			.fw_name = "xo", .name = "xo_board",
 150		},
 151		.num_parents = 1,
 152		.ops = &clk_pll_ops,
 153	},
 154};
 155
 156static struct clk_regmap bimc_pll_vote = {
 157	.enable_reg = 0x45000,
 158	.enable_mask = BIT(3),
 159	.hw.init = &(struct clk_init_data){
 160		.name = "bimc_pll_vote",
 161		.parent_hws = (const struct clk_hw*[]){
 162			&bimc_pll.clkr.hw,
 163		},
 164		.num_parents = 1,
 165		.ops = &clk_pll_vote_ops,
 166	},
 167};
 168
 169static const struct parent_map gcc_xo_gpll0_map[] = {
 170	{ P_XO, 0 },
 171	{ P_GPLL0, 1 },
 172};
 173
 174static const struct clk_parent_data gcc_xo_gpll0[] = {
 175	{ .fw_name = "xo", .name = "xo_board" },
 176	{ .hw = &gpll0_vote.hw },
 177};
 178
 179static const struct parent_map gcc_xo_gpll0_bimc_map[] = {
 180	{ P_XO, 0 },
 181	{ P_GPLL0, 1 },
 182	{ P_BIMC, 2 },
 183};
 184
 185static const struct clk_parent_data gcc_xo_gpll0_bimc[] = {
 186	{ .fw_name = "xo", .name = "xo_board" },
 187	{ .hw = &gpll0_vote.hw },
 188	{ .hw = &bimc_pll_vote.hw },
 189};
 190
 191static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2a_map[] = {
 192	{ P_XO, 0 },
 193	{ P_GPLL0_AUX, 3 },
 194	{ P_GPLL1, 1 },
 195	{ P_GPLL2_AUX, 2 },
 196};
 197
 198static const struct clk_parent_data gcc_xo_gpll0a_gpll1_gpll2a[] = {
 199	{ .fw_name = "xo", .name = "xo_board" },
 200	{ .hw = &gpll0_vote.hw },
 201	{ .hw = &gpll1_vote.hw },
 202	{ .hw = &gpll2_vote.hw },
 203};
 204
 205static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
 206	{ P_XO, 0 },
 207	{ P_GPLL0, 1 },
 208	{ P_GPLL2, 2 },
 209};
 210
 211static const struct clk_parent_data gcc_xo_gpll0_gpll2[] = {
 212	{ .fw_name = "xo", .name = "xo_board" },
 213	{ .hw = &gpll0_vote.hw },
 214	{ .hw = &gpll2_vote.hw },
 215};
 216
 217static const struct parent_map gcc_xo_gpll0a_map[] = {
 218	{ P_XO, 0 },
 219	{ P_GPLL0_AUX, 2 },
 220};
 221
 222static const struct clk_parent_data gcc_xo_gpll0a[] = {
 223	{ .fw_name = "xo", .name = "xo_board" },
 224	{ .hw = &gpll0_vote.hw },
 225};
 226
 227static const struct parent_map gcc_xo_gpll0_gpll1a_sleep_map[] = {
 228	{ P_XO, 0 },
 229	{ P_GPLL0, 1 },
 230	{ P_GPLL1_AUX, 2 },
 231	{ P_SLEEP_CLK, 6 },
 232};
 233
 234static const struct clk_parent_data gcc_xo_gpll0_gpll1a_sleep[] = {
 235	{ .fw_name = "xo", .name = "xo_board" },
 236	{ .hw = &gpll0_vote.hw },
 237	{ .hw = &gpll1_vote.hw },
 238	{ .fw_name = "sleep_clk", .name = "sleep_clk" },
 239};
 240
 241static const struct parent_map gcc_xo_gpll0_gpll1a_map[] = {
 242	{ P_XO, 0 },
 243	{ P_GPLL0, 1 },
 244	{ P_GPLL1_AUX, 2 },
 245};
 246
 247static const struct clk_parent_data gcc_xo_gpll0_gpll1a[] = {
 248	{ .fw_name = "xo", .name = "xo_board" },
 249	{ .hw = &gpll0_vote.hw },
 250	{ .hw = &gpll1_vote.hw },
 251};
 252
 253static const struct parent_map gcc_xo_dsibyte_map[] = {
 254	{ P_XO, 0, },
 255	{ P_DSI0_PHYPLL_BYTE, 2 },
 256};
 257
 258static const struct clk_parent_data gcc_xo_dsibyte[] = {
 259	{ .fw_name = "xo", .name = "xo_board" },
 260	{ .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
 261};
 262
 263static const struct parent_map gcc_xo_gpll0a_dsibyte_map[] = {
 264	{ P_XO, 0 },
 265	{ P_GPLL0_AUX, 2 },
 266	{ P_DSI0_PHYPLL_BYTE, 1 },
 267};
 268
 269static const struct clk_parent_data gcc_xo_gpll0a_dsibyte[] = {
 270	{ .fw_name = "xo", .name = "xo_board" },
 271	{ .hw = &gpll0_vote.hw },
 272	{ .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
 273};
 274
 275static const struct parent_map gcc_xo_gpll0_dsiphy_map[] = {
 276	{ P_XO, 0 },
 277	{ P_GPLL0, 1 },
 278	{ P_DSI0_PHYPLL_DSI, 2 },
 279};
 280
 281static const struct clk_parent_data gcc_xo_gpll0_dsiphy[] = {
 282	{ .fw_name = "xo", .name = "xo_board" },
 283	{ .hw = &gpll0_vote.hw },
 284	{ .fw_name = "dsi0pll", .name = "dsi0pll" },
 285};
 286
 287static const struct parent_map gcc_xo_gpll0a_dsiphy_map[] = {
 288	{ P_XO, 0 },
 289	{ P_GPLL0_AUX, 2 },
 290	{ P_DSI0_PHYPLL_DSI, 1 },
 291};
 292
 293static const struct clk_parent_data gcc_xo_gpll0a_dsiphy[] = {
 294	{ .fw_name = "xo", .name = "xo_board" },
 295	{ .hw = &gpll0_vote.hw },
 296	{ .fw_name = "dsi0pll", .name = "dsi0pll" },
 297};
 298
 299static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2_map[] = {
 300	{ P_XO, 0 },
 301	{ P_GPLL0_AUX, 1 },
 302	{ P_GPLL1, 3 },
 303	{ P_GPLL2, 2 },
 304};
 305
 306static const struct clk_parent_data gcc_xo_gpll0a_gpll1_gpll2[] = {
 307	{ .fw_name = "xo", .name = "xo_board" },
 308	{ .hw = &gpll0_vote.hw },
 309	{ .hw = &gpll1_vote.hw },
 310	{ .hw = &gpll2_vote.hw },
 311};
 312
 313static const struct parent_map gcc_xo_gpll0_gpll1_sleep_map[] = {
 314	{ P_XO, 0 },
 315	{ P_GPLL0, 1 },
 316	{ P_GPLL1, 2 },
 317	{ P_SLEEP_CLK, 6 }
 318};
 319
 320static const struct clk_parent_data gcc_xo_gpll0_gpll1_sleep[] = {
 321	{ .fw_name = "xo", .name = "xo_board" },
 322	{ .hw = &gpll0_vote.hw },
 323	{ .hw = &gpll1_vote.hw },
 324	{ .fw_name = "sleep_clk", .name = "sleep_clk" },
 325};
 326
 327static const struct parent_map gcc_xo_gpll1_epi2s_emclk_sleep_map[] = {
 328	{ P_XO, 0 },
 329	{ P_GPLL1, 1 },
 330	{ P_EXT_PRI_I2S, 2 },
 331	{ P_EXT_MCLK, 3 },
 332	{ P_SLEEP_CLK, 6 }
 333};
 334
 335static const struct clk_parent_data gcc_xo_gpll1_epi2s_emclk_sleep[] = {
 336	{ .fw_name = "xo", .name = "xo_board" },
 337	{ .hw = &gpll1_vote.hw },
 338	{ .fw_name = "ext_pri_i2s", .name = "ext_pri_i2s" },
 339	{ .fw_name = "ext_mclk", .name = "ext_mclk" },
 340	{ .fw_name = "sleep_clk", .name = "sleep_clk" },
 341};
 342
 343static const struct parent_map gcc_xo_gpll1_esi2s_emclk_sleep_map[] = {
 344	{ P_XO, 0 },
 345	{ P_GPLL1, 1 },
 346	{ P_EXT_SEC_I2S, 2 },
 347	{ P_EXT_MCLK, 3 },
 348	{ P_SLEEP_CLK, 6 }
 349};
 350
 351static const struct clk_parent_data gcc_xo_gpll1_esi2s_emclk_sleep[] = {
 352	{ .fw_name = "xo", .name = "xo_board" },
 353	{ .hw = &gpll1_vote.hw },
 354	{ .fw_name = "ext_sec_i2s", .name = "ext_sec_i2s" },
 355	{ .fw_name = "ext_mclk", .name = "ext_mclk" },
 356	{ .fw_name = "sleep_clk", .name = "sleep_clk" },
 357};
 358
 359static const struct parent_map gcc_xo_sleep_map[] = {
 360	{ P_XO, 0 },
 361	{ P_SLEEP_CLK, 6 }
 362};
 363
 364static const struct clk_parent_data gcc_xo_sleep[] = {
 365	{ .fw_name = "xo", .name = "xo_board" },
 366	{ .fw_name = "sleep_clk", .name = "sleep_clk" },
 367};
 368
 369static const struct parent_map gcc_xo_gpll1_emclk_sleep_map[] = {
 370	{ P_XO, 0 },
 371	{ P_GPLL1, 1 },
 372	{ P_EXT_MCLK, 2 },
 373	{ P_SLEEP_CLK, 6 }
 374};
 375
 376static const struct clk_parent_data gcc_xo_gpll1_emclk_sleep[] = {
 377	{ .fw_name = "xo", .name = "xo_board" },
 378	{ .hw = &gpll1_vote.hw },
 379	{ .fw_name = "ext_mclk", .name = "ext_mclk" },
 380	{ .fw_name = "sleep_clk", .name = "sleep_clk" },
 381};
 382
 383static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
 384	.cmd_rcgr = 0x27000,
 385	.hid_width = 5,
 386	.parent_map = gcc_xo_gpll0_bimc_map,
 387	.clkr.hw.init = &(struct clk_init_data){
 388		.name = "pcnoc_bfdcd_clk_src",
 389		.parent_data = gcc_xo_gpll0_bimc,
 390		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc),
 391		.ops = &clk_rcg2_ops,
 392	},
 393};
 394
 395static struct clk_rcg2 system_noc_bfdcd_clk_src = {
 396	.cmd_rcgr = 0x26004,
 397	.hid_width = 5,
 398	.parent_map = gcc_xo_gpll0_bimc_map,
 399	.clkr.hw.init = &(struct clk_init_data){
 400		.name = "system_noc_bfdcd_clk_src",
 401		.parent_data = gcc_xo_gpll0_bimc,
 402		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc),
 403		.ops = &clk_rcg2_ops,
 404	},
 405};
 406
 407static const struct freq_tbl ftbl_gcc_camss_ahb_clk[] = {
 408	F(40000000, P_GPLL0, 10, 1, 2),
 409	F(80000000, P_GPLL0, 10, 0, 0),
 410	{ }
 411};
 412
 413static struct clk_rcg2 camss_ahb_clk_src = {
 414	.cmd_rcgr = 0x5a000,
 415	.mnd_width = 8,
 416	.hid_width = 5,
 417	.parent_map = gcc_xo_gpll0_map,
 418	.freq_tbl = ftbl_gcc_camss_ahb_clk,
 419	.clkr.hw.init = &(struct clk_init_data){
 420		.name = "camss_ahb_clk_src",
 421		.parent_data = gcc_xo_gpll0,
 422		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 423		.ops = &clk_rcg2_ops,
 424	},
 425};
 426
 427static const struct freq_tbl ftbl_apss_ahb_clk[] = {
 428	F(19200000, P_XO, 1, 0, 0),
 429	F(50000000, P_GPLL0, 16, 0, 0),
 430	F(100000000, P_GPLL0, 8, 0, 0),
 431	F(133330000, P_GPLL0, 6, 0, 0),
 432	{ }
 433};
 434
 435static struct clk_rcg2 apss_ahb_clk_src = {
 436	.cmd_rcgr = 0x46000,
 437	.hid_width = 5,
 438	.parent_map = gcc_xo_gpll0_map,
 439	.freq_tbl = ftbl_apss_ahb_clk,
 440	.clkr.hw.init = &(struct clk_init_data){
 441		.name = "apss_ahb_clk_src",
 442		.parent_data = gcc_xo_gpll0,
 443		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 444		.ops = &clk_rcg2_ops,
 445	},
 446};
 447
 448static const struct freq_tbl ftbl_gcc_camss_csi0_1_clk[] = {
 449	F(100000000, P_GPLL0, 8, 0,	0),
 450	F(200000000, P_GPLL0, 4, 0,	0),
 451	{ }
 452};
 453
 454static struct clk_rcg2 csi0_clk_src = {
 455	.cmd_rcgr = 0x4e020,
 456	.hid_width = 5,
 457	.parent_map = gcc_xo_gpll0_map,
 458	.freq_tbl = ftbl_gcc_camss_csi0_1_clk,
 459	.clkr.hw.init = &(struct clk_init_data){
 460		.name = "csi0_clk_src",
 461		.parent_data = gcc_xo_gpll0,
 462		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 463		.ops = &clk_rcg2_ops,
 464	},
 465};
 466
 467static struct clk_rcg2 csi1_clk_src = {
 468	.cmd_rcgr = 0x4f020,
 469	.hid_width = 5,
 470	.parent_map = gcc_xo_gpll0_map,
 471	.freq_tbl = ftbl_gcc_camss_csi0_1_clk,
 472	.clkr.hw.init = &(struct clk_init_data){
 473		.name = "csi1_clk_src",
 474		.parent_data = gcc_xo_gpll0,
 475		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 476		.ops = &clk_rcg2_ops,
 477	},
 478};
 479
 480static const struct freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = {
 481	F(19200000, P_XO, 1, 0, 0),
 482	F(50000000, P_GPLL0_AUX, 16, 0, 0),
 483	F(80000000, P_GPLL0_AUX, 10, 0, 0),
 484	F(100000000, P_GPLL0_AUX, 8, 0, 0),
 485	F(160000000, P_GPLL0_AUX, 5, 0, 0),
 486	F(177780000, P_GPLL0_AUX, 4.5, 0, 0),
 487	F(200000000, P_GPLL0_AUX, 4, 0, 0),
 488	F(266670000, P_GPLL0_AUX, 3, 0, 0),
 489	F(294912000, P_GPLL1, 3, 0, 0),
 490	F(310000000, P_GPLL2, 3, 0, 0),
 491	F(400000000, P_GPLL0_AUX, 2, 0, 0),
 492	{ }
 493};
 494
 495static struct clk_rcg2 gfx3d_clk_src = {
 496	.cmd_rcgr = 0x59000,
 497	.hid_width = 5,
 498	.parent_map = gcc_xo_gpll0a_gpll1_gpll2a_map,
 499	.freq_tbl = ftbl_gcc_oxili_gfx3d_clk,
 500	.clkr.hw.init = &(struct clk_init_data){
 501		.name = "gfx3d_clk_src",
 502		.parent_data = gcc_xo_gpll0a_gpll1_gpll2a,
 503		.num_parents = ARRAY_SIZE(gcc_xo_gpll0a_gpll1_gpll2a),
 504		.ops = &clk_rcg2_ops,
 505	},
 506};
 507
 508static const struct freq_tbl ftbl_gcc_camss_vfe0_clk[] = {
 509	F(50000000, P_GPLL0, 16, 0, 0),
 510	F(80000000, P_GPLL0, 10, 0, 0),
 511	F(100000000, P_GPLL0, 8, 0, 0),
 512	F(160000000, P_GPLL0, 5, 0, 0),
 513	F(177780000, P_GPLL0, 4.5, 0, 0),
 514	F(200000000, P_GPLL0, 4, 0, 0),
 515	F(266670000, P_GPLL0, 3, 0, 0),
 516	F(320000000, P_GPLL0, 2.5, 0, 0),
 517	F(400000000, P_GPLL0, 2, 0, 0),
 518	F(465000000, P_GPLL2, 2, 0, 0),
 519	{ }
 520};
 521
 522static struct clk_rcg2 vfe0_clk_src = {
 523	.cmd_rcgr = 0x58000,
 524	.hid_width = 5,
 525	.parent_map = gcc_xo_gpll0_gpll2_map,
 526	.freq_tbl = ftbl_gcc_camss_vfe0_clk,
 527	.clkr.hw.init = &(struct clk_init_data){
 528		.name = "vfe0_clk_src",
 529		.parent_data = gcc_xo_gpll0_gpll2,
 530		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
 531		.ops = &clk_rcg2_ops,
 532	},
 533};
 534
 535static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = {
 536	F(19200000, P_XO, 1, 0, 0),
 537	F(50000000, P_GPLL0, 16, 0, 0),
 538	{ }
 539};
 540
 541static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 542	.cmd_rcgr = 0x0200c,
 543	.hid_width = 5,
 544	.parent_map = gcc_xo_gpll0_map,
 545	.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 546	.clkr.hw.init = &(struct clk_init_data){
 547		.name = "blsp1_qup1_i2c_apps_clk_src",
 548		.parent_data = gcc_xo_gpll0,
 549		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 550		.ops = &clk_rcg2_ops,
 551	},
 552};
 553
 554static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = {
 555	F(100000, P_XO, 16, 2, 24),
 556	F(250000, P_XO, 16, 5, 24),
 557	F(500000, P_XO, 8, 5, 24),
 558	F(960000, P_XO, 10, 1, 2),
 559	F(1000000, P_XO, 4, 5, 24),
 560	F(4800000, P_XO, 4, 0, 0),
 561	F(9600000, P_XO, 2, 0, 0),
 562	F(16000000, P_GPLL0, 10, 1, 5),
 563	F(19200000, P_XO, 1, 0, 0),
 564	F(25000000, P_GPLL0, 16, 1, 2),
 565	F(50000000, P_GPLL0, 16, 0, 0),
 566	{ }
 567};
 568
 569static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 570	.cmd_rcgr = 0x02024,
 571	.mnd_width = 8,
 572	.hid_width = 5,
 573	.parent_map = gcc_xo_gpll0_map,
 574	.freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 575	.clkr.hw.init = &(struct clk_init_data){
 576		.name = "blsp1_qup1_spi_apps_clk_src",
 577		.parent_data = gcc_xo_gpll0,
 578		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 579		.ops = &clk_rcg2_ops,
 580	},
 581};
 582
 583static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 584	.cmd_rcgr = 0x03000,
 585	.hid_width = 5,
 586	.parent_map = gcc_xo_gpll0_map,
 587	.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 588	.clkr.hw.init = &(struct clk_init_data){
 589		.name = "blsp1_qup2_i2c_apps_clk_src",
 590		.parent_data = gcc_xo_gpll0,
 591		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 592		.ops = &clk_rcg2_ops,
 593	},
 594};
 595
 596static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 597	.cmd_rcgr = 0x03014,
 598	.mnd_width = 8,
 599	.hid_width = 5,
 600	.parent_map = gcc_xo_gpll0_map,
 601	.freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 602	.clkr.hw.init = &(struct clk_init_data){
 603		.name = "blsp1_qup2_spi_apps_clk_src",
 604		.parent_data = gcc_xo_gpll0,
 605		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 606		.ops = &clk_rcg2_ops,
 607	},
 608};
 609
 610static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 611	.cmd_rcgr = 0x04000,
 612	.hid_width = 5,
 613	.parent_map = gcc_xo_gpll0_map,
 614	.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 615	.clkr.hw.init = &(struct clk_init_data){
 616		.name = "blsp1_qup3_i2c_apps_clk_src",
 617		.parent_data = gcc_xo_gpll0,
 618		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 619		.ops = &clk_rcg2_ops,
 620	},
 621};
 622
 623static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 624	.cmd_rcgr = 0x04024,
 625	.mnd_width = 8,
 626	.hid_width = 5,
 627	.parent_map = gcc_xo_gpll0_map,
 628	.freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 629	.clkr.hw.init = &(struct clk_init_data){
 630		.name = "blsp1_qup3_spi_apps_clk_src",
 631		.parent_data = gcc_xo_gpll0,
 632		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 633		.ops = &clk_rcg2_ops,
 634	},
 635};
 636
 637static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 638	.cmd_rcgr = 0x05000,
 639	.hid_width = 5,
 640	.parent_map = gcc_xo_gpll0_map,
 641	.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 642	.clkr.hw.init = &(struct clk_init_data){
 643		.name = "blsp1_qup4_i2c_apps_clk_src",
 644		.parent_data = gcc_xo_gpll0,
 645		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 646		.ops = &clk_rcg2_ops,
 647	},
 648};
 649
 650static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 651	.cmd_rcgr = 0x05024,
 652	.mnd_width = 8,
 653	.hid_width = 5,
 654	.parent_map = gcc_xo_gpll0_map,
 655	.freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 656	.clkr.hw.init = &(struct clk_init_data){
 657		.name = "blsp1_qup4_spi_apps_clk_src",
 658		.parent_data = gcc_xo_gpll0,
 659		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 660		.ops = &clk_rcg2_ops,
 661	},
 662};
 663
 664static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 665	.cmd_rcgr = 0x06000,
 666	.hid_width = 5,
 667	.parent_map = gcc_xo_gpll0_map,
 668	.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 669	.clkr.hw.init = &(struct clk_init_data){
 670		.name = "blsp1_qup5_i2c_apps_clk_src",
 671		.parent_data = gcc_xo_gpll0,
 672		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 673		.ops = &clk_rcg2_ops,
 674	},
 675};
 676
 677static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 678	.cmd_rcgr = 0x06024,
 679	.mnd_width = 8,
 680	.hid_width = 5,
 681	.parent_map = gcc_xo_gpll0_map,
 682	.freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 683	.clkr.hw.init = &(struct clk_init_data){
 684		.name = "blsp1_qup5_spi_apps_clk_src",
 685		.parent_data = gcc_xo_gpll0,
 686		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 687		.ops = &clk_rcg2_ops,
 688	},
 689};
 690
 691static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 692	.cmd_rcgr = 0x07000,
 693	.hid_width = 5,
 694	.parent_map = gcc_xo_gpll0_map,
 695	.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 696	.clkr.hw.init = &(struct clk_init_data){
 697		.name = "blsp1_qup6_i2c_apps_clk_src",
 698		.parent_data = gcc_xo_gpll0,
 699		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 700		.ops = &clk_rcg2_ops,
 701	},
 702};
 703
 704static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 705	.cmd_rcgr = 0x07024,
 706	.mnd_width = 8,
 707	.hid_width = 5,
 708	.parent_map = gcc_xo_gpll0_map,
 709	.freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 710	.clkr.hw.init = &(struct clk_init_data){
 711		.name = "blsp1_qup6_spi_apps_clk_src",
 712		.parent_data = gcc_xo_gpll0,
 713		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 714		.ops = &clk_rcg2_ops,
 715	},
 716};
 717
 718static const struct freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = {
 719	F(3686400, P_GPLL0, 1, 72, 15625),
 720	F(7372800, P_GPLL0, 1, 144, 15625),
 721	F(14745600, P_GPLL0, 1, 288, 15625),
 722	F(16000000, P_GPLL0, 10, 1, 5),
 723	F(19200000, P_XO, 1, 0, 0),
 724	F(24000000, P_GPLL0, 1, 3, 100),
 725	F(25000000, P_GPLL0, 16, 1, 2),
 726	F(32000000, P_GPLL0, 1, 1, 25),
 727	F(40000000, P_GPLL0, 1, 1, 20),
 728	F(46400000, P_GPLL0, 1, 29, 500),
 729	F(48000000, P_GPLL0, 1, 3, 50),
 730	F(51200000, P_GPLL0, 1, 8, 125),
 731	F(56000000, P_GPLL0, 1, 7, 100),
 732	F(58982400, P_GPLL0, 1, 1152, 15625),
 733	F(60000000, P_GPLL0, 1, 3, 40),
 734	{ }
 735};
 736
 737static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 738	.cmd_rcgr = 0x02044,
 739	.mnd_width = 16,
 740	.hid_width = 5,
 741	.parent_map = gcc_xo_gpll0_map,
 742	.freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
 743	.clkr.hw.init = &(struct clk_init_data){
 744		.name = "blsp1_uart1_apps_clk_src",
 745		.parent_data = gcc_xo_gpll0,
 746		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 747		.ops = &clk_rcg2_ops,
 748	},
 749};
 750
 751static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 752	.cmd_rcgr = 0x03034,
 753	.mnd_width = 16,
 754	.hid_width = 5,
 755	.parent_map = gcc_xo_gpll0_map,
 756	.freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
 757	.clkr.hw.init = &(struct clk_init_data){
 758		.name = "blsp1_uart2_apps_clk_src",
 759		.parent_data = gcc_xo_gpll0,
 760		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 761		.ops = &clk_rcg2_ops,
 762	},
 763};
 764
 765static const struct freq_tbl ftbl_gcc_camss_cci_clk[] = {
 766	F(19200000,	P_XO, 1, 0,	0),
 767	{ }
 768};
 769
 770static struct clk_rcg2 cci_clk_src = {
 771	.cmd_rcgr = 0x51000,
 772	.mnd_width = 8,
 773	.hid_width = 5,
 774	.parent_map = gcc_xo_gpll0a_map,
 775	.freq_tbl = ftbl_gcc_camss_cci_clk,
 776	.clkr.hw.init = &(struct clk_init_data){
 777		.name = "cci_clk_src",
 778		.parent_data = gcc_xo_gpll0a,
 779		.num_parents = ARRAY_SIZE(gcc_xo_gpll0a),
 780		.ops = &clk_rcg2_ops,
 781	},
 782};
 783
 784/*
 785 * This is a frequency table for "General Purpose" clocks.
 786 * These clocks can be muxed to the SoC pins and may be used by
 787 * external devices. They're often used as PWM source.
 788 *
 789 * See comment at ftbl_gcc_gp1_3_clk.
 790 */
 791static const struct freq_tbl ftbl_gcc_camss_gp0_1_clk[] = {
 792	F(10000,   P_XO,    16,  1, 120),
 793	F(100000,  P_XO,    16,  1,  12),
 794	F(500000,  P_GPLL0, 16,  1, 100),
 795	F(1000000, P_GPLL0, 16,  1,  50),
 796	F(2500000, P_GPLL0, 16,  1,  20),
 797	F(5000000, P_GPLL0, 16,  1,  10),
 798	F(100000000, P_GPLL0, 8, 0, 0),
 799	F(200000000, P_GPLL0, 4, 0, 0),
 800	{ }
 801};
 802
 803static struct clk_rcg2 camss_gp0_clk_src = {
 804	.cmd_rcgr = 0x54000,
 805	.mnd_width = 8,
 806	.hid_width = 5,
 807	.parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
 808	.freq_tbl = ftbl_gcc_camss_gp0_1_clk,
 809	.clkr.hw.init = &(struct clk_init_data){
 810		.name = "camss_gp0_clk_src",
 811		.parent_data = gcc_xo_gpll0_gpll1a_sleep,
 812		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
 813		.ops = &clk_rcg2_ops,
 814	},
 815};
 816
 817static struct clk_rcg2 camss_gp1_clk_src = {
 818	.cmd_rcgr = 0x55000,
 819	.mnd_width = 8,
 820	.hid_width = 5,
 821	.parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
 822	.freq_tbl = ftbl_gcc_camss_gp0_1_clk,
 823	.clkr.hw.init = &(struct clk_init_data){
 824		.name = "camss_gp1_clk_src",
 825		.parent_data = gcc_xo_gpll0_gpll1a_sleep,
 826		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
 827		.ops = &clk_rcg2_ops,
 828	},
 829};
 830
 831static const struct freq_tbl ftbl_gcc_camss_jpeg0_clk[] = {
 832	F(133330000, P_GPLL0, 6, 0,	0),
 833	F(266670000, P_GPLL0, 3, 0,	0),
 834	F(320000000, P_GPLL0, 2.5, 0, 0),
 835	{ }
 836};
 837
 838static struct clk_rcg2 jpeg0_clk_src = {
 839	.cmd_rcgr = 0x57000,
 840	.hid_width = 5,
 841	.parent_map = gcc_xo_gpll0_map,
 842	.freq_tbl = ftbl_gcc_camss_jpeg0_clk,
 843	.clkr.hw.init = &(struct clk_init_data){
 844		.name = "jpeg0_clk_src",
 845		.parent_data = gcc_xo_gpll0,
 846		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 847		.ops = &clk_rcg2_ops,
 848	},
 849};
 850
 851static const struct freq_tbl ftbl_gcc_camss_mclk0_1_clk[] = {
 852	F(9600000, P_XO, 2, 0, 0),
 853	F(23880000, P_GPLL0, 1, 2, 67),
 854	F(66670000, P_GPLL0, 12, 0, 0),
 855	{ }
 856};
 857
 858static struct clk_rcg2 mclk0_clk_src = {
 859	.cmd_rcgr = 0x52000,
 860	.mnd_width = 8,
 861	.hid_width = 5,
 862	.parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
 863	.freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
 864	.clkr.hw.init = &(struct clk_init_data){
 865		.name = "mclk0_clk_src",
 866		.parent_data = gcc_xo_gpll0_gpll1a_sleep,
 867		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
 868		.ops = &clk_rcg2_ops,
 869	},
 870};
 871
 872static struct clk_rcg2 mclk1_clk_src = {
 873	.cmd_rcgr = 0x53000,
 874	.mnd_width = 8,
 875	.hid_width = 5,
 876	.parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
 877	.freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
 878	.clkr.hw.init = &(struct clk_init_data){
 879		.name = "mclk1_clk_src",
 880		.parent_data = gcc_xo_gpll0_gpll1a_sleep,
 881		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
 882		.ops = &clk_rcg2_ops,
 883	},
 884};
 885
 886static const struct freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk[] = {
 887	F(100000000, P_GPLL0, 8, 0,	0),
 888	F(200000000, P_GPLL0, 4, 0,	0),
 889	{ }
 890};
 891
 892static struct clk_rcg2 csi0phytimer_clk_src = {
 893	.cmd_rcgr = 0x4e000,
 894	.hid_width = 5,
 895	.parent_map = gcc_xo_gpll0_gpll1a_map,
 896	.freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
 897	.clkr.hw.init = &(struct clk_init_data){
 898		.name = "csi0phytimer_clk_src",
 899		.parent_data = gcc_xo_gpll0_gpll1a,
 900		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a),
 901		.ops = &clk_rcg2_ops,
 902	},
 903};
 904
 905static struct clk_rcg2 csi1phytimer_clk_src = {
 906	.cmd_rcgr = 0x4f000,
 907	.hid_width = 5,
 908	.parent_map = gcc_xo_gpll0_gpll1a_map,
 909	.freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
 910	.clkr.hw.init = &(struct clk_init_data){
 911		.name = "csi1phytimer_clk_src",
 912		.parent_data = gcc_xo_gpll0_gpll1a,
 913		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a),
 914		.ops = &clk_rcg2_ops,
 915	},
 916};
 917
 918static const struct freq_tbl ftbl_gcc_camss_cpp_clk[] = {
 919	F(160000000, P_GPLL0, 5, 0, 0),
 920	F(320000000, P_GPLL0, 2.5, 0, 0),
 921	F(465000000, P_GPLL2, 2, 0, 0),
 922	{ }
 923};
 924
 925static struct clk_rcg2 cpp_clk_src = {
 926	.cmd_rcgr = 0x58018,
 927	.hid_width = 5,
 928	.parent_map = gcc_xo_gpll0_gpll2_map,
 929	.freq_tbl = ftbl_gcc_camss_cpp_clk,
 930	.clkr.hw.init = &(struct clk_init_data){
 931		.name = "cpp_clk_src",
 932		.parent_data = gcc_xo_gpll0_gpll2,
 933		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
 934		.ops = &clk_rcg2_ops,
 935	},
 936};
 937
 938static const struct freq_tbl ftbl_gcc_crypto_clk[] = {
 939	F(50000000, P_GPLL0, 16, 0, 0),
 940	F(80000000, P_GPLL0, 10, 0, 0),
 941	F(100000000, P_GPLL0, 8, 0, 0),
 942	F(160000000, P_GPLL0, 5, 0, 0),
 943	{ }
 944};
 945
 946static struct clk_rcg2 crypto_clk_src = {
 947	.cmd_rcgr = 0x16004,
 948	.hid_width = 5,
 949	.parent_map = gcc_xo_gpll0_map,
 950	.freq_tbl = ftbl_gcc_crypto_clk,
 951	.clkr.hw.init = &(struct clk_init_data){
 952		.name = "crypto_clk_src",
 953		.parent_data = gcc_xo_gpll0,
 954		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 955		.ops = &clk_rcg2_ops,
 956	},
 957};
 958
 959/*
 960 * This is a frequency table for "General Purpose" clocks.
 961 * These clocks can be muxed to the SoC pins and may be used by
 962 * external devices. They're often used as PWM source.
 963 *
 964 * Please note that MND divider must be enabled for duty-cycle
 965 * control to be possible. (M != N) Also since D register is configured
 966 * with a value multiplied by 2, and duty cycle is calculated as
 967 *                             (2 * D) % 2^W
 968 *                DutyCycle = ----------------
 969 *                              2 * (N % 2^W)
 970 * (where W = .mnd_width)
 971 * N must be half or less than maximum value for the register.
 972 * Otherwise duty-cycle control would be limited.
 973 * (e.g. for 8-bit NMD N should be less than 128)
 974 */
 975static const struct freq_tbl ftbl_gcc_gp1_3_clk[] = {
 976	F(10000,   P_XO,    16,  1, 120),
 977	F(100000,  P_XO,    16,  1,  12),
 978	F(500000,  P_GPLL0, 16,  1, 100),
 979	F(1000000, P_GPLL0, 16,  1,  50),
 980	F(2500000, P_GPLL0, 16,  1,  20),
 981	F(5000000, P_GPLL0, 16,  1,  10),
 982	F(19200000, P_XO, 1, 0,	0),
 983	{ }
 984};
 985
 986static struct clk_rcg2 gp1_clk_src = {
 987	.cmd_rcgr = 0x08004,
 988	.mnd_width = 8,
 989	.hid_width = 5,
 990	.parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
 991	.freq_tbl = ftbl_gcc_gp1_3_clk,
 992	.clkr.hw.init = &(struct clk_init_data){
 993		.name = "gp1_clk_src",
 994		.parent_data = gcc_xo_gpll0_gpll1a_sleep,
 995		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
 996		.ops = &clk_rcg2_ops,
 997	},
 998};
 999
1000static struct clk_rcg2 gp2_clk_src = {
1001	.cmd_rcgr = 0x09004,
1002	.mnd_width = 8,
1003	.hid_width = 5,
1004	.parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
1005	.freq_tbl = ftbl_gcc_gp1_3_clk,
1006	.clkr.hw.init = &(struct clk_init_data){
1007		.name = "gp2_clk_src",
1008		.parent_data = gcc_xo_gpll0_gpll1a_sleep,
1009		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
1010		.ops = &clk_rcg2_ops,
1011	},
1012};
1013
1014static struct clk_rcg2 gp3_clk_src = {
1015	.cmd_rcgr = 0x0a004,
1016	.mnd_width = 8,
1017	.hid_width = 5,
1018	.parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
1019	.freq_tbl = ftbl_gcc_gp1_3_clk,
1020	.clkr.hw.init = &(struct clk_init_data){
1021		.name = "gp3_clk_src",
1022		.parent_data = gcc_xo_gpll0_gpll1a_sleep,
1023		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1a_sleep),
1024		.ops = &clk_rcg2_ops,
1025	},
1026};
1027
1028static struct clk_rcg2 byte0_clk_src = {
1029	.cmd_rcgr = 0x4d044,
1030	.hid_width = 5,
1031	.parent_map = gcc_xo_gpll0a_dsibyte_map,
1032	.clkr.hw.init = &(struct clk_init_data){
1033		.name = "byte0_clk_src",
1034		.parent_data = gcc_xo_gpll0a_dsibyte,
1035		.num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsibyte),
1036		.ops = &clk_byte2_ops,
1037		.flags = CLK_SET_RATE_PARENT,
1038	},
1039};
1040
1041static const struct freq_tbl ftbl_gcc_mdss_esc0_clk[] = {
1042	F(19200000, P_XO, 1, 0, 0),
1043	{ }
1044};
1045
1046static struct clk_rcg2 esc0_clk_src = {
1047	.cmd_rcgr = 0x4d05c,
1048	.hid_width = 5,
1049	.parent_map = gcc_xo_dsibyte_map,
1050	.freq_tbl = ftbl_gcc_mdss_esc0_clk,
1051	.clkr.hw.init = &(struct clk_init_data){
1052		.name = "esc0_clk_src",
1053		.parent_data = gcc_xo_dsibyte,
1054		.num_parents = ARRAY_SIZE(gcc_xo_dsibyte),
1055		.ops = &clk_rcg2_ops,
1056	},
1057};
1058
1059static const struct freq_tbl ftbl_gcc_mdss_mdp_clk[] = {
1060	F(50000000, P_GPLL0, 16, 0, 0),
1061	F(80000000, P_GPLL0, 10, 0, 0),
1062	F(100000000, P_GPLL0, 8, 0, 0),
1063	F(160000000, P_GPLL0, 5, 0, 0),
1064	F(177780000, P_GPLL0, 4.5, 0, 0),
1065	F(200000000, P_GPLL0, 4, 0, 0),
1066	F(266670000, P_GPLL0, 3, 0, 0),
1067	F(320000000, P_GPLL0, 2.5, 0, 0),
1068	{ }
1069};
1070
1071static struct clk_rcg2 mdp_clk_src = {
1072	.cmd_rcgr = 0x4d014,
1073	.hid_width = 5,
1074	.parent_map = gcc_xo_gpll0_dsiphy_map,
1075	.freq_tbl = ftbl_gcc_mdss_mdp_clk,
1076	.clkr.hw.init = &(struct clk_init_data){
1077		.name = "mdp_clk_src",
1078		.parent_data = gcc_xo_gpll0_dsiphy,
1079		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_dsiphy),
1080		.ops = &clk_rcg2_ops,
1081	},
1082};
1083
1084static struct clk_rcg2 pclk0_clk_src = {
1085	.cmd_rcgr = 0x4d000,
1086	.mnd_width = 8,
1087	.hid_width = 5,
1088	.parent_map = gcc_xo_gpll0a_dsiphy_map,
1089	.clkr.hw.init = &(struct clk_init_data){
1090		.name = "pclk0_clk_src",
1091		.parent_data = gcc_xo_gpll0a_dsiphy,
1092		.num_parents = ARRAY_SIZE(gcc_xo_gpll0a_dsiphy),
1093		.ops = &clk_pixel_ops,
1094		.flags = CLK_SET_RATE_PARENT,
1095	},
1096};
1097
1098static const struct freq_tbl ftbl_gcc_mdss_vsync_clk[] = {
1099	F(19200000, P_XO, 1, 0,	0),
1100	{ }
1101};
1102
1103static struct clk_rcg2 vsync_clk_src = {
1104	.cmd_rcgr = 0x4d02c,
1105	.hid_width = 5,
1106	.parent_map = gcc_xo_gpll0a_map,
1107	.freq_tbl = ftbl_gcc_mdss_vsync_clk,
1108	.clkr.hw.init = &(struct clk_init_data){
1109		.name = "vsync_clk_src",
1110		.parent_data = gcc_xo_gpll0a,
1111		.num_parents = ARRAY_SIZE(gcc_xo_gpll0a),
1112		.ops = &clk_rcg2_ops,
1113	},
1114};
1115
1116static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
1117	F(64000000, P_GPLL0, 12.5, 0, 0),
1118	{ }
1119};
1120
1121static struct clk_rcg2 pdm2_clk_src = {
1122	.cmd_rcgr = 0x44010,
1123	.hid_width = 5,
1124	.parent_map = gcc_xo_gpll0_map,
1125	.freq_tbl = ftbl_gcc_pdm2_clk,
1126	.clkr.hw.init = &(struct clk_init_data){
1127		.name = "pdm2_clk_src",
1128		.parent_data = gcc_xo_gpll0,
1129		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1130		.ops = &clk_rcg2_ops,
1131	},
1132};
1133
1134static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = {
1135	F(144000, P_XO, 16, 3, 25),
1136	F(400000, P_XO, 12, 1, 4),
1137	F(20000000, P_GPLL0, 10, 1, 4),
1138	F(25000000, P_GPLL0, 16, 1, 2),
1139	F(50000000, P_GPLL0, 16, 0, 0),
1140	F(100000000, P_GPLL0, 8, 0, 0),
1141	F(177770000, P_GPLL0, 4.5, 0, 0),
1142	{ }
1143};
1144
1145static struct clk_rcg2 sdcc1_apps_clk_src = {
1146	.cmd_rcgr = 0x42004,
1147	.mnd_width = 8,
1148	.hid_width = 5,
1149	.parent_map = gcc_xo_gpll0_map,
1150	.freq_tbl = ftbl_gcc_sdcc1_apps_clk,
1151	.clkr.hw.init = &(struct clk_init_data){
1152		.name = "sdcc1_apps_clk_src",
1153		.parent_data = gcc_xo_gpll0,
1154		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1155		.ops = &clk_rcg2_floor_ops,
1156	},
1157};
1158
1159static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk[] = {
1160	F(144000, P_XO, 16, 3, 25),
1161	F(400000, P_XO, 12, 1, 4),
1162	F(20000000, P_GPLL0, 10, 1, 4),
1163	F(25000000, P_GPLL0, 16, 1, 2),
1164	F(50000000, P_GPLL0, 16, 0, 0),
1165	F(100000000, P_GPLL0, 8, 0, 0),
1166	F(200000000, P_GPLL0, 4, 0, 0),
1167	{ }
1168};
1169
1170static struct clk_rcg2 sdcc2_apps_clk_src = {
1171	.cmd_rcgr = 0x43004,
1172	.mnd_width = 8,
1173	.hid_width = 5,
1174	.parent_map = gcc_xo_gpll0_map,
1175	.freq_tbl = ftbl_gcc_sdcc2_apps_clk,
1176	.clkr.hw.init = &(struct clk_init_data){
1177		.name = "sdcc2_apps_clk_src",
1178		.parent_data = gcc_xo_gpll0,
1179		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1180		.ops = &clk_rcg2_floor_ops,
1181	},
1182};
1183
1184static const struct freq_tbl ftbl_gcc_apss_tcu_clk[] = {
1185	F(155000000, P_GPLL2, 6, 0, 0),
1186	F(310000000, P_GPLL2, 3, 0, 0),
1187	F(400000000, P_GPLL0, 2, 0, 0),
1188	{ }
1189};
1190
1191static struct clk_rcg2 apss_tcu_clk_src = {
1192	.cmd_rcgr = 0x1207c,
1193	.hid_width = 5,
1194	.parent_map = gcc_xo_gpll0a_gpll1_gpll2_map,
1195	.freq_tbl = ftbl_gcc_apss_tcu_clk,
1196	.clkr.hw.init = &(struct clk_init_data){
1197		.name = "apss_tcu_clk_src",
1198		.parent_data = gcc_xo_gpll0a_gpll1_gpll2,
1199		.num_parents = ARRAY_SIZE(gcc_xo_gpll0a_gpll1_gpll2),
1200		.ops = &clk_rcg2_ops,
1201	},
1202};
1203
1204static const struct freq_tbl ftbl_gcc_bimc_gpu_clk[] = {
1205	F(19200000, P_XO, 1, 0, 0),
1206	F(100000000, P_GPLL0, 8, 0, 0),
1207	F(200000000, P_GPLL0, 4, 0, 0),
1208	F(266500000, P_BIMC, 4, 0, 0),
1209	F(400000000, P_GPLL0, 2, 0, 0),
1210	F(533000000, P_BIMC, 2, 0, 0),
1211	{ }
1212};
1213
1214static struct clk_rcg2 bimc_gpu_clk_src = {
1215	.cmd_rcgr = 0x31028,
1216	.hid_width = 5,
1217	.parent_map = gcc_xo_gpll0_bimc_map,
1218	.freq_tbl = ftbl_gcc_bimc_gpu_clk,
1219	.clkr.hw.init = &(struct clk_init_data){
1220		.name = "bimc_gpu_clk_src",
1221		.parent_data = gcc_xo_gpll0_bimc,
1222		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc),
1223		.flags = CLK_GET_RATE_NOCACHE,
1224		.ops = &clk_rcg2_ops,
1225	},
1226};
1227
1228static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
1229	F(80000000, P_GPLL0, 10, 0, 0),
1230	{ }
1231};
1232
1233static struct clk_rcg2 usb_hs_system_clk_src = {
1234	.cmd_rcgr = 0x41010,
1235	.hid_width = 5,
1236	.parent_map = gcc_xo_gpll0_map,
1237	.freq_tbl = ftbl_gcc_usb_hs_system_clk,
1238	.clkr.hw.init = &(struct clk_init_data){
1239		.name = "usb_hs_system_clk_src",
1240		.parent_data = gcc_xo_gpll0,
1241		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1242		.ops = &clk_rcg2_ops,
1243	},
1244};
1245
1246static const struct freq_tbl ftbl_gcc_ultaudio_ahb_clk[] = {
1247	F(3200000, P_XO, 6, 0, 0),
1248	F(6400000, P_XO, 3, 0, 0),
1249	F(9600000, P_XO, 2, 0, 0),
1250	F(19200000, P_XO, 1, 0, 0),
1251	F(40000000, P_GPLL0, 10, 1, 2),
1252	F(66670000, P_GPLL0, 12, 0, 0),
1253	F(80000000, P_GPLL0, 10, 0, 0),
1254	F(100000000, P_GPLL0, 8, 0, 0),
1255	{ }
1256};
1257
1258static struct clk_rcg2 ultaudio_ahbfabric_clk_src = {
1259	.cmd_rcgr = 0x1c010,
1260	.hid_width = 5,
1261	.mnd_width = 8,
1262	.parent_map = gcc_xo_gpll0_gpll1_sleep_map,
1263	.freq_tbl = ftbl_gcc_ultaudio_ahb_clk,
1264	.clkr.hw.init = &(struct clk_init_data){
1265		.name = "ultaudio_ahbfabric_clk_src",
1266		.parent_data = gcc_xo_gpll0_gpll1_sleep,
1267		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_sleep),
1268		.ops = &clk_rcg2_ops,
1269	},
1270};
1271
1272static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_clk = {
1273	.halt_reg = 0x1c028,
1274	.clkr = {
1275		.enable_reg = 0x1c028,
1276		.enable_mask = BIT(0),
1277		.hw.init = &(struct clk_init_data){
1278			.name = "gcc_ultaudio_ahbfabric_ixfabric_clk",
1279			.parent_hws = (const struct clk_hw*[]){
1280				&ultaudio_ahbfabric_clk_src.clkr.hw,
1281			},
1282			.num_parents = 1,
1283			.flags = CLK_SET_RATE_PARENT,
1284			.ops = &clk_branch2_ops,
1285		},
1286	},
1287};
1288
1289static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_lpm_clk = {
1290	.halt_reg = 0x1c024,
1291	.clkr = {
1292		.enable_reg = 0x1c024,
1293		.enable_mask = BIT(0),
1294		.hw.init = &(struct clk_init_data){
1295			.name = "gcc_ultaudio_ahbfabric_ixfabric_lpm_clk",
1296			.parent_hws = (const struct clk_hw*[]){
1297				&ultaudio_ahbfabric_clk_src.clkr.hw,
1298			},
1299			.num_parents = 1,
1300			.flags = CLK_SET_RATE_PARENT,
1301			.ops = &clk_branch2_ops,
1302		},
1303	},
1304};
1305
1306static const struct freq_tbl ftbl_gcc_ultaudio_lpaif_i2s_clk[] = {
1307	F(128000, P_XO, 10, 1, 15),
1308	F(256000, P_XO, 5, 1, 15),
1309	F(384000, P_XO, 5, 1, 10),
1310	F(512000, P_XO, 5, 2, 15),
1311	F(576000, P_XO, 5, 3, 20),
1312	F(705600, P_GPLL1, 16, 1, 80),
1313	F(768000, P_XO, 5, 1, 5),
1314	F(800000, P_XO, 5, 5, 24),
1315	F(1024000, P_XO, 5, 4, 15),
1316	F(1152000, P_XO, 1, 3, 50),
1317	F(1411200, P_GPLL1, 16, 1, 40),
1318	F(1536000, P_XO, 1, 2, 25),
1319	F(1600000, P_XO, 12, 0, 0),
1320	F(1728000, P_XO, 5, 9, 20),
1321	F(2048000, P_XO, 5, 8, 15),
1322	F(2304000, P_XO, 5, 3, 5),
1323	F(2400000, P_XO, 8, 0, 0),
1324	F(2822400, P_GPLL1, 16, 1, 20),
1325	F(3072000, P_XO, 5, 4, 5),
1326	F(4096000, P_GPLL1, 9, 2, 49),
1327	F(4800000, P_XO, 4, 0, 0),
1328	F(5644800, P_GPLL1, 16, 1, 10),
1329	F(6144000, P_GPLL1, 7, 1, 21),
1330	F(8192000, P_GPLL1, 9, 4, 49),
1331	F(9600000, P_XO, 2, 0, 0),
1332	F(11289600, P_GPLL1, 16, 1, 5),
1333	F(12288000, P_GPLL1, 7, 2, 21),
1334	{ }
1335};
1336
1337static struct clk_rcg2 ultaudio_lpaif_pri_i2s_clk_src = {
1338	.cmd_rcgr = 0x1c054,
1339	.hid_width = 5,
1340	.mnd_width = 8,
1341	.parent_map = gcc_xo_gpll1_epi2s_emclk_sleep_map,
1342	.freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
1343	.clkr.hw.init = &(struct clk_init_data){
1344		.name = "ultaudio_lpaif_pri_i2s_clk_src",
1345		.parent_data = gcc_xo_gpll1_epi2s_emclk_sleep,
1346		.num_parents = ARRAY_SIZE(gcc_xo_gpll1_epi2s_emclk_sleep),
1347		.ops = &clk_rcg2_ops,
1348	},
1349};
1350
1351static struct clk_branch gcc_ultaudio_lpaif_pri_i2s_clk = {
1352	.halt_reg = 0x1c068,
1353	.clkr = {
1354		.enable_reg = 0x1c068,
1355		.enable_mask = BIT(0),
1356		.hw.init = &(struct clk_init_data){
1357			.name = "gcc_ultaudio_lpaif_pri_i2s_clk",
1358			.parent_hws = (const struct clk_hw*[]){
1359				&ultaudio_lpaif_pri_i2s_clk_src.clkr.hw,
1360			},
1361			.num_parents = 1,
1362			.flags = CLK_SET_RATE_PARENT,
1363			.ops = &clk_branch2_ops,
1364		},
1365	},
1366};
1367
1368static struct clk_rcg2 ultaudio_lpaif_sec_i2s_clk_src = {
1369	.cmd_rcgr = 0x1c06c,
1370	.hid_width = 5,
1371	.mnd_width = 8,
1372	.parent_map = gcc_xo_gpll1_esi2s_emclk_sleep_map,
1373	.freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
1374	.clkr.hw.init = &(struct clk_init_data){
1375		.name = "ultaudio_lpaif_sec_i2s_clk_src",
1376		.parent_data = gcc_xo_gpll1_esi2s_emclk_sleep,
1377		.num_parents = ARRAY_SIZE(gcc_xo_gpll1_esi2s_emclk_sleep),
1378		.ops = &clk_rcg2_ops,
1379	},
1380};
1381
1382static struct clk_branch gcc_ultaudio_lpaif_sec_i2s_clk = {
1383	.halt_reg = 0x1c080,
1384	.clkr = {
1385		.enable_reg = 0x1c080,
1386		.enable_mask = BIT(0),
1387		.hw.init = &(struct clk_init_data){
1388			.name = "gcc_ultaudio_lpaif_sec_i2s_clk",
1389			.parent_hws = (const struct clk_hw*[]){
1390				&ultaudio_lpaif_sec_i2s_clk_src.clkr.hw,
1391			},
1392			.num_parents = 1,
1393			.flags = CLK_SET_RATE_PARENT,
1394			.ops = &clk_branch2_ops,
1395		},
1396	},
1397};
1398
1399static struct clk_rcg2 ultaudio_lpaif_aux_i2s_clk_src = {
1400	.cmd_rcgr = 0x1c084,
1401	.hid_width = 5,
1402	.mnd_width = 8,
1403	.parent_map = gcc_xo_gpll1_emclk_sleep_map,
1404	.freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
1405	.clkr.hw.init = &(struct clk_init_data){
1406		.name = "ultaudio_lpaif_aux_i2s_clk_src",
1407		.parent_data = gcc_xo_gpll1_esi2s_emclk_sleep,
1408		.num_parents = ARRAY_SIZE(gcc_xo_gpll1_esi2s_emclk_sleep),
1409		.ops = &clk_rcg2_ops,
1410	},
1411};
1412
1413static struct clk_branch gcc_ultaudio_lpaif_aux_i2s_clk = {
1414	.halt_reg = 0x1c098,
1415	.clkr = {
1416		.enable_reg = 0x1c098,
1417		.enable_mask = BIT(0),
1418		.hw.init = &(struct clk_init_data){
1419			.name = "gcc_ultaudio_lpaif_aux_i2s_clk",
1420			.parent_hws = (const struct clk_hw*[]){
1421				&ultaudio_lpaif_aux_i2s_clk_src.clkr.hw,
1422			},
1423			.num_parents = 1,
1424			.flags = CLK_SET_RATE_PARENT,
1425			.ops = &clk_branch2_ops,
1426		},
1427	},
1428};
1429
1430static const struct freq_tbl ftbl_gcc_ultaudio_xo_clk[] = {
1431	F(19200000, P_XO, 1, 0, 0),
1432	{ }
1433};
1434
1435static struct clk_rcg2 ultaudio_xo_clk_src = {
1436	.cmd_rcgr = 0x1c034,
1437	.hid_width = 5,
1438	.parent_map = gcc_xo_sleep_map,
1439	.freq_tbl = ftbl_gcc_ultaudio_xo_clk,
1440	.clkr.hw.init = &(struct clk_init_data){
1441		.name = "ultaudio_xo_clk_src",
1442		.parent_data = gcc_xo_sleep,
1443		.num_parents = ARRAY_SIZE(gcc_xo_sleep),
1444		.ops = &clk_rcg2_ops,
1445	},
1446};
1447
1448static struct clk_branch gcc_ultaudio_avsync_xo_clk = {
1449	.halt_reg = 0x1c04c,
1450	.clkr = {
1451		.enable_reg = 0x1c04c,
1452		.enable_mask = BIT(0),
1453		.hw.init = &(struct clk_init_data){
1454			.name = "gcc_ultaudio_avsync_xo_clk",
1455			.parent_hws = (const struct clk_hw*[]){
1456				&ultaudio_xo_clk_src.clkr.hw,
1457			},
1458			.num_parents = 1,
1459			.flags = CLK_SET_RATE_PARENT,
1460			.ops = &clk_branch2_ops,
1461		},
1462	},
1463};
1464
1465static struct clk_branch gcc_ultaudio_stc_xo_clk = {
1466	.halt_reg = 0x1c050,
1467	.clkr = {
1468		.enable_reg = 0x1c050,
1469		.enable_mask = BIT(0),
1470		.hw.init = &(struct clk_init_data){
1471			.name = "gcc_ultaudio_stc_xo_clk",
1472			.parent_hws = (const struct clk_hw*[]){
1473				&ultaudio_xo_clk_src.clkr.hw,
1474			},
1475			.num_parents = 1,
1476			.flags = CLK_SET_RATE_PARENT,
1477			.ops = &clk_branch2_ops,
1478		},
1479	},
1480};
1481
1482static const struct freq_tbl ftbl_codec_clk[] = {
1483	F(9600000, P_XO, 2, 0, 0),
1484	F(12288000, P_XO, 1, 16, 25),
1485	F(19200000, P_XO, 1, 0, 0),
1486	F(11289600, P_EXT_MCLK, 1, 0, 0),
1487	{ }
1488};
1489
1490static struct clk_rcg2 codec_digcodec_clk_src = {
1491	.cmd_rcgr = 0x1c09c,
1492	.mnd_width = 8,
1493	.hid_width = 5,
1494	.parent_map = gcc_xo_gpll1_emclk_sleep_map,
1495	.freq_tbl = ftbl_codec_clk,
1496	.clkr.hw.init = &(struct clk_init_data){
1497		.name = "codec_digcodec_clk_src",
1498		.parent_data = gcc_xo_gpll1_emclk_sleep,
1499		.num_parents = ARRAY_SIZE(gcc_xo_gpll1_emclk_sleep),
1500		.ops = &clk_rcg2_ops,
1501	},
1502};
1503
1504static struct clk_branch gcc_codec_digcodec_clk = {
1505	.halt_reg = 0x1c0b0,
1506	.clkr = {
1507		.enable_reg = 0x1c0b0,
1508		.enable_mask = BIT(0),
1509		.hw.init = &(struct clk_init_data){
1510			.name = "gcc_ultaudio_codec_digcodec_clk",
1511			.parent_hws = (const struct clk_hw*[]){
1512				&codec_digcodec_clk_src.clkr.hw,
1513			},
1514			.num_parents = 1,
1515			.flags = CLK_SET_RATE_PARENT,
1516			.ops = &clk_branch2_ops,
1517		},
1518	},
1519};
1520
1521static struct clk_branch gcc_ultaudio_pcnoc_mport_clk = {
1522	.halt_reg = 0x1c000,
1523	.clkr = {
1524		.enable_reg = 0x1c000,
1525		.enable_mask = BIT(0),
1526		.hw.init = &(struct clk_init_data){
1527			.name = "gcc_ultaudio_pcnoc_mport_clk",
1528			.parent_hws = (const struct clk_hw*[]){
1529				&pcnoc_bfdcd_clk_src.clkr.hw,
1530			},
1531			.num_parents = 1,
1532			.ops = &clk_branch2_ops,
1533		},
1534	},
1535};
1536
1537static struct clk_branch gcc_ultaudio_pcnoc_sway_clk = {
1538	.halt_reg = 0x1c004,
1539	.clkr = {
1540		.enable_reg = 0x1c004,
1541		.enable_mask = BIT(0),
1542		.hw.init = &(struct clk_init_data){
1543			.name = "gcc_ultaudio_pcnoc_sway_clk",
1544			.parent_hws = (const struct clk_hw*[]){
1545				&pcnoc_bfdcd_clk_src.clkr.hw,
1546			},
1547			.num_parents = 1,
1548			.ops = &clk_branch2_ops,
1549		},
1550	},
1551};
1552
1553static const struct freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = {
1554	F(100000000, P_GPLL0, 8, 0, 0),
1555	F(160000000, P_GPLL0, 5, 0, 0),
1556	F(228570000, P_GPLL0, 3.5, 0, 0),
1557	{ }
1558};
1559
1560static struct clk_rcg2 vcodec0_clk_src = {
1561	.cmd_rcgr = 0x4C000,
1562	.mnd_width = 8,
1563	.hid_width = 5,
1564	.parent_map = gcc_xo_gpll0_map,
1565	.freq_tbl = ftbl_gcc_venus0_vcodec0_clk,
1566	.clkr.hw.init = &(struct clk_init_data){
1567		.name = "vcodec0_clk_src",
1568		.parent_data = gcc_xo_gpll0,
1569		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1570		.ops = &clk_rcg2_ops,
1571	},
1572};
1573
1574static struct clk_branch gcc_blsp1_ahb_clk = {
1575	.halt_reg = 0x01008,
1576	.halt_check = BRANCH_HALT_VOTED,
1577	.clkr = {
1578		.enable_reg = 0x45004,
1579		.enable_mask = BIT(10),
1580		.hw.init = &(struct clk_init_data){
1581			.name = "gcc_blsp1_ahb_clk",
1582			.parent_hws = (const struct clk_hw*[]){
1583				&pcnoc_bfdcd_clk_src.clkr.hw,
1584			},
1585			.num_parents = 1,
1586			.ops = &clk_branch2_ops,
1587		},
1588	},
1589};
1590
1591static struct clk_branch gcc_blsp1_sleep_clk = {
1592	.halt_reg = 0x01004,
1593	.clkr = {
1594		.enable_reg = 0x01004,
1595		.enable_mask = BIT(0),
1596		.hw.init = &(struct clk_init_data){
1597			.name = "gcc_blsp1_sleep_clk",
1598			.parent_data = &(const struct clk_parent_data){
1599				.fw_name = "sleep_clk", .name = "sleep_clk_src",
1600			},
1601			.num_parents = 1,
1602			.flags = CLK_SET_RATE_PARENT,
1603			.ops = &clk_branch2_ops,
1604		},
1605	},
1606};
1607
1608static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1609	.halt_reg = 0x02008,
1610	.clkr = {
1611		.enable_reg = 0x02008,
1612		.enable_mask = BIT(0),
1613		.hw.init = &(struct clk_init_data){
1614			.name = "gcc_blsp1_qup1_i2c_apps_clk",
1615			.parent_hws = (const struct clk_hw*[]){
1616				&blsp1_qup1_i2c_apps_clk_src.clkr.hw,
1617			},
1618			.num_parents = 1,
1619			.flags = CLK_SET_RATE_PARENT,
1620			.ops = &clk_branch2_ops,
1621		},
1622	},
1623};
1624
1625static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1626	.halt_reg = 0x02004,
1627	.clkr = {
1628		.enable_reg = 0x02004,
1629		.enable_mask = BIT(0),
1630		.hw.init = &(struct clk_init_data){
1631			.name = "gcc_blsp1_qup1_spi_apps_clk",
1632			.parent_hws = (const struct clk_hw*[]){
1633				&blsp1_qup1_spi_apps_clk_src.clkr.hw,
1634			},
1635			.num_parents = 1,
1636			.flags = CLK_SET_RATE_PARENT,
1637			.ops = &clk_branch2_ops,
1638		},
1639	},
1640};
1641
1642static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1643	.halt_reg = 0x03010,
1644	.clkr = {
1645		.enable_reg = 0x03010,
1646		.enable_mask = BIT(0),
1647		.hw.init = &(struct clk_init_data){
1648			.name = "gcc_blsp1_qup2_i2c_apps_clk",
1649			.parent_hws = (const struct clk_hw*[]){
1650				&blsp1_qup2_i2c_apps_clk_src.clkr.hw,
1651			},
1652			.num_parents = 1,
1653			.flags = CLK_SET_RATE_PARENT,
1654			.ops = &clk_branch2_ops,
1655		},
1656	},
1657};
1658
1659static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1660	.halt_reg = 0x0300c,
1661	.clkr = {
1662		.enable_reg = 0x0300c,
1663		.enable_mask = BIT(0),
1664		.hw.init = &(struct clk_init_data){
1665			.name = "gcc_blsp1_qup2_spi_apps_clk",
1666			.parent_hws = (const struct clk_hw*[]){
1667				&blsp1_qup2_spi_apps_clk_src.clkr.hw,
1668			},
1669			.num_parents = 1,
1670			.flags = CLK_SET_RATE_PARENT,
1671			.ops = &clk_branch2_ops,
1672		},
1673	},
1674};
1675
1676static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1677	.halt_reg = 0x04020,
1678	.clkr = {
1679		.enable_reg = 0x04020,
1680		.enable_mask = BIT(0),
1681		.hw.init = &(struct clk_init_data){
1682			.name = "gcc_blsp1_qup3_i2c_apps_clk",
1683			.parent_hws = (const struct clk_hw*[]){
1684				&blsp1_qup3_i2c_apps_clk_src.clkr.hw,
1685			},
1686			.num_parents = 1,
1687			.flags = CLK_SET_RATE_PARENT,
1688			.ops = &clk_branch2_ops,
1689		},
1690	},
1691};
1692
1693static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1694	.halt_reg = 0x0401c,
1695	.clkr = {
1696		.enable_reg = 0x0401c,
1697		.enable_mask = BIT(0),
1698		.hw.init = &(struct clk_init_data){
1699			.name = "gcc_blsp1_qup3_spi_apps_clk",
1700			.parent_hws = (const struct clk_hw*[]){
1701				&blsp1_qup3_spi_apps_clk_src.clkr.hw,
1702			},
1703			.num_parents = 1,
1704			.flags = CLK_SET_RATE_PARENT,
1705			.ops = &clk_branch2_ops,
1706		},
1707	},
1708};
1709
1710static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1711	.halt_reg = 0x05020,
1712	.clkr = {
1713		.enable_reg = 0x05020,
1714		.enable_mask = BIT(0),
1715		.hw.init = &(struct clk_init_data){
1716			.name = "gcc_blsp1_qup4_i2c_apps_clk",
1717			.parent_hws = (const struct clk_hw*[]){
1718				&blsp1_qup4_i2c_apps_clk_src.clkr.hw,
1719			},
1720			.num_parents = 1,
1721			.flags = CLK_SET_RATE_PARENT,
1722			.ops = &clk_branch2_ops,
1723		},
1724	},
1725};
1726
1727static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1728	.halt_reg = 0x0501c,
1729	.clkr = {
1730		.enable_reg = 0x0501c,
1731		.enable_mask = BIT(0),
1732		.hw.init = &(struct clk_init_data){
1733			.name = "gcc_blsp1_qup4_spi_apps_clk",
1734			.parent_hws = (const struct clk_hw*[]){
1735				&blsp1_qup4_spi_apps_clk_src.clkr.hw,
1736			},
1737			.num_parents = 1,
1738			.flags = CLK_SET_RATE_PARENT,
1739			.ops = &clk_branch2_ops,
1740		},
1741	},
1742};
1743
1744static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1745	.halt_reg = 0x06020,
1746	.clkr = {
1747		.enable_reg = 0x06020,
1748		.enable_mask = BIT(0),
1749		.hw.init = &(struct clk_init_data){
1750			.name = "gcc_blsp1_qup5_i2c_apps_clk",
1751			.parent_hws = (const struct clk_hw*[]){
1752				&blsp1_qup5_i2c_apps_clk_src.clkr.hw,
1753			},
1754			.num_parents = 1,
1755			.flags = CLK_SET_RATE_PARENT,
1756			.ops = &clk_branch2_ops,
1757		},
1758	},
1759};
1760
1761static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1762	.halt_reg = 0x0601c,
1763	.clkr = {
1764		.enable_reg = 0x0601c,
1765		.enable_mask = BIT(0),
1766		.hw.init = &(struct clk_init_data){
1767			.name = "gcc_blsp1_qup5_spi_apps_clk",
1768			.parent_hws = (const struct clk_hw*[]){
1769				&blsp1_qup5_spi_apps_clk_src.clkr.hw,
1770			},
1771			.num_parents = 1,
1772			.flags = CLK_SET_RATE_PARENT,
1773			.ops = &clk_branch2_ops,
1774		},
1775	},
1776};
1777
1778static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1779	.halt_reg = 0x07020,
1780	.clkr = {
1781		.enable_reg = 0x07020,
1782		.enable_mask = BIT(0),
1783		.hw.init = &(struct clk_init_data){
1784			.name = "gcc_blsp1_qup6_i2c_apps_clk",
1785			.parent_hws = (const struct clk_hw*[]){
1786				&blsp1_qup6_i2c_apps_clk_src.clkr.hw,
1787			},
1788			.num_parents = 1,
1789			.flags = CLK_SET_RATE_PARENT,
1790			.ops = &clk_branch2_ops,
1791		},
1792	},
1793};
1794
1795static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1796	.halt_reg = 0x0701c,
1797	.clkr = {
1798		.enable_reg = 0x0701c,
1799		.enable_mask = BIT(0),
1800		.hw.init = &(struct clk_init_data){
1801			.name = "gcc_blsp1_qup6_spi_apps_clk",
1802			.parent_hws = (const struct clk_hw*[]){
1803				&blsp1_qup6_spi_apps_clk_src.clkr.hw,
1804			},
1805			.num_parents = 1,
1806			.flags = CLK_SET_RATE_PARENT,
1807			.ops = &clk_branch2_ops,
1808		},
1809	},
1810};
1811
1812static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1813	.halt_reg = 0x0203c,
1814	.clkr = {
1815		.enable_reg = 0x0203c,
1816		.enable_mask = BIT(0),
1817		.hw.init = &(struct clk_init_data){
1818			.name = "gcc_blsp1_uart1_apps_clk",
1819			.parent_hws = (const struct clk_hw*[]){
1820				&blsp1_uart1_apps_clk_src.clkr.hw,
1821			},
1822			.num_parents = 1,
1823			.flags = CLK_SET_RATE_PARENT,
1824			.ops = &clk_branch2_ops,
1825		},
1826	},
1827};
1828
1829static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1830	.halt_reg = 0x0302c,
1831	.clkr = {
1832		.enable_reg = 0x0302c,
1833		.enable_mask = BIT(0),
1834		.hw.init = &(struct clk_init_data){
1835			.name = "gcc_blsp1_uart2_apps_clk",
1836			.parent_hws = (const struct clk_hw*[]){
1837				&blsp1_uart2_apps_clk_src.clkr.hw,
1838			},
1839			.num_parents = 1,
1840			.flags = CLK_SET_RATE_PARENT,
1841			.ops = &clk_branch2_ops,
1842		},
1843	},
1844};
1845
1846static struct clk_branch gcc_boot_rom_ahb_clk = {
1847	.halt_reg = 0x1300c,
1848	.halt_check = BRANCH_HALT_VOTED,
1849	.clkr = {
1850		.enable_reg = 0x45004,
1851		.enable_mask = BIT(7),
1852		.hw.init = &(struct clk_init_data){
1853			.name = "gcc_boot_rom_ahb_clk",
1854			.parent_hws = (const struct clk_hw*[]){
1855				&pcnoc_bfdcd_clk_src.clkr.hw,
1856			},
1857			.num_parents = 1,
1858			.ops = &clk_branch2_ops,
1859		},
1860	},
1861};
1862
1863static struct clk_branch gcc_camss_cci_ahb_clk = {
1864	.halt_reg = 0x5101c,
1865	.clkr = {
1866		.enable_reg = 0x5101c,
1867		.enable_mask = BIT(0),
1868		.hw.init = &(struct clk_init_data){
1869			.name = "gcc_camss_cci_ahb_clk",
1870			.parent_hws = (const struct clk_hw*[]){
1871				&camss_ahb_clk_src.clkr.hw,
1872			},
1873			.num_parents = 1,
1874			.flags = CLK_SET_RATE_PARENT,
1875			.ops = &clk_branch2_ops,
1876		},
1877	},
1878};
1879
1880static struct clk_branch gcc_camss_cci_clk = {
1881	.halt_reg = 0x51018,
1882	.clkr = {
1883		.enable_reg = 0x51018,
1884		.enable_mask = BIT(0),
1885		.hw.init = &(struct clk_init_data){
1886			.name = "gcc_camss_cci_clk",
1887			.parent_hws = (const struct clk_hw*[]){
1888				&cci_clk_src.clkr.hw,
1889			},
1890			.num_parents = 1,
1891			.flags = CLK_SET_RATE_PARENT,
1892			.ops = &clk_branch2_ops,
1893		},
1894	},
1895};
1896
1897static struct clk_branch gcc_camss_csi0_ahb_clk = {
1898	.halt_reg = 0x4e040,
1899	.clkr = {
1900		.enable_reg = 0x4e040,
1901		.enable_mask = BIT(0),
1902		.hw.init = &(struct clk_init_data){
1903			.name = "gcc_camss_csi0_ahb_clk",
1904			.parent_hws = (const struct clk_hw*[]){
1905				&camss_ahb_clk_src.clkr.hw,
1906			},
1907			.num_parents = 1,
1908			.flags = CLK_SET_RATE_PARENT,
1909			.ops = &clk_branch2_ops,
1910		},
1911	},
1912};
1913
1914static struct clk_branch gcc_camss_csi0_clk = {
1915	.halt_reg = 0x4e03c,
1916	.clkr = {
1917		.enable_reg = 0x4e03c,
1918		.enable_mask = BIT(0),
1919		.hw.init = &(struct clk_init_data){
1920			.name = "gcc_camss_csi0_clk",
1921			.parent_hws = (const struct clk_hw*[]){
1922				&csi0_clk_src.clkr.hw,
1923			},
1924			.num_parents = 1,
1925			.flags = CLK_SET_RATE_PARENT,
1926			.ops = &clk_branch2_ops,
1927		},
1928	},
1929};
1930
1931static struct clk_branch gcc_camss_csi0phy_clk = {
1932	.halt_reg = 0x4e048,
1933	.clkr = {
1934		.enable_reg = 0x4e048,
1935		.enable_mask = BIT(0),
1936		.hw.init = &(struct clk_init_data){
1937			.name = "gcc_camss_csi0phy_clk",
1938			.parent_hws = (const struct clk_hw*[]){
1939				&csi0_clk_src.clkr.hw,
1940			},
1941			.num_parents = 1,
1942			.flags = CLK_SET_RATE_PARENT,
1943			.ops = &clk_branch2_ops,
1944		},
1945	},
1946};
1947
1948static struct clk_branch gcc_camss_csi0pix_clk = {
1949	.halt_reg = 0x4e058,
1950	.clkr = {
1951		.enable_reg = 0x4e058,
1952		.enable_mask = BIT(0),
1953		.hw.init = &(struct clk_init_data){
1954			.name = "gcc_camss_csi0pix_clk",
1955			.parent_hws = (const struct clk_hw*[]){
1956				&csi0_clk_src.clkr.hw,
1957			},
1958			.num_parents = 1,
1959			.flags = CLK_SET_RATE_PARENT,
1960			.ops = &clk_branch2_ops,
1961		},
1962	},
1963};
1964
1965static struct clk_branch gcc_camss_csi0rdi_clk = {
1966	.halt_reg = 0x4e050,
1967	.clkr = {
1968		.enable_reg = 0x4e050,
1969		.enable_mask = BIT(0),
1970		.hw.init = &(struct clk_init_data){
1971			.name = "gcc_camss_csi0rdi_clk",
1972			.parent_hws = (const struct clk_hw*[]){
1973				&csi0_clk_src.clkr.hw,
1974			},
1975			.num_parents = 1,
1976			.flags = CLK_SET_RATE_PARENT,
1977			.ops = &clk_branch2_ops,
1978		},
1979	},
1980};
1981
1982static struct clk_branch gcc_camss_csi1_ahb_clk = {
1983	.halt_reg = 0x4f040,
1984	.clkr = {
1985		.enable_reg = 0x4f040,
1986		.enable_mask = BIT(0),
1987		.hw.init = &(struct clk_init_data){
1988			.name = "gcc_camss_csi1_ahb_clk",
1989			.parent_hws = (const struct clk_hw*[]){
1990				&camss_ahb_clk_src.clkr.hw,
1991			},
1992			.num_parents = 1,
1993			.flags = CLK_SET_RATE_PARENT,
1994			.ops = &clk_branch2_ops,
1995		},
1996	},
1997};
1998
1999static struct clk_branch gcc_camss_csi1_clk = {
2000	.halt_reg = 0x4f03c,
2001	.clkr = {
2002		.enable_reg = 0x4f03c,
2003		.enable_mask = BIT(0),
2004		.hw.init = &(struct clk_init_data){
2005			.name = "gcc_camss_csi1_clk",
2006			.parent_hws = (const struct clk_hw*[]){
2007				&csi1_clk_src.clkr.hw,
2008			},
2009			.num_parents = 1,
2010			.flags = CLK_SET_RATE_PARENT,
2011			.ops = &clk_branch2_ops,
2012		},
2013	},
2014};
2015
2016static struct clk_branch gcc_camss_csi1phy_clk = {
2017	.halt_reg = 0x4f048,
2018	.clkr = {
2019		.enable_reg = 0x4f048,
2020		.enable_mask = BIT(0),
2021		.hw.init = &(struct clk_init_data){
2022			.name = "gcc_camss_csi1phy_clk",
2023			.parent_hws = (const struct clk_hw*[]){
2024				&csi1_clk_src.clkr.hw,
2025			},
2026			.num_parents = 1,
2027			.flags = CLK_SET_RATE_PARENT,
2028			.ops = &clk_branch2_ops,
2029		},
2030	},
2031};
2032
2033static struct clk_branch gcc_camss_csi1pix_clk = {
2034	.halt_reg = 0x4f058,
2035	.clkr = {
2036		.enable_reg = 0x4f058,
2037		.enable_mask = BIT(0),
2038		.hw.init = &(struct clk_init_data){
2039			.name = "gcc_camss_csi1pix_clk",
2040			.parent_hws = (const struct clk_hw*[]){
2041				&csi1_clk_src.clkr.hw,
2042			},
2043			.num_parents = 1,
2044			.flags = CLK_SET_RATE_PARENT,
2045			.ops = &clk_branch2_ops,
2046		},
2047	},
2048};
2049
2050static struct clk_branch gcc_camss_csi1rdi_clk = {
2051	.halt_reg = 0x4f050,
2052	.clkr = {
2053		.enable_reg = 0x4f050,
2054		.enable_mask = BIT(0),
2055		.hw.init = &(struct clk_init_data){
2056			.name = "gcc_camss_csi1rdi_clk",
2057			.parent_hws = (const struct clk_hw*[]){
2058				&csi1_clk_src.clkr.hw,
2059			},
2060			.num_parents = 1,
2061			.flags = CLK_SET_RATE_PARENT,
2062			.ops = &clk_branch2_ops,
2063		},
2064	},
2065};
2066
2067static struct clk_branch gcc_camss_csi_vfe0_clk = {
2068	.halt_reg = 0x58050,
2069	.clkr = {
2070		.enable_reg = 0x58050,
2071		.enable_mask = BIT(0),
2072		.hw.init = &(struct clk_init_data){
2073			.name = "gcc_camss_csi_vfe0_clk",
2074			.parent_hws = (const struct clk_hw*[]){
2075				&vfe0_clk_src.clkr.hw,
2076			},
2077			.num_parents = 1,
2078			.flags = CLK_SET_RATE_PARENT,
2079			.ops = &clk_branch2_ops,
2080		},
2081	},
2082};
2083
2084static struct clk_branch gcc_camss_gp0_clk = {
2085	.halt_reg = 0x54018,
2086	.clkr = {
2087		.enable_reg = 0x54018,
2088		.enable_mask = BIT(0),
2089		.hw.init = &(struct clk_init_data){
2090			.name = "gcc_camss_gp0_clk",
2091			.parent_hws = (const struct clk_hw*[]){
2092				&camss_gp0_clk_src.clkr.hw,
2093			},
2094			.num_parents = 1,
2095			.flags = CLK_SET_RATE_PARENT,
2096			.ops = &clk_branch2_ops,
2097		},
2098	},
2099};
2100
2101static struct clk_branch gcc_camss_gp1_clk = {
2102	.halt_reg = 0x55018,
2103	.clkr = {
2104		.enable_reg = 0x55018,
2105		.enable_mask = BIT(0),
2106		.hw.init = &(struct clk_init_data){
2107			.name = "gcc_camss_gp1_clk",
2108			.parent_hws = (const struct clk_hw*[]){
2109				&camss_gp1_clk_src.clkr.hw,
2110			},
2111			.num_parents = 1,
2112			.flags = CLK_SET_RATE_PARENT,
2113			.ops = &clk_branch2_ops,
2114		},
2115	},
2116};
2117
2118static struct clk_branch gcc_camss_ispif_ahb_clk = {
2119	.halt_reg = 0x50004,
2120	.clkr = {
2121		.enable_reg = 0x50004,
2122		.enable_mask = BIT(0),
2123		.hw.init = &(struct clk_init_data){
2124			.name = "gcc_camss_ispif_ahb_clk",
2125			.parent_hws = (const struct clk_hw*[]){
2126				&camss_ahb_clk_src.clkr.hw,
2127			},
2128			.num_parents = 1,
2129			.flags = CLK_SET_RATE_PARENT,
2130			.ops = &clk_branch2_ops,
2131		},
2132	},
2133};
2134
2135static struct clk_branch gcc_camss_jpeg0_clk = {
2136	.halt_reg = 0x57020,
2137	.clkr = {
2138		.enable_reg = 0x57020,
2139		.enable_mask = BIT(0),
2140		.hw.init = &(struct clk_init_data){
2141			.name = "gcc_camss_jpeg0_clk",
2142			.parent_hws = (const struct clk_hw*[]){
2143				&jpeg0_clk_src.clkr.hw,
2144			},
2145			.num_parents = 1,
2146			.flags = CLK_SET_RATE_PARENT,
2147			.ops = &clk_branch2_ops,
2148		},
2149	},
2150};
2151
2152static struct clk_branch gcc_camss_jpeg_ahb_clk = {
2153	.halt_reg = 0x57024,
2154	.clkr = {
2155		.enable_reg = 0x57024,
2156		.enable_mask = BIT(0),
2157		.hw.init = &(struct clk_init_data){
2158			.name = "gcc_camss_jpeg_ahb_clk",
2159			.parent_hws = (const struct clk_hw*[]){
2160				&camss_ahb_clk_src.clkr.hw,
2161			},
2162			.num_parents = 1,
2163			.flags = CLK_SET_RATE_PARENT,
2164			.ops = &clk_branch2_ops,
2165		},
2166	},
2167};
2168
2169static struct clk_branch gcc_camss_jpeg_axi_clk = {
2170	.halt_reg = 0x57028,
2171	.clkr = {
2172		.enable_reg = 0x57028,
2173		.enable_mask = BIT(0),
2174		.hw.init = &(struct clk_init_data){
2175			.name = "gcc_camss_jpeg_axi_clk",
2176			.parent_hws = (const struct clk_hw*[]){
2177				&system_noc_bfdcd_clk_src.clkr.hw,
2178			},
2179			.num_parents = 1,
2180			.flags = CLK_SET_RATE_PARENT,
2181			.ops = &clk_branch2_ops,
2182		},
2183	},
2184};
2185
2186static struct clk_branch gcc_camss_mclk0_clk = {
2187	.halt_reg = 0x52018,
2188	.clkr = {
2189		.enable_reg = 0x52018,
2190		.enable_mask = BIT(0),
2191		.hw.init = &(struct clk_init_data){
2192			.name = "gcc_camss_mclk0_clk",
2193			.parent_hws = (const struct clk_hw*[]){
2194				&mclk0_clk_src.clkr.hw,
2195			},
2196			.num_parents = 1,
2197			.flags = CLK_SET_RATE_PARENT,
2198			.ops = &clk_branch2_ops,
2199		},
2200	},
2201};
2202
2203static struct clk_branch gcc_camss_mclk1_clk = {
2204	.halt_reg = 0x53018,
2205	.clkr = {
2206		.enable_reg = 0x53018,
2207		.enable_mask = BIT(0),
2208		.hw.init = &(struct clk_init_data){
2209			.name = "gcc_camss_mclk1_clk",
2210			.parent_hws = (const struct clk_hw*[]){
2211				&mclk1_clk_src.clkr.hw,
2212			},
2213			.num_parents = 1,
2214			.flags = CLK_SET_RATE_PARENT,
2215			.ops = &clk_branch2_ops,
2216		},
2217	},
2218};
2219
2220static struct clk_branch gcc_camss_micro_ahb_clk = {
2221	.halt_reg = 0x5600c,
2222	.clkr = {
2223		.enable_reg = 0x5600c,
2224		.enable_mask = BIT(0),
2225		.hw.init = &(struct clk_init_data){
2226			.name = "gcc_camss_micro_ahb_clk",
2227			.parent_hws = (const struct clk_hw*[]){
2228				&camss_ahb_clk_src.clkr.hw,
2229			},
2230			.num_parents = 1,
2231			.flags = CLK_SET_RATE_PARENT,
2232			.ops = &clk_branch2_ops,
2233		},
2234	},
2235};
2236
2237static struct clk_branch gcc_camss_csi0phytimer_clk = {
2238	.halt_reg = 0x4e01c,
2239	.clkr = {
2240		.enable_reg = 0x4e01c,
2241		.enable_mask = BIT(0),
2242		.hw.init = &(struct clk_init_data){
2243			.name = "gcc_camss_csi0phytimer_clk",
2244			.parent_hws = (const struct clk_hw*[]){
2245				&csi0phytimer_clk_src.clkr.hw,
2246			},
2247			.num_parents = 1,
2248			.flags = CLK_SET_RATE_PARENT,
2249			.ops = &clk_branch2_ops,
2250		},
2251	},
2252};
2253
2254static struct clk_branch gcc_camss_csi1phytimer_clk = {
2255	.halt_reg = 0x4f01c,
2256	.clkr = {
2257		.enable_reg = 0x4f01c,
2258		.enable_mask = BIT(0),
2259		.hw.init = &(struct clk_init_data){
2260			.name = "gcc_camss_csi1phytimer_clk",
2261			.parent_hws = (const struct clk_hw*[]){
2262				&csi1phytimer_clk_src.clkr.hw,
2263			},
2264			.num_parents = 1,
2265			.flags = CLK_SET_RATE_PARENT,
2266			.ops = &clk_branch2_ops,
2267		},
2268	},
2269};
2270
2271static struct clk_branch gcc_camss_ahb_clk = {
2272	.halt_reg = 0x5a014,
2273	.clkr = {
2274		.enable_reg = 0x5a014,
2275		.enable_mask = BIT(0),
2276		.hw.init = &(struct clk_init_data){
2277			.name = "gcc_camss_ahb_clk",
2278			.parent_hws = (const struct clk_hw*[]){
2279				&camss_ahb_clk_src.clkr.hw,
2280			},
2281			.num_parents = 1,
2282			.flags = CLK_SET_RATE_PARENT,
2283			.ops = &clk_branch2_ops,
2284		},
2285	},
2286};
2287
2288static struct clk_branch gcc_camss_top_ahb_clk = {
2289	.halt_reg = 0x56004,
2290	.clkr = {
2291		.enable_reg = 0x56004,
2292		.enable_mask = BIT(0),
2293		.hw.init = &(struct clk_init_data){
2294			.name = "gcc_camss_top_ahb_clk",
2295			.parent_hws = (const struct clk_hw*[]){
2296				&pcnoc_bfdcd_clk_src.clkr.hw,
2297			},
2298			.num_parents = 1,
2299			.flags = CLK_SET_RATE_PARENT,
2300			.ops = &clk_branch2_ops,
2301		},
2302	},
2303};
2304
2305static struct clk_branch gcc_camss_cpp_ahb_clk = {
2306	.halt_reg = 0x58040,
2307	.clkr = {
2308		.enable_reg = 0x58040,
2309		.enable_mask = BIT(0),
2310		.hw.init = &(struct clk_init_data){
2311			.name = "gcc_camss_cpp_ahb_clk",
2312			.parent_hws = (const struct clk_hw*[]){
2313				&camss_ahb_clk_src.clkr.hw,
2314			},
2315			.num_parents = 1,
2316			.flags = CLK_SET_RATE_PARENT,
2317			.ops = &clk_branch2_ops,
2318		},
2319	},
2320};
2321
2322static struct clk_branch gcc_camss_cpp_clk = {
2323	.halt_reg = 0x5803c,
2324	.clkr = {
2325		.enable_reg = 0x5803c,
2326		.enable_mask = BIT(0),
2327		.hw.init = &(struct clk_init_data){
2328			.name = "gcc_camss_cpp_clk",
2329			.parent_hws = (const struct clk_hw*[]){
2330				&cpp_clk_src.clkr.hw,
2331			},
2332			.num_parents = 1,
2333			.flags = CLK_SET_RATE_PARENT,
2334			.ops = &clk_branch2_ops,
2335		},
2336	},
2337};
2338
2339static struct clk_branch gcc_camss_vfe0_clk = {
2340	.halt_reg = 0x58038,
2341	.clkr = {
2342		.enable_reg = 0x58038,
2343		.enable_mask = BIT(0),
2344		.hw.init = &(struct clk_init_data){
2345			.name = "gcc_camss_vfe0_clk",
2346			.parent_hws = (const struct clk_hw*[]){
2347				&vfe0_clk_src.clkr.hw,
2348			},
2349			.num_parents = 1,
2350			.flags = CLK_SET_RATE_PARENT,
2351			.ops = &clk_branch2_ops,
2352		},
2353	},
2354};
2355
2356static struct clk_branch gcc_camss_vfe_ahb_clk = {
2357	.halt_reg = 0x58044,
2358	.clkr = {
2359		.enable_reg = 0x58044,
2360		.enable_mask = BIT(0),
2361		.hw.init = &(struct clk_init_data){
2362			.name = "gcc_camss_vfe_ahb_clk",
2363			.parent_hws = (const struct clk_hw*[]){
2364				&camss_ahb_clk_src.clkr.hw,
2365			},
2366			.num_parents = 1,
2367			.flags = CLK_SET_RATE_PARENT,
2368			.ops = &clk_branch2_ops,
2369		},
2370	},
2371};
2372
2373static struct clk_branch gcc_camss_vfe_axi_clk = {
2374	.halt_reg = 0x58048,
2375	.clkr = {
2376		.enable_reg = 0x58048,
2377		.enable_mask = BIT(0),
2378		.hw.init = &(struct clk_init_data){
2379			.name = "gcc_camss_vfe_axi_clk",
2380			.parent_hws = (const struct clk_hw*[]){
2381				&system_noc_bfdcd_clk_src.clkr.hw,
2382			},
2383			.num_parents = 1,
2384			.flags = CLK_SET_RATE_PARENT,
2385			.ops = &clk_branch2_ops,
2386		},
2387	},
2388};
2389
2390static struct clk_branch gcc_crypto_ahb_clk = {
2391	.halt_reg = 0x16024,
2392	.halt_check = BRANCH_HALT_VOTED,
2393	.clkr = {
2394		.enable_reg = 0x45004,
2395		.enable_mask = BIT(0),
2396		.hw.init = &(struct clk_init_data){
2397			.name = "gcc_crypto_ahb_clk",
2398			.parent_hws = (const struct clk_hw*[]){
2399				&pcnoc_bfdcd_clk_src.clkr.hw,
2400			},
2401			.num_parents = 1,
2402			.flags = CLK_SET_RATE_PARENT,
2403			.ops = &clk_branch2_ops,
2404		},
2405	},
2406};
2407
2408static struct clk_branch gcc_crypto_axi_clk = {
2409	.halt_reg = 0x16020,
2410	.halt_check = BRANCH_HALT_VOTED,
2411	.clkr = {
2412		.enable_reg = 0x45004,
2413		.enable_mask = BIT(1),
2414		.hw.init = &(struct clk_init_data){
2415			.name = "gcc_crypto_axi_clk",
2416			.parent_hws = (const struct clk_hw*[]){
2417				&pcnoc_bfdcd_clk_src.clkr.hw,
2418			},
2419			.num_parents = 1,
2420			.flags = CLK_SET_RATE_PARENT,
2421			.ops = &clk_branch2_ops,
2422		},
2423	},
2424};
2425
2426static struct clk_branch gcc_crypto_clk = {
2427	.halt_reg = 0x1601c,
2428	.halt_check = BRANCH_HALT_VOTED,
2429	.clkr = {
2430		.enable_reg = 0x45004,
2431		.enable_mask = BIT(2),
2432		.hw.init = &(struct clk_init_data){
2433			.name = "gcc_crypto_clk",
2434			.parent_hws = (const struct clk_hw*[]){
2435				&crypto_clk_src.clkr.hw,
2436			},
2437			.num_parents = 1,
2438			.flags = CLK_SET_RATE_PARENT,
2439			.ops = &clk_branch2_ops,
2440		},
2441	},
2442};
2443
2444static struct clk_branch gcc_oxili_gmem_clk = {
2445	.halt_reg = 0x59024,
2446	.clkr = {
2447		.enable_reg = 0x59024,
2448		.enable_mask = BIT(0),
2449		.hw.init = &(struct clk_init_data){
2450			.name = "gcc_oxili_gmem_clk",
2451			.parent_hws = (const struct clk_hw*[]){
2452				&gfx3d_clk_src.clkr.hw,
2453			},
2454			.num_parents = 1,
2455			.flags = CLK_SET_RATE_PARENT,
2456			.ops = &clk_branch2_ops,
2457		},
2458	},
2459};
2460
2461static struct clk_branch gcc_gp1_clk = {
2462	.halt_reg = 0x08000,
2463	.clkr = {
2464		.enable_reg = 0x08000,
2465		.enable_mask = BIT(0),
2466		.hw.init = &(struct clk_init_data){
2467			.name = "gcc_gp1_clk",
2468			.parent_hws = (const struct clk_hw*[]){
2469				&gp1_clk_src.clkr.hw,
2470			},
2471			.num_parents = 1,
2472			.flags = CLK_SET_RATE_PARENT,
2473			.ops = &clk_branch2_ops,
2474		},
2475	},
2476};
2477
2478static struct clk_branch gcc_gp2_clk = {
2479	.halt_reg = 0x09000,
2480	.clkr = {
2481		.enable_reg = 0x09000,
2482		.enable_mask = BIT(0),
2483		.hw.init = &(struct clk_init_data){
2484			.name = "gcc_gp2_clk",
2485			.parent_hws = (const struct clk_hw*[]){
2486				&gp2_clk_src.clkr.hw,
2487			},
2488			.num_parents = 1,
2489			.flags = CLK_SET_RATE_PARENT,
2490			.ops = &clk_branch2_ops,
2491		},
2492	},
2493};
2494
2495static struct clk_branch gcc_gp3_clk = {
2496	.halt_reg = 0x0a000,
2497	.clkr = {
2498		.enable_reg = 0x0a000,
2499		.enable_mask = BIT(0),
2500		.hw.init = &(struct clk_init_data){
2501			.name = "gcc_gp3_clk",
2502			.parent_hws = (const struct clk_hw*[]){
2503				&gp3_clk_src.clkr.hw,
2504			},
2505			.num_parents = 1,
2506			.flags = CLK_SET_RATE_PARENT,
2507			.ops = &clk_branch2_ops,
2508		},
2509	},
2510};
2511
2512static struct clk_branch gcc_mdss_ahb_clk = {
2513	.halt_reg = 0x4d07c,
2514	.clkr = {
2515		.enable_reg = 0x4d07c,
2516		.enable_mask = BIT(0),
2517		.hw.init = &(struct clk_init_data){
2518			.name = "gcc_mdss_ahb_clk",
2519			.parent_hws = (const struct clk_hw*[]){
2520				&pcnoc_bfdcd_clk_src.clkr.hw,
2521			},
2522			.num_parents = 1,
2523			.flags = CLK_SET_RATE_PARENT,
2524			.ops = &clk_branch2_ops,
2525		},
2526	},
2527};
2528
2529static struct clk_branch gcc_mdss_axi_clk = {
2530	.halt_reg = 0x4d080,
2531	.clkr = {
2532		.enable_reg = 0x4d080,
2533		.enable_mask = BIT(0),
2534		.hw.init = &(struct clk_init_data){
2535			.name = "gcc_mdss_axi_clk",
2536			.parent_hws = (const struct clk_hw*[]){
2537				&system_noc_bfdcd_clk_src.clkr.hw,
2538			},
2539			.num_parents = 1,
2540			.flags = CLK_SET_RATE_PARENT,
2541			.ops = &clk_branch2_ops,
2542		},
2543	},
2544};
2545
2546static struct clk_branch gcc_mdss_byte0_clk = {
2547	.halt_reg = 0x4d094,
2548	.clkr = {
2549		.enable_reg = 0x4d094,
2550		.enable_mask = BIT(0),
2551		.hw.init = &(struct clk_init_data){
2552			.name = "gcc_mdss_byte0_clk",
2553			.parent_hws = (const struct clk_hw*[]){
2554				&byte0_clk_src.clkr.hw,
2555			},
2556			.num_parents = 1,
2557			.flags = CLK_SET_RATE_PARENT,
2558			.ops = &clk_branch2_ops,
2559		},
2560	},
2561};
2562
2563static struct clk_branch gcc_mdss_esc0_clk = {
2564	.halt_reg = 0x4d098,
2565	.clkr = {
2566		.enable_reg = 0x4d098,
2567		.enable_mask = BIT(0),
2568		.hw.init = &(struct clk_init_data){
2569			.name = "gcc_mdss_esc0_clk",
2570			.parent_hws = (const struct clk_hw*[]){
2571				&esc0_clk_src.clkr.hw,
2572			},
2573			.num_parents = 1,
2574			.flags = CLK_SET_RATE_PARENT,
2575			.ops = &clk_branch2_ops,
2576		},
2577	},
2578};
2579
2580static struct clk_branch gcc_mdss_mdp_clk = {
2581	.halt_reg = 0x4D088,
2582	.clkr = {
2583		.enable_reg = 0x4D088,
2584		.enable_mask = BIT(0),
2585		.hw.init = &(struct clk_init_data){
2586			.name = "gcc_mdss_mdp_clk",
2587			.parent_hws = (const struct clk_hw*[]){
2588				&mdp_clk_src.clkr.hw,
2589			},
2590			.num_parents = 1,
2591			.flags = CLK_SET_RATE_PARENT,
2592			.ops = &clk_branch2_ops,
2593		},
2594	},
2595};
2596
2597static struct clk_branch gcc_mdss_pclk0_clk = {
2598	.halt_reg = 0x4d084,
2599	.clkr = {
2600		.enable_reg = 0x4d084,
2601		.enable_mask = BIT(0),
2602		.hw.init = &(struct clk_init_data){
2603			.name = "gcc_mdss_pclk0_clk",
2604			.parent_hws = (const struct clk_hw*[]){
2605				&pclk0_clk_src.clkr.hw,
2606			},
2607			.num_parents = 1,
2608			.flags = CLK_SET_RATE_PARENT,
2609			.ops = &clk_branch2_ops,
2610		},
2611	},
2612};
2613
2614static struct clk_branch gcc_mdss_vsync_clk = {
2615	.halt_reg = 0x4d090,
2616	.clkr = {
2617		.enable_reg = 0x4d090,
2618		.enable_mask = BIT(0),
2619		.hw.init = &(struct clk_init_data){
2620			.name = "gcc_mdss_vsync_clk",
2621			.parent_hws = (const struct clk_hw*[]){
2622				&vsync_clk_src.clkr.hw,
2623			},
2624			.num_parents = 1,
2625			.flags = CLK_SET_RATE_PARENT,
2626			.ops = &clk_branch2_ops,
2627		},
2628	},
2629};
2630
2631static struct clk_branch gcc_mss_cfg_ahb_clk = {
2632	.halt_reg = 0x49000,
2633	.clkr = {
2634		.enable_reg = 0x49000,
2635		.enable_mask = BIT(0),
2636		.hw.init = &(struct clk_init_data){
2637			.name = "gcc_mss_cfg_ahb_clk",
2638			.parent_hws = (const struct clk_hw*[]){
2639				&pcnoc_bfdcd_clk_src.clkr.hw,
2640			},
2641			.num_parents = 1,
2642			.flags = CLK_SET_RATE_PARENT,
2643			.ops = &clk_branch2_ops,
2644		},
2645	},
2646};
2647
2648static struct clk_branch gcc_oxili_ahb_clk = {
2649	.halt_reg = 0x59028,
2650	.clkr = {
2651		.enable_reg = 0x59028,
2652		.enable_mask = BIT(0),
2653		.hw.init = &(struct clk_init_data){
2654			.name = "gcc_oxili_ahb_clk",
2655			.parent_hws = (const struct clk_hw*[]){
2656				&pcnoc_bfdcd_clk_src.clkr.hw,
2657			},
2658			.num_parents = 1,
2659			.flags = CLK_SET_RATE_PARENT,
2660			.ops = &clk_branch2_ops,
2661		},
2662	},
2663};
2664
2665static struct clk_branch gcc_oxili_gfx3d_clk = {
2666	.halt_reg = 0x59020,
2667	.clkr = {
2668		.enable_reg = 0x59020,
2669		.enable_mask = BIT(0),
2670		.hw.init = &(struct clk_init_data){
2671			.name = "gcc_oxili_gfx3d_clk",
2672			.parent_hws = (const struct clk_hw*[]){
2673				&gfx3d_clk_src.clkr.hw,
2674			},
2675			.num_parents = 1,
2676			.flags = CLK_SET_RATE_PARENT,
2677			.ops = &clk_branch2_ops,
2678		},
2679	},
2680};
2681
2682static struct clk_branch gcc_pdm2_clk = {
2683	.halt_reg = 0x4400c,
2684	.clkr = {
2685		.enable_reg = 0x4400c,
2686		.enable_mask = BIT(0),
2687		.hw.init = &(struct clk_init_data){
2688			.name = "gcc_pdm2_clk",
2689			.parent_hws = (const struct clk_hw*[]){
2690				&pdm2_clk_src.clkr.hw,
2691			},
2692			.num_parents = 1,
2693			.flags = CLK_SET_RATE_PARENT,
2694			.ops = &clk_branch2_ops,
2695		},
2696	},
2697};
2698
2699static struct clk_branch gcc_pdm_ahb_clk = {
2700	.halt_reg = 0x44004,
2701	.clkr = {
2702		.enable_reg = 0x44004,
2703		.enable_mask = BIT(0),
2704		.hw.init = &(struct clk_init_data){
2705			.name = "gcc_pdm_ahb_clk",
2706			.parent_hws = (const struct clk_hw*[]){
2707				&pcnoc_bfdcd_clk_src.clkr.hw,
2708			},
2709			.num_parents = 1,
2710			.flags = CLK_SET_RATE_PARENT,
2711			.ops = &clk_branch2_ops,
2712		},
2713	},
2714};
2715
2716static struct clk_branch gcc_prng_ahb_clk = {
2717	.halt_reg = 0x13004,
2718	.halt_check = BRANCH_HALT_VOTED,
2719	.clkr = {
2720		.enable_reg = 0x45004,
2721		.enable_mask = BIT(8),
2722		.hw.init = &(struct clk_init_data){
2723			.name = "gcc_prng_ahb_clk",
2724			.parent_hws = (const struct clk_hw*[]){
2725				&pcnoc_bfdcd_clk_src.clkr.hw,
2726			},
2727			.num_parents = 1,
2728			.ops = &clk_branch2_ops,
2729		},
2730	},
2731};
2732
2733static struct clk_branch gcc_sdcc1_ahb_clk = {
2734	.halt_reg = 0x4201c,
2735	.clkr = {
2736		.enable_reg = 0x4201c,
2737		.enable_mask = BIT(0),
2738		.hw.init = &(struct clk_init_data){
2739			.name = "gcc_sdcc1_ahb_clk",
2740			.parent_hws = (const struct clk_hw*[]){
2741				&pcnoc_bfdcd_clk_src.clkr.hw,
2742			},
2743			.num_parents = 1,
2744			.flags = CLK_SET_RATE_PARENT,
2745			.ops = &clk_branch2_ops,
2746		},
2747	},
2748};
2749
2750static struct clk_branch gcc_sdcc1_apps_clk = {
2751	.halt_reg = 0x42018,
2752	.clkr = {
2753		.enable_reg = 0x42018,
2754		.enable_mask = BIT(0),
2755		.hw.init = &(struct clk_init_data){
2756			.name = "gcc_sdcc1_apps_clk",
2757			.parent_hws = (const struct clk_hw*[]){
2758				&sdcc1_apps_clk_src.clkr.hw,
2759			},
2760			.num_parents = 1,
2761			.flags = CLK_SET_RATE_PARENT,
2762			.ops = &clk_branch2_ops,
2763		},
2764	},
2765};
2766
2767static struct clk_branch gcc_sdcc2_ahb_clk = {
2768	.halt_reg = 0x4301c,
2769	.clkr = {
2770		.enable_reg = 0x4301c,
2771		.enable_mask = BIT(0),
2772		.hw.init = &(struct clk_init_data){
2773			.name = "gcc_sdcc2_ahb_clk",
2774			.parent_hws = (const struct clk_hw*[]){
2775				&pcnoc_bfdcd_clk_src.clkr.hw,
2776			},
2777			.num_parents = 1,
2778			.flags = CLK_SET_RATE_PARENT,
2779			.ops = &clk_branch2_ops,
2780		},
2781	},
2782};
2783
2784static struct clk_branch gcc_sdcc2_apps_clk = {
2785	.halt_reg = 0x43018,
2786	.clkr = {
2787		.enable_reg = 0x43018,
2788		.enable_mask = BIT(0),
2789		.hw.init = &(struct clk_init_data){
2790			.name = "gcc_sdcc2_apps_clk",
2791			.parent_hws = (const struct clk_hw*[]){
2792				&sdcc2_apps_clk_src.clkr.hw,
2793			},
2794			.num_parents = 1,
2795			.flags = CLK_SET_RATE_PARENT,
2796			.ops = &clk_branch2_ops,
2797		},
2798	},
2799};
2800
2801static struct clk_rcg2 bimc_ddr_clk_src = {
2802	.cmd_rcgr = 0x32004,
2803	.hid_width = 5,
2804	.parent_map = gcc_xo_gpll0_bimc_map,
2805	.clkr.hw.init = &(struct clk_init_data){
2806		.name = "bimc_ddr_clk_src",
2807		.parent_data = gcc_xo_gpll0_bimc,
2808		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc),
2809		.ops = &clk_rcg2_ops,
2810		.flags = CLK_GET_RATE_NOCACHE,
2811	},
2812};
2813
2814static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
2815	.halt_reg = 0x49004,
2816	.clkr = {
2817		.enable_reg = 0x49004,
2818		.enable_mask = BIT(0),
2819		.hw.init = &(struct clk_init_data){
2820			.name = "gcc_mss_q6_bimc_axi_clk",
2821			.parent_hws = (const struct clk_hw*[]){
2822				&bimc_ddr_clk_src.clkr.hw,
2823			},
2824			.num_parents = 1,
2825			.flags = CLK_SET_RATE_PARENT,
2826			.ops = &clk_branch2_ops,
2827		},
2828	},
2829};
2830
2831static struct clk_branch gcc_apss_tcu_clk = {
2832	.halt_reg = 0x12018,
2833	.clkr = {
2834		.enable_reg = 0x4500c,
2835		.enable_mask = BIT(1),
2836		.hw.init = &(struct clk_init_data){
2837			.name = "gcc_apss_tcu_clk",
2838			.parent_hws = (const struct clk_hw*[]){
2839				&bimc_ddr_clk_src.clkr.hw,
2840			},
2841			.num_parents = 1,
2842			.ops = &clk_branch2_ops,
2843		},
2844	},
2845};
2846
2847static struct clk_branch gcc_gfx_tcu_clk = {
2848	.halt_reg = 0x12020,
2849	.clkr = {
2850		.enable_reg = 0x4500c,
2851		.enable_mask = BIT(2),
2852		.hw.init = &(struct clk_init_data){
2853			.name = "gcc_gfx_tcu_clk",
2854			.parent_hws = (const struct clk_hw*[]){
2855				&bimc_ddr_clk_src.clkr.hw,
2856			},
2857			.num_parents = 1,
2858			.ops = &clk_branch2_ops,
2859		},
2860	},
2861};
2862
2863static struct clk_branch gcc_gtcu_ahb_clk = {
2864	.halt_reg = 0x12044,
2865	.clkr = {
2866		.enable_reg = 0x4500c,
2867		.enable_mask = BIT(13),
2868		.hw.init = &(struct clk_init_data){
2869			.name = "gcc_gtcu_ahb_clk",
2870			.parent_hws = (const struct clk_hw*[]){
2871				&pcnoc_bfdcd_clk_src.clkr.hw,
2872			},
2873			.num_parents = 1,
2874			.flags = CLK_SET_RATE_PARENT,
2875			.ops = &clk_branch2_ops,
2876		},
2877	},
2878};
2879
2880static struct clk_branch gcc_bimc_gfx_clk = {
2881	.halt_reg = 0x31024,
2882	.clkr = {
2883		.enable_reg = 0x31024,
2884		.enable_mask = BIT(0),
2885		.hw.init = &(struct clk_init_data){
2886			.name = "gcc_bimc_gfx_clk",
2887			.parent_hws = (const struct clk_hw*[]){
2888				&bimc_gpu_clk_src.clkr.hw,
2889			},
2890			.num_parents = 1,
2891			.flags = CLK_SET_RATE_PARENT,
2892			.ops = &clk_branch2_ops,
2893		},
2894	},
2895};
2896
2897static struct clk_branch gcc_bimc_gpu_clk = {
2898	.halt_reg = 0x31040,
2899	.clkr = {
2900		.enable_reg = 0x31040,
2901		.enable_mask = BIT(0),
2902		.hw.init = &(struct clk_init_data){
2903			.name = "gcc_bimc_gpu_clk",
2904			.parent_hws = (const struct clk_hw*[]){
2905				&bimc_gpu_clk_src.clkr.hw,
2906			},
2907			.num_parents = 1,
2908			.flags = CLK_SET_RATE_PARENT,
2909			.ops = &clk_branch2_ops,
2910		},
2911	},
2912};
2913
2914static struct clk_branch gcc_jpeg_tbu_clk = {
2915	.halt_reg = 0x12034,
2916	.clkr = {
2917		.enable_reg = 0x4500c,
2918		.enable_mask = BIT(10),
2919		.hw.init = &(struct clk_init_data){
2920			.name = "gcc_jpeg_tbu_clk",
2921			.parent_hws = (const struct clk_hw*[]){
2922				&system_noc_bfdcd_clk_src.clkr.hw,
2923			},
2924			.num_parents = 1,
2925			.flags = CLK_SET_RATE_PARENT,
2926			.ops = &clk_branch2_ops,
2927		},
2928	},
2929};
2930
2931static struct clk_branch gcc_mdp_tbu_clk = {
2932	.halt_reg = 0x1201c,
2933	.clkr = {
2934		.enable_reg = 0x4500c,
2935		.enable_mask = BIT(4),
2936		.hw.init = &(struct clk_init_data){
2937			.name = "gcc_mdp_tbu_clk",
2938			.parent_hws = (const struct clk_hw*[]){
2939				&system_noc_bfdcd_clk_src.clkr.hw,
2940			},
2941			.num_parents = 1,
2942			.flags = CLK_SET_RATE_PARENT,
2943			.ops = &clk_branch2_ops,
2944		},
2945	},
2946};
2947
2948static struct clk_branch gcc_smmu_cfg_clk = {
2949	.halt_reg = 0x12038,
2950	.clkr = {
2951		.enable_reg = 0x4500c,
2952		.enable_mask = BIT(12),
2953		.hw.init = &(struct clk_init_data){
2954			.name = "gcc_smmu_cfg_clk",
2955			.parent_hws = (const struct clk_hw*[]){
2956				&pcnoc_bfdcd_clk_src.clkr.hw,
2957			},
2958			.num_parents = 1,
2959			.flags = CLK_SET_RATE_PARENT,
2960			.ops = &clk_branch2_ops,
2961		},
2962	},
2963};
2964
2965static struct clk_branch gcc_venus_tbu_clk = {
2966	.halt_reg = 0x12014,
2967	.clkr = {
2968		.enable_reg = 0x4500c,
2969		.enable_mask = BIT(5),
2970		.hw.init = &(struct clk_init_data){
2971			.name = "gcc_venus_tbu_clk",
2972			.parent_hws = (const struct clk_hw*[]){
2973				&system_noc_bfdcd_clk_src.clkr.hw,
2974			},
2975			.num_parents = 1,
2976			.flags = CLK_SET_RATE_PARENT,
2977			.ops = &clk_branch2_ops,
2978		},
2979	},
2980};
2981
2982static struct clk_branch gcc_vfe_tbu_clk = {
2983	.halt_reg = 0x1203c,
2984	.clkr = {
2985		.enable_reg = 0x4500c,
2986		.enable_mask = BIT(9),
2987		.hw.init = &(struct clk_init_data){
2988			.name = "gcc_vfe_tbu_clk",
2989			.parent_hws = (const struct clk_hw*[]){
2990				&system_noc_bfdcd_clk_src.clkr.hw,
2991			},
2992			.num_parents = 1,
2993			.flags = CLK_SET_RATE_PARENT,
2994			.ops = &clk_branch2_ops,
2995		},
2996	},
2997};
2998
2999static struct clk_branch gcc_usb2a_phy_sleep_clk = {
3000	.halt_reg = 0x4102c,
3001	.clkr = {
3002		.enable_reg = 0x4102c,
3003		.enable_mask = BIT(0),
3004		.hw.init = &(struct clk_init_data){
3005			.name = "gcc_usb2a_phy_sleep_clk",
3006			.parent_data = &(const struct clk_parent_data){
3007				.fw_name = "sleep_clk", .name = "sleep_clk_src",
3008			},
3009			.num_parents = 1,
3010			.flags = CLK_SET_RATE_PARENT,
3011			.ops = &clk_branch2_ops,
3012		},
3013	},
3014};
3015
3016static struct clk_branch gcc_usb_hs_ahb_clk = {
3017	.halt_reg = 0x41008,
3018	.clkr = {
3019		.enable_reg = 0x41008,
3020		.enable_mask = BIT(0),
3021		.hw.init = &(struct clk_init_data){
3022			.name = "gcc_usb_hs_ahb_clk",
3023			.parent_hws = (const struct clk_hw*[]){
3024				&pcnoc_bfdcd_clk_src.clkr.hw,
3025			},
3026			.num_parents = 1,
3027			.flags = CLK_SET_RATE_PARENT,
3028			.ops = &clk_branch2_ops,
3029		},
3030	},
3031};
3032
3033static struct clk_branch gcc_usb_hs_system_clk = {
3034	.halt_reg = 0x41004,
3035	.clkr = {
3036		.enable_reg = 0x41004,
3037		.enable_mask = BIT(0),
3038		.hw.init = &(struct clk_init_data){
3039			.name = "gcc_usb_hs_system_clk",
3040			.parent_hws = (const struct clk_hw*[]){
3041				&usb_hs_system_clk_src.clkr.hw,
3042			},
3043			.num_parents = 1,
3044			.flags = CLK_SET_RATE_PARENT,
3045			.ops = &clk_branch2_ops,
3046		},
3047	},
3048};
3049
3050static struct clk_branch gcc_venus0_ahb_clk = {
3051	.halt_reg = 0x4c020,
3052	.clkr = {
3053		.enable_reg = 0x4c020,
3054		.enable_mask = BIT(0),
3055		.hw.init = &(struct clk_init_data){
3056			.name = "gcc_venus0_ahb_clk",
3057			.parent_hws = (const struct clk_hw*[]){
3058				&pcnoc_bfdcd_clk_src.clkr.hw,
3059			},
3060			.num_parents = 1,
3061			.flags = CLK_SET_RATE_PARENT,
3062			.ops = &clk_branch2_ops,
3063		},
3064	},
3065};
3066
3067static struct clk_branch gcc_venus0_axi_clk = {
3068	.halt_reg = 0x4c024,
3069	.clkr = {
3070		.enable_reg = 0x4c024,
3071		.enable_mask = BIT(0),
3072		.hw.init = &(struct clk_init_data){
3073			.name = "gcc_venus0_axi_clk",
3074			.parent_hws = (const struct clk_hw*[]){
3075				&system_noc_bfdcd_clk_src.clkr.hw,
3076			},
3077			.num_parents = 1,
3078			.flags = CLK_SET_RATE_PARENT,
3079			.ops = &clk_branch2_ops,
3080		},
3081	},
3082};
3083
3084static struct clk_branch gcc_venus0_vcodec0_clk = {
3085	.halt_reg = 0x4c01c,
3086	.clkr = {
3087		.enable_reg = 0x4c01c,
3088		.enable_mask = BIT(0),
3089		.hw.init = &(struct clk_init_data){
3090			.name = "gcc_venus0_vcodec0_clk",
3091			.parent_hws = (const struct clk_hw*[]){
3092				&vcodec0_clk_src.clkr.hw,
3093			},
3094			.num_parents = 1,
3095			.flags = CLK_SET_RATE_PARENT,
3096			.ops = &clk_branch2_ops,
3097		},
3098	},
3099};
3100
3101static struct gdsc venus_gdsc = {
3102	.gdscr = 0x4c018,
3103	.pd = {
3104		.name = "venus",
3105	},
3106	.pwrsts = PWRSTS_OFF_ON,
3107};
3108
3109static struct gdsc mdss_gdsc = {
3110	.gdscr = 0x4d078,
3111	.pd = {
3112		.name = "mdss",
3113	},
3114	.pwrsts = PWRSTS_OFF_ON,
3115};
3116
3117static struct gdsc jpeg_gdsc = {
3118	.gdscr = 0x5701c,
3119	.pd = {
3120		.name = "jpeg",
3121	},
3122	.pwrsts = PWRSTS_OFF_ON,
3123};
3124
3125static struct gdsc vfe_gdsc = {
3126	.gdscr = 0x58034,
3127	.pd = {
3128		.name = "vfe",
3129	},
3130	.pwrsts = PWRSTS_OFF_ON,
3131};
3132
3133static struct gdsc oxili_gdsc = {
3134	.gdscr = 0x5901c,
3135	.pd = {
3136		.name = "oxili",
3137	},
3138	.pwrsts = PWRSTS_OFF_ON,
3139};
3140
3141static struct clk_regmap *gcc_msm8916_clocks[] = {
3142	[GPLL0] = &gpll0.clkr,
3143	[GPLL0_VOTE] = &gpll0_vote,
3144	[BIMC_PLL] = &bimc_pll.clkr,
3145	[BIMC_PLL_VOTE] = &bimc_pll_vote,
3146	[GPLL1] = &gpll1.clkr,
3147	[GPLL1_VOTE] = &gpll1_vote,
3148	[GPLL2] = &gpll2.clkr,
3149	[GPLL2_VOTE] = &gpll2_vote,
3150	[PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
3151	[SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
3152	[CAMSS_AHB_CLK_SRC] = &camss_ahb_clk_src.clkr,
3153	[APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
3154	[CSI0_CLK_SRC] = &csi0_clk_src.clkr,
3155	[CSI1_CLK_SRC] = &csi1_clk_src.clkr,
3156	[GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
3157	[VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
3158	[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
3159	[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
3160	[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3161	[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3162	[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3163	[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3164	[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
3165	[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
3166	[BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
3167	[BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
3168	[BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
3169	[BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
3170	[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3171	[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3172	[CCI_CLK_SRC] = &cci_clk_src.clkr,
3173	[CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
3174	[CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
3175	[JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
3176	[MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
3177	[MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
3178	[CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
3179	[CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
3180	[CPP_CLK_SRC] = &cpp_clk_src.clkr,
3181	[CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
3182	[GP1_CLK_SRC] = &gp1_clk_src.clkr,
3183	[GP2_CLK_SRC] = &gp2_clk_src.clkr,
3184	[GP3_CLK_SRC] = &gp3_clk_src.clkr,
3185	[BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
3186	[ESC0_CLK_SRC] = &esc0_clk_src.clkr,
3187	[MDP_CLK_SRC] = &mdp_clk_src.clkr,
3188	[PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
3189	[VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
3190	[PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
3191	[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
3192	[SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
3193	[APSS_TCU_CLK_SRC] = &apss_tcu_clk_src.clkr,
3194	[USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
3195	[VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
3196	[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3197	[GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
3198	[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3199	[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3200	[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3201	[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3202	[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3203	[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3204	[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
3205	[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
3206	[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
3207	[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
3208	[GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
3209	[GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
3210	[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3211	[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3212	[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3213	[GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr,
3214	[GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr,
3215	[GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,
3216	[GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,
3217	[GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr,
3218	[GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,
3219	[GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,
3220	[GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,
3221	[GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,
3222	[GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,
3223	[GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
3224	[GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
3225	[GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
3226	[GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
3227	[GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,
3228	[GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,
3229	[GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr,
3230	[GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr,
3231	[GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr,
3232	[GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
3233	[GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
3234	[GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr,
3235	[GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
3236	[GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
3237	[GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr,
3238	[GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
3239	[GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr,
3240	[GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr,
3241	[GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,
3242	[GCC_CAMSS_VFE_AHB_CLK] = &gcc_camss_vfe_ahb_clk.clkr,
3243	[GCC_CAMSS_VFE_AXI_CLK] = &gcc_camss_vfe_axi_clk.clkr,
3244	[GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
3245	[GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
3246	[GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
3247	[GCC_OXILI_GMEM_CLK] = &gcc_oxili_gmem_clk.clkr,
3248	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3249	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3250	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3251	[GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
3252	[GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
3253	[GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
3254	[GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
3255	[GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
3256	[GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
3257	[GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
3258	[GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
3259	[GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
3260	[GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
3261	[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3262	[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3263	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3264	[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3265	[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3266	[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3267	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3268	[GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr,
3269	[GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr,
3270	[GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
3271	[GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
3272	[GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr,
3273	[GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
3274	[GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
3275	[GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
3276	[GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
3277	[GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr,
3278	[GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr,
3279	[GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
3280	[BIMC_DDR_CLK_SRC] = &bimc_ddr_clk_src.clkr,
3281	[GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
3282	[GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr,
3283	[BIMC_GPU_CLK_SRC] = &bimc_gpu_clk_src.clkr,
3284	[GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
3285	[GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
3286	[ULTAUDIO_AHBFABRIC_CLK_SRC] = &ultaudio_ahbfabric_clk_src.clkr,
3287	[ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC] = &ultaudio_lpaif_pri_i2s_clk_src.clkr,
3288	[ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC] = &ultaudio_lpaif_sec_i2s_clk_src.clkr,
3289	[ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC] = &ultaudio_lpaif_aux_i2s_clk_src.clkr,
3290	[ULTAUDIO_XO_CLK_SRC] = &ultaudio_xo_clk_src.clkr,
3291	[CODEC_DIGCODEC_CLK_SRC] = &codec_digcodec_clk_src.clkr,
3292	[GCC_ULTAUDIO_PCNOC_MPORT_CLK] = &gcc_ultaudio_pcnoc_mport_clk.clkr,
3293	[GCC_ULTAUDIO_PCNOC_SWAY_CLK] = &gcc_ultaudio_pcnoc_sway_clk.clkr,
3294	[GCC_ULTAUDIO_AVSYNC_XO_CLK] = &gcc_ultaudio_avsync_xo_clk.clkr,
3295	[GCC_ULTAUDIO_STC_XO_CLK] = &gcc_ultaudio_stc_xo_clk.clkr,
3296	[GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK] =	&gcc_ultaudio_ahbfabric_ixfabric_clk.clkr,
3297	[GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_lpm_clk.clkr,
3298	[GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK] = &gcc_ultaudio_lpaif_pri_i2s_clk.clkr,
3299	[GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK] = &gcc_ultaudio_lpaif_sec_i2s_clk.clkr,
3300	[GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK] = &gcc_ultaudio_lpaif_aux_i2s_clk.clkr,
3301	[GCC_CODEC_DIGCODEC_CLK] = &gcc_codec_digcodec_clk.clkr,
3302	[GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
3303};
3304
3305static struct gdsc *gcc_msm8916_gdscs[] = {
3306	[VENUS_GDSC] = &venus_gdsc,
3307	[MDSS_GDSC] = &mdss_gdsc,
3308	[JPEG_GDSC] = &jpeg_gdsc,
3309	[VFE_GDSC] = &vfe_gdsc,
3310	[OXILI_GDSC] = &oxili_gdsc,
3311};
3312
3313static const struct qcom_reset_map gcc_msm8916_resets[] = {
3314	[GCC_BLSP1_BCR] = { 0x01000 },
3315	[GCC_BLSP1_QUP1_BCR] = { 0x02000 },
3316	[GCC_BLSP1_UART1_BCR] = { 0x02038 },
3317	[GCC_BLSP1_QUP2_BCR] = { 0x03008 },
3318	[GCC_BLSP1_UART2_BCR] = { 0x03028 },
3319	[GCC_BLSP1_QUP3_BCR] = { 0x04018 },
3320	[GCC_BLSP1_QUP4_BCR] = { 0x05018 },
3321	[GCC_BLSP1_QUP5_BCR] = { 0x06018 },
3322	[GCC_BLSP1_QUP6_BCR] = { 0x07018 },
3323	[GCC_IMEM_BCR] = { 0x0e000 },
3324	[GCC_SMMU_BCR] = { 0x12000 },
3325	[GCC_APSS_TCU_BCR] = { 0x12050 },
3326	[GCC_SMMU_XPU_BCR] = { 0x12054 },
3327	[GCC_PCNOC_TBU_BCR] = { 0x12058 },
3328	[GCC_PRNG_BCR] = { 0x13000 },
3329	[GCC_BOOT_ROM_BCR] = { 0x13008 },
3330	[GCC_CRYPTO_BCR] = { 0x16000 },
3331	[GCC_SEC_CTRL_BCR] = { 0x1a000 },
3332	[GCC_AUDIO_CORE_BCR] = { 0x1c008 },
3333	[GCC_ULT_AUDIO_BCR] = { 0x1c0b4 },
3334	[GCC_DEHR_BCR] = { 0x1f000 },
3335	[GCC_SYSTEM_NOC_BCR] = { 0x26000 },
3336	[GCC_PCNOC_BCR] = { 0x27018 },
3337	[GCC_TCSR_BCR] = { 0x28000 },
3338	[GCC_QDSS_BCR] = { 0x29000 },
3339	[GCC_DCD_BCR] = { 0x2a000 },
3340	[GCC_MSG_RAM_BCR] = { 0x2b000 },
3341	[GCC_MPM_BCR] = { 0x2c000 },
3342	[GCC_SPMI_BCR] = { 0x2e000 },
3343	[GCC_SPDM_BCR] = { 0x2f000 },
3344	[GCC_MM_SPDM_BCR] = { 0x2f024 },
3345	[GCC_BIMC_BCR] = { 0x31000 },
3346	[GCC_RBCPR_BCR] = { 0x33000 },
3347	[GCC_TLMM_BCR] = { 0x34000 },
3348	[GCC_USB_HS_BCR] = { 0x41000 },
3349	[GCC_USB2A_PHY_BCR] = { 0x41028 },
3350	[GCC_SDCC1_BCR] = { 0x42000 },
3351	[GCC_SDCC2_BCR] = { 0x43000 },
3352	[GCC_PDM_BCR] = { 0x44000 },
3353	[GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000 },
3354	[GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000 },
3355	[GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008 },
3356	[GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010 },
3357	[GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018 },
3358	[GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020 },
3359	[GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028 },
3360	[GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030 },
3361	[GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038 },
3362	[GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040 },
3363	[GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048 },
3364	[GCC_MMSS_BCR] = { 0x4b000 },
3365	[GCC_VENUS0_BCR] = { 0x4c014 },
3366	[GCC_MDSS_BCR] = { 0x4d074 },
3367	[GCC_CAMSS_PHY0_BCR] = { 0x4e018 },
3368	[GCC_CAMSS_CSI0_BCR] = { 0x4e038 },
3369	[GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 },
3370	[GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c },
3371	[GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 },
3372	[GCC_CAMSS_PHY1_BCR] = { 0x4f018 },
3373	[GCC_CAMSS_CSI1_BCR] = { 0x4f038 },
3374	[GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 },
3375	[GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c },
3376	[GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 },
3377	[GCC_CAMSS_ISPIF_BCR] = { 0x50000 },
3378	[GCC_CAMSS_CCI_BCR] = { 0x51014 },
3379	[GCC_CAMSS_MCLK0_BCR] = { 0x52014 },
3380	[GCC_CAMSS_MCLK1_BCR] = { 0x53014 },
3381	[GCC_CAMSS_GP0_BCR] = { 0x54014 },
3382	[GCC_CAMSS_GP1_BCR] = { 0x55014 },
3383	[GCC_CAMSS_TOP_BCR] = { 0x56000 },
3384	[GCC_CAMSS_MICRO_BCR] = { 0x56008 },
3385	[GCC_CAMSS_JPEG_BCR] = { 0x57018 },
3386	[GCC_CAMSS_VFE_BCR] = { 0x58030 },
3387	[GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c },
3388	[GCC_OXILI_BCR] = { 0x59018 },
3389	[GCC_GMEM_BCR] = { 0x5902c },
3390	[GCC_CAMSS_AHB_BCR] = { 0x5a018 },
3391	[GCC_MDP_TBU_BCR] = { 0x62000 },
3392	[GCC_GFX_TBU_BCR] = { 0x63000 },
3393	[GCC_GFX_TCU_BCR] = { 0x64000 },
3394	[GCC_MSS_TBU_AXI_BCR] = { 0x65000 },
3395	[GCC_MSS_TBU_GSS_AXI_BCR] = { 0x66000 },
3396	[GCC_MSS_TBU_Q6_AXI_BCR] = { 0x67000 },
3397	[GCC_GTCU_AHB_BCR] = { 0x68000 },
3398	[GCC_SMMU_CFG_BCR] = { 0x69000 },
3399	[GCC_VFE_TBU_BCR] = { 0x6a000 },
3400	[GCC_VENUS_TBU_BCR] = { 0x6b000 },
3401	[GCC_JPEG_TBU_BCR] = { 0x6c000 },
3402	[GCC_PRONTO_TBU_BCR] = { 0x6d000 },
3403	[GCC_SMMU_CATS_BCR] = { 0x7c000 },
3404};
3405
3406static const struct regmap_config gcc_msm8916_regmap_config = {
3407	.reg_bits	= 32,
3408	.reg_stride	= 4,
3409	.val_bits	= 32,
3410	.max_register	= 0x80000,
3411	.fast_io	= true,
3412};
3413
3414static const struct qcom_cc_desc gcc_msm8916_desc = {
3415	.config = &gcc_msm8916_regmap_config,
3416	.clks = gcc_msm8916_clocks,
3417	.num_clks = ARRAY_SIZE(gcc_msm8916_clocks),
3418	.resets = gcc_msm8916_resets,
3419	.num_resets = ARRAY_SIZE(gcc_msm8916_resets),
3420	.gdscs = gcc_msm8916_gdscs,
3421	.num_gdscs = ARRAY_SIZE(gcc_msm8916_gdscs),
3422};
3423
3424static const struct of_device_id gcc_msm8916_match_table[] = {
3425	{ .compatible = "qcom,gcc-msm8916" },
3426	{ }
3427};
3428MODULE_DEVICE_TABLE(of, gcc_msm8916_match_table);
3429
3430static int gcc_msm8916_probe(struct platform_device *pdev)
3431{
3432	int ret;
3433	struct device *dev = &pdev->dev;
3434
3435	ret = qcom_cc_register_board_clk(dev, "xo_board", "xo", 19200000);
3436	if (ret)
3437		return ret;
3438
3439	ret = qcom_cc_register_sleep_clk(dev);
3440	if (ret)
3441		return ret;
3442
3443	return qcom_cc_probe(pdev, &gcc_msm8916_desc);
3444}
3445
3446static struct platform_driver gcc_msm8916_driver = {
3447	.probe		= gcc_msm8916_probe,
3448	.driver		= {
3449		.name	= "gcc-msm8916",
3450		.of_match_table = gcc_msm8916_match_table,
3451	},
3452};
3453
3454static int __init gcc_msm8916_init(void)
3455{
3456	return platform_driver_register(&gcc_msm8916_driver);
3457}
3458core_initcall(gcc_msm8916_init);
3459
3460static void __exit gcc_msm8916_exit(void)
3461{
3462	platform_driver_unregister(&gcc_msm8916_driver);
3463}
3464module_exit(gcc_msm8916_exit);
3465
3466MODULE_DESCRIPTION("Qualcomm GCC MSM8916 Driver");
3467MODULE_LICENSE("GPL v2");
3468MODULE_ALIAS("platform:gcc-msm8916");